Test methods, apparatus, systems, and computer-readable media

Abstract

The application discloses a test method, device, system and computer readable medium, and relates to the chip technical field. The method comprises the following steps: in the case that a signal end of a to-be-tested chip is connected with a signal pin, testing the to-be-tested chip through the signal pin; when the testing is completed, triggering the isolation device to perform an electrical isolation operation on the signal pin, and in the case that the to-be-tested chip is disconnected with the signal pin, controlling the test chip to keep a power-on state. Therefore, when the to-be-tested chip is tested, the test chip triggers the isolation device to perform the electrical isolation operation on the signal pin, so that the signal pin can be electrically isolated, the leakage of the test system can be prevented from affecting the to-be-tested chip, and the timing of the test system can also be prevented from being affected. Meanwhile, the test chip can keep a power-on state, and the test chip can be prevented from being frequently restarted.

Description

Technical Field

[0001] This application relates to the field of chip technology, and more specifically, to a testing method, apparatus, system, and computer-readable medium. Background Technology

[0002] SLT (System Level Test) refers to the testing performed on a chip after it has been installed on the motherboard and booted into the operating system. System-level testing is commonly used for chips with complex logic functions and a large number of gate circuits, such as CPUs and GPUs. The industry generally performs system-level testing after the final test (FT). FT is the final test before the chip leaves the factory, and it is performed on packaged chips. Typically, chip probing (CP, also known as wafer testing) is followed by packaging, and then FT testing is performed. As chips become increasingly complex, the firmware or OS program used for SLT testing takes longer to load. For some chips, a test chip is required to complete the test. Therefore, when replacing a new chip after testing one chip, the test chip needs to be restarted, which severely impacts testing efficiency and speed. Summary of the Invention

[0003] This application proposes a testing method, apparatus, system, and computer-readable medium to improve the above-mentioned deficiencies.

[0004] In a first aspect, embodiments of this application provide a testing method applied to a test chip in a testing system. The testing system further includes an isolation device and test pins. The test chip is connected to the isolation device, and the test pins include signal pins. The method includes: testing the test chip through the signal pins when the signal terminal of the chip under test is connected to the signal pins; when the test is completed, triggering the isolation device to perform an electrical isolation operation on the signal pins; and controlling the test chip to remain powered on when the chip under test is disconnected from the signal pins.

[0005] Secondly, embodiments of this application also provide a testing apparatus for a test chip in a testing system. The testing system further includes an isolation device and test pins. The test chip is connected to the isolation device, and the test pins include signal pins. The apparatus includes a processing unit and an isolation unit. The processing unit is used to test the chip under test (DUT) through the signal pins when the signal terminal of the DUT is connected to the signal pins. The isolation unit is used to trigger the isolation device to perform electrical isolation on the signal pins when the test is completed, and to control the test chip to remain powered on when the DUT is disconnected from the signal pins.

[0006] Thirdly, embodiments of this application also provide a testing system, including: an isolation device, a test chip, and test pins, wherein the test chip is connected to the isolation device, and the test pins include signal pins; the test chip is used to perform the above-described method.

[0007] Fourthly, embodiments of this application also provide a computer-readable medium storing processor-executable program code, which, when executed by the processor, causes the processor to perform the above-described method.

[0008] The testing method, apparatus, system, and computer-readable medium provided in this application include a test chip, an isolation device, and test pins. The test pins include signal pins. When a chip under test (DUT) needs to be tested, the DUT is connected to the signal pins. Therefore, when the signal terminal of the DUT is connected to the signal pins, the test chip can also be connected to the signal pins, allowing the test chip to test the DUT through the signal pins. When the DUT test is complete, the test chip triggers the isolation device to perform electrical isolation on the signal pins, thereby electrically isolating the signal pins and preventing leakage current in the test system from affecting the DUT, as well as affecting the timing of the test system. Simultaneously, it keeps the test chip powered on, avoiding frequent restarts of the test chip.

[0009] Other features and advantages of the embodiments of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the embodiments of this application. The objects and other advantages of the embodiments of this application may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 A schematic diagram of a test system provided in one embodiment of this application is shown;

[0012] Figure 2 A flowchart of a testing method provided in an embodiment of this application is shown;

[0013] Figure 3 A schematic diagram of a test pin provided in one embodiment of this application is shown;

[0014] Figure 4 A schematic diagram of a test system provided in another embodiment of this application is shown;

[0015] Figure 5 A schematic diagram of a test system provided in yet another embodiment of this application is shown;

[0016] Figure 6 A schematic diagram of a test system provided in another embodiment of this application is shown;

[0017] Figure 7 A schematic diagram of a test system provided in another embodiment of this application is shown;

[0018] Figure 8 A schematic diagram of a test system provided in yet another embodiment of this application is shown;

[0019] Figure 9 A flowchart of a testing method provided in another embodiment of this application is shown;

[0020] Figure 10 A schematic diagram of a test system provided in yet another embodiment of this application is shown;

[0021] Figure 11 A schematic diagram of a test system provided in another embodiment of this application is shown;

[0022] Figure 12 A flowchart of a testing method provided in another embodiment of this application is shown;

[0023] Figure 13 A schematic diagram of a test system provided in yet another embodiment of this application is shown;

[0024] Figure 14 A schematic diagram of the isolation device provided in an embodiment of this application is shown;

[0025] Figure 15 A schematic diagram of a test system provided in yet another embodiment of this application is shown;

[0026] Figure 16 A block diagram of a test apparatus provided in one embodiment of this application is shown;

[0027] Figure 17 A schematic diagram of a computer storage medium provided in an embodiment of this application is shown. Detailed Implementation

[0028] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, and not all of them. The components of the embodiments of the present application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without inventive effort are within the scope of protection of the present application.

[0029] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0030] SLT (System-Level Test) refers to the testing performed on a chip after it has been installed on the motherboard and booted into the operating system. System-level testing is commonly used for chips with complex logic functions and a large number of gate circuits, such as CPUs and GPUs. The industry generally performs system-level testing after the final test (FT). FT is the final test before the chip leaves the factory, and it is performed on packaged chips. Typically, chip probing (CP, also known as wafer testing) is followed by packaging, and then FT testing is conducted. As chips become increasingly complex, the firmware or OS program used for SLT testing takes longer to load. For some chips, a test chip is required to complete the test; therefore, when replacing a new chip with the test chip after completing the test of another chip, the test chip needs to be restarted.

[0031] Specifically, for SLT testing of a chip under test (DUT) that requires the participation of other System-on-Chip (SoC) devices, these other SoCs can be paired chips, i.e., system-on-chips that work together with the DUT to form a system-level test. For example, if a DUT requires an Application Processor (AP) chip to function properly, the AP chip acts as the paired chip for that DUT. Currently, the SLT testing process involves powering down the entire test board, then a robotic arm removes the tested chip, and then the robotic arm places a new DUT on it before powering the test board back on. Because the entire test board needs to be powered back on, both the DUT and the paired chip need to be restarted. Removing or placing chips while they are powered on can affect power-on / off timing, leakage current, and other abnormalities. Therefore, SLT testing currently always involves powering down the chip before removing or placing it.

[0032] However, the inventors discovered in their research that for SLT testing of chips that require the participation of other SoCs, in order to avoid the impact of chip handling on the power-on / off timing of the test system and abnormal phenomena such as leakage current on the test system, each chip needs to be restarted, which will seriously affect the test efficiency and speed.

[0033] Therefore, to overcome the above-mentioned shortcomings, embodiments of this application provide a testing method, apparatus, and system that can avoid frequently restarting the chip under test when replacing it. Specifically, please refer to... Figure 1 , Figure 1 This application illustrates a test system provided in an embodiment of the present application. The test system includes a test chip 110, an isolation device 120, a chip under test (DUT) 130, and test pins. It should be noted that the test pins are not limited to pins transmitting test signals or test data; any pin related to the test can be used as a test pin. The test pins include a signal pin 210. The isolation device 120 is connected to the signal pin 210. The test chip 110 is connected to both the isolation device 120 and the signal pin 210. Specifically, the test chip 110 can be connected to the signal pin 210 via the isolation device 120 or directly to the signal pin 210. Specifically, the isolation device 120 performs electrical isolation on the test pin. The specific method of electrical isolation can be to change the voltage level of the test pin to a low level or to set the test pin to a high impedance state. Therefore, the connection method between the test chip 110 and the signal pin 210 differs depending on the electrical isolation method used. This will be explained in detail in the following embodiments.

[0034] Please see Figure 2 , Figure 2This application illustrates a testing method provided by an embodiment of the present application. This testing method can be applied to the testing system mentioned in any embodiment of the present application. Specifically, the execution subject of the method can be the test chip of the testing system, and the method can include: S201 to S202.

[0035] S201: When the signal terminal of the chip under test is connected to the signal pin, the chip under test is tested through the signal pin.

[0036] In one implementation, when the chip under test (DUT) is tested, it needs to be connected to a matching chip. That is, the signal terminals of the DUT need to be connected to signal pins, and then the matching chip also needs to be connected to its signal pins. Thus, the DUT and the matching chip are connected via signal pins, allowing the matching chip to transmit test-related instructions or data to the DUT. When the DUT test is finished, it can be disconnected from its signal pins, allowing a new DUT to be replaced. The new DUT is then reconnected to its signal pins, thus completing the testing of one chip and the preparatory work for testing a new chip—namely, establishing the connection between the signal terminals of the matching chip and the DUT.

[0037] In this embodiment of the application, to facilitate the connection or conduction of the chip under test (DUT) with the signal pins and the replacement of the DUT, the test system further includes a chip mounting component. Test pins are disposed on this chip mounting component. The DUT can be mounted on the chip mounting component, and upon successful mounting, each pin of the DUT is connected to each pin on the chip mounting component. Figure 3 As shown, the chip mounting component 160 can be a chip socket. Figure 3 The shaded area shown represents the sockets of the chip mounting component. Each socket of the chip mounting component can serve as a test pin. When the chip under test (DUT) is inserted into the chip mounting component 160, the pins of the DUT can be inserted into the sockets and electrically connected to them. In other words, each pin of the DUT can be connected to the test pin corresponding to its position. Figure 3 As shown, the signal terminal 131 of the chip under test 130 can be inserted into the socket of the chip mounting component 160, which serves as the signal pin 210, to achieve an electrical connection between the signal terminal 131 of the chip under test 130 and the signal pin 210.

[0038] In one implementation, the test chip can be connected to the signal pin while the signal terminal of the chip under test is connected to the signal pin. Specifically, the test chip and the signal pin can remain connected, or the test chip and the signal pin can remain connected while the signal terminal of the chip under test is connected to the signal pin, and when the signal terminal of the chip under test is disconnected from the signal pin, the test chip and the signal pin are also disconnected. Specifically, this is related to electrical isolation operation, which will be described in detail later.

[0039] With the signal terminal of the chip under test (DUT) connected to the signal pin, the test chip performs tests on the DUT. For example, the test chip controls the DUT to specify test tasks. Specifically, the test chip and the DUT jointly complete the test tasks. The DUT's test system and corresponding test software all run within the test chip. The DUT can perform various functional and performance tests on the DUT, thereby obtaining the test results.

[0040] It should be noted that, for ease of testing, all electronic components within the testing system can be mounted on a single test motherboard, allowing the testing system to operate relatively independently of other systems. Specifically, for example... Figure 4 As shown, the test system may include a test motherboard 300. Each chip or electronic component of the test system can be mounted on the test motherboard 300. Specifically, it can be seen that the test chip 110, the isolation device 120, and the chip mounting component 160 are all mounted on the test motherboard 300. Therefore, when testing a chip under test, the chip under test is mounted on the test motherboard 300 to achieve the connection between the chip under test and the test pins. Specifically, the chip under test can be mounted in the chip mounting component 160 so that each pin of the chip under test is electrically connected to the test pins on the chip mounting component 160.

[0041] In one implementation, the testing equipment may send test task information to the chip under test (DUT), which then performs test operations based on the test task. The test task information includes specified operations to be performed by the DUT, execution parameters for each operation, and the DUT's operating environment parameters. This test task information is related to the test operations. After the DUT's test operations are completed, the DUT sends the current test status information and test results to the testing equipment. The testing equipment can store this status information and test results, or push them to a designated client. This designated client can be a client used by testers to operate the DUT's test operations, allowing testers to view the DUT's status information and test results. This status information includes information other than the test result information, such as the chip's identification number (e.g., lot ID information).

[0042] like Figure 4 The other chips shown may be chips other than the test chip that also participate in the test operation of the chip under test, such as power chips or chips that work with the chip under test to complete a certain preset task, such as testing the control operation of the chip under test. In this case, the other chips may include controlled chips that can be controlled by the chip under test. Specifically, the other chips will be described in detail in the following embodiments.

[0043] S202: When the test is completed, the isolation device is triggered to perform electrical isolation operation on the signal pin, and the test chip is kept powered on when the chip under test is disconnected from the test pin.

[0044] When the test of the chip under test is completed or other situations require disconnecting the chip under test from the signal pins, the chip under test can be removed from the chip mounting component 160. To avoid removing the chip under test while it is powered on, an isolation operation can be performed first, and then the chip under test can be removed from the test motherboard 300, thereby disconnecting the chip under test from the signal pins. At this time, the chip under test remains powered on and the isolation device continues to perform electrical isolation operation on the signal pins. In other words, the electrical isolation operation continues. In one implementation, the chip can include a power-on state and a power-off state. A chip in a power-off state refers to a state in which the chip cannot work normally due to power failure, loss of power, or insufficient power quality. Switching the chip to a power-off state usually means stopping the power supply to the chip. For example, the chip can be disconnected from its power supply. The power-on state is the opposite of the power-off state, which means that the chip can work normally when the power quality meets the requirements. For example, the chip has sufficient power and is connected to the power supply. If the chip is restarted, it will first enter the power-off state and then return to the power-on state. The way to keep the test chip in the power-on state is to keep the power supply of the test chip able to deliver a power signal that meets the power requirements of the test chip and not actively disconnect the connection between the power supply and the test chip.

[0045] While the test chip remains powered on, the isolation device is triggered to perform an electrical isolation operation on the signal pin. As one implementation, this isolation operation may include setting the pin to a low level or a high impedance state; that is, the isolation device performing an electrical isolation operation on the signal pin may include setting the signal pin to a low level or a high impedance state. For example, the test chip sends an isolation command to the isolation device, and the isolation device responds to the isolation command by performing an electrical isolation operation on the signal pin.

[0046] In one implementation, if the isolation device performs electrical isolation on the signal pin by setting the signal pin to a low level, it can connect the signal pin to ground. For example, the isolation device can be a switching element, such as an analog switch, transistor, or field-effect transistor. This switching element includes a first terminal and a second terminal; the first terminal is grounded, and the second terminal is connected to the signal pin. The isolation device conducts the first and second terminals, thereby connecting the signal pin to ground. Alternatively, the isolation device can continuously input a low-level signal to the signal pin. In this case, the test chip can be directly connected to the signal pin, or it can be connected through the isolation device.

[0047] Specifically, such as Figure 5As shown, the test chip 110 includes a signal test terminal 101 and a control terminal 102. The signal test terminal 101 of the test chip 110 is connected to the signal pin 210, and the control terminal 102 of the test chip 110 is connected to one end 120 of the isolation device. The other end of the isolation device 120 is connected to the signal pin 210. That is, the signal test terminal 101 of the test chip 110 can be directly connected to the signal pin 210. The test chip 110 can send test task information to the chip under test 130 and obtain status or test results data from the chip under test 130 through the signal test terminal 101 and the signal pin 210. The test chip 110 can send isolation commands to the isolation device 120 through the control terminal 102 to cause the isolation device 120 to perform electrical isolation operation. Specifically, since the signal test terminal 101 of the test chip 110 can be directly connected to the signal pin 210, Figure 5 In the illustrated embodiment, the electrical isolation operation performed by the isolation device 120 is to turn the test pin low, for example, to ground the test pin. So that when the chip under test 130 is disconnected from the test pin, if the chip under test 110 leaks current, the leaked charge can flow directly into the isolation device, that is, the leaked charge is quickly released through the aforementioned low level, so as to avoid the leaked charge from affecting the current chip under test or other chips under test.

[0048] like Figure 6 As shown, the signal test terminal 101 and control terminal 102 of the test chip 110 are both connected to the isolation device 120. The isolation device 120 is also connected to the signal pin 210. For example, the isolation device 120 includes a first input terminal, a second input terminal, and a first output terminal. The signal test terminal 101 of the test chip 110 is connected to the first input terminal of the isolation device 120, the control terminal 102 of the test chip 110 is connected to the second input terminal of the isolation device 120, and the first output terminal of the isolation device 120 is connected to the signal pin 210. That is to say, the test task information output by the signal test terminal 101 of the test chip 110 needs to be sent to the signal pin through the isolation device 120 and then input to the chip under test 130. Therefore, for Figure 6 In the embodiment shown, the electrical isolation operation performed by the isolation device 120 is to change the test pin to a low level or a high impedance state. For example, the isolation device 120 can ground both the first input terminal and the second input terminal, or it can disconnect both the first input terminal and the second input terminal from the first output terminal. If leakage occurs in the test chip 110, the charge generated by the leakage will either be released to ground by the isolation device or blocked from being transmitted to the signal pin by the high impedance state of the isolation device.

[0049] It should be noted that when the chip under test (DUT) is performing tests, the test chip will send specified information back to the test chip after the DUT has completed all test operations. This specified information indicates that the test is complete. Upon detecting this specified information, the test chip can determine that the test is complete. Alternatively, the test chip can also determine that the test is complete when it detects that the test has been terminated; this is not limited here.

[0050] Therefore, the test system can include a test chip, an isolation device, and test pins. The test pins include signal pins. When the chip under test (DUT) needs to be tested, the DUT is connected to the signal pin. Thus, when the signal terminal of the DUT is connected to the signal pin, the test chip can also connect to the signal pin, allowing the test chip to test the DUT through the signal pin. When the DUT test is complete, the test chip triggers the isolation device to perform electrical isolation on the signal pin, thereby electrically isolating the signal pin and preventing leakage current in the test system from affecting the DUT, as well as affecting the timing of the test system. Simultaneously, it keeps the test chip powered on, avoiding frequent restarts of the test chip.

[0051] Furthermore, if the test system may also include a power supply, then the impact of the power supply on the chip under test also needs to be considered. Specifically, for example... Figure 7 and 8 As shown, the test pins also include a power supply pin 220, through which power is supplied to the chip under test 130. Figure 7 As shown, the signal test terminal 101 of the test chip is connected to the signal pin 210, and the control terminal 102 of the test chip is connected to the isolation device 120. The isolation device 120 is connected to both the signal pin 210 and the power supply pin 220. The isolation device 120 can ground both the signal pin 210 and the power supply pin 220 to achieve electrical isolation between them. Figure 8 As shown, the isolation device may include two devices. The signal test terminal 101 of the test chip is connected to the signal pin 210 through the isolation device 120A. The control terminal 102 of the test chip is connected to the isolation device 120A and the isolation device 120B respectively. The power supply 140 is connected to the power supply pin 220 through the isolation device 120B. When it is necessary to electrically isolate the test pin of the chip under test, the isolation device 120A can be controlled to disconnect the test chip 110 from the signal pin 210 or to ground the isolation device 120A, thereby pulling the level of the signal pin 210 low, for example, to 0 level.

[0052] like Figure 9 As shown, Figure 9 A test method is shown, which is applied to the aforementioned test system. Specifically, the test system may include a power supply. For example, refer to... Figure 7 and 8 The test system shown, specifically, the method may include: S901 to S902.

[0053] S901: When the signal terminal of the chip under test is connected to the signal pin, the chip under test is tested through the signal pin.

[0054] The implementation method of S901 can be referred to the foregoing embodiments, and will not be repeated here.

[0055] S902: When the test is completed, the isolation device is triggered to perform electrical isolation operation on the power supply pin and the signal pin, and the chip under test is kept powered on when the chip under test is disconnected from the test pin.

[0056] As one implementation, the test system described above further includes a power supply, and the test pins also include power supply pins. When the chip under test (DUT) is disconnected from both the signal pins and the power supply pins, the DUT remains powered on. Then, the DUT triggers the isolation device to perform electrical isolation on the power supply pins and also triggers electrical isolation on the signal pins. The electrical isolation operation of the signal pins can be referred to in the aforementioned embodiments and will not be repeated here. The method by which the isolation device triggers the electrical isolation operation of the signal pins can also refer to the electrical isolation operation of the signal pins; that is, the power supply pins can also be set to a low level or a high impedance state.

[0057] It should be noted that, in addition to setting the power supply pin to a low level or high impedance state as described above, the method of performing electrical isolation operation on the power supply pin can also be to trigger the power supply to stop supplying power to the power supply pin. Therefore, as... Figure 10 As shown, the power supply 140 can be directly connected to the power supply pin 220. The testing chip 110 can control the power supply 140 and trigger the power supply to stop supplying power to the power supply pin, for example, by turning off the power supply. Alternatively, the power supply can be triggered to turn off by an isolation device. In this case, the testing chip can send a power-off command to the isolation device, and the isolation device will trigger the power supply to turn off.

[0058] Furthermore, the test pins may also include auxiliary pins. The chip under test (DUT) can connect to a designated chip via these auxiliary pins. The designated chip works with the DUT to complete a specified test task. For example, the designated chip could be a camera chip that controls the camera to perform image acquisition operations and processes the acquired data into image data of a specified format. If the specified test task for the DUT is to take a picture and open a specified filter mode, then the DUT and the designated chip need to work together to complete this task. It should be noted that the designated chip differs from the chip under test in that the chip under test includes the firmware of the DUT and the operating system running on the DUT. This chip controls the DUT to perform various test tasks and provides the operating environment for the DUT. The designated chip, on the other hand, participates in a specific test task of the DUT, acting as a participant in certain stages of that test task. Figure 11 As shown, unlike the aforementioned test system, the chip under test (DUT) is also connected to the designated chip via an isolation device 120C. When the DUT test is completed, the paired chip can control the isolation device 120C to perform electrical isolation on the auxiliary pin 230. Specifically, as... Figure 12 As shown, this application provides a testing method that can be applied to the aforementioned testing system. The method includes steps S1201 to S1203.

[0059] S1201: When the signal terminal of the chip under test is connected to the signal pin, the chip under test is tested through the signal pin.

[0060] S1202: When the test is completed, the isolation device is triggered to perform electrical isolation operation on the test pin, and the test chip is kept powered on when the chip under test is disconnected from the test pin.

[0061] In one implementation, if the test pin includes a signal pin and a power supply pin, triggering the isolation device to perform electrical isolation on the test pin can be achieved by triggering the isolation device to perform electrical isolation on both the power supply pin and the signal pin, or by triggering the isolation device to perform electrical isolation on the signal pin and controlling the power supply to stop supplying power to the power supply pin. Specifically, this can be achieved by triggering the isolation device to perform electrical isolation on the signal pin and controlling the power supply to stop supplying power to the power supply pin when it is determined that the power supply can be turned off.

[0062] As another implementation, if the test pin includes a signal pin and an auxiliary pin, the implementation of triggering the isolation device to perform electrical isolation operation on the test pin can be to trigger the isolation device to perform electrical isolation operation on both the signal pin and the auxiliary pin, or to trigger the isolation device to put the signal pin and a specified chip into a low level or high impedance state, for example, to switch the specified chip to a power-down state.

[0063] Specifically, it can be determined whether the designated port of the designated chip can be switched to a low level or a high impedance state. That is, it can be determined whether the signal terminal of the designated chip can be set to a low level or a high impedance state. If so, when it is determined that the test of the chip under test is completed, the isolation device can be triggered to perform an electrical isolation operation on the signal pin. Then, the designated port of the designated chip can be triggered to switch to a low level or a high impedance state, and the connection between the designated port of the designated chip and the auxiliary pin is maintained. Since the designated port of the designated chip is switched to a low level or a high impedance state, that is, it has been isolated, the current when the designated chip leaks current will not reach the auxiliary pin through the designated port.

[0064] As one implementation, test pins may include signal pins, power supply pins, and auxiliary pins. Since other electronic devices besides the test chip can be set to a power-down state or a high-impedance state, it can be determined whether a test pin can be directly connected to an electronic device based on whether the electronic device connected to different pins can self-isolate. For electronic devices that cannot self-isolate, the test pins connected to those devices need to be electrically isolated by an isolation device. Specifically, such as... Figure 13As shown, the isolation device includes a first switch circuit 121, a second switch circuit 122, and a third switch circuit 123. The test chip includes a processor, the power supply includes a first power supply 141, a second power supply 142, and a PMIC chip 143, the designated chips include a camera chip 151 and a PMIC chip 152, and the test pins include a first signal pin 211, a second signal pin 212, a first power supply pin 221, a second power supply pin 222, a third power supply pin 223, and an auxiliary pin 230. When the chip under test 130 needs to be tested, the chip under test 130 needs to be installed on the test motherboard. Then, the chip under test 130 is connected to the first signal pin 211, the second signal pin 212, the first power supply pin 221, the second power supply pin 222, the third power supply pin 223, and the auxiliary pin 230 respectively. Then, the camera chip 151 is connected to the auxiliary pin 230, the first power supply 141 is connected to the first signal pin 221, the second power supply 142 is connected to the second power supply pin 222 through the third switch circuit 123, the second power supply 142 is connected to the processor 111, the first signal terminal of the processor 111 is connected to the first signal pin 211, the second signal terminal of the processor 111 is connected to the second signal pin 212 through the first switch circuit 121, and the PMIC chip is connected to the third power supply pin 223 through the second switch circuit 122.

[0065] In this embodiment, the PMIC chip provides a clock signal to the chip under test (DUT). To avoid timing issues caused by disconnecting the DUT from the test pins, the connection between the PMIC chip and the third power supply pin 223 needs to be disconnected via the second switch circuit 122 before disconnecting the DUT from the test pins. The processor can be the aforementioned AP chip. The processor provides a termination signal and an I2C signal to the DUT via a second signal terminal and a second signal pin 212. The first switch circuit 121 can disconnect the second signal terminal and the second signal pin 212 or ground the second signal pin 212, thus achieving electrical isolation. The processor's first signal terminal communicates with the first signal pin 211 of the DUT via MIPI / SDIO. This MIPI signal is an input signal to the AP, and due to its high impedance (high impedance state), the isolation of this MIPI signal can be simplified to a direct connection. If this signal is an SDIO signal, when the chip under test is disconnected from the test pin, the first signal terminal of the processor is set as a GPIO port. Then, the first signal terminal is set to 0 level or high impedance state, and then the SDIO signal is set to a low level signal.

[0066] Since the camera chip 151 communicates with the chip under test (DUT) 130 via MIPI, and automatically switches to a power-down state when the connection between the camera chip 151 and the DUT 130 is lost, the camera chip 151 can be directly connected to the DUT 130. The first power supply 141 supplies power to the DUT 130 separately and can be controlled to be turned off when the DUT is disconnected from the test pin, and turned on when the DUT or a new test chip is connected to the test pin. Therefore, the first power supply 141 can be directly connected to the first power supply pin 221 of the DUT. Additionally, the second power supply powers both the DUT and the matching test chip. This power supply cannot be turned off because the AP is constantly operating during testing, and therefore requires isolation through a third switching circuit.

[0067] As one implementation method, the aforementioned switching circuits can all be MOSFET switches, or they can be analog circuits, such as... Figure 14 As shown, the isolation device can be an analog switch, which may include a switch chip IC1, a first resistor R1, a second resistor R2, and a third resistor R3. The D+ pin of switch chip IC1 is connected to the first terminal through the third resistor R3, and the HSD2+ pin of switch chip IC1 is connected to the second terminal. The S pin of switch chip IC1 is connected to the control signal receiving terminal V through the second resistor R2. Switch chip IC1 is a 1-to-2 switch chip, and the path is selected by the level of the S pin. When the control signal receiving terminal V receives a low-level signal, the S pin is also low, thus D+ and HSD1+ are connected. Similarly, when the S pin is high, D+ and HSD2+ are connected. Therefore, when the S pin is low, HSD2+ is not connected to D+ and is in a high-impedance state. One of the first and second terminals is connected to a test pin, and the other can be connected to a test chip, power supply, or a designated chip. For example, the first terminal is connected to a PMIC chip, and the second terminal is connected to a third power supply pin.

[0068] S1203: Send a specified instruction to the grasping device.

[0069] It should be noted that, in order to facilitate control of electrical isolation operations and to facilitate the replacement of different chips under test for testing, a gripping device can be set up, such as... Figure 15As shown, the testing system also includes a gripping device 400, which can be connected to the test chip 110. The testing machine is connected to the test chip 110 and is used to receive the test results of the chip under test fed back by the test chip. Specifically, when the chip under test is installed on the test motherboard, that is, when the chip under test is connected to the test pins on the test motherboard, the test chip and the chip under test form a system-level test scheme. The testing system and corresponding test software run on the test chip system, which can perform various functional and performance tests on the chip under test, and then feed the test results back to the testing machine. When the chip under test is tested, the test chip controls the isolation device to isolate the test pin at a specified point, and then sends a specified instruction to the gripping device. The specified instruction is used to trigger the gripping device to move the chip under test from the test chip. The test motherboard is removed to disconnect the connection between the test pins and the chip under test (DUT). Specifically, the test chip can directly send a specified command to the gripping device, or the test chip can send a specified command to the testing machine, which then forwards the command to the gripping device. Additionally, the test chip can control the gripping device to place the target chip onto the test motherboard, thus establishing a connection between the target chip and the test pins. During the period when the DUT is disconnected from the test pins (i.e., while the DUT is being removed from the test motherboard), the test pins are continuously electrically isolated by an isolation device. The target chip can be any chip other than the DUT that needs to be tested, or it can be the DUT itself; specific limitations are not specified here.

[0070] Without using isolation devices to electrically isolate test pins, it's impossible to ensure that the power or signal pins of the chip under test (DUT) are at zero level or that other systems are in a high-impedance state during DUT replacement. This can have destructive effects on the DUT or the test board (e.g., leakage current can damage the DUT or cause abnormal test results). The isolation system for power and signals includes, but is not limited to: controlling power devices (such as PMIC / DCDC / LDO, etc.) to shut off power output; using switching devices (such as MOSFETs / relays, etc.) to disconnect power or signals; configuring the pins of devices connected to the DUT with signals to a high-impedance state; and powering down devices connected to the DUT with signals.

[0071] In the embodiments of this application, the testing chip mentioned in the foregoing embodiments can be a processor. Optionally, the processor can be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor can integrate one or a combination of several of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), and a modem. The CPU mainly handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the displayed content; and the modem is used for wireless communication. It is understood that the modem can also be implemented separately as a communication chip, without being integrated into the processor. For example, the testing chip can be an AP processor. Additionally, the test system can also include a memory that stores program code. When the program code is executed by the processor, it can perform the aforementioned methods. The memory can include Random Access Memory (RAM) or Read-Only Memory (ROM). The memory can be used to store instructions, programs, code, code sets, or instruction sets. The memory may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for implementing at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the various method embodiments described below, etc.

[0072] Please see Figure 16 The diagram shows a structural block diagram of a testing device 1600 provided in an embodiment of this application. The device may include a processing unit 1601 and an isolation unit 1602.

[0073] The processing unit 1601 is used to test the chip under test through the signal pin when the signal terminal of the chip under test is connected to the signal pin.

[0074] The isolation unit 1602 is used to trigger the isolation device to perform electrical isolation operation on the signal pin when the test is completed, and to control the test chip to remain powered on when the chip under test is disconnected from the signal pin.

[0075] Furthermore, the test system also includes a power supply, and the test pin also includes a power supply pin. The isolation unit 1602 is also used to trigger the isolation device to perform electrical isolation operation on the power supply pin and the signal pin.

[0076] Furthermore, the test system also includes a power supply, and the test pin also includes a power supply pin. The isolation unit 1602 is also used to trigger the isolation device to perform electrical isolation operation on the signal pin, and to control the power supply to stop supplying power to the power supply pin.

[0077] Furthermore, the test pin also includes an auxiliary pin, which is used to connect the chip under test to a designated chip. The isolation unit 1602 is also used to trigger the isolation device to perform electrical isolation operations on both the signal pin and the auxiliary pin. Specifically, the isolation unit 1602 is also used to determine whether a designated port of the designated chip can be switched to a low level or a high impedance state; if it cannot be switched to a low level or a high impedance state, the isolation device is triggered to perform electrical isolation operations on both the signal pin and the auxiliary pin; if it can be switched to a low level or a high impedance state, the isolation device is triggered to perform electrical isolation operations on the signal pin and to trigger the designated port of the designated chip to switch to a low level or a high impedance state. The electrical isolation operation includes setting to a low level or a high impedance state.

[0078] Furthermore, the testing system also includes: a test motherboard and a gripping device, the gripping device being connected to the chip under test, the test pins being disposed on the test motherboard, and the isolation unit 1602 being used to trigger the isolation device to perform electrical isolation operation on the signal pins; and to send a specified instruction to the gripping device, the specified instruction being used to trigger the gripping device to remove the chip under test from the test motherboard, so as to disconnect the connection between the test pins and the chip under test.

[0079] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the above-described device and module can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0080] In the several embodiments provided in this application, the coupling between modules can be electrical, mechanical, or other forms of coupling.

[0081] Furthermore, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0082] Please refer to Figure 17 This diagram illustrates a structural block diagram of a computer-readable storage medium provided in an embodiment of this application. The computer-readable medium 1700 stores program code that can be called by a processor to execute the methods described in the above method embodiments.

[0083] The computer-readable storage medium 1700 may be an electronic memory such as flash memory, EEPROM (Electrically Erasable Programmable Read-Only Memory), EPROM, hard disk, or ROM. Optionally, the computer-readable storage medium 1700 includes a non-transitory computer-readable storage medium. The computer-readable storage medium 1700 has storage space for program code 1710 that performs any of the method steps described above. This program code can be read from or written to one or more computer program products. The program code 1710 may, for example, be compressed in a suitable form.

[0084] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A testing method, characterized in that, A test chip is used in a test system, the test system further including an isolation device and test pins, the test chip is connected to the isolation device, the isolation device is connected to the test pins, the test pins including signal pins, and the method includes: With the signal terminal of the chip under test connected to the signal pin, the chip under test is tested through the signal pin; When the test is completed, the isolation device is triggered to perform electrical isolation operation on the signal pin. When the chip under test is disconnected from the test pin, the chip under test is controlled to remain powered on and the isolation device is kept performing electrical isolation operation on the signal pin. The electrical isolation operation on the signal pin includes setting the signal pin to a low level or a high impedance state.

2. The method according to claim 1, characterized in that, The test system also includes a power supply, and the test pins also include power supply pins. Triggering the isolation device to perform electrical isolation on the signal pins includes: The isolation device is triggered to perform electrical isolation operation on the power supply pin and the signal pin.

3. The method according to claim 1, characterized in that, The test system also includes a power supply, and the test pins also include power supply pins. Triggering the isolation device to perform electrical isolation on the signal pins includes: The isolation device is triggered to perform electrical isolation on the signal pin, and the power supply is controlled to stop supplying power to the power supply pin.

4. The method according to claim 1, characterized in that, The test pin also includes an auxiliary pin, which is used to connect the chip under test to a designated chip, and the designated chip is used to work with the chip under test to complete a designated test task. The step of triggering the isolation device to perform electrical isolation operation on the signal pin includes: The isolation device is triggered to perform electrical isolation operations on both the signal pin and the auxiliary pin.

5. The method according to claim 4, characterized in that, The designated port of the designated chip is connected to the auxiliary pin, and the triggering of the isolation device to perform electrical isolation operation on both the signal pin and the auxiliary pin includes: Determine whether a specified port of the specified chip can be switched to a low level or a high impedance state; If it cannot be switched to a low level or a high impedance state, the isolation device is triggered to perform electrical isolation operation on both the signal pin and the auxiliary pin.

6. The method according to claim 5, characterized in that, Also includes: If it can be switched to a low level or a high impedance state, the isolation device is triggered to perform an electrical isolation operation on the signal pin, and the designated port of the designated chip is triggered to switch to a low level or a high impedance state.

7. The method according to claim 1, characterized in that, The testing system further includes: a test motherboard and a gripping device, the gripping device being connected to the chip under test, the test pins being disposed on the test motherboard, and the chip under test being located on the test motherboard when connected to the test pins; triggering the isolation device to perform electrical isolation operation on the signal pins includes: The isolation device is triggered to perform an electrical isolation operation on the signal pin; A specified instruction is sent to the gripping device, which triggers the gripping device to remove the chip under test from the test motherboard to disconnect the connection between the test pin and the chip under test.

8. A testing device, characterized in that, A test chip is used in a test system, the test system further including an isolation device and test pins. The test chip is connected to the isolation device, and the isolation device is connected to the test pins. The test pins include signal pins. The device includes: The processing unit is used to test the chip under test through the signal pin when the signal terminal of the chip under test is connected to the signal pin. An isolation unit is used to trigger the isolation device to perform an electrical isolation operation on the signal pin when the test is completed, and to control the test chip to remain powered on and maintain the isolation device performing an electrical isolation operation on the signal pin when the chip under test is disconnected from the signal pin. The electrical isolation operation on the signal pin includes setting the signal pin to a low level or a high impedance state.

9. A testing system, characterized in that, include: An isolation device, a test chip, and test pins are provided, wherein the test chip is connected to the isolation device, the isolation device is connected to the test pins, and the test pins include signal pins; the test chip is used to perform the method described in any one of claims 1-7.

10. A computer-readable medium, characterized in that, The computer-readable medium stores processor-executable program code, which, when executed by the processor, causes the processor to perform the method according to any one of claims 1-7.

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