Test key structure and method for manufacturing the same

Abstract

The present invention discloses a test key structure and a manufacturing method thereof. The test key structure is located in a dicing lane of a wafer and includes a substrate, a dielectric layer, a metal layer, a first via window, a second via window, a shielding layer, a first pad, and a second pad. The dielectric layer is disposed on the substrate. The metal layer is disposed in the dielectric layer. The first via window and the second via window are disposed in the dielectric layer and are electrically connected to the metal layer respectively. The shielding layer is disposed on the dielectric layer and is directly above a part of the metal layer. The first pad and the second pad are disposed on the dielectric layer and are electrically connected to the first via window and the second via window respectively.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a test key structure and a method for manufacturing the same. Background Art

[0002] In the back-end manufacturing process of semiconductor devices, a chip area is protected by a protective layer to prevent the atmosphere from corroding the metal layer in the chip area. However, although some types of protective layers (such as polyimide protective layers) have good ability to block the atmosphere, such protective layers will adhere to the cutting blade during chip cutting, resulting in contamination in subsequent cutting manufacturing processes. The current solution is to remove the protective layer in the dicing lane to prevent the protective layer from adhering to the cutting blade during chip cutting.

[0003] However, when removing the protective layer in the dicing lane by an etching process performed on the chip area (such as a laser fuse region), in addition to removing the protective layer, the inter-metal dielectric (IMD) in the dicing lane is also removed, exposing the test key located in the dicing lane. As a result, the test key is corroded by the atmosphere, leading to abnormal testing. Summary of the Invention

[0004] The present invention provides a test key structure and a method for manufacturing the same, which can effectively prevent the metal layer in the test key structure from being corroded by the atmosphere, thereby improving the testability of the test key structure.

[0005] The present invention proposes a test key structure located in the dicing lane of a wafer, and includes a substrate, a dielectric layer, a metal layer, a first via, a second via, a shielding layer, a first pad, and a second pad. The dielectric layer is disposed on the substrate. The metal layer is disposed in the dielectric layer. The first via and the second via are disposed in the dielectric layer and are respectively electrically connected to the metal layer. The shielding layer is disposed on the dielectric layer and is located directly above a part of the metal layer. The first pad and the second pad are disposed on the dielectric layer and are respectively electrically connected to the first via and the second via.

[0006] According to an embodiment of the present invention, in the above test key structure, the first via, the second via, and the shielding layer may be derived from the same layer of conductor material layer.

[0007] According to an embodiment of the present invention, in the above-described test key structure, the dielectric layer may include a first upper surface, a second upper surface, and a third upper surface. The first upper surface and the second upper surface may be higher than the third upper surface. The first pad and the second pad may be located on the first upper surface and the second upper surface, respectively. The shielding layer may be located on the third upper surface.

[0008] According to an embodiment of the present invention, in the above-described test key structure, the top surfaces of the first via, the second via, and the shielding layer may be at the same height. The bottom surface of the first via and the bottom surface of the second via may be lower than the bottom surface of the shielding layer.

[0009] According to an embodiment of the present invention, in the above-described test key structure, slits may be formed in the dielectric layer between the shielding layer and the first pad and in the dielectric layer between the shielding layer and the second pad.

[0010] According to an embodiment of the present invention, in the above-described test key structure, the line width of the metal layer directly below the slit may be greater than the line width of the metal layer directly below the shielding layer.

[0011] The present invention provides a method for manufacturing a test key structure, where the test key structure is located in the scribe line of a wafer. The method for manufacturing the test key structure may include the following steps. Provide a substrate. Form a dielectric layer on the substrate. Form a metal layer in the dielectric layer. Form a first via and a second via in the dielectric layer. The first via and the second via are electrically connected to the metal layer respectively. Form a shielding layer on the dielectric layer. The shielding layer is located directly above a part of the metal layer. Form a first pad and a second pad on the dielectric layer. The first pad and the second pad are electrically connected to the first via and the second via respectively.

[0012] According to an embodiment of the present invention, in the above-described method for manufacturing a test key structure, the method for forming the first via, the second via, and the shielding layer may include the following steps. Form a first opening, a second opening, and a third opening in the dielectric layer. The depth of the third opening may be less than the depth of the first opening and the depth of the second opening. Form a conductor material layer filling the first opening, the second opening, and the third opening. Remove the conductor material layer located outside the first opening, outside the second opening, and outside the third opening.

[0013] According to an embodiment of the present invention, in the above-described method for manufacturing a test key structure, the method for removing the conductor material layer located outside the first opening, outside the second opening, and outside the third opening is, for example, chemical mechanical polishing.

[0014] According to an embodiment of the present invention, in the manufacturing method of the above test key structure, the following steps may further be included. A protective layer covering the first pad and the second pad is formed on the dielectric layer. The protective layer located in the scribe lane and the partial dielectric layer not covered by the masking layer, the first pad, and the second pad are removed, and slits are formed in the dielectric layer between the masking layer and the first pad and in the dielectric layer between the masking layer and the second pad.

[0015] Based on the above, in the test key structure and its manufacturing method proposed by the present invention, since the masking layer is located directly above a part of the metal layer, the metal layer directly below the masking layer can be prevented from being exposed to the atmosphere, thereby significantly reducing the area of the metal layer exposed to the atmosphere. In this way, the metal layer in the test key structure can be effectively prevented from being corroded by the atmosphere, and thus the test ability of the test key structure can be improved.

[0016] To make the above features and advantages of the present invention more obvious and understandable, specific embodiments are hereinafter given and detailed descriptions are made in conjunction with the accompanying drawings as follows. Brief Description of the Drawings

[0017] Figure 1 Is a top view of a test key structure according to an embodiment of the present invention;

[0018] Figures 2A to 2F Is a manufacturing process cross-sectional view of the test key structure along the I-I' section line in Figure 1

[0019] Symbol Description

[0020] 10: Test key structure

[0021] 100: Substrate

[0022] 102: Dielectric layer

[0023] 104: Metal layer

[0024] 106: Patterning photoresist layer

[0025] 108: Conductor material layer

[0026] 108a, 108b: Via window

[0027] 108c: Masking layer

[0028] 110, 112: Pad

[0029] 114: Dielectric layer

[0030] 116: Protective layer

[0031] BS1~BS3: Bottom surface

[0032] D1~D3: Depth​

[0033] OP1 to OP3: Opening

[0034] S1 to S3: Upper surface

[0035] SL: Scribing lane

[0036] SS: Slit

[0037] TS1 to TS3: Top surface

[0038] W1 to W6: Width

[0039] W7, W8: Line width Detailed implementation manners

[0040] Figure 1 It is a top view of a test key structure according to an embodiment of the present invention. Figures 2A to 2F It is along Figure 1 A manufacturing process cross-sectional view of the test key structure along the I-I' section line in Figure 1 In Figure 2F Some components in Figure 1 are omitted to clearly describe the configuration relationship between the components in

[0041] Please refer to Figure 2A to provide a substrate 100. The substrate 100 can be a semiconductor substrate, such as a silicon substrate. In some embodiments, according to product requirements, the substrate 100 in the scribing lane SL may further include a metal interconnect structure and / or active components (such as, metal-oxide-semiconductor field-effect transistor (MOSFET)) and other structures (not shown).

[0042] Next, a dielectric layer 102 is formed on the substrate 100. In some embodiments, the dielectric layer 102 can be a multi-layer structure. The material of the dielectric layer 102 can be silicon oxide, silicon nitride, silicon carbonitride, or a combination thereof. Then, a metal layer 104 is formed in the dielectric layer 102. In this embodiment, as Figure 1 shown, the top view shape of the metal layer 104 can include a linear part and an S-shaped part, but the present invention is not limited thereto. In other embodiments, the top view shape of the metal layer 104 can be linear, curved, or a combination thereof. The material of the metal layer 104 is, for example, a metal such as copper. In addition, the formation methods of the dielectric layer 102 and the metal layer 104 include deposition processes, photolithography processes, etching processes, and / or damascene processes and other manufacturing processes. In addition, according to product requirements, the dielectric layer 102 under the metal layer 104 may further include a required metal interconnect structure (not shown).

[0043] Next, a patterned photoresist layer 106 can be formed on the dielectric layer 102. The patterned photoresist layer 106 can expose a part of the dielectric layer 102. The patterned photoresist layer 106 can be formed by a photolithography manufacturing process.

[0044] Please refer to Figure 2B , the patterned photoresist layer 106 can be used as a mask to remove a part of the dielectric layer 102, and openings OP1, OP2, and OP3 are formed in the dielectric layer 102. The opening OP3 can be located between the opening OP1 and the opening OP2. The openings OP1, OP2, and OP3 can be located above the metal layer 104. In addition, the openings OP1 and OP2 can respectively expose a part of the metal layer 104. The width W3 of OP3 can be greater than the width W1 of the opening OP1 and the width W2 of the opening OP2. Due to the influence of the etching loading effect, when removing a part of the dielectric layer 102 by an etching manufacturing process, the etching speed of a large area is slower, so the depth D3 of the opening OP3 can be less than the depth D1 of the opening OP1 and the depth D2 of the opening OP2. The method for removing a part of the dielectric layer 102 is, for example, a dry etching method.

[0045] In addition, after the openings OP1, OP2, and OP3 are formed, the dielectric layer 102 can include an upper surface S1, an upper surface S2, and an upper surface S3. The upper surface S1 and the upper surface S2 can be higher than the upper surface S3.

[0046] Please refer to Figure 2C , the patterned photoresist layer 106 can be removed. The method for removing the patterned photoresist layer 170 is, for example, a dry stripping method or a wet stripping method.

[0047] Then, a conductor material layer 108 filling the openings OP1, OP2, and OP3 can be formed. The material of the conductor material layer 108 is, for example, a metal such as tungsten. The method for forming the conductor material layer 108 is, for example, a chemical vapor deposition method.

[0048] Please refer to Figure 2D, the conductor material layer 108 located outside the opening OP1, outside the opening OP2, and outside the opening OP3 can be removed, and via holes 108a, via holes 108b, and a shielding layer 108c are respectively formed in the opening OP1, the opening OP2, and the opening OP3. Thus, via holes 108a and via holes 108b can be formed in the dielectric layer 102, and the shielding layer 108c can be formed on the dielectric layer 102. The via holes 108a and the via holes 108b are respectively electrically connected to the metal layer 104. The shielding layer 108c is located directly above a part of the metal layer 104. The shielding layer 108c can be located between the via holes 108a and the via holes 108b. The shielding layer 108c can be located on the upper surface S3. A method for removing the conductor material layer 108 located outside the opening OP1, outside the opening OP2, and outside the opening OP3 is, for example, chemical mechanical polishing.

[0049] The via holes 108a, the via holes 108b, and the shielding layer 108c can be derived from the same conductor material layer 108, that is, the via holes 108a, the via holes 108b, and the shielding layer 108c can be formed by the same conductor material layer 108. In addition, the top surface TS1 of the via hole 108a, the top surface TS2 of the via hole 108b, and the top surface TS3 of the shielding layer 108c can be at the same height. The bottom surface BS1 of the via hole 108a and the bottom surface BS2 of the via hole 108b can be lower than the bottom surface BS3 of the shielding layer 108c. Additionally, the width W6 of the shielding layer 108c can be greater than the width W4 of the via hole 108a and the width W5 of the via hole 108b.

[0050] Please refer to Figure 2E , pads 110 and pads 112 are formed on the dielectric layer 102. The pads 110 and the pads 112 are respectively electrically connected to the via holes 108a and the via holes 108b. The pads 110 and the pads 112 can be respectively located on the upper surface S1 and the upper surface S2. The materials of the pads 110 and the pads 112 are, for example, metals such as aluminum. A method for forming the pads 110 and the pads 112 is, for example, first forming a pad material layer on the dielectric layer 102 through a deposition manufacturing process, and then patterning the pad material layer through a photolithography manufacturing process and an etching manufacturing process, but the present invention is not limited thereto.

[0051] Next, a dielectric layer 114 covering the pads 110 and the pads 112 can be formed on the dielectric layer 102. The material of the dielectric layer 114 is, for example, silicon oxide. A method for forming the dielectric layer 114 is, for example, chemical vapor deposition.

[0052] Then, a protective layer 116 covering the pads 110 and the pads 112 can be formed on the dielectric layer 102. In this embodiment, the protective layer 116 can be formed on the dielectric layer 114. The material of the protective layer 116 is, for example, polyimide. A method for forming the protective layer 116 is, for example, spin coating.

[0053] Please refer to Figure 2F , the protective layer 116, the dielectric layer 114, and the partial dielectric layer 102 that are not covered by the shielding layer 108c, the pads 110, and the pads 112 located in the scribe lane SL can be removed, and slits SS are formed in the dielectric layer 102 between the shielding layer 108c and the pad 110 and in the dielectric layer 102 between the shielding layer 108c and the pad 112.

[0054] In some embodiments, the protective layer 116, the dielectric layer 114, and the partial dielectric layer 102 that are not covered by the shielding layer 108c, the pads 110, and the pads 112 located in the scribe lane SL can be simultaneously removed by an etching process (such as a dry etching process) performed on a chip region (such as a laser fuse region (not shown)). In the above etching process, since the shielding layer 108c can serve as an etching stop layer, the metal layer 104 directly under the shielding layer 108c can be covered by the shielding layer 108c and the dielectric layer 102 directly under the shielding layer 108c, so as to greatly reduce the area of the metal layer 104 exposed to the atmosphere. On the other hand, in the above etching process, the pads 110 and the pads 112 can also serve as etching stop layers, whereby the pads 110, the pads 112, and the dielectric layer 102 directly under the pads 110 and the pads 112 can cover a part of the metal layer 104 to reduce the area of the metal layer 104 exposed to the atmosphere.

[0055] In some embodiments, the slit SS can expose a part of the metal layer 104. In addition, as Figure 1 shown, the line width W7 of the metal layer 104 directly under the slit SS can be greater than the line width W8 of the metal layer 104 directly under the shielding layer 108c. Thus, even if the slit SS exposes a part of the metal layer 104, since the exposed metal layer 104 in the slit SS has a larger line width W7, the adverse effects caused by the exposure of the metal layer 104 directly under the slit SS to the atmosphere can be reduced.

[0056] Hereinafter, through Figure 1 and Figure 2F the test key structure 10 of the above embodiment will be described. In addition, although the formation method of the test key structure 10 is described by taking the above method as an example, the present invention is not limited thereto.

[0057] Please refer to Figure 1 and Figure 2F, the test key structure 10 can be located in the saw street SL of the wafer. The test key structure 10 can be used for wafer acceptance test (WAT), stress migration (SM) test or electromigration (EM) test. The test key structure 10 includes a substrate 100, a dielectric layer 102, a metal layer 104, via holes 108a, via holes 108b, a masking layer 108c, pads 110 and pads 112. The dielectric layer 102 is disposed on the substrate 100. The metal layer 104 is disposed in the dielectric layer 102. The via holes 108a and the via holes 108b are disposed in the dielectric layer 102 and are electrically connected to the metal layer 104 respectively. The masking layer 108c is disposed on the dielectric layer 102 and is directly above a part of the metal layer 104. The masking layer 108c can be located between the via hole 108a and the via hole 108b. The via hole 108a, the via hole 108b and the masking layer 108c can be derived from the same layer of conductor material layer 108. The top surface TS1 of the via hole 108a, the top surface TS2 of the via hole 108b and the top surface TS3 of the masking layer 108c can be at the same height. The bottom surface BS1 of the via hole 108a and the bottom surface BS2 of the via hole 108b can be lower than the bottom surface BS3 of the masking layer 108c. The width W6 of the masking layer 108c can be greater than the width W4 of the via hole 108a and the width W5 of the via hole 108b. The pads 110 and the pads 112 are disposed on the dielectric layer 102 and are electrically connected to the via hole 108a and the via hole 108b respectively. In some embodiments, slits SS can be formed in the dielectric layer 102 between the masking layer 108c and the pad 110 and in the dielectric layer 102 between the masking layer 108c and the pad 112. The line width W7 of the metal layer 104 directly below the slit SS can be greater than the line width W8 of the metal layer 104 directly below the masking layer 108c( Figure 1 ).

[0058] In addition, the dielectric layer 102 can include an upper surface S1, an upper surface S2 and an upper surface S3. The upper surface S1 and the upper surface S2 can be higher than the upper surface S3. The first pad and the second pad can be located on the first upper surface and the second upper surface respectively. The pads 110 and the pads 112 can be located on the upper surface S1 and the upper surface S2 respectively. The masking layer 108c can be located on the upper surface S3.

[0059] In addition, the materials, setting methods, forming methods and functions of each component in the test key structure 10 have been described in detail in the above embodiments and will not be described herein again.

[0060] As can be seen from the above embodiments, in the test key structure 10 and its manufacturing method, since the shielding layer 108c is located directly above a part of the metal layer 104, the metal layer 104 directly below the shielding layer 108c can be prevented from being exposed to the atmosphere, thereby greatly reducing the area of the metal layer 104 exposed to the atmosphere. In this way, the metal layer 104 in the test key structure 10 can be effectively prevented from being corroded by the atmosphere, and thus the test ability of the test key structure 10 can be improved.

[0061] In summary, in the test key structure and its manufacturing method of the above embodiments, since the shielding layer can prevent the test key structure from being exposed to the atmosphere, the metal layer in the test key structure can be prevented from being corroded by the atmosphere, and thus the test ability of the test key structure can be improved.

[0062] Although the present invention is disclosed in combination with the above embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field to which the present invention pertains can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims

1. A test key structure is located in the dicing street of a wafer, and is characterized in that, The test key structure includes: a substrate; a dielectric layer disposed on the substrate; a metal layer disposed in the dielectric layer, wherein a metal interconnect structure is included in the dielectric layer below the metal layer; a first via and a second via disposed in the dielectric layer and electrically connected to the metal layer respectively; a shielding layer disposed on the dielectric layer and directly above a part of the metal layer; and a first pad and a second pad disposed on the dielectric layer and electrically connected to the first via and the second via respectively.

2. The test key structure according to claim 1, wherein the first via, the second via and the shielding layer are derived from the same layer of conductor material.

3. The test key structure according to claim 1, wherein the dielectric layer includes a first upper surface, a second upper surface and a third upper surface, wherein the first upper surface and the second upper surface are higher than the third upper surface, the first pad and the second pad are respectively located on the first upper surface and the second upper surface, and the shielding layer is located on the third upper surface.

4. The test key structure according to claim 1, wherein the top surfaces of the first via, the second via and the shielding layer are at the same height, and the bottom surfaces of the first via and the second via are lower than the bottom surface of the shielding layer.

5. The test key structure according to claim 1, wherein slits are provided in the dielectric layer between the shielding layer and the first pad and in the dielectric layer between the shielding layer and the second pad.

6. The test key structure according to claim 5, wherein the line width of the metal layer directly below the slit is greater than the line width of the metal layer directly below the shielding layer.

7. A method for manufacturing a test key structure, wherein the test key structure is located in a dicing channel of a wafer, and the method for manufacturing the test key structure includes: providing a substrate; forming a dielectric layer on the substrate; forming a metal layer in the dielectric layer, wherein a metal interconnect structure is included in the dielectric layer below the metal layer; forming a first via and a second via in the dielectric layer, wherein the first via and the second via are electrically connected to the metal layer respectively; forming a shielding layer on the dielectric layer, wherein the shielding layer is directly above a part of the metal layer; and forming a first pad and a second pad on the dielectric layer, wherein the first pad and the second pad are electrically connected to the first via and the second via respectively.

8. The method for manufacturing a test key structure according to claim 7, wherein the method for forming the first via, the second via and the shielding layer includes: forming a first opening, a second opening and a third opening in the dielectric layer, wherein the depth of the third opening is less than the depth of the first opening and the depth of the second opening; forming a conductor material layer filling the first opening, the second opening and the third opening; and removing the conductor material layer located outside the first opening, outside the second opening and outside the third opening.

9. The manufacturing method of the test key structure as claimed in claim 8, wherein the method for removing the conductor material layer located outside the first opening, outside the second opening, and outside the third opening includes chemical mechanical polishing.

10. The manufacturing method of the test key structure as claimed in claim 7 further includes: forming a protective layer covering the first pad and the second pad on the dielectric layer; and removing the protective layer located in the dicing lane and a part of the dielectric layer not covered by the shielding layer, the first pad, and the second pad, and forming slits in the dielectric layer between the shielding layer and the first pad and in the dielectric layer between the shielding layer and the second pad.

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