Fan-out double-sided packaging structure and method for preparing the fan-out double-sided packaging structure

Abstract

The embodiment of the present invention provides a fan-out double-sided packaging structure and a method for preparing the fan-out double-sided packaging structure, which relates to the field of semiconductor packaging technology. The fan-out double-sided packaging structure includes a first carrier, a second carrier, a first chip, a second chip, a first plastic package, a third chip, a second plastic package and a wiring combination layer. The packaging is achieved by the first carrier and the second carrier. Compared with the single-wafer packaging structure, its wiring density is greater, which is conducive to achieving higher density wiring requirements, thereby increasing the number of stacking, and the first carrier and the second carrier respectively play a supporting role, thereby effectively solving the delamination problem between the plastic package and the chip surface and the delamination problem between the plastic package and the substrate. In addition, the electrical connection of the second chip is achieved through the first conductive wire and the second conductive wire, and the wire stacking of the chip placement direction on the same side is achieved, ensuring the diversity of mounting methods and wiring methods.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging technology, and in particular to a fan-out double-sided packaging structure and a method for preparing the fan-out double-sided packaging structure. Background Art

[0002] With the rapid development of the semiconductor industry, fan-out wafer level package (FOWLP) packaging structure is widely used in the semiconductor industry. Generally, a single chip is cut from a wafer and then packaged on a carrier wafer. The main advantages are high-density integration, small package product size, superior product performance, fast signal transmission frequency, etc. The fan-out technology is mainly to achieve multi-pin output and smaller output pin spacing. The traditional fan-out packaging product structure is mainly formed on the front and back sides of the same substrate. Since there are multiple packaging materials in the double-sided packaging structure formed on the substrate, and the materials used for different packaging bodies are different, the CTE coefficients between the materials are different. In the reliability process, the product has warping problems, which easily lead to delamination problems between the plastic package and the chip surface, and delamination problems between the plastic package and the substrate. At the same time, the plastic package is performed on both sides of the same substrate, and the wiring density of the substrate is limited, and it is impossible to achieve higher density wiring requirements. In addition, the existing double-sided packaging structure cannot achieve wire stacking in the same side chip placement direction, which greatly limits the chip mounting method and the wiring method of the circuit layer. Summary of the invention

[0003] The objects of the present invention include, for example, providing a fan-out double-sided packaging structure and a method for preparing a fan-out double-sided packaging structure, which can improve the warping phenomenon, alleviate the delamination problem, and at the same time improve the wiring density, realize higher density wiring requirements, and can realize wire stacking, thereby improving the diversity of chip mounting methods and the diversity of circuit layer wiring methods, and has a wider applicability.

[0004] The embodiments of the present invention can be implemented as follows:

[0005] In a first aspect, the present invention provides a fan-out double-sided packaging structure, comprising:

[0006] A first carrier having a first circuit layer;

[0007] A second carrier attached to a side surface of the first carrier and provided with a second circuit layer, and a recess penetrating to the second carrier is provided on the first carrier;

[0008] A first chip mounted on the other side surface of the first carrier and electrically connected to the first circuit layer;

[0009] A second chip mounted on the second carrier in the recess;

[0010] A first plastic package body disposed on the first carrier and in the clearance groove and covering the first chip and the second chip;

[0011] A third chip mounted on a surface of the second carrier away from the first chip and electrically connected to the second circuit layer;

[0012] A second plastic package body disposed on the second carrier and covering the third chip;

[0013] and, a wiring assembly layer disposed on a surface of the second plastic package body on a side away from the first chip;

[0014] The first circuit layer is electrically connected to the second circuit layer, the second chip is mounted in the recess, and the second chip is provided with a first conductive wire and a second conductive wire, the first conductive wire is connected to the first carrier or the second carrier so that the first conductive wire is electrically connected to the first circuit layer or the second circuit layer, and the second conductive wire is electrically connected to the second carrier so that the second conductive wire is electrically connected to the second circuit layer.

[0015] In an optional embodiment, a conductive column is further provided in the second plastic package, and the conductive column is respectively provided on at least two sides of the third chip, and one end of the conductive column extends to the second carrier and is electrically connected to the second circuit layer, and the other end of the conductive column extends to the wiring combination layer and is electrically connected to the wiring combination layer.

[0016] In an optional embodiment, the wiring combination layer includes a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer and a solder ball, the first dielectric layer covers the surface of the second plastic package, the first metal layer is arranged in the first dielectric layer and is electrically connected to the conductive column, the second dielectric layer covers the surface of the first dielectric layer, the second metal layer is arranged in the second dielectric layer and is electrically connected to the first metal layer, and the solder ball is arranged on a side of the second dielectric layer away from the second plastic package and is electrically connected to the second metal layer.

[0017] In an optional embodiment, a first wire bonding pad is provided on the surface of the first carrier, the first wire bonding pad is located between the first chip and the second chip and is electrically connected to the first circuit layer, a second wire bonding pad is provided on the surface of the second carrier, the second wire bonding pad is electrically connected to the second circuit layer, a wire bonding bump is provided on the side of the second chip away from the second carrier, one end of the first conductive wire is connected to the first wire bonding pad, and the other end is connected to the wire bonding bump, one end of the second conductive wire is connected to the second wire bonding pad, and the other end is connected to the wire bonding bump, so that the second chip is electrically connected to the first circuit layer and the second circuit layer at the same time.

[0018] In an optional embodiment, a surface of the first plastic package body on one side away from the second carrier is flush with a surface of the first chip on one side away from the first carrier, and the first chip is exposed from the first plastic package body.

[0019] In an optional embodiment, a fourth chip is also mounted on the second carrier in the give way groove, the fourth chip is located between the first carrier and the second chip, and the fourth chip is electrically connected to the second circuit layer, and the first conductive line is bridged over the fourth chip to achieve electromagnetic shielding for the fourth chip.

[0020] In an optional embodiment, a first wire bonding pad and a second wire bonding pad are provided on the surface of the second carrier, the first wire bonding pad and the second wire bonding pad are respectively provided on both sides of the second chip, and a wire bonding bump is provided on the side of the second chip away from the second carrier, the first conductive wire simultaneously connects the wire bonding bump and the first wire bonding pad, the second conductive wire simultaneously connects the wire bonding bump and the second wire bonding pad, a fifth chip is also provided on the edge of one side of the first carrier close to the second chip, the fifth chip is electrically connected to the first circuit layer, and the fifth chip partially extends out of the first carrier and is electrically connected to the second circuit layer.

[0021] In an optional embodiment, an electrical support column electrically connected to the second circuit layer is provided on the second carrier, and the electrical support column is correspondingly engaged with the portion of the fifth chip extending out of the first carrier for supporting the fifth chip, and the fifth chip is electrically connected to the second circuit layer through the electrical support column.

[0022] In an optional embodiment, a circuit pad is provided on a surface of the first carrier away from the second carrier, and the circuit pad is electrically connected to the first circuit layer. A welding bump is provided on the first chip, and the welding bump is correspondingly bonded to the circuit pad so that the first chip is flipped on the first carrier.

[0023] In an optional embodiment, a filling groove is further provided on the first carrier, the filling groove is located below the first conductive line, and the first plastic package body extends into the filling groove.

[0024] In a second aspect, the present invention provides a method for preparing a fan-out double-sided packaging structure, which is used to prepare the fan-out double-sided packaging structure as described in any one of the aforementioned embodiments, and the preparation method comprises:

[0025] Laying the second carrier on one side surface of the first carrier;

[0026] A groove is formed on the first carrier to form a clearance groove which passes through to the second carrier;

[0027] Mounting a first chip on the surface of the other side of the first carrier;

[0028] Mounting a second chip on the second carrier in the recess;

[0029] Forming a first plastic package covering the first chip and the second chip on the first carrier and in the clearance groove;

[0030] Mounting a third chip on the surface of the second carrier away from the first chip;

[0031] forming a second plastic package covering the third chip on the second carrier;

[0032] forming a wiring assembly layer on a surface of the second plastic package body at a side away from the first chip;

[0033] Among them, the first carrier is provided with a first circuit layer, the second carrier is provided with a second circuit layer, the first chip is electrically connected to the first circuit layer, the second chip and the third chip are electrically connected to the second circuit layer, the first circuit layer is electrically connected to the second circuit layer, the second chip is installed in the give way groove, and the second chip is provided with a first conductive wire and a second conductive wire, the first conductive wire is connected to the first carrier or the second carrier so that the first conductive wire is electrically connected to the first circuit layer or the second circuit layer, and the second conductive wire is electrically connected to the second carrier so that the second conductive wire is electrically connected to the second circuit layer.

[0034] The beneficial effects of the embodiments of the present invention include, for example:

[0035] The present invention provides a fan-out double-sided packaging structure and a preparation method of the fan-out double-sided packaging structure. The structure is achieved by laminating a first carrier provided with a first circuit layer and a second carrier provided with a second circuit layer together, and providing a clearance groove penetrating to the second carrier on the first carrier, mounting a first chip on the first carrier, mounting a second chip in a second carrier in the clearance groove, and mounting a third chip on a side of the second carrier away from the first chip, thereby realizing a double-sided packaging structure, and realizing fan-out packaging by providing a wiring combination layer. The packaging is realized by the first carrier and the second carrier. Compared with a single-wafer packaging structure, the wiring density is greater, which is conducive to realizing a higher density wiring requirement, thereby increasing the number of stacking, and the first carrier and the second carrier respectively play a supporting role. Compared with a single-board structure, the problem of plastic packaging warping can be alleviated, thereby effectively solving the problem of stratification between the plastic packaging body and the chip surface and the problem of stratification between the plastic packaging body and the substrate. Furthermore, by forming the first conductive wire and the second conductive wire on the second chip through bonding, the electrical connection of the second chip is achieved through the first conductive wire and the second conductive wire, so that the first chip and the second chip on the same side can be presented in different mounting methods, and the bonding stacking in the placement direction of the chips on the same side is achieved, thereby ensuring the diversity of mounting methods and wiring methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 A schematic diagram of a fan-out double-sided packaging structure provided by a first embodiment of the present invention;

[0038] Figures 2 to 8 A process flow chart of a method for preparing a fan-out double-sided packaging structure provided by the first embodiment of the present invention;

[0039] Fig. 9 A schematic diagram of a fan-out double-sided packaging structure provided by a second embodiment of the present invention;

[0040] Fig.10 A schematic diagram of a fan-out double-sided packaging structure provided by a third embodiment of the present invention;

[0041] Fig.11 A schematic diagram of a fan-out double-sided packaging structure provided by a fourth embodiment of the present invention;

[0042] Fig.12 A schematic diagram of a fan-out double-sided packaging structure provided in accordance with a fifth embodiment of the present invention;

[0043] Fig.13 A schematic diagram of a fan-out double-sided packaging structure provided in accordance with a sixth embodiment of the present invention.

[0044] Icon: 100-fan-out double-sided packaging structure; 110-first carrier; 111-first circuit layer; 113-give way groove; 115-first wire bonding pad; 117-filling groove; 120-second carrier; 121-second circuit layer; 123-second wire bonding pad; 130-first chip; 140-second chip; 141-first conductive wire; 143-second conductive wire; 145-wire bonding bump; 150-first plastic package; 160-third chip; 170-second plastic package; 171-conductive column; 180-wiring combination layer; 181-first dielectric layer; 182-first metal layer; 183-second dielectric layer; 184-second metal layer; 185-solder ball; 190-fourth chip; 191-fifth chip; 193-electrical support column. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0046] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0048] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear to indicate an orientation or position relationship, they are based on the orientation or position relationship shown in the accompanying drawings, or are the orientation or position relationship in which the product of the invention is usually placed when used. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0049] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0050] As disclosed in the background technology, the existing double-sided packaging structure is packaged on both sides of the same substrate, and the wiring density of the substrate is limited, which cannot meet the wiring requirements of higher density, and is not conducive to increasing the number of chip packaging stacks. At the same time, the single-board double-sided packaging structure has a low support degree during plastic sealing, and there is a problem of delamination between the plastic sealing body and the chip surface, and between the plastic sealing body and the substrate. In addition, its heat dissipation effect is poor. At the same time, the existing double-sided packaging structure cannot achieve the reverse placement of the chip on the same side, which greatly limits the chip mounting method and the wiring method of the circuit layer.

[0051] In order to solve the above problems, the present invention provides a fan-out double-sided packaging structure and a preparation method thereof. It should be noted that the features in the embodiments of the present invention can be combined with each other without conflict.

[0052] First embodiment

[0053] See also Figure 1 This embodiment provides a fan-out double-sided packaging structure 100, which can improve the warping phenomenon, alleviate the delamination problem, and at the same time improve the wiring density, realize higher density wiring requirements, and can realize wire stacking, thereby improving the diversity of chip mounting methods and the diversity of circuit layer wiring methods, and has a wider applicability.

[0054] The fan-out double-sided packaging structure 100 provided in this embodiment includes a first carrier 110, a second carrier 120, a first chip 130, a second chip 140, a first plastic package 150, a third chip 160, a second plastic package 170 and a wiring assembly layer 180. The first carrier 110 is provided with a first circuit layer 111, the second carrier 120 is provided with a second circuit layer 121 and is attached to a side surface of the first carrier 110, and a recess 113 penetrating to the second carrier 120 is provided on the first carrier 110. The first chip 130 is mounted on the other side surface of the first carrier 110 and is electrically connected to the first circuit layer 111. The second chip 140 is mounted on the second carrier 120 in the recess 113. The first plastic package 150 is arranged on the first carrier 110 and in the recess 113, and covers the first chip 130 and the outside of the first chip 130. The third chip 160 is mounted on a side surface of the second carrier 120 away from the first chip 130, and is electrically connected to the second circuit layer 121. The second plastic package 170 is disposed on the second carrier 120 and covers the third chip 160. The wiring assembly layer 180 is disposed on a side surface of the second plastic package 170 away from the first chip 130, wherein the first circuit layer 111 is electrically connected to the second circuit layer 121, the second chip 140 is mounted in the recess 113, and the first conductive wire 141 and the second conductive wire 143 are disposed on the second chip 140, the first conductive wire 141 is connected to the first carrier 110 or the second carrier 120, so that the first conductive wire 141 is electrically connected to the first circuit layer 111 or the second circuit layer 121, and the second conductive wire 143 is electrically connected to the second carrier 120, so that the second conductive wire 143 is electrically connected to the second circuit layer 121.

[0055] In this embodiment, the first carrier 110 and the second carrier 120 are attached to each other, and the electrical connection between the first circuit layer 111 and the second circuit layer 121 is realized through the circuit pad, and the clearance groove 113 is an open groove, which extends to the edge of the second carrier 120. In actual preparation, the first carrier 110 and the second carrier 120 can be attached first, and then part of the first carrier 110 is cut off to form the clearance groove 113. By forming the clearance groove 113, the width of the first carrier 110 can be made smaller than the width of the second carrier 120. Preferably, the width of the first carrier 110 is half of the width of the second carrier 120 to ensure that there is enough mounting area to complete the mounting of the first chip 130 and the second chip 140.

[0056] In this embodiment, a conductive column 171 is further disposed in the second plastic package 170, and the conductive column 171 is respectively disposed on at least two sides of the third chip 160, and one end of the conductive column 171 extends to the second carrier 120 and is electrically connected to the second circuit layer 121, and the other end of the conductive column 171 extends to the wiring assembly layer 180 and is electrically connected to the wiring assembly layer 180. Specifically, a plurality of third chips 160 are disposed on the second carrier 120, and conductive columns 171 are disposed on both sides of each third chip 160. Preferably, there are two third chips 160, and the two third chips 160 are disposed at intervals.

[0057] It should be noted that, in this embodiment, the two third chips 160 are respectively arranged corresponding to the first chip 130 and the second chip 140, and the two third chips 160 are both flipped on the second carrier 120, and are electrically connected to the second circuit layer 121 through pad connection. At the same time, the conductive column 171 is also electrically connected to the second circuit layer 121 through pad connection.

[0058] In this embodiment, a circuit pad is provided on a surface of one side of the first carrier 110 away from the second carrier 120, and the circuit pad is electrically connected to the first circuit layer 111. A welding bump is provided on the first chip 130, and the welding bump is correspondingly joined to the circuit pad so that the first chip 130 is flipped on the first carrier 110, that is, the first chip 130 and the second chip 140 adopt opposite mounting methods. Of course, the first chip 130 can also be mounted upright here. The specific mounting method of the first chip 130 is not described in detail here.

[0059] The wiring assembly layer 180 includes a first dielectric layer 181, a first metal layer 182, a second dielectric layer 183, a second metal layer 184 and a solder ball 185. The first dielectric layer 181 covers the surface of the second plastic package 170, the first metal layer 182 is arranged in the first dielectric layer 181 and is electrically connected to the conductive column 171, the second dielectric layer 183 covers the surface of the first dielectric layer 181, the second metal layer 184 is arranged in the second dielectric layer 183 and is electrically connected to the first metal layer 182, and the solder ball 185 is arranged on the side of the second dielectric layer 183 away from the second plastic package 170 and is electrically connected to the second metal layer 184. Specifically, the first metal layer 182 is a wiring structure, which can be bonded to the end of the conductive column 171 away from the second carrier 120, and the second metal layer 184 is electrically connected to the first metal layer 182, and the solder ball 185 is electrically connected to the second metal layer 184, thereby realizing a fan-out packaging structure. It should be noted that the wiring method, electrical connection principle and preparation method of the wiring combination layer 180 here are consistent with the wiring layer of the conventional fan-out packaging structure, and will not be introduced in detail here.

[0060] In this embodiment, a first bonding pad 115 is disposed on the surface of the first carrier 110, the first bonding pad 115 is located between the first chip 130 and the second chip 140, and is electrically connected to the first circuit layer 111, a second bonding pad 123 is disposed on the surface of the second carrier 120, the second bonding pad 123 is electrically connected to the second circuit layer 121, a bonding bump 145 is disposed on the side of the second chip 140 away from the second carrier 120, one end of the first conductive wire 141 is connected to the first bonding pad 115, and the other end is connected to the bonding bump 145, one end of the second conductive wire 143 is connected to the second bonding pad 123, and the other end is connected to the bonding bump 145, so that the second chip 140 is electrically connected to the first circuit layer 111 and the second circuit layer 121 at the same time. Specifically, the first wire pad is arranged on the first carrier 110 near the edge of the second chip 140, and the wire bumps 145 are distributed on both side edges of the second chip 140, and there may be multiple wire bumps 145, and the first conductive wire 141 and the second conductive wire 143 are respectively connected to the wire bumps 145 located on both side edges, thereby realizing wire connection. Among them, the first conductive wire 141 and the second conductive wire 143 may also be multiple, and the first wire pad 115 and the second wire pad 123 may also correspond to multiple, thereby realizing multi-wire connection.

[0061] In this embodiment, the first conductive wire 141 is used to electrically connect the second chip 140 and the first circuit layer 111, and the second conductive wire 143 is used to electrically connect the second chip 140 and the second circuit layer 121, so that the wiring structure connected to the second chip 140 can be diversified, and the wiring of the second carrier 120 at the corresponding position of the second chip 140 can be reduced, so that the wiring on the second carrier 120 can be connected to more third chips 160, which helps to increase the number of third chips 160 stacked.

[0062] In this embodiment, the first conductive wire 141 and the second conductive wire 143 are both copper wires, and both adopt an arc-shaped wiring method, so that the first conductive wire 141 and the second conductive wire 143 can be closer to the side surface of the first plastic package 150 away from the second carrier 120. Compared with the conventional flip-chip structure, the use of the first conductive wire 141 and the second conductive wire 143 can make the heat generated by the chip quickly transfer to the surroundings and conduct it to the wiring combination layer 180, thereby improving the overall heat dissipation performance of the device.

[0063] In this embodiment, the first plastic package 150 entirely covers the first chip 130 and the second chip 140 , and the first chip 130 and the second chip 140 are completely covered inside the first plastic package 150 , so that the first plastic package 150 can achieve good protection for the first chip 130 and the second chip 140 .

[0064] This embodiment also provides a method for preparing a fan-out package structure, which is used to prepare the aforementioned fan-out package structure. The method comprises the following steps:

[0065] S1: attaching the second carrier 120 to one side surface of the first carrier 110 .

[0066] Specifically, see Figure 2 First, a first carrier 110 and a second carrier 120 that have been wired in advance are provided respectively, a first circuit layer 111 is provided on the first carrier 110, and a second circuit layer 121 is provided on the second carrier 120. The first carrier 110 and the second carrier 120 can both be made of glass, silicon oxide, metal and other materials, and are made after wiring is completed. When executing step S1, the first carrier 110 can be bonded to the second carrier 120, so that the back pad of the first carrier 110 is combined with the surface pad of the second carrier 120, and the welding combination can be achieved by using solder paste, adhesive or high temperature annealing welding of the pad.

[0067] S2: A groove is formed on the first carrier 110 to form a clearance groove 113 penetrating to the second carrier 120 .

[0068] Specifically, see Figure 3 The preset area on the first carrier 110, i.e. the chip mounting area, can be removed by etching or laser grooving, thereby forming a clearance groove 113 to expose the second carrier 120. When the clearance groove 113 is formed, the second carrier 120 plays a supporting role.

[0069] S3 : mounting the first chip 130 on the other side surface of the first carrier 110 .

[0070] Specifically, see Figure 4 After the preparation of the give way groove 113 is completed, the first chip 130 is mounted on the ungrooved area of ​​the first carrier 110. The first chip 130 can adopt a flip-chip structure and use the bottom pad to bond with the surface pad on the first carrier 110 to achieve electrical connection between the first chip 130 and the first circuit layer 111.

[0071] S4 : mounting the second chip 140 on the second carrier 120 in the clearance groove 113 .

[0072] For details, please refer to Figure 4, the second chip 140 is mounted on the surface of the second carrier 120 in the clearance groove 113, and the second chip 140 is mounted on the second carrier 120. The back of the second chip 140 can be attached to the second carrier 120 by adhesive, so that the wire bonding bumps 145 on the second chip 140 are set upward. Among them, step S3 and step S4 can be performed simultaneously, that is, the mounting action of the first chip 130 and the second chip 140 is completed at the same time.

[0073] After the mounting of the second chip 140 is completed, the first conductive wire 141 and the second conductive wire 143 are formed by wire bonding process, that is, the first conductive wire 141 and the second conductive wire 143 are arranged on the second chip 140, the first conductive wire 141 is connected to the first carrier 110, so that the first conductive wire 141 is electrically connected to the first circuit layer 111, and the second conductive wire 143 is electrically connected to the second carrier 120, so that the second conductive wire 143 is electrically connected to the second circuit layer 121. Thus, the second chip 140 is electrically connected to the first carrier 110 and the second carrier 120 at the same time, achieving better electrical connection characteristics.

[0074] S5 : forming a first plastic package 150 on the first carrier 110 and in the clearance groove 113 to cover the first chip 130 and the second chip 140 .

[0075] Specifically, see Figure 5 After the wire bonding is completed, a first plastic encapsulation body 150 is formed on the first carrier 110 and the second carrier 120 in the clearance groove 113 by using a plastic encapsulation process. The first plastic encapsulation body 150 can cover the first chip 130 and the second chip 140, thereby playing a good protective role. At the same time, the first plastic encapsulation body 150 can also cover the first conductive wire 141 and the second conductive wire 143 to protect the wire bonding structure.

[0076] S6 : Mounting the third chip 160 on the surface of the second carrier 120 away from the first chip 130 .

[0077] Specifically, see Figure 6 After forming the first plastic package 150, the package structure is flipped over, and then the third chip 160 is mounted on the second carrier 120. There are multiple third chips 160, which correspond to the first chip 130 and the second chip 140 respectively. The third chip 160 can be a flip chip, and is fixed on the second carrier 120 by a pad connection method, so that the third chip 160 is electrically connected to the second circuit layer 121.

[0078] S7 : forming a second plastic package 170 covering the third chip 160 on the second carrier 120 .

[0079] Specifically, see Figure 7After the third chip 160 is mounted, a second plastic package 170 is formed by a plastic packaging process. The second plastic package 170 is disposed on the second carrier 120 and covers the third chip 160 .

[0080] After forming the second plastic package 170, it is necessary to complete the preparation of the conductive pillar 171. Specifically, a laser grooving process can be used to form a groove on the surface of the second plastic package 170, and then a copper layer is electroplated in the groove by electroplating, thereby forming the conductive pillar 171. Here, the conductive pillar 171 is a copper pillar. Of course, the material of the conductive pillar 171 is only an example and does not play a limiting role.

[0081] S8: forming a wiring assembly layer 180 on a surface of the second plastic package body 170 away from the first chip 130 .

[0082] Specifically, see Figure 8 After the preparation of the conductive pillar 171 is completed, a dielectric material can be spin-coated on the surface of the second plastic package 170, or a dielectric material can be deposited by a physical vapor deposition process (PVD), a chemical vapor deposition process (CVD), or the like to form a first dielectric layer 181. Then, the first dielectric layer 181 is patterned, and a metal material is electroplated after forming an open groove to form a first metal layer 182 in the first dielectric layer 181. The first metal layer 182 can be a copper layer. Here, the first metal layer 182 is used as a circuit layer to complete the wiring, and the first metal layer 182 needs to be connected to the conductive pillar 171. Then, a dielectric material is spin-coated again on the first dielectric layer 181, or a dielectric material is deposited by a physical vapor deposition process (PVD), a chemical vapor deposition process (CVD), or the like to form a second dielectric layer 183. Similarly, a metal material is electroplated after a groove is formed on the second dielectric layer 183 to form a second metal layer 184. The second metal layer 184 can also be a copper layer, and the second metal layer 184 is electrically connected to the first metal layer 182. After forming the second metal layer 184, the preparation of the UBM metal layer is completed, and then the preparation of the solder ball 185 is completed on the second metal layer 184. Specifically, the ball planting process can be performed on the second metal layer 184 by steel screen printing or ball planting, and the material of the solder ball 185 can be SnAg, SnAgCu, etc. The dielectric material can be silicon nitride, silicon oxynitride, polyimide, benzocyclobutene, etc.

[0083] Specifically, after completing step S8, a cutting process is required to form a final product.

[0084] In summary, the fan-out packaging structure and the preparation method thereof provided in the present embodiment are as follows: a first carrier 110 provided with a first circuit layer 111 and a second carrier 120 provided with a second circuit layer 121 are bonded together, and a clearance groove 113 penetrating to the second carrier 120 is provided on the first carrier 110, and a first chip 130 is mounted on the first carrier 110, a second chip 140 is mounted in the second carrier 120 in the clearance groove 113, and a third chip 160 is mounted on a side surface of the second carrier 120 away from the first chip 130. , thereby realizing a double-sided packaging structure, and realizing fan-out packaging by setting a wiring combination layer 180, and realizing packaging by the first carrier 110 and the second carrier 120. Compared with the single wafer packaging structure, the wiring density of this embodiment is greater, which is conducive to realizing higher density wiring requirements, thereby increasing the number of stacking, and the first carrier 110 and the second carrier 120 respectively play a supporting role, which can reduce the problem of plastic packaging warping compared with the single board structure, thereby effectively solving the problem of stratification between the plastic packaging body and the chip surface and the problem of stratification between the plastic packaging body and the substrate. In addition, by forming the first conductive wire 141 and the second conductive wire 143 on the second chip 140, the electrical connection of the second chip 140 is realized by the first conductive wire 141 and the second conductive wire 143, which can make the first chip 130 and the second chip 140 on the same side present different mounting methods, realize the wire stacking of the chip placement direction on the same side, and ensure the diversity of mounting methods and wiring methods.

[0085] Second embodiment

[0086] See also Fig. 9 This embodiment provides a fan-out double-sided packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding contents in the first embodiment.

[0087] In this embodiment, the fan-out double-sided packaging structure 100 includes a first carrier 110, a second carrier 120, a first chip 130, a second chip 140, a first plastic package 150, a third chip 160, a second plastic package 170 and a wiring assembly layer 180. The first carrier 110 is provided with a first circuit layer 111, the second carrier 120 is provided with a second circuit layer 121 and is attached to one side surface of the first carrier 110, and the first carrier 110 is provided with a makeshift groove 113 that passes through the second carrier 120. The first chip 130 is mounted on the other side surface of the first carrier 110 and is electrically connected to the first circuit layer 111. The second chip 140 is mounted on the second carrier 120 in the makeshift groove 113. The first plastic package 150 is arranged on the first carrier 110 and in the makeshift groove 113, and covers the first chip 130 and the outside of the first chip 130. The third chip 160 is mounted on a side surface of the second carrier 120 away from the first chip 130, and is electrically connected to the second circuit layer 121. The second plastic package 170 is disposed on the second carrier 120 and covers the third chip 160. The wiring assembly layer 180 is disposed on a side surface of the second plastic package 170 away from the first chip 130, wherein the first circuit layer 111 is electrically connected to the second circuit layer 121, the second chip 140 is mounted in the recess 113, and the first conductive wire 141 and the second conductive wire 143 are disposed on the second chip 140, the first conductive wire 141 is connected to the first carrier 110 so that the first conductive wire 141 is electrically connected to the first circuit layer 111, and the second conductive wire 143 is electrically connected to the second carrier 120 so that the second conductive wire 143 is electrically connected to the second circuit layer 121.

[0088] In this embodiment, the surface of one side of the first plastic package 150 away from the second carrier 120 is flush with the surface of one side of the first chip 130 away from the first carrier 110, and the first chip 130 is exposed from the first plastic package 150. Specifically, after the first plastic package 150 is formed, the first plastic package 150 can be thinned by grinding, and the first chip 130 is exposed from the first plastic package 150. On the one hand, the first chip 130 is directly exposed, so that its heat dissipation effect is better. On the other hand, by thinning the first plastic package 150, the distance between the first wire and the second wire and the surface of the plastic package can be shortened, thereby greatly improving the heat dissipation effect of the second chip 140.

[0089] It should be noted that, during actual wire bonding, due to the height difference between the first chip 130 and the second chip 140, the first carrier 110 can be used as the height difference of the wire bonding of the second chip 140, and the first conductive wire 141 is formed by wire bonding on the first carrier 110 to achieve connection with the wire bonding bump 145 on the second chip 140. The wire bonding height is less than or equal to the surface height of the first chip 130, and it is preferred that the first conductive wire 141 and the second conductive wire 143 are both lower than the surface height of the first chip 130, so that the first conductive wire 141 and the second conductive wire 143 are as close to the surface of the first plastic package 150 as possible while ensuring that they are covered in the first plastic package 150, so as to improve the heat dissipation performance.

[0090] In this embodiment, the first conductive line 141 is brought closer to the surface of the first plastic package 150 by grinding, so that the static electricity generated on the first plastic package 150 can be taken away and released through the grounding line, thereby preventing the static electricity from affecting the electrical performance of the device.

[0091] Third embodiment

[0092] See also Fig.10 This embodiment provides a fan-out double-sided packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding contents in the first embodiment.

[0093] In this embodiment, a fourth chip 190 is also mounted on the second carrier 120 in the recess 113. The fourth chip 190 is located between the first carrier 110 and the second chip 140, and the fourth chip 190 is electrically connected to the second circuit layer 121. The first conductive wire 141 is connected across the fourth chip 190 to achieve electromagnetic shielding of the fourth chip 190. Specifically, the fourth chip 190 is flipped on the second carrier 120, and is electrically connected to the second circuit layer 121 through the pad connection at the bottom, and the fourth chip 190 is encapsulated in the first plastic package 150. Here, there can be multiple first conductive wires 141, and multiple first conductive wires 141 are connected across the side of the fourth chip 190 away from the second carrier 120, so as to form a shielding net around the fourth chip 190, achieve electromagnetic shielding of the fourth chip 190, and further achieve the local electromagnetic shielding function of the device.

[0094] It should be noted that in this embodiment, the second chip 140 and the fourth chip 190 can both be small-sized chips, so as to ensure that the second chip 140 and the fourth chip 190 can be mounted in the recess 113 at the same time, and the second chip 140 and the fourth chip 190 are arranged at intervals.

[0095] In this embodiment, in order to ensure the electrical connection characteristics of the second chip 140, additional wire bonding can be performed and conductive wires can be set to connect to the second carrier 120, so that the second chip 140 can be completely mounted on the second carrier 120 and electrically connected to the second circuit layer 121 through wire bonding on both sides.

[0096] This embodiment arranges the fourth chip 190 in the make way slot 113, which, on the one hand, greatly increases the number of chips stacked in the packaging structure, and on the other hand, can achieve electromagnetic shielding of the fourth chip 190, thereby realizing the local electromagnetic shielding function of the device, and some special chips can be placed in the make way slot 113 for electromagnetic shielding.

[0097] Fourth embodiment

[0098] See also Fig.11 This embodiment provides a fan-out double-sided packaging structure 100, whose basic structure and principle and the technical effects produced are the same as those of the first embodiment or the third embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding contents in the first embodiment or the third embodiment.

[0099] In this embodiment, a fourth chip 190 is also mounted on the second carrier 120 in the recess 113. The fourth chip 190 is located between the first carrier 110 and the second chip 140, and the fourth chip 190 is electrically connected to the second circuit layer 121. The first conductive wire 141 is connected across the fourth chip 190 to achieve electromagnetic shielding of the fourth chip 190. In addition, in this embodiment, the surface of the first plastic package 150 away from the second carrier 120 is flush with the surface of the first chip 130 away from the first carrier 110, and the first chip 130 is exposed to the first plastic package 150. Specifically, after the first plastic package 150 is formed, the first plastic package 150 can be thinned by grinding, and the first chip 130 is exposed to the first plastic package 150. On the one hand, the first chip 130 is directly exposed, so that its heat dissipation effect is better. On the other hand, by thinning the first plastic package 150 , the distance between the first wire and the second wire and the surface of the plastic package can be shortened, thereby greatly improving the heat dissipation effect of the second chip 140 .

[0100] In this embodiment, the first conductive line 141 is brought closer to the surface of the first plastic package 150 by grinding, so that the static electricity generated on the first plastic package 150 can be taken away and released through the grounding line, thereby preventing the static electricity from affecting the electrical performance of the device.

[0101] Fifth embodiment

[0102] See also Fig.12This embodiment provides a fan-out double-sided packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding contents in the first embodiment.

[0103] In this embodiment, the second chip 140 is mounted on the second carrier 120 in the recess 113 , and the first conductive wire 141 and the second conductive wire 143 are both connected to the second carrier 120 , so that the second chip 140 is only electrically connected to the second circuit layer 121 .

[0104] Specifically, a first bonding pad 115 and a second bonding pad 123 are provided on the surface of the second carrier 120, and the first bonding pad 115 and the second bonding pad 123 are respectively provided on both sides of the second chip 140, and a bonding bump 145 is provided on the side of the second chip 140 away from the second carrier 120, the first conductive wire 141 simultaneously connects the bonding bump 145 and the first bonding pad 115, the second conductive wire 143 simultaneously connects the bonding bump 145 and the second bonding pad 123, and a fifth chip 191 is also provided on the edge of one side of the first carrier 110 close to the second chip 140, the fifth chip 191 is electrically connected to the first circuit layer 111, and the fifth chip 191 partially extends out of the first carrier 110 and is electrically connected to the second circuit layer 121.

[0105] In this embodiment, an electrical support column 193 electrically connected to the second circuit layer 121 is provided on the second carrier 120, and the electrical support column 193 is correspondingly engaged with the portion of the fifth chip 191 extending out of the first carrier 110, and is used to support the fifth chip 191, and the fifth chip 191 is electrically connected to the second circuit layer 121 through the electrical support column 193. Specifically, the electrical support column 193 can be a copper column and is directly made on the first carrier 110. When the first carrier 110 is removed by etching or laser, a part of the first carrier 110 is removed, and the electrical support column 193 is left, so that the electrical support column 193 is set on the second carrier 120. Of course, here, after the recess 113 is formed, the electrical support column 193 can be re-electroplated on the surface of the second carrier 120.

[0106] In actual preparation, it is necessary to make a bonding copper column area on the first carrier 110. During etching, a protective film is used to protect the area that does not need to be etched to form a copper column, and then the fifth chip 191 is mounted again. The fifth chip 191 is bonded to the first carrier 110 and the second carrier 120 at the same time. The electrical support column 193 serves as a support bonding area, which improves the chip integration and wiring density in the middle area. And the use of the electrical support column 193 can avoid welding deformation in the middle area and improve the overall structural strength. Here, the first plastic package 150 can be ground to leak out the first chip 130 and the fifth chip 191, while improving the heat dissipation performance. The thickness of the fifth chip 191 can also be lower than that of the first chip 130, so that the fifth chip 191 does not leak out. The specific selection can be based on the design.

[0107] The fan-out double-sided packaging structure 100 provided in this embodiment can increase the number of chip stacking of the device by setting the fifth chip 191, and can also increase the overall structural strength, improve the wiring structure, and enhance the device performance.

[0108] Sixth embodiment

[0109] See also Fig.13 This embodiment provides a fan-out double-sided packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding contents in the first embodiment.

[0110] The fan-out double-sided packaging structure 100 provided in this embodiment includes a first carrier 110, a second carrier 120, a first chip 130, a second chip 140, a first plastic package 150, a third chip 160, a second plastic package 170 and a wiring assembly layer 180. The first carrier 110 is provided with a first circuit layer 111, the second carrier 120 is provided with a second circuit layer 121 and is attached to a side surface of the first carrier 110, and a recess 113 penetrating to the second carrier 120 is provided on the first carrier 110. The first chip 130 is mounted on the other side surface of the first carrier 110 and is electrically connected to the first circuit layer 111. The second chip 140 is mounted on the second carrier 120 in the recess 113. The first plastic package 150 is arranged on the first carrier 110 and in the recess 113, and covers the first chip 130 and the outside of the first chip 130. The third chip 160 is mounted on a side surface of the second carrier 120 away from the first chip 130 and is electrically connected to the second circuit layer 121. The second plastic package 170 is disposed on the second carrier 120 and covers the third chip 160. The wiring assembly layer 180 is disposed on a side surface of the second plastic package 170 away from the first chip 130.

[0111] In this embodiment, the first circuit layer 111 is electrically connected to the second circuit layer 121, the second chip 140 is installed in the recess 113, and the first conductive wire 141 and the second conductive wire 143 are arranged on the second chip 140. The first conductive wire 141 is connected to the first carrier 110 or the second carrier 120 so that the first conductive wire 141 is electrically connected to the first circuit layer 111 or the second circuit layer 121, and the second conductive wire 143 is electrically connected to the second carrier 120 so that the second conductive wire 143 is electrically connected to the second circuit layer 121.

[0112] Furthermore, in this embodiment, a filling groove 117 is further provided on the first carrier 110, and the filling groove 117 is located below the first conductive line 141, and the first plastic package body 150 extends into the filling groove 117. Specifically, the filling groove 117 is located between the first wire bonding pad 115 and the second chip 140, and the first conductive line 141 is bridged over the filling groove 117, so that when the first plastic package body 150 is formed, the plastic package material can flow to the bottom of the first conductive line 141 as much as possible and fill the filling groove, thereby avoiding the formation of bubbles under the first conductive line 141 during plastic packaging and affecting the plastic packaging quality.

[0113] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A fan-out double-sided packaging structure, characterized in that: include: A first carrier having a first circuit layer; A second carrier attached to a side surface of the first carrier and provided with a second circuit layer, and a recess penetrating to the second carrier is provided on the first carrier; A first chip mounted on the other side surface of the first carrier and electrically connected to the first circuit layer; A second chip mounted on the second carrier in the recess; A first plastic package body disposed on the first carrier and in the clearance groove and covering the first chip and the second chip; A third chip mounted on a surface of the second carrier away from the first chip and electrically connected to the second circuit layer; A second plastic package body disposed on the second carrier and covering the third chip; and, a wiring assembly layer disposed on a surface of the second plastic package body on a side away from the first chip; The first circuit layer is electrically connected to the second circuit layer, the second chip is mounted in the recess, and the second chip is provided with a first conductive wire and a second conductive wire, the first conductive wire is connected to the first carrier or the second carrier so that the first conductive wire is electrically connected to the first circuit layer or the second circuit layer, and the second conductive wire is electrically connected to the second carrier so that the second conductive wire is electrically connected to the second circuit layer.

2. The fan-out double-sided packaging structure according to claim 1, characterized in that: Conductive columns are also provided in the second plastic package, and the conductive columns are respectively provided on at least two sides of the third chip, and one end of the conductive column extends to the second carrier and is electrically connected to the second circuit layer, and the other end of the conductive column extends to the wiring assembly layer and is electrically connected to the wiring assembly layer.

3. The fan-out double-sided packaging structure according to claim 2, characterized in that: The wiring combination layer includes a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer and a solder ball, wherein the first dielectric layer covers the surface of the second plastic package body, the first metal layer is arranged in the first dielectric layer and is electrically connected to the conductive column, the second dielectric layer covers the surface of the first dielectric layer, the second metal layer is arranged in the second dielectric layer and is electrically connected to the first metal layer, and the solder ball is arranged on a side of the second dielectric layer away from the second plastic package body and is electrically connected to the second metal layer.

4. The fan-out double-sided packaging structure according to claim 1, characterized in that: A first wire bonding pad is provided on the surface of the first carrier, the first wire bonding pad is located between the first chip and the second chip and is electrically connected to the first circuit layer, a second wire bonding pad is provided on the surface of the second carrier, the second wire bonding pad is electrically connected to the second circuit layer, a wire bonding bump is provided on the side of the second chip away from the second carrier, one end of the first conductive wire is connected to the first wire bonding pad, and the other end is connected to the wire bonding bump, one end of the second conductive wire is connected to the second wire bonding pad, and the other end is connected to the wire bonding bump, so that the second chip is electrically connected to the first circuit layer and the second circuit layer at the same time.

5. The fan-out double-sided packaging structure according to claim 4, characterized in that: A surface of the first plastic package body on one side away from the second carrier is flush with a surface of the first chip on one side away from the first carrier, and the first chip is exposed outside the first plastic package body.

6. The fan-out double-sided packaging structure according to claim 4 or 5, characterized in that: A fourth chip is also mounted on the second carrier in the recess. The fourth chip is located between the first carrier and the second chip, and is electrically connected to the second circuit layer. The first conductive line is bridged over the fourth chip to achieve electromagnetic shielding for the fourth chip.

7. The fan-out double-sided packaging structure according to claim 1, characterized in that: A first wire bonding pad and a second wire bonding pad are provided on the surface of the second carrier, the first wire bonding pad and the second wire bonding pad are respectively provided on both sides of the second chip, and a wire bonding bump is provided on the side of the second chip away from the second carrier, the first conductive wire simultaneously connects the wire bonding bump and the first wire bonding pad, the second conductive wire simultaneously connects the wire bonding bump and the second wire bonding pad, a fifth chip is also provided on the edge of one side of the first carrier close to the second chip, the fifth chip is electrically connected to the first circuit layer, and the fifth chip partially extends out of the first carrier and is electrically connected to the second circuit layer.

8. The fan-out double-sided packaging structure according to claim 7, characterized in that: The second carrier is provided with an electrical support column electrically connected to the second circuit layer. The electrical support column is correspondingly engaged with the portion of the fifth chip extending out of the first carrier for supporting the fifth chip. The fifth chip is electrically connected to the second circuit layer through the electrical support column.

9. The fan-out double-sided packaging structure according to claim 1, characterized in that: A circuit pad is provided on a surface of the first carrier away from the second carrier, and the circuit pad is electrically connected to the first circuit layer. A welding bump is provided on the first chip, and the welding bump is correspondingly bonded to the circuit pad so that the first chip is flipped on the first carrier.

10. The fan-out double-sided packaging structure according to claim 1, characterized in that: The first carrier is also provided with a filling groove, the filling groove is located below the first conductive line, and the first plastic package body extends into the filling groove.

11. A method for preparing a fan-out double-sided packaging structure, used for preparing the fan-out double-sided packaging structure according to any one of claims 1 to 10, characterized in that: The preparation method comprises: Laying the second carrier on one side surface of the first carrier; A groove is formed on the first carrier to form a clearance groove which passes through to the second carrier; Mounting a first chip on the surface of the other side of the first carrier; Mounting a second chip on the second carrier in the recess; Forming a first plastic package covering the first chip and the second chip on the first carrier and in the clearance groove; Mounting a third chip on the surface of the second carrier away from the first chip; forming a second plastic package covering the third chip on the second carrier; forming a wiring assembly layer on a surface of the second plastic package body at a side away from the first chip; Among them, the first carrier is provided with a first circuit layer, the second carrier is provided with a second circuit layer, the first chip is electrically connected to the first circuit layer, the second chip and the third chip are electrically connected to the second circuit layer, the first circuit layer is electrically connected to the second circuit layer, the second chip is installed in the give way groove, and the second chip is provided with a first conductive wire and a second conductive wire, the first conductive wire is connected to the first carrier or the second carrier so that the first conductive wire is electrically connected to the first circuit layer or the second circuit layer, and the second conductive wire is electrically connected to the second carrier so that the second conductive wire is electrically connected to the second circuit layer.

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