SiC module with low parasitic inductance and high heat dissipation performance and manufacturing process thereof

Abstract

The application relates to the technical field of power electronic device packaging integration, in particular to a SiC module with low parasitic inductance and high heat dissipation performance and a manufacturing process, wherein the SiC module comprises an outer shell, a metal bottom plate, a DBC plate, a PCB driving plate and a silicon carbide element which are stacked from bottom to top, and the metal bottom plate, the DBC plate, the PCB driving plate and the silicon carbide element are arranged in the outer shell; the DBC plate comprises two copper layers and an AlN layer, the AlN layer is located between the two copper layers, the silicon carbide element, the copper layer and the PCB driving plate are electrically connected, and a plurality of power terminals are arranged on the DBC plate. By adjusting the layout of the module as a whole, the parasitic inductance of the module as a whole can be greatly reduced, and by replacing the ceramic material in the DBC plate, the heat dissipation capacity of the module as a whole is enhanced.

Description

Technical Field

[0001] This invention relates to the field of power electronic device packaging and integration technology, specifically to a SiC module with low parasitic inductance and high heat dissipation performance and its manufacturing process. Background Technology

[0002] The development of third-generation power semiconductor devices, primarily based on silicon carbide (SiC) devices, is rapid. Compared to traditional silicon devices, SiC devices possess numerous superior characteristics, including low on-resistance, low parasitic capacitance, high maximum switching frequency, and high maximum operating junction temperature. Therefore, SiC devices have enormous potential and broad development prospects in a wide range of applications, including electric vehicle charging stations and motor drive systems, photovoltaic inverters, electric aircraft, marine power systems, and DC circuit breakers in power grids.

[0003] In the manufacturing process of SiC devices, to improve chip yield, the area of ​​a single SiC device is typically small, which further results in a relatively small current capacity per device. To further improve the current capacity of SiC devices, a modular packaging method is usually used to integrate multiple chips in parallel. Currently, the packaging and integration technology for SiC devices still follows the traditional packaging technology for Si devices, which has led to some problems.

[0004] The traditional 62mm package design introduces significant parasitic inductance through the bonding wire process, leading to severe voltage overshoot and oscillation in SiC devices during high-speed switching. Furthermore, the ceramic layer in traditional direct-bonded ceramic (DBC) substrates uses Al2O3, which has low thermal conductivity. This results in poor heat dissipation and excessive heat generation in SiC devices at high frequencies, necessitating large heat sinks. Currently, commercially available aluminum heat sinks typically measure 111mm x 63mm x 50mm. These factors prevent the full realization of the high switching speed and frequency advantages of SiC devices, becoming a technological bottleneck hindering the development of the entire industry.

[0005] Several optimization design strategies have been proposed to address the high parasitic inductance of SiC modules, including optimizing the layout of the main power circuit, the drive circuit, and adjusting the terminal structure. However, the parasitic inductance of the improved modules is still between 10nH and 20nH, requiring further improvement. Additionally, some optimization design strategies have been proposed to address the heat dissipation problem of SiC modules, including using double-sided heat dissipation packaging structures and replacing traditional solder with sintered silver. However, these methods are not only more complex in their processes but also more expensive, making them unsuitable for widespread application. Summary of the Invention

[0006] To address the problems existing in the prior art, the present invention provides a SiC module with low parasitic inductance and high heat dissipation performance, as well as its manufacturing process.

[0007] This invention is achieved through the following technical solution:

[0008] A SiC module with low parasitic inductance and high heat dissipation performance includes a housing and a metal base plate, a DBC board, a PCB driver board, and silicon carbide components stacked from bottom to top. The metal base plate, DBC board, PCB driver board, and silicon carbide components are all disposed inside the housing. The DBC board includes two copper layers and an AlN layer, with the AlN layer located between the two copper layers. The silicon carbide components, copper layers, and PCB driver board are electrically connected. The DBC board is provided with multiple power terminals.

[0009] Preferably, the metal base plate is further provided with a plurality of positioning blocks at its edge, the plurality of positioning blocks forming a mounting cavity on the metal base plate, and the DBC plate being located in the mounting cavity; the thickness of the DBC plate is equal to the thickness of the positioning blocks.

[0010] Preferably, the silicon carbide element, the copper layer, and the PCB driver board are electrically connected by bonding wires.

[0011] Preferably, the PCB driver board is provided with an outer upper bridge arm gate, an inner upper bridge arm gate, an outer upper bridge arm source, an inner upper bridge arm source, an outer lower bridge arm gate, an inner lower bridge arm gate, an outer lower bridge arm source, and an inner lower bridge arm source. The silicon carbide element includes multiple silicon carbide MOSFETs and multiple silicon carbide diodes, which are alternately arranged. The source of the silicon carbide MOSFET and the anode of the silicon carbide diode are electrically connected to the copper layer.

[0012] Preferably, the gate of the silicon carbide MOSFET is connected to the gate of the inner upper bridge arm and the gate of the inner lower bridge arm; the Kelvin source of the silicon carbide MOSFET is electrically connected to the source of the inner upper bridge arm and the source of the inner lower bridge arm.

[0013] Preferably, the PCB driver board is further provided with multiple pin headers, and the outer upper bridge arm gate, outer upper bridge arm source, outer lower bridge arm gate, and outer lower bridge arm source are all connected to the pin headers, which are used to lead out the driving electrode.

[0014] A SiC module fabrication process with low parasitic inductance and high heat dissipation performance includes the following steps:

[0015] S1, connect the DBC board and silicon carbide components using the first solder to form the first assembly;

[0016] S2, the side of the first assembly exposed on the DBC board is connected to the metal base plate using the first solder to form the second assembly;

[0017] S3 connects the silicon carbide components, the copper layer of the DBC board, and the PCB driver board;

[0018] S4, connect the power terminals to the copper layer of the DBC board using the second solder;

[0019] S5 connects the metal base plate to the outer casing;

[0020] S6, glue application.

[0021] Preferably, the melting point of the first solder is higher than that of the second solder.

[0022] Preferably, in S3, the connection between the silicon carbide element, the copper layer, and the PCB driver board is achieved using a wire bonding process.

[0023] Preferably, in S5, after the metal base plate is connected to the outer shell, the gap between the metal base plate and the outer shell is filled with glue.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] The SiC module with low parasitic inductance and high heat dissipation performance used in this invention enhances the overall heat dissipation capacity of the module by replacing the ceramic material in the DBC. The thermal conductivity of Al2O3 ceramic material is 10 W / m·K, and the thermal conductivity of AlN material is 170 W / m·K. It can be seen that by using the new AlN material, the heat dissipation performance of the power module will be significantly improved, and the volume of the heat sink used will also be significantly reduced.

[0026] Secondly, a PCB driver board is used to construct the drive circuit and make it perpendicular to the power circuit to reduce the influence of the drive circuit on the power circuit.

[0027] In addition, since the parasitic inductance of the power module is inversely related to the width of the current path, and the copper layer of the DBC and the power terminals are important components of the current path, the present invention reduces the overall parasitic inductance of the module by increasing the width of the contact surface between the power terminals and the DBC.

[0028] Furthermore, the thickness of the DBC board is equal to the thickness of the positioning block to ensure the fit between the DBC board and the PCB driver board, facilitating the connection between the DBC board and the PCB driver board.

[0029] Furthermore, multiple pin headers are used to bring out the driver stage to accommodate the DBC board's configuration.

[0030] This invention provides a SiC module manufacturing process with low parasitic inductance and high heat dissipation performance. While reducing parasitic inductance and improving heat dissipation, it is compatible with traditional bonding wire and soldering processes. It is easy to manufacture and does not require additional costs, making it suitable for large-scale market applications.

[0031] Furthermore, the melting point of the first solder is higher than that of the second solder in order to reduce the impact of the two solders during welding. Attached Figure Description

[0032] Figure 1 This is a diagram of the internal structure of a traditional SiC module.

[0033] Figure 2 This is an overall structural view of the present invention;

[0034] Figure 3 This is an internal structural view of the present invention;

[0035] Figure 4 This is the layout of the DBC board of the present invention;

[0036] Figure 5 This is a side view of the DBC board of the present invention;

[0037] Figure 6 This is a schematic diagram of the assembly of the metal base plate and the positioning block in this invention;

[0038] Figure 7 This is a schematic diagram of the PCB driver board of the present invention;

[0039] Figure 8 This is a schematic diagram of the power terminal structure of the present invention;

[0040] Figure 9 This is a schematic diagram of the outer shell structure of the present invention.

[0041] In the diagram, 1. Bonding wire; 2. Silicon carbide MOSFET; 3. Silicon carbide diode; 4. Positioning block; 5. Metal base plate; 6. Threaded hole; 7. Outer upper bridge arm gate; 8. Inner upper bridge arm gate; 9. Outer upper bridge arm source; 10. Inner upper bridge arm source; 11. Outer lower bridge arm gate; 12. Inner lower bridge arm gate; 13. Outer lower bridge arm source; 14. Inner lower bridge arm source; 15. Pin header; 16. Power terminal; 17. Housing; 18. DBC board; 181. Copper layer; 182. AlN layer; 19. PCB driver board; 20. Housing opening; 21. Driver terminal. Detailed Implementation

[0042] The present invention will be further described in detail below with reference to specific embodiments. These descriptions are for explanation purposes only and are not intended to limit the scope of the invention.

[0043] Reference Figure 1In the traditional 62mm package structure, the parasitic inductance introduced by the bonding wire process is large, which leads to severe voltage overshoot and oscillation of SiC devices during high-speed switching. The ceramic layer in the traditional substrate, namely the direct bonded ceramic substrate (DBC), uses Al2O3 material, which has low thermal conductivity. This causes SiC devices to generate a lot of heat due to poor heat dissipation under high-frequency operating conditions.

[0044] This invention discloses a SiC module with low parasitic inductance and high heat dissipation performance, referring to... Figure 2 , 3 4, including the outer shell 17 and the metal base plate 5, DBC board 18, PCB driver board 19 and silicon carbide components stacked from bottom to top, the metal base plate 5, DBC board 18, PCB driver board 19 and silicon carbide components are all disposed inside the outer shell 17.

[0045] Reference Figure 4 , 5 The DBC board 18 includes two copper layers 181 and an AlN layer 182, with the AlN layer 182 located between the two copper layers 181. Multiple positioning blocks 4 are provided at the edge of the metal base plate 5, and the positioning blocks 4 are mechanically connected to the metal base plate 5 using screws. Figure 6 The metal base plate 5 has M1.25 threaded holes 6, and the positioning blocks 4 have corresponding holes. The positioning blocks 4 are made of copper. Multiple positioning blocks 4 form a mounting cavity on the metal base plate 5, and the DBC plate 18 is located in the mounting cavity. The thickness of the DBC plate 18 is equal to the thickness of the positioning blocks 4. In this embodiment, there are two positioning blocks 4, and the DBC plate 18 is located between the two positioning blocks 4.

[0046] Reference Figure 3 The silicon carbide components, copper layer 181 and PCB driver board 19 are electrically connected by bonding wire 1. The silicon carbide components include multiple silicon carbide MOSFETs 2 and multiple silicon carbide diodes 3, which are arranged alternately.

[0047] Reference Figure 3 and Figure 7 The source of silicon carbide MOSFET 2 and the anode of silicon carbide diode 3 are electrically connected to copper layer 181. The PCB driver board 19 is provided with outer upper bridge arm gate 7, inner upper bridge arm gate 8, outer upper bridge arm source 9, inner upper bridge arm source 10, outer lower bridge arm gate 11, inner lower bridge arm gate 12, outer lower bridge arm source 13 and inner lower bridge arm source 14. The gate of silicon carbide MOSFET 2 is connected to inner upper bridge arm gate 8 and inner lower bridge arm gate 12; the Kelvin source of silicon carbide MOSFET 2 is electrically connected to inner upper bridge arm source 10 and inner lower bridge arm source 14.

[0048] The PCB driver board 19 is also provided with multiple pin headers 15. The outer upper bridge arm gate 7, outer upper bridge arm source 9, outer lower bridge arm gate 11, and outer lower bridge arm source 13 are all soldered to the pin headers 15. In this embodiment, the pin headers 15 are L-shaped and are used to lead out the driving electrode.

[0049] Reference Figure 8 The DBC board 18 is provided with multiple power terminals 16, and in this embodiment, the drive segment is provided with three.

[0050] A SiC module fabrication process with low parasitic inductance and high heat dissipation performance includes the following steps:

[0051] S1, connect the DBC board 18 to the silicon carbide components (silicon carbide MOSFET 2 and silicon carbide diode 3) using a first solder to form a first assembly; in this embodiment, the first solder is SAC-305 solder paste with a melting point of 230℃. During soldering, the temperature profile of the first solder is set as shown in Table 1:

[0052] Table 1 Temperature profile settings for the first solder

[0053] Time (S) 0 30 60 90 390 420 Temperature (°C) 0 190 190 250 250 0

[0054] During the soldering process, the solder paste is heated to 190°C for 30 seconds to dry out the moisture, and then melted at 250°C to ensure that the solder paste melts completely.

[0055] S2, the first assembly is connected to the metal base plate 5 with the side of the DBC board 18 exposed by the first solder to form the second assembly.

[0056] Apply the first solder to the corresponding position on the metal base plate 5. The metal plate has a threaded hole 6. Fix the two positioning blocks 4 and the metal base plate 5 with M1.25 screws at the threaded hole 6. Then place the DBC board 18 between the two positioning blocks 4. The positioning blocks 4 can fix the position of the DBC board 18 and prevent the DBC board 18 from shifting during the welding process.

[0057] S3 connects the silicon carbide element, copper layer 181, and PCB driver board 19.

[0058] First, mechanically connect the PCB driver board 19 to the DBC board 18. After removing the M1.25 screws, place the PCB driver board 19 on top and then secure it with the M1.25 screws. In this embodiment, the copper layer 181 of the DBC board 18 has a thickness of 0.3mm, the ceramic layer has a thickness of 0.1mm, and the positioning block 4 has a thickness of 0.7mm. Therefore, after assembling the PCB, the PCB can fit against the DBC, preventing failure of bonding wire 1.

[0059] The gate of the silicon carbide MOSFET 2 is then bonded to the gate 8 of the inner upper bridge arm and the gate 12 of the inner lower bridge arm.

[0060] The Kelvin source of the silicon carbide MOSFET 2 is then bonded to the inner upper bridge arm source 10 and the inner lower bridge arm source 14.

[0061] Finally, the pin header 15 is soldered to the upper outer bridge arm gate 7, the upper outer bridge arm source 9, the lower outer bridge arm gate 11, and the lower outer bridge arm source 13, and the pin header 15 leads out the drive electrode.

[0062] S4, connect the power terminal 16 to the copper layer 181 of the DBC board 18 using the second solder;

[0063] During soldering, a mold is used for assistance. First, the power terminal 16 is attached to the mold, and then the second solder is used to connect the power terminal 16 to the copper layer 181 of the DCB board. In this embodiment, the second solder is CVP-520 solder paste, which has a melting point of 180°C. The temperature profile is set as shown in Table 2. The solder paste is kept at 140°C for 30 seconds to dry the moisture in the solder paste, and then melted at 200°C to ensure that the solder paste melts completely.

[0064] Table 2 Temperature profile settings for the second solder

[0065] Time (S) 0 30 60 90 390 420 Temperature (°C) 0 140 140 200 200 0

[0066] S5, connect the metal base plate 5 to the outer shell 17; remove the mold, connect the metal base plate 5 to the outer shell 17 using an M6 nut, and fill the gap between the metal base plate 5 and the outer shell 17 with glue. Prevent potting compound from flowing out of the gap.

[0067] S6, potting. (Refer to...) Figure 9 Apply the prepared epoxy resin transparent potting compound (836 potting compound, 1:1 ratio, insulation class 10kV / mm) to the opening 20 on the outer shell and let it stand for 24 hours.

[0068] Compared to traditional layouts, adjusting the overall module layout—specifically increasing the width of the DBC copper layer and terminals, and shortening the distance between terminals to reduce current flow paths—can significantly reduce the overall parasitic inductance of the module. The overall module dimensions are 109mm*63mm*10.2mm. Q3D simulations show that the overall parasitic inductance of the upper bridge arm circuit is 2.7nH, and the overall parasitic inductance of the lower bridge arm circuit is 3.2nH.

[0069] In terms of heat dissipation, a heat sink is required to achieve good heat dissipation performance. The heat sink measures 111mm*63mm*31mm, which is 40% smaller in volume compared to a typical aluminum heat sink. ICEPAK simulations show that the heat dissipation is good after adding the heat sink, with a thermal resistance of 0.2℃ / W from the chip to the metal base plate.

Claims

1. A SiC module with low parasitic inductance and high heat dissipation performance, characterized in that, The device includes a housing (17) and a metal base plate (5), a DBC board (18), a PCB driver board (19), and silicon carbide components stacked from bottom to top. The metal base plate (5), the DBC board (18), the PCB driver board (19), and the silicon carbide components are all disposed inside the housing (17). The DBC board (18) includes two copper layers (181) and an AlN layer (182). The AlN layer (182) is located between the two copper layers (181). The silicon carbide components, the copper layers (181), and the PCB driver board (19) are electrically connected. The DBC board (18) is provided with multiple power terminals (16). The silicon carbide element includes a plurality of silicon carbide MOSFETs (2) and a plurality of silicon carbide diodes (3), wherein the silicon carbide MOSFETs (2) and silicon carbide diodes (3) are arranged alternately; the source of the silicon carbide MOSFET (2) and the anode of the silicon carbide diode (3) are electrically connected to the copper layer (181); The PCB driver board (19) is provided with an outer upper bridge arm gate (7), an inner upper bridge arm gate (8), an outer upper bridge arm source (9), an inner upper bridge arm source (10), an outer lower bridge arm gate (11), an inner lower bridge arm gate (12), an outer lower bridge arm source (13), and an inner lower bridge arm source (14). The gate of the silicon carbide MOSFET (2) is connected to the inner upper bridge arm gate (8) and the inner lower bridge arm gate (12). The Kelvin source of the silicon carbide MOSFET (2) is electrically connected to the inner upper bridge arm source (10) and the inner lower bridge arm source (14). The PCB driver board (19) is also provided with multiple pin headers (15). The outer upper bridge arm gate (7), outer upper bridge arm source (9), outer lower bridge arm gate (11), and outer lower bridge arm source (13) are all connected to the pin headers (15). The pin headers (15) are used to lead out the driving electrode. The pin headers (15) are L-shaped.

2. The SiC module with low parasitic inductance and high heat dissipation performance according to claim 1, characterized in that, The metal base plate (5) is also provided with a plurality of positioning blocks (4) at its edge. The plurality of positioning blocks (4) form an installation cavity on the metal base plate (5), and the DBC plate (18) is located in the installation cavity. The thickness of the DBC plate (18) is equal to the thickness of the positioning blocks (4).

3. The SiC module with low parasitic inductance and high heat dissipation performance according to claim 1, characterized in that, The silicon carbide element, copper layer (181) and PCB driver board (19) are electrically connected by bonding wires (1).

4. A SiC module fabrication process with low parasitic inductance and high heat dissipation performance as described in any one of claims 1 to 3, characterized in that, Includes the following steps: S1, the DBC board (18) and silicon carbide components are connected using the first solder to form the first assembly; S2, the side of the first assembly exposed on the DBC board (18) is connected to the metal base plate (5) using the first solder to form the second assembly; S3, connect the silicon carbide components, the copper layer (181) of the DBC board (18) and the PCB driver board (19); S4, the power terminal (16) is connected to the copper layer (181) of the DBC board (18) using a second solder; the melting point of the first solder is higher than that of the second solder; S5, connect the metal base plate (5) to the outer shell (17); S6, glue application.

5. The SiC module fabrication process with low parasitic inductance and high heat dissipation performance according to claim 4, characterized in that, In S3, the connection between the silicon carbide element, the copper layer (181) of the DBC board (18) and the PCB driver board (19) is achieved using a bonding wire (1) process.

6. The SiC module fabrication process with low parasitic inductance and high heat dissipation performance according to claim 4, characterized in that, In S5, after the metal base plate (5) is connected to the outer shell (17), glue is used to fill the gap between the metal base plate (5) and the outer shell (17).

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