A display panel and a display device

Abstract

The present invention discloses a display panel and a display device. The display panel includes a substrate, a plurality of scan lines, data lines, and pixel units disposed on the substrate. The scan lines include a first scan line. The pixel units include a driving transistor, a second transistor connected between the data line and the second pole of the driving transistor, and a third transistor connected between the gate of the driving transistor and the first pole of the driving transistor. The gate of the driving transistor is connected to the third transistor through a first connection line; a first branch line and a second branch line connected to the first scan line; the gate of the third transistor is connected to the first scan line; the gate of the second transistor is connected to the first scan line through the second branch line; the orthographic projection of the first branch line on the substrate does not overlap with the orthographic projection of the first connection line on the substrate; the orthographic projection of the second branch line on the substrate does not overlap with the orthographic projection of the first connection line on the substrate. The technical solution provided by the embodiments of the present invention improves the display effect of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] With the development of display technologies, people's requirements for display technologies are getting higher and higher. The structure of the pixel driving circuit of the display panel is becoming more and more complex, resulting in signal interference between the signal lines and the driving circuit of the display panel, which affects the display effect of the display panel. Summary of the Invention

[0003] The present invention provides a display panel and a display device to solve the problem that signal interference between the signal lines and the driving circuit of the display panel affects the display effect.

[0004] According to one aspect of the present invention, a display panel is provided. The display panel includes:

[0005] A substrate;

[0006] A plurality of scan lines disposed on the substrate; the scan lines include a first scan line;

[0007] A plurality of data lines located on the substrate;

[0008] A plurality of pixel units arranged in an array on the substrate; the pixel unit includes: a driving transistor; a third transistor connected between the gate and the first pole of the driving transistor; a second transistor connected between the data line and the second pole of the driving transistor;

[0009] A first connection line, the gate of the driving transistor is connected to the third transistor through the first connection line;

[0010] A first branch line and a second branch line connected to the first scan line; the gate of the third transistor is formed on the first branch line, and the gate of the second transistor is formed on the second branch line;

[0011] The orthographic projection of the first branch line on the substrate does not overlap with the orthographic projection of the first connection line on the substrate; the orthographic projection of the second branch line on the substrate does not overlap with the orthographic projection of the first connection line on the substrate.

[0012] Optionally, the orthographic projection of the first branch line on the substrate does not overlap with the orthographic projection of the gate of the driving transistor on the substrate; the orthographic projection of the second branch line on the substrate does not overlap with the orthographic projection of the gate of the driving transistor on the substrate; the orthographic projection of the first branch line on the substrate does not overlap with the orthographic projection of the second branch line on the substrate.

[0013] Optionally, the gates of the third transistor and the second transistor are connected to the same first scanning line; the orthogonal projection of the first scanning line on the substrate does not overlap with the orthogonal projection of the gate of the driving transistor on the substrate; the orthogonal projection of the first scanning line on the substrate does not overlap with the orthogonal projection of the first connection line on the substrate.

[0014] Optionally, the display panel further includes: a plurality of initialization lines disposed on the substrate; a second connection line, on which a first pole and a second pole of the driving transistor are formed; the pixel unit further includes: a fourth transistor, the gate of the driving transistor is connected to the first pole of the fourth transistor through the first connection line and the second connection line; the second pole of the fourth transistor is connected to the initialization line.

[0015] Optionally, the orthogonal projection of the first scanning line on the substrate does not overlap with the orthogonal projection of the second connection line on the substrate.

[0016] Optionally, the pixel unit further includes: a storage capacitor, the storage capacitor includes a first electrode and a second electrode; the first electrode is disposed on the same layer as the gate of the driving transistor, and the second electrode is disposed on a side of the first electrode away from the substrate;

[0017] Preferably, the display panel further includes:

[0018] a plurality of power supply lines disposed on the substrate;

[0019] a third connection line disposed on the same layer as the second electrode, the third connection line is connected to the power supply line; the third connection line is used to transmit a driving power signal to the pixel unit;

[0020] the first scanning line is disposed on a side of the third connection line away from the substrate;

[0021] The second connection line includes a first region, wherein the orthogonal projection of the first scanning line on the second connection line overlaps with at least a part of the second connection line and overlaps in the first region;

[0022] The orthogonal projection of the third connection line on the substrate covers the orthogonal projection of the first region of the second connection line on the substrate.

[0023] Optionally, the first scanning line and the data line are disposed on a side of the second electrode of the storage capacitor away from the substrate;

[0024] The first scanning line and the data line are disposed on different layers.

[0025] Optionally, the first connection line is disposed on a side of the second electrode of the storage capacitor away from the substrate; the first connection line and the gate of the driving transistor are connected through a via;

[0026] The first scanning line and the first connection line are disposed on the same layer; or,

[0027] The first scanning line is disposed on a side of the first connection line away from the substrate.

[0028] Optionally, the power line includes a first wiring layer and a second wiring layer. The first wiring layer is disposed on the same layer as the first connection line; the second wiring layer is disposed on a side of the first connection line away from the substrate;

[0029] The power line includes a second region, and a positive projection of the first scanning line on the power line overlaps the power line in the second region;

[0030] The power line located in the second region includes the first wiring layer or the second wiring layer, and the power line is disposed on a different layer from the first scanning line.

[0031] In a second aspect, an embodiment of the present invention provides a display device, including: the display panel according to any item of the first aspect.

[0032] The technical solution of the embodiment of the present invention is achieved by providing that a third transistor is connected between the gate of the driving transistor and the first pole of the driving transistor. A second transistor is connected between the data line and the second pole of the driving transistor. The gate of the driving transistor is connected to the third transistor through the first connection line. The gate of the third transistor is formed on the first branch line, and the gate of the second transistor is formed on the second branch line. A positive projection of the first branch line on the substrate does not overlap a positive projection of the first connection line on the substrate, and a positive projection of the second branch line on the substrate does not overlap a positive projection of the first connection line on the substrate, reducing the coupling capacitance between the first connection line and the first and second branch lines connected to the first scanning line, thereby reducing the mutual interference of signals between the gate of the driving transistor and the first connection line and the first and second branch lines, and improving the display effect of the display panel.

[0033] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0035] Figure 1 is a schematic structural diagram of a display device provided by an embodiment of the present invention;

[0036] Figure 2 is a schematic diagram of the circuit principle of a display panel provided by an embodiment of the present invention;

[0037] Figure 3 It is a schematic diagram of the layout of a display panel provided by an embodiment of the present invention;

[0038] Figure 4 It is a schematic diagram of the layout of the active layer of a display panel provided by an embodiment of the present invention;

[0039] Figure 5 It is a schematic diagram of the layout of the gate layer of a display panel provided by an embodiment of the present invention;

[0040] Figure 6 It is a schematic diagram of the layout of the first metal layer of a display panel provided by an embodiment of the present invention;

[0041] Figure 7 It is a schematic diagram of the layout of the second metal layer of a display panel provided by an embodiment of the present invention;

[0042] Figure 8 It is a schematic diagram of the layout of the third metal layer of a display panel provided by an embodiment of the present invention;

[0043] Figure 9 It is a schematic diagram of the layout of another display panel provided by an embodiment of the present invention;

[0044] Figure 10 It is a schematic diagram of the layout of the first metal layer of another display panel provided by an embodiment of the present invention;

[0045] Figure 11 It is a schematic diagram of the layout of the second metal layer of another display panel provided by an embodiment of the present invention;

[0046] Figure 12 It is a schematic diagram of the layout of yet another display panel provided by an embodiment of the present invention;

[0047] Figure 13 It is a schematic diagram of the layout of the second metal layer of yet another display panel provided by an embodiment of the present invention;

[0048] Figure 14 It is a schematic diagram of the layout of the third metal layer of yet another display panel provided by an embodiment of the present invention;

[0049] Figure 15 It is a schematic diagram of the structure of a display device provided by an embodiment of the present invention. Detailed implementation manners

[0050] To enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0051] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned accompanying drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0052] As mentioned in the background art, the structure of the pixel driving circuit of the display panel is becoming more and more complex, so that there is a coupling capacitance between the signal lines such as the scanning signal lines of the display panel and the gate of the driving transistor, which affects the display effect of the display panel. The inventor has found through research that since the trace connected to the gate of the driving transistor in the display panel has the same potential as the gate of the driving transistor, there will also be a coupling capacitance when the signal lines such as the scanning signal lines of the display panel overlap with the trace connected to the gate of the driving transistor, which affects the display effect of the display panel.

[0053] Figure 1 It is a schematic structural diagram of a display device provided by an embodiment of the present invention. Figure 2 It is a schematic diagram of the circuit principle of a display panel provided by an embodiment of the present invention. Figure 3 It is a schematic diagram of the layout of a display panel provided by an embodiment of the present invention. In combination with Figures 1 to 3, the display panel provided by the present invention includes a substrate 1; a plurality of scan lines Scan 1 to Scan n, which are disposed on the substrate 1; the scan lines include a first scan line Scan 2; a plurality of data lines Vdata 1 to Vdata n, which are located on the substrate 1; a plurality of pixel units 2 arranged in an array on the substrate 1; the pixel unit 2 includes: a driving transistor T1; a third transistor T3 connected between the gate of the driving transistor T1 and the first pole of the driving transistor T1; a second transistor T2 connected between the data line and the second pole of the driving transistor T1; a first connection line 3, the gate of the driving transistor T1 is connected to the third transistor T3 through the first connection line 3; a first branch line 4 and a second branch line 5 connected to the first scan line Scan 2; the gate of the third transistor T3 is formed on the first branch line 4, and the gate of the second transistor T2 is formed on the second branch line 5; the gate of the third transistor T3 is connected to the first scan line Scan 2 through the first branch line 4; the gate of the second transistor T2 is connected to the first scan line Scan 2 through the second branch line 5; the orthographic projection of the first branch line 4 on the substrate does not overlap with the orthographic projection of the first connection line 3 on the substrate; the orthographic projection of the second branch line 5 on the substrate does not overlap with the orthographic projection of the first connection line 3 on the substrate.

[0054] Specifically, referring to Figure 1 and Figure 2 , the display device 200 includes a display panel 100. The display device 200 may include an OLED (Organic light-emitting diode) display device, such as a terminal such as a smart phone, a tablet computer, or a wearable device. Figure 1 Exemplarily shows the setting of the display panel 100 in the display device 200.

[0055] The display panel 100 includes a plurality of pixel units 2, and the pixel unit 2 includes a light-emitting element D1 and its corresponding pixel circuit 21. The light-emitting element D1 may include light-emitting elements with different light-emitting colors. It should be noted that in this application, the light-emitting elements with red light-emitting color, green light-emitting color, and blue light-emitting color are taken as examples for illustration. The light-emitting element D1 may also include light-emitting elements of other colors, and no limitation is made here. The light-emitting element D1 is driven by the pixel circuit 21 to emit light. The pixel circuit 21 may adopt, for example, Figure 2 the pixel circuit shown.

[0056] The display panel 100 further includes an initialization line Vref. Each pixel circuit 10 is respectively connected to a first power supply line ELVDD, a second power supply line ELVSS, and the initialization line Vref. The first power supply line ELVDD is used to transmit a first voltage signal to the anode of the light-emitting element D1, and the first voltage signal is generally a high-level signal. The second power supply line ELVSS is used to transmit a second voltage signal to the cathode of the light-emitting element D1, and the second voltage signal is generally a low-level signal. In each pixel unit 2, the pixel circuit 21 includes a plurality of thin-film transistors and a storage capacitor. The thin-film transistors may include a driving transistor T1 and a switching transistor. The driving transistor T1 and the light-emitting element D1 are sequentially connected between the first power supply line ELVDD and the second power supply line ELVSS. The driving transistor T1 can generate a driving current to drive the light-emitting element D1 connected to the pixel circuit 21 to emit light, and the switching transistor mainly functions as a switch.

[0057] Combined with Figure 1 and Figure 2 , the display panel 100 may further include a plurality of scan lines Scan 1 - Scan n, a plurality of data lines Vdata 1 - Vdata n, a plurality of light-emitting control lines EM 1 - EM n, and a driving chip 300. The pixel circuit 21 is disposed in an area defined by the intersection of the scan line Scan and the data line Vdata. A scan signal is input to the corresponding pixel circuit 21 through the scan line. Under the action of the scan signal input by the scan line to which it is electrically connected, the pixel circuit 21 connects to the corresponding data line. The driving chip 300 inputs a data signal to the corresponding pixel circuit 21 through the data line. The voltage of the data signal corresponds to the driving voltage, which determines the light-emitting brightness of the light-emitting element D1, that is, determines the display gray level of the light-emitting element D1.

[0058] It should be noted that the driving transistor T1, the switching transistor, and the storage capacitor can form various forms of pixel circuits 21 with various connection relationships. Figure 2 The pixel circuit 21 shown is only an example. The pixel circuit 21 can also be other forms of pixel circuits, such as 7T1C pixel circuits and 8T2C pixel circuits, etc. Herein, T represents a transistor and C represents a capacitor. Figure 2 The case of the 7T1C pixel circuit is exemplarily shown, which does not limit the pixel circuit 21.

[0059] Combined with Figure 2 and Figure 3 , the pixel circuit 21 provided in this embodiment can correspond to Figure 1 a specific circuit structure of the pixel circuit 21 of the pixel unit 2 in the display panel 100 shown, such as a 7T1C pixel circuit. Combined with Figure 1 and Figure 2, the pixel circuit 21 includes a driving transistor T1, a fourth transistor T4, a seventh transistor T7, a second transistor T2, a third transistor T3, a fifth transistor T5, a sixth transistor T6, and a storage capacitor Cst. In the data writing stage, the scanning signal input by the first scanning line Scan 2 can control the second transistor T2 and the third transistor T3 to turn on, so as to write the data signal input by the data line Vdata into the second pole of the driving transistor T1.

[0060] Combined with Figure 2 and Figure 3 , the third transistor T3 is connected between the gate of the driving transistor T1 and the first pole of the driving transistor T1. The second transistor T2 is connected between the data line and the second pole of the driving transistor T1. The gate of the driving transistor T1 is connected to the third transistor T3 through the first connection line 3. The gate of the third transistor T3 is formed on the first branch line 4, and the gate of the second transistor T2 is formed on the second branch line 5. Such an arrangement facilitates the formation of the first branch line 4 and the second branch line 5 on the same layer, which is convenient for wiring, saves the process, and is beneficial to reducing the thickness of the display panel. The gate of the third transistor T3 is connected to the first scanning line Scan 2 through the first branch line 4, and the gate of the second transistor T2 is connected to the first scanning line Scan 2 through the second branch line 5. Such an arrangement facilitates connecting the gate of the third transistor T3 to the first scanning line Scan 2 through the first branch line 4 on the same layer as the gate of the third transistor T3, and connecting the gate of the second transistor T2 to the first scanning line Scan 2 through the second branch line 5 on the same layer as the gate of the second transistor T2. The first scanning line Scan 2 can transmit the scanning signal to the gates of the second transistor T2 and the third transistor T3 respectively.

[0061] See Figure 2 and Figure 3, the orthographic projection of the first branch line 4 on the substrate does not overlap with the orthographic projection of the first connection line 3 on the substrate. Since the signal change of the first connection line 3 connected to the gate of the driving transistor T1 will cause the potential fluctuation of the gate of the driving transistor T1. The change of the signal transmitted on the first branch line 4 connected to the first scan line Scan2 will affect the stability of the signal transmitted on the first scan line Scan2. The orthographic projection of the first connection line 3 connected to the gate of the driving transistor T1 on the substrate and the orthographic projection of the first branch line 4 connected to the first scan line Scan2 on the substrate do not overlap. Such a setting makes the first connection line 3 connected to the gate of the driving transistor T1, the first scan line Scan2 and the first branch line 4 have no vertically facing area, reducing the coupling capacitance between the first connection line 3 connected to the gate of the driving transistor T1 and the first branch line 4 connected to the first scan line Scan2, and further reducing the mutual interference of signals between the first connection line 3 connected to the gate of the driving transistor T1 and the first branch line 4 connected to the first scan line Scan2, improving the display effect of the display panel.

[0062] See Figure 2 and Figure 3 , the orthographic projection of the second branch line 5 on the substrate does not overlap with the orthographic projection of the first connection line 3 on the substrate. The orthographic projection of the first connection line 3 connected to the gate of the driving transistor T1 on the substrate and the orthographic projection of the second branch line 5 connected to the first scan line Scan2 on the substrate do not overlap. Such a setting makes the first connection line 3 connected to the gate of the driving transistor T1 and the second branch line 5 connected to the first scan line Scan2 have no vertically facing area, reducing the coupling capacitance between the first connection line 3 connected to the gate of the driving transistor T1 and the second branch line 5 connected to the first scan line Scan2, and further reducing the mutual interference of signals between the first connection line 3 connected to the gate of the driving transistor T1 and the second branch line 5 connected to the first scan line Scan2, improving the display effect of the display panel.

[0063] In the display panel provided in this embodiment, a third transistor is arranged to be connected between the gate of the driving transistor and the first pole of the driving transistor. A second transistor is connected between the data line and the second pole of the driving transistor. The gate of the driving transistor is connected to the third transistor through a first connection line. The gate of the third transistor is formed on the first branch line, and the gate of the second transistor is formed on the second branch line. The orthographic projection of the first branch line on the substrate does not overlap with the orthographic projection of the first connection line on the substrate, and the orthographic projection of the second branch line on the substrate does not overlap with the orthographic projection of the first connection line on the substrate, reducing the coupling capacitance between the first connection line and the first and second branch lines connected to the first scan line, thereby reducing the mutual interference of signals between the gate of the driving transistor and the first connection line and the first and second branch lines, and improving the display effect of the display panel.

[0064] Optionally, Figure 4 is a schematic diagram of the layout of the active layer of a display panel provided by an embodiment of the present invention. Figure 5 is a schematic diagram of the layout of the gate layer of a display panel provided by an embodiment of the present invention. Figure 6 is a schematic diagram of the layout of the first metal layer of a display panel provided by an embodiment of the present invention. Figure 7 is a schematic diagram of the layout of the second metal layer of a display panel provided by an embodiment of the present invention. Figure 8 is a schematic diagram of the layout of the third metal layer of a display panel provided by an embodiment of the present invention. On the basis of the above embodiment, in combination with Figures 2 to 8 , the orthographic projection of the first branch line 4 on the substrate does not overlap with the orthographic projection of the gate of the driving transistor T1 on the substrate; the orthographic projection of the second branch line 5 on the substrate does not overlap with the orthographic projection of the gate of the driving transistor T1 on the substrate; the orthographic projection of the first branch line 4 on the substrate does not overlap with the orthographic projection of the second branch line 5 on the substrate.

[0065] Specifically, the display panel includes an active layer, a gate layer, a first metal layer, a second metal layer, and a third metal layer that are sequentially stacked on one side of the substrate. The active layer can be a silicon substrate layer such as a P-Si layer. The gate layer is used to form the gates of the driving transistor T1 and the switching transistor. The pixel unit 2 further includes: a storage capacitor Cst, and the storage capacitor Cst includes a first electrode and a second electrode; the first electrode can be arranged on the same layer as the gate of the driving transistor T1, and the second electrode is arranged on the side of the first electrode away from the substrate. The first metal layer can be the film layer where the second electrode of the storage capacitor Cst is located. The second metal layer is arranged on the side of the first metal layer away from the substrate, and the second metal layer can include a scan line and a first connection line 3. The third metal layer is arranged on the side of the second metal layer away from the substrate, and the third metal layer can include a data line and a power line. It should be noted that the power line can be double-layer routed, Figure 7 and Figure 8Exemplarily, it is shown that the power line has a double-layer routing, and the power lines are respectively arranged on the second metal layer and the third metal layer. No limitation is made here.

[0066] By setting the orthographic projection of the first branch line 4 on the substrate not to overlap with the orthographic projection of the gate of the driving transistor T1 on the substrate, there is no perpendicular facing area between the first branch line 4 connected to the first scan line Scan 2 and the gate of the driving transistor T1, reducing the coupling capacitance between the first branch line 4 connected to the first scan line Scan 2 and the gate of the driving transistor T1, reducing the mutual interference of signals between the first branch line 4 connected to the first scan line Scan 2 and the gate of the driving transistor T1, and further improving the display effect of the display panel.

[0067] By setting the orthographic projection of the second branch line 5 on the substrate not to overlap with the orthographic projection of the gate of the driving transistor T1 on the substrate, there is no perpendicular facing area between the second branch line 5 connected to the first scan line Scan 2 and the gate of the driving transistor T1, reducing the coupling capacitance between the second branch line 5 connected to the first scan line Scan 2 and the gate of the driving transistor T1, reducing the mutual interference of signals between the second branch line 5 connected to the first scan line Scan2 and the gate of the driving transistor T1, and further improving the display effect of the display panel.

[0068] By setting the orthographic projection of the first branch line 4 on the substrate not to overlap with the orthographic projection of the second branch line 5 on the substrate, the first branch line 4 and the second branch line 5 are routed separately, facilitating the flexible arrangement of the connection lines between the first scan line Scan 2 and the gates of the second transistor T2 and the third transistor T3, and more conveniently reducing the coupling capacitance between the first scan line Scan 2 and the first branch line 4 and the second branch line 5 and the gate of the driving transistor T1, and further improving the display effect of the display panel.

[0069] Optionally, on the basis of the above embodiments, continue to combine Figures 2 to 8 , the gates of the third transistor T3 and the second transistor T2 are connected to the same first scan line Scan 2; the orthographic projection of the first scan line Scan 2 on the substrate does not overlap with the orthographic projection of the gate of the driving transistor T1 on the substrate; the orthographic projection of the first scan line Scan 2 on the substrate does not overlap with the orthographic projection of the first connection line 3 on the substrate.

[0070] Specifically, the same first scan line Scan 2 is connected to the gate of the third transistor T3 through the first branch line 4 and to the gate of the second transistor T2 through the second branch line 5. The scan signal is transmitted from the same first scan line Scan 2 to the gates of the third transistor T3 and the second transistor T2. By setting the orthographic projection of the first scan line Scan 2 on the substrate not to overlap with the orthographic projection of the gate of the driving transistor T1 on the substrate, the vertical facing area between the first scan line Scan 2 and the gate of the driving transistor T1 is avoided, the coupling capacitance between the first scan line Scan 2 and the gate of the driving transistor T1 is reduced, and the display effect of the display panel is further improved.

[0071] Since the first connection line 3 is connected to the gate of the driving transistor T1 and the first connection line 3 and the gate of the driving transistor T1 have the same potential, setting the orthographic projection of the first scan line Scan 2 on the substrate not to overlap with the orthographic projection of the first connection line 3 on the substrate can avoid the vertical facing area between the first scan line Scan 2 and the first connection line 3, reduce the coupling capacitance between the first scan line Scan 2 and the first connection line 3, and further improve the display effect of the display panel.

[0072] Optionally, on the basis of the above embodiments, continuing to combine Figures 2 to 4 , the display panel may further include: a plurality of initialization lines Vref, which are disposed on the substrate; a second connection line 6, on which a first pole and a second pole of the driving transistor T1 are formed; the pixel unit 2 further includes: a fourth transistor T4, the gate of the driving transistor T1 is connected to the first pole of the fourth transistor T4 through the first connection line 3 and the second connection line 6; the second pole of the fourth transistor T4 is connected to the initialization line Vref.

[0073] Specifically, a first pole and a second pole of the driving transistor T1 are formed on the second connection line 6. The second connection line 6 is fabricated on the same layer as the active layer. By adjusting the doping concentration of the P-Si layer, the wiring position of the second connection line 6 can be adjusted, which is convenient for making the wiring of the display panel more compact and reducing the thickness of the display panel.

[0074] The gate of the driving transistor T1 is connected to the first pole of the fourth transistor T4 through the first connection line 3 and the second connection line 6. The first connection line 3 and the second connection line 6 can be specifically connected through vias. In the initialization stage, the scan signal input by the scan line Scan 1 can control the fourth transistor T4 to conduct, so as to write the initialization signal input by the initialization line Vref into the storage capacitor Cst and the gate of the driving transistor T1.

[0075] Optionally, on the basis of the above embodiments, continuing to combine Figures 2 to 4, the orthographic projection of the first scan line Scan2 on the substrate does not overlap with the orthographic projection of the second connection line 6 on the substrate.

[0076] Specifically, since the second connection line 6 is connected to the first connection line 3, the second connection line 6 and the first connection line 3 have the same potential. Since the first connection line 3 connected to the second connection line 6 is also connected to the gate of the driving transistor T1, the second connection line 6 and the gate of the driving transistor T1 have the same potential. By setting the orthographic projection of the first scan line Scan 2 on the substrate not to overlap with the orthographic projection of the second connection line 6 on the substrate, the coupling capacitance between the first scan line Scan 2 and the second connection line 6 can be reduced, and the mutual interference of signals between the first scan line Scan 2 and the gate of the driving transistor T1 can be further reduced, further improving the display effect of the display panel.

[0077] Optionally, Figure 9 is a schematic diagram of the layout of another display panel provided by an embodiment of the present invention. Figure 10 is a schematic diagram of the layout of the first metal layer of another display panel provided by an embodiment of the present invention. Figure 11 is a schematic diagram of the layout of the second metal layer of another display panel provided by an embodiment of the present invention. On the basis of the above embodiment, continue to combine Figure 2 , Figure 4 , Figure 5 , Figures 8 to 11 , the display panel may further include: a plurality of power supply lines ELVDD, the power supply lines ELVDD are disposed on the substrate; a third connection line 7, the third connection line 7 is disposed on the same layer as the second electrode of the storage capacitor Cst, and the third connection line 7 is connected to the power supply line ELVDD; the third connection line 7 is used to transmit a driving power signal to the pixel unit 2; the first scan line Scan 2 is disposed on a side of the third connection line 7 away from the substrate; the second connection line 6 includes a first region N1, wherein the orthographic projection of the first scan line Scan 2 on the second connection line 6 overlaps with at least a part of the second connection line 6 and overlaps in the first region N1; the orthographic projection of the third connection line 7 on the substrate covers the orthographic projection of the first region N1 of the second connection line 6 on the substrate. It should be noted that Figure 9 exemplarily shows the situation where the orthographic projection of the first scan line Scan 2 on the second connection line 6 overlaps with at least a part of the second connection line 6 and overlaps in the first region N1, Figure 4 exemplarily shows applicable to Figure 9 a schematic diagram of the layout of the active layer of the display panel in Figure 6 exemplarily shows applicable to Figure 9 a schematic diagram of the layout of the first metal layer of the display panel in

[0078] Specifically, the third connection line 7 is connected to the power line ELVDD, so that the third connection line 7 and the power line ELVDD have the same potential. The third connection line 7 and the second electrode of the storage capacitor Cst are arranged in the same layer, and the third connection line 7 and the second electrode of the storage capacitor Cst can be fabricated in the same layer, saving the manufacturing process of the display panel and being beneficial to thinning the display panel. When the positive projection of the first scan line Scan 2 on the second connection line 6 at least partially overlaps the second connection line 6 and overlaps in the first region N1, by setting the positive projection of the third connection line 7 on the substrate to cover the positive projection of the first region N1 of the second connection line 6 on the substrate, the first region N1 where the positive projection of the first scan line Scan 2 on the second connection line 6 overlaps the second connection line 6 is between the first scan line Scan 2 and the second connection line 6 due to the third connection line 7 with the same potential as the power line ELVDD. The third connection line 7 with the same potential as the power line ELVDD can play a good shielding role to reduce the coupling capacitance between the first scan line Scan 2 and the second connection line 6 in the first region where the positive projection of the first scan line Scan 2 on the second connection line 6 overlaps the second connection line 6. Since the second connection line 6 is connected to the gate of the driving transistor T1 through the first connection line 3, such a setting can enable the third connection line 7 to effectively shield the mutual interference of signals between the second connection line 6 and the gate of the driving transistor T1 and the first scan line Scan 2, further improving the display effect of the display panel.

[0079] Optionally, on the basis of the above embodiments, continue to combine Figure 3 、 Figure 7 and Figure 8 , the first scan line Scan 2 and the data line Vdata are arranged on the side of the second electrode of the storage capacitor Cst away from the substrate; the first scan line Scan 2 and the data line Vdata are arranged in different layers.

[0080] Specifically, such a setting facilitates the hierarchical arrangement of the first scan line Scan 2 and the data line Vdata, is convenient for routing, reduces the mutual interference between the signals transmitted on the first scan line Scan 2 and the data line Vdata, and further improves the display effect of the display panel. Figure 7 Exemplarily shows the case where the first scan line Scan 2 extends along the X direction. The X direction can be the width direction of the display panel. Figure 8 Exemplarily shows the case where the data line Vdata extends along the Y direction. The Y direction can be the length direction of the display panel.

[0081] Optionally, on the basis of the above embodiments, continue to combine Figure 3 and Figure 7, the first connection line 3 is disposed on a side of the second electrode of the storage capacitor Cst away from the substrate; the first connection line 3 is connected to the gate of the driving transistor T1 through a via; the first scan line Scan 2 is disposed on the same layer as the first connection line 3; or, the first scan line Scan 2 is disposed on a side of the first connection line 3 away from the substrate.

[0082] Specifically, the first connection line 3 is disposed on a side of the second electrode of the storage capacitor Cst away from the substrate, and the first connection line 3 is connected to the gate of the driving transistor T1 through a via. By arranging the first connection line 3 in the thickness direction of the display panel, the space in the X direction or Y direction of the display panel can be saved. Figure 7 An exemplary case where the first connection line 3 and the first scan line Scan 2 are fabricated on the same layer is shown.

[0083] Figure 12 It is a schematic diagram of the layout of another display panel provided by an embodiment of the present invention. Figure 13 It is a schematic diagram of the layout of the second metal layer of another display panel provided by an embodiment of the present invention. Figure 14 It is a schematic diagram of the layout of the third metal layer of another display panel provided by an embodiment of the present invention. On the basis of the above embodiments, Figures 12 to 14 , an exemplary case where the first scan line Scan 2 is disposed on a side of the first connection line 3 away from the substrate is shown. No limitation is made here.

[0084] Optionally, on the basis of the above embodiments, continuing to combine Figure 8 , Figure 9 and Figure 11 , the power supply line ELVDD may include a first wiring layer and a second wiring layer. The first wiring layer is disposed on the same layer as the first connection line 3; the second wiring layer is disposed on a side of the first connection line 3 away from the substrate; the power supply line ELVDD includes a second region N2, and the orthographic projection of the first scan line Scan 2 on the power supply line ELVDD overlaps with the power supply line ELVDD in the second region N2; the power supply line ELVDD in the second region includes the first wiring layer or the second wiring layer, and the power supply line ELVDD and the first scan line Scan 2 are disposed on different layers. It should be noted that, Figure 11 An exemplary illustration of Figure 9 the first wiring layer of the power supply line ELVDD shown in Figure 8 An exemplary illustration of Figure 9 the second wiring layer of the power supply line ELVDD in

[0085] Specifically, the power supply line ELVDD is provided with a first wiring layer and a second wiring layer, which can increase the cross-sectional area of the power supply line ELVDD, reduce the line resistance of the power supply line ELVDD, and reduce the voltage drop of the power supply line ELVDD. The first wiring layer is arranged on the same layer as the first connection line 3; the second wiring layer is arranged on the side of the first connection line 3 away from the substrate. Such an arrangement can avoid increasing the thickness of the display panel and facilitate the thinning of the display panel.

[0086] The positive projection of the first scan line Scan 2 on the power supply line ELVDD overlaps with the power supply line ELVDD in the second region N2 of the power supply line ELVDD. The power supply line ELVDD in the second region N2 is single-layer wired and the power supply line ELVDD is arranged on a different layer from the first scan line Scan2. Such an arrangement neither increases the thickness of the display panel nor increases the thickness of the display panel, and the power supply line ELVDD outside the second region N2 can be arranged as double-layer wiring, reducing the line resistance of the power supply line ELVDD and reducing the voltage drop of the power supply signal transmitted on the power supply line ELVDD, further improving the display effect of the display panel and improving the layout rationality of the pixel units 2 of the display panel.

[0087] It should be noted that, for the convenience of viewing the relationship between the wirings of different layers and the pixel circuit 21, Figures 3 to 14 the positions of the driving transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are exemplarily shown, and no limitation is made here.

[0088] Figure 15 It is a schematic structural diagram of a display device provided by an embodiment of the present invention. An embodiment of the present invention provides a display device 200, including the display panel 100 proposed in any of the above embodiments, and having the beneficial effects of the display panel proposed in any of the above embodiments, which will not be elaborated here. The display device provided by the embodiment of the present invention may include terminals such as mobile phones, tablet computers, and wearable devices.

[0089] It should be understood that the various forms of processes shown above can be reordered, added, or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved, and no limitation is made herein.

[0090] The above specific embodiments do not constitute a limitation to the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A display panel, characterized in that, the display panel includes: a substrate; a plurality of scan lines disposed on the substrate; the scan lines include a first scan line; a plurality of data lines located on the substrate; a plurality of pixel units arranged in an array on the substrate; the pixel unit includes: a driving transistor; a third transistor connected between the gate of the driving transistor and the first pole of the driving transistor; a second transistor connected between the data line and the second pole of the driving transistor; a first connection line, the gate of the driving transistor is connected to the third transistor through the first connection line; a first branch line and a second branch line connected to the first scan line; the gate of the third transistor is formed on the first branch line, and the gate of the second transistor is formed on the second branch line; the orthographic projection of the first branch line on the substrate does not overlap with the orthographic projection of the first connection line on the substrate; the orthographic projection of the second branch line on the substrate does not overlap with the orthographic projection of the first connection line on the substrate.

2. The display panel according to claim 1, characterized in that, the orthographic projection of the first branch line on the substrate does not overlap with the orthographic projection of the gate of the driving transistor on the substrate; the orthographic projection of the second branch line on the substrate does not overlap with the orthographic projection of the gate of the driving transistor on the substrate; the orthographic projection of the first branch line on the substrate does not overlap with the orthographic projection of the second branch line on the substrate.

3. The display panel according to claim 1, characterized in that, the gates of the third transistor and the second transistor are connected to the same first scan line; the orthographic projection of the first scan line on the substrate does not overlap with the orthographic projection of the gate of the driving transistor on the substrate; the orthographic projection of the first scan line on the substrate does not overlap with the orthographic projection of the first connection line on the substrate.

4. The display panel according to claim 1, characterized in that, the display panel further includes: a plurality of initialization lines disposed on the substrate; a second connection line, the first pole and the second pole of the driving transistor are formed on the second connection line; the pixel unit further includes: a fourth transistor, the gate of the driving transistor is connected to the first pole of the fourth transistor through the first connection line and the second connection line; the second pole of the fourth transistor is connected to the initialization line.

5. The display panel according to claim 4, characterized in that, the orthographic projection of the first scan line on the substrate does not overlap with the orthographic projection of the second connection line on the substrate.

6. The display panel according to claim 4, characterized in that, the pixel unit further includes: a storage capacitor, the storage capacitor includes a first electrode and a second electrode; the first electrode is disposed on the same layer as the gate of the driving transistor, and the second electrode is disposed on a side of the first electrode away from the substrate.

7. The display panel according to claim 6, characterized in that, The display panel further includes: A plurality of power lines disposed on the substrate; A third connection line, which is disposed on the same layer as the second electrode, and the third connection line is connected to the power line; the third connection line is used to transmit a driving power signal to the pixel unit; The first scanning line is disposed on a side of the third connection line away from the substrate; The second connection line includes a first region, wherein a positive projection of the first scanning line on the second connection line overlaps at least a part of the second connection line and overlaps in the first region; A positive projection of the third connection line on the substrate covers a positive projection of the first region of the second connection line on the substrate.

8. The display panel according to claim 7, wherein, The first scanning line and the data line are disposed on a side of the second electrode of the storage capacitor away from the substrate; The first scanning line and the data line are disposed on different layers.

9. The display panel according to claim 7, wherein, The first connection line is disposed on a side of the second electrode of the storage capacitor away from the substrate; the first connection line is connected to the gate of the driving transistor through a via; The first scanning line and the first connection line are disposed on the same layer; or, The first scanning line is disposed on a side of the first connection line away from the substrate.

10. The display panel according to claim 9, wherein, The power line includes a first wiring layer and a second wiring layer, the first wiring layer is disposed on the same layer as the first connection line; the second wiring layer is disposed on a side of the first connection line away from the substrate; The power line includes a second region, and a positive projection of the first scanning line on the power line overlaps the power line in the second region; The power line in the second region includes the first wiring layer or the second wiring layer, and the power line and the first scanning line are disposed on different layers.

11. A display device, wherein, It includes: The display panel according to any one of claims 1-10.

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