High electron mobility transistor and manufacturing method thereof

Abstract

The present invention discloses a high electron mobility transistor and a method for manufacturing the same. The method for manufacturing the high electron mobility transistor comprises the following steps: first forming a buffer layer on a substrate, then performing an in-situ doping process to form a first fluorine-containing layer on the buffer layer, forming a barrier layer on the first fluorine-containing layer, forming a second fluorine-containing layer on the barrier layer, forming a gate electrode on the second fluorine-containing layer, and then forming a source electrode and a drain electrode on both sides of the gate electrode.

Description

Technical Field

[0001] The invention relates to a high electron mobility transistor and a manufacturing method thereof. Background Art

[0002] High-electron-mobility transistors (HEMTs) based on gallium nitride (GaN) materials possess numerous advantages in electronic, mechanical, and chemical properties, including wide bandgap, high breakdown voltage, high electron mobility, large elastic modulus, high piezoelectric and piezoresistive coefficients, and chemical passivity. These advantages make GaN-based materials suitable for the fabrication of devices in applications such as high-brightness light-emitting diodes, power switching devices, regulators, battery protectors, panel display drivers, and communications components. Summary of the Invention

[0003] One embodiment of the present invention discloses a method for fabricating a high electron mobility transistor. The method includes first forming a buffer layer on a substrate, then performing an in-situ doping process to form a first fluorine-containing layer on the buffer layer, then forming a barrier layer on the first fluorine-containing layer, then forming a second fluorine-containing layer on the barrier layer, then forming a gate electrode on the second fluorine-containing layer, and finally forming a source electrode and a drain electrode on either side of the gate electrode.

[0004] Another embodiment of the present invention discloses a high electron mobility transistor, which mainly includes a buffer layer disposed on a substrate, a first fluorine-containing layer disposed on the buffer layer, a barrier layer disposed on the first fluorine-containing layer, a gate electrode disposed on the barrier layer, and a source electrode and a drain electrode disposed on both sides of the gate electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 Schematic diagram of the structure of a high electron mobility transistor according to an embodiment of the present invention;

[0006] Figure 2 FIG. 1 is a schematic structural diagram of a high electron mobility transistor according to an embodiment of the present invention.

[0007] Description of main component symbols

[0008] 12: Base

[0009] 14: Nuclear crystal layer

[0010] 16: buffer layer

[0011] 18: Unintentionally doped buffer layer

[0012] 20: Barrier layer

[0013] 22: Gate structure

[0014] 24: Gate dielectric layer

[0015] 26: Gate electrode

[0016] 28: Source electrode

[0017] 30: drain electrode

[0018] 32: Fluorine-containing layer

[0019] 34: Fluorine-containing layer DETAILED DESCRIPTION

[0020] Please refer to Figure 1 , Figure 1 FIG. 1 is a schematic structural diagram of a high electron mobility transistor according to an embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, such as a substrate composed of silicon, silicon carbide, or aluminum oxide (or sapphire). The substrate 12 can be a single-layer substrate, a multi-layer substrate, a gradient substrate, or a combination thereof. According to other embodiments of the present invention, the substrate 12 can also include a silicon-on-insulator (SOI) substrate.

[0021] Then, a selective nucleation layer 14 and a buffer layer 16 are formed on the surface of the substrate 12. In one embodiment, the nucleation layer 14 preferably comprises aluminum nitride, and the buffer layer 16 comprises a Group III-V semiconductor such as gallium nitride or, more specifically, carbon-doped gallium nitride. The thickness of the buffer layer 16 may be between 0.5 microns and 10 microns. In one embodiment, the buffer layer 16 may be formed on the substrate 12 using a molecular-beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or a combination thereof.

[0022] It should be noted that in this embodiment, an in-situ doping process is preferably performed when forming the buffer layer 16 to form a fluorine-containing layer 32 on the surface of the buffer layer 16, wherein the fluorine concentration in the fluorine-containing layer 32 is preferably about 1.0×10 15ions per square centimeter, and the thickness of the fluorine-containing layer 32 is preferably approximately equal to or less than one-third of the overall thickness of the buffer layer 16. Additionally, in this embodiment, the buffer layer 16 can be optionally composed of a graded buffer layer or can be composed of a superlattice buffer layer. If the buffer layer 16 is composed of a graded buffer layer, the buffer layer 16 preferably includes a plurality of graded aluminum gallium nitride (AlGaN) layers, and if the buffer layer 16 is composed of a superlattice buffer layer, the buffer layer 16 preferably includes a plurality of carbon-doped gallium nitride layers.

[0023] Next, a non-intentionally doped buffer layer 18 is formed on the surface of the buffer layer 16 or the previously formed fluorine-containing layer 32. In this embodiment, the non-intentionally doped buffer layer 18 preferably includes a III-V semiconductor, such as gallium nitride or more specifically non-intentionally doped gallium nitride. In one embodiment, the non-intentionally doped buffer layer 18 can be formed on the buffer layer 16 by using a molecular-beam epitaxy (MBE) fabrication process, a metal organic chemical vapor deposition (MOCVD) fabrication process, a chemical vapor deposition (CVD) fabrication process, a hydride vapor phase epitaxy (HVPE) fabrication process, or a combination of the above.

[0024] Subsequently, a barrier layer 20 is formed on the surface of the non-intentionally doped buffer layer 18. In this embodiment, the barrier layer 20 preferably includes a III-V semiconductor such as N-type aluminum gallium nitride (Al x Ga 1-x N), where 0 < x < 1. The barrier layer 20 preferably includes an epitaxial layer formed by an epitaxial growth fabrication process, and the barrier layer 20 can include dopants of silicon or germanium. Similar to the manner of forming the buffer layer 16 and the non-intentionally doped buffer layer 18 as described above, the barrier layer 20 can be formed on the non-intentionally doped buffer layer 18 by using a molecular-beam epitaxy (MBE) fabrication process, a metal organic chemical vapor deposition (MOCVD) fabrication process, a chemical vapor deposition (CVD) fabrication process, a hydride vapor phase epitaxy (HVPE) fabrication process, or a combination of the above.

[0025] A gate dielectric layer and a gate material layer are then sequentially formed on the surface of the barrier layer 20. A photolithography and etching process is then used to remove portions of the gate material layer and the gate dielectric layer to form a gate structure 22 on the surface of the barrier layer 20. The gate structure 22 preferably includes a patterned gate dielectric layer 24 and a gate electrode 26. In this embodiment, the lower portion of the gate electrode 26 may comprise a semiconductor material such as p-type gallium nitride, while the upper portion of the gate electrode 26 preferably comprises a metal, such as a Schottky metal such as gold, silver, or platinum. The gate dielectric layer 24 may comprise materials such as silicon oxide, aluminum nitride, or aluminum oxide.

[0026] A source electrode 28 and a drain electrode 30 are then formed on both sides of the gate electrode 26. In this embodiment, the source electrode 28 and the drain electrode 30 are preferably made of metal. However, unlike the upper portion of the gate electrode 26, which is made of Schottky metal, the source electrode 28 and the drain electrode 30 are preferably made of ohmic contact metal. According to one embodiment of the present invention, the source electrode 28 and the drain electrode 30 may each comprise titanium, aluminum, tungsten, palladium, or a combination thereof. In some embodiments, a portion of the barrier layer 20 on both sides of the gate electrode 26 may be removed by photolithography and etching to form a recess. Electrode material is then formed in the recess by electroplating, sputtering, resistance heating evaporation, electron beam evaporation, physical vapor deposition (PVD), chemical vapor deposition (CVD), or a combination thereof. The electrode material is then patterned by etching to form the source electrode 28 and the drain electrode 30.

[0027] Please refer to Figure 2 , Figure 2 A schematic structural diagram of a high electron mobility transistor according to an embodiment of the present invention is disclosed. Figure 2 As shown, compared to the previous embodiment in which the gate structure 22 is directly fabricated after the barrier layer 20 is formed, the present invention can optionally perform another in-situ doping process when forming the barrier layer 20 to form another fluorine-containing layer 34 on the surface of the barrier layer 20. The fluorine concentration in the fluorine-containing layer 34 can be equal to or different from the fluorine concentration in the fluorine-containing layer 32, for example but not limited to preferably about 1.0×10 15 ions / cm2, and the thickness of the fluorine-containing layer 34 is preferably about one-third of the entire thickness of the barrier layer 20.

[0028] Subsequently, a portion of the fluorine-containing layer 34 may be removed using a photolithography and etching process before the subsequent gate structure 22 is fabricated. Alternatively, the aforementioned gate dielectric layer and gate material layer may be directly formed on the surface of the fluorine-containing layer 34, and then a photolithography and etching process may be used to remove portions of the gate material layer, the gate dielectric layer, and the fluorine-containing layer 34 to form the gate structure 22 on the patterned surface of the fluorine-containing layer 34. These methods are all within the scope of the present invention. Structurally, the top of the fluorine-containing layer 34 may be aligned with or slightly higher than the tops of the barrier layers 20 on either side. The width of the fluorine-containing layer 34 may be equal to or greater than the width of the gate structure 22 above it, and the left and right sidewalls of the fluorine-containing layer 34 may or may not be aligned with the left and right sidewalls of the gate structure 22. Furthermore, since the fluorine-containing layer 34 is preferably patterned using a photolithography and etching process, its width is preferably smaller than the width of the fluorine-containing layer 32 disposed on the surface of the buffer layer 16.

[0029] Generally speaking, due to the different band gaps of the materials used in the buffer and barrier layers, the interface between the buffer and barrier layers preferably forms a heterojunction. The energy bands at the heterojunction bend, and a quantum well forms deep within the conduction band bend. This confines electrons generated by the piezoelectric effect within the quantum well, forming a channel region 58 or a two-dimensional electron gas (2DEG) at the interface between the buffer and barrier layers, thereby generating an on-state current.

[0030] One current method for fabricating a high electron mobility transistor (HEMT) to switch from a normally on mode to a normally off mode is to first form a hard mask on a barrier layer, pattern the hard mask to form an opening exposing the barrier layer surface, and then directly implant fluorine ions into the barrier layer using an ion implantation process. The implanted fluorine ions preferably attract a free electron and become a negative fixed charge, modulating its local potential and thereby depleting the 2DEG. However, given that the current fluorine ion implantation method is difficult to control in terms of depth, which can affect device resistance, the present invention preferably employs an in-situ doping method to implant fluorine ions into the surface of the buffer layer 16 and / or barrier layer 20, thereby improving the uniformity of the formed fluorine-containing layer and reducing device flicker noise.

[0031] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A method for manufacturing a high electron mobility transistor (HEMT), characterized in that: Include: forming a buffer layer on the substrate; forming a first fluorine-containing layer on the buffer layer, wherein the width of the first fluorine-containing layer is the same as that of the buffer layer; forming a barrier layer on the first fluorine-containing layer; forming a gate electrode on the barrier layer; as well as forming a source electrode and a drain electrode on both sides of the gate electrode, The width of the first fluorine-containing layer and the width of the buffer layer both refer to the width in the direction from the source electrode to the drain electrode. 2 . The method according to claim 1 , further comprising performing an in-situ doping process to form the first fluorine-containing layer.

3. The method of claim 1, further comprising: forming an unintentionally doped buffer layer on the buffer layer; and The barrier layer is formed on the non-intentionally doped buffer layer. The method of claim 1 , wherein the buffer layer comprises a Group III-V semiconductor. The method of claim 1 , wherein the buffer layer comprises a gradient buffer layer. The method of claim 5 , wherein the buffer layer comprises a plurality of graded aluminum gallium nitride (AlGaN) layers. The method of claim 1 , wherein the buffer layer comprises a superlattice buffer layer. 8 . The method of claim 7 , wherein the buffer layer comprises a plurality of carbon-doped gallium nitride layers.

9. The method of claim 1, further comprising: forming a second fluorine-containing layer on the barrier layer; patterning the second fluorine-containing layer; and The gate electrode is formed on the second fluorine-containing layer.

10. The method of claim 1, wherein the barrier layer comprises aluminum gallium nitride (Al x Ga 1-x N).

11. A high electron mobility transistor (HEMT), characterized in that: Include: a buffer layer disposed on the substrate; a first fluorine-containing layer disposed on the buffer layer, wherein the width of the first fluorine-containing layer is the same as that of the buffer layer; a barrier layer disposed on the first fluorine-containing layer; a gate electrode disposed on the barrier layer; and The source electrode and the drain electrode are provided on both sides of the gate electrode. The width of the first fluorine-containing layer and the width of the buffer layer both refer to the width in the direction from the source electrode to the drain electrode.

12. The high electron mobility transistor according to claim 11, further comprising: an unintentionally doped buffer layer disposed on the buffer layer; and The barrier layer is disposed on the non-intentionally doped buffer layer. 13 . The high electron mobility transistor of claim 11 , wherein the buffer layer comprises a Group III-V semiconductor. The high electron mobility transistor of claim 11 , wherein the buffer layer comprises a gradient buffer layer. 15 . The high electron mobility transistor of claim 14 , wherein the buffer layer comprises a plurality of gradient aluminum gallium nitride (AlGaN) layers. The high electron mobility transistor of claim 11 , wherein the buffer layer comprises a superlattice buffer layer. 17 . The high electron mobility transistor of claim 16 , wherein the buffer layer comprises a plurality of carbon-doped gallium nitride layers. 18 . The high electron mobility transistor according to claim 11 , further comprising a second fluorine-containing layer disposed between the barrier layer and the gate electrode. 19 . The high electron mobility transistor of claim 18 , wherein a width of the first fluorine-containing layer is greater than a width of the second fluorine-containing layer.

20. The high electron mobility transistor of claim 11, wherein the barrier layer comprises aluminum gallium nitride (AlGaN). x Ga 1- x N).

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