An enhanced gallium oxide power transistor and method of fabrication

Abstract

The application relates to an enhanced gallium oxide power transistor and a manufacturing method, the power transistor comprising a beta-Ga2O3 substrate, a beta-Ga2O3 unintentionally doped layer, a p-type NiOx buffer layer, an n-type beta-Ga2O3 channel layer, a p-type NiOx cap layer, a source electrode, a drain electrode and a gate electrode, wherein the beta-Ga2O3 substrate, the beta-Ga2O3 unintentionally doped layer, the p-type NiOx buffer layer and the n-type beta-Ga2O3 channel layer are stacked in sequence; the source electrode is located at one end of the n-type beta-Ga2O3 channel layer, the drain electrode is located at the other end of the n-type beta-Ga2O3 channel layer; the p-type NiOx cap layer is located on the n-type beta-Ga2O3 channel layer and between the source electrode and the drain electrode; and the gate electrode is located on the p-type NiOx cap layer. In the power transistor, a pn junction is formed between the p-type NiOx buffer layer and the upper n-type beta-Ga2O3 channel layer, which can prevent impurity ions in the beta-Ga2O3 unintentionally doped layer from penetrating into the channel layer, reduce the compensation effect of the impurity ions penetrating into the channel layer, improve the electron mobility of the channel layer, and improve the electron concentration in the channel layer and the current density of the device.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of microelectronics technology, and particularly relates to an enhanced gallium oxide power transistor and a manufacturing method. BACKGROUND

[0002] Since the beta-Ga2O3 material has an ultra-wide band gap and a high breakdown field strength, the power device made of beta-Ga2O3 has the characteristics of high voltage resistance and high power, and has the potential to be applied in the field of power electronics. In recent years, many scholars have conducted research on beta-Ga2O3 crystal materials and power devices.

[0003] However, it is difficult to form p-type doping of gallium oxide material, which seriously restricts the implementation of gallium oxide-based enhancement devices. At the same time, the unintentionally doped (UID) layer in the material layer usually has impurity ions, which have a high probability of penetrating into the channel layer during actual operation of the device, resulting in a decrease in the electron mobility and current density of the device channel. Therefore, it is necessary to improve the device current density and mobility of the gallium oxide enhancement power transistor. SUMMARY

[0004] In order to solve the above problems existing in the prior art, the present application provides an enhanced gallium oxide power transistor and a manufacturing method. The technical problem to be solved by the present application is solved by the following technical scheme:

[0005] The embodiment of the present application provides an enhanced gallium oxide power transistor, which comprises a beta-Ga2O3 substrate, a beta-Ga2O3 unintentionally doped layer, a p-type NiOx buffer layer, an n-type beta-Ga2O3 channel layer, a p-type NiOx cap layer, a source electrode, a drain electrode and a gate electrode, wherein

[0006] The beta-Ga2O3 substrate, the beta-Ga2O3 unintentionally doped layer, the p-type NiOx buffer layer and the n-type beta-Ga2O3 channel layer are stacked in sequence;

[0007] The source electrode is located at one end of the n-type beta-Ga2O3 channel layer, and the drain electrode is located at the other end of the n-type beta-Ga2O3 channel layer;

[0008] The p-type NiOx cap layer is located on the n-type beta-Ga2O3 channel layer and between the source electrode and the drain electrode;

[0009] The gate electrode is located on the p-type NiOx cap layer.

[0010] In an embodiment of the present application, the doping element of the beta-Ga2O3 substrate comprises Fe.

[0011] In one embodiment of the present application, the thickness of the β-Ga2O3 unintentionally doped layer is 100-500 nm, and the carrier concentration is 1x10 14 cm -3 -1x10 16 cm -3 .

[0012] In one embodiment of the present application, the thickness of the p-type NiOx buffer layer is 50-150 nm, and the p-type doping concentration is 1x10 14 cm -3 -1x10 18 cm -3 .

[0013] In one embodiment of the present application, the thickness of the n-type β-Ga2O3 channel layer is 200-600 nm, and the doping concentration is 1x10 17 cm -3 -1x10 19 cm -3 .

[0014] In one embodiment of the present application, the thickness of the p-type NiOx cap layer is 50-150 nm, and the p-type doping concentration is 1x10 14 cm -3 -1x10 18 cm -3 .

[0015] Another embodiment of the present application provides a method for manufacturing an enhanced gallium oxide power transistor, comprising the steps of:

[0016] growing a β-Ga2O3 unintentionally doped layer on a β-Ga2O3 substrate;

[0017] growing a p-type NiOx buffer layer on the β-Ga2O3 unintentionally doped layer;

[0018] growing an n-type β-Ga2O3 channel layer on the p-type NiOx buffer layer;

[0019] growing a p-type NiOx material on the n-type β-Ga2O3 channel layer, and selectively etching the p-type NiOx material outside the gate region to expose the n-type β-Ga2O3 channel layer, forming a p-type NiOx cap layer;

[0020] preparing a source electrode and a drain electrode on the n-type β-Ga2O3 channel layer, such that the source electrode is located at one end of the n-type β-Ga2O3 channel layer, the drain electrode is located at the other end of the n-type β-Ga2O3 channel layer, and the p-type NiOx cap layer is located between the source electrode and the drain electrode;

[0021] A gate electrode is prepared on the p-type NiOx cap layer.

[0022] In an embodiment of the present application, the thickness of the β-Ga2O3 unintentionally doped layer is 100-500 nm, and the carrier concentration is 1x10 14 cm -3 -1x10 16 cm -3 .

[0023] In an embodiment of the present application, the thickness of the p-type NiOx buffer layer is 50-150 nm, and the p-type doping concentration is 1x10 14 cm -3 -1x10 18 cm -3 .

[0024] In an embodiment of the present application, the thickness of the n-type β-Ga2O3 channel layer is 200-600 nm, and the doping concentration is 1x10 17 cm -3 -1x10 19 cm -3 .

[0025] Compared with the prior art, the present application has the following advantages:

[0026] 1. In the enhancement-mode gallium oxide power transistor of the present application, a pn junction is formed between the p-type NiOx buffer layer and the upper n-type β-Ga2O3 channel layer, which prevents the impurity ions in the β-Ga2O3 unintentionally doped layer from penetrating into the channel layer, reduces the compensation effect of the impurity ions penetrating into the channel layer, improves the electron mobility of the channel layer, and increases the electron concentration in the channel layer and the current density of the device.

[0027] 2. The present application introduces a p-type NiOx cap layer to positively shift the threshold voltage of the device, realizes an enhancement-mode device, and solves the problem of excessive negative threshold voltage of the current depletion-mode gallium oxide power transistor. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 FIG. 1 is a structural schematic diagram of an enhancement-mode gallium oxide power transistor according to an embodiment of the present application;

[0029] Figures 2a-2g FIG. 2 is a process schematic diagram of a manufacturing method of an enhancement-mode gallium oxide power transistor according to an embodiment of the present application. DETAILED DESCRIPTION

[0030] The present application will be further described in detail below in conjunction with specific embodiments, but the embodiments of the present application are not limited thereto.

[0031] Embodiment One

[0032] See Figure 1 , Figure 1 A structure diagram of an enhanced gallium oxide power transistor provided by an embodiment of the present application.

[0033] The enhanced gallium oxide power transistor comprises a β-Ga2O3 substrate 1, a β-Ga2O3 unintentionally doped layer 2, a p-type NiOx buffer layer 3, an n-type β-Ga2O3 channel layer 4, a p-type NiOx cap layer 5, a source electrode 6, a drain electrode 7, and a gate electrode 8. The β-Ga2O3 substrate 1, the β-Ga2O3 unintentionally doped layer 2, the p-type NiOx buffer layer 3, and the n-type β-Ga2O3 channel layer 4 are stacked in sequence. The source electrode 6 is located at one end of the n-type β-Ga2O3 channel layer 4, and the drain electrode 7 is located at the other end of the n-type β-Ga2O3 channel layer 4. The p-type NiOx cap layer 5 is located on the n-type β-Ga2O3 channel layer 4 and between the source electrode 6 and the drain electrode 7. The gate electrode 8 is located on the p-type NiOx cap layer 5.

[0034] Specifically, the band gap of the p-type NiOx buffer layer 3 is about 3.7 eV, and the band gap of Ga2O3 is about 4.8 eV. The band gaps of the two are similar, which can ensure that the band difference of the heterojunction is small and a potential well is not easily formed.

[0035] Specifically, the p-type NiOx cap layer 5, the source electrode 6, and the drain electrode 7 are all located on the n-type β-Ga2O3 channel layer 4. The p-type NiOx cap layer 5 is located in the middle of the n-type β-Ga2O3 channel layer 4, the source electrode 6 is located at one end of the n-type β-Ga2O3 channel layer 4, and the drain electrode 7 is located at the other end of the n-type β-Ga2O3 channel layer 4. Moreover, the p-type NiOx cap layer 5 does not contact the source electrode 6 and the drain electrode 7.

[0036] In one specific embodiment, the doping element of the β-Ga2O3 substrate 1 includes Fe, and the crystal direction can be a (010) crystal direction or a (100) crystal direction, which is not limited in the present embodiment. The thickness of the β-Ga2O3 unintentionally doped layer 2 is 100-500 nm, the carrier concentration is 1×10 14 cm -3 -1×10 16 cm -3 -1×10 14 cm -3 -1×10 18 cm -3 -1×10 17 cm -1×10-3 ~1x10 19 cm -3 The thickness of the p-type NiOx cap layer 5 is 50-150 nm, and the p-type doping concentration is 1x10 14 cm -3 ~1x10 18 cm -3 The material of the source electrode 6 and the drain electrode 7 includes one or more of Ti, Au, and the material of the gate electrode includes one or more of Ni, Au.

[0037] In the embodiment, the doping elements that can form the p-type can be used for the doping of the p-type NiOx buffer layer 3 and the p-type NiOx cap layer 5, and the doping elements that can form the n-type can be used for the doping of the n-type β-Ga2O3 channel layer 4.

[0038] In the enhancement-mode gallium oxide power transistor of the embodiment, the pn junction is formed between the p-type NiOx buffer layer and the upper n-type β-Ga2O3 channel layer, which can prevent the impurity ions in the β-Ga2O3 unintentionally doped layer from penetrating into the channel layer, reduce the compensation effect of the impurity ions penetrating into the channel layer, improve the electron mobility of the channel layer, and improve the electron concentration in the channel layer and the current density of the device.

[0039] In the embodiment, the introduction of the p-type NiOx cap layer causes the positive shift of the threshold voltage of the device, realizes the enhancement-mode device, and solves the problem of the excessively negative threshold voltage of the current depletion-mode gallium oxide power transistor.

[0040] Embodiment Two

[0041] On the basis of the embodiment one, the embodiment describes the manufacturing method of the enhancement-mode gallium oxide power transistor.

[0042] Please refer to Figures 2a-2g , Figures 2a-2g The embodiment provides a process schematic diagram of the manufacturing method of the enhancement-mode gallium oxide power transistor. The manufacturing method includes the following steps:

[0043] S1, growing a β-Ga2O3 unintentionally doped layer 2 on a β-Ga2O3 substrate 1, please refer to Figure 2a .

[0044] Specifically, a β-Ga2O3 unintentionally doped (UID) layer is grown on a Fe-doped (010) crystal direction β-Ga2O3 substrate 1, the thickness is 100-500 nm, and the carrier concentration is controlled to be 1x10 14 cm -3 ~1x10 16 cm -3 .

[0045] S2, growing a p-type NiOx buffer layer 3 on the β-Ga2O3 unintentionally doped layer 2, please refer to Figure 2b wherein the band gap of the p-type NiOx buffer layer 3 is similar to the band gap of Ga2O3.

[0046] Specifically, a 50-150 nm thick p-type NiOx material is deposited on the β-Ga2O3 unintentionally doped layer 2, the band gap of the p-type NiOx material is similar to the band gap of Ga2O3, and the doping concentration of the p-type NiOx material is 1×10 14 cm -3 -1×10 18 cm -3 , to obtain the p-type NiOx buffer layer 3.

[0047] S3, growing an n-type β-Ga2O3 channel layer 4 on the p-type NiOx buffer layer 3, please refer to Figure 2c .

[0048] Specifically, an n-doped β-Ga2O3 material is grown on the p-type NiOx buffer layer 3 as an n-type β-Ga2O3 channel layer 4, the channel layer has a thickness of 200-600 nm and a doping concentration of 1×10 17 cm -3 -1×10 19 cm -3 .

[0049] S4, growing a p-type NiOx material on the n-type β-Ga2O3 channel layer 4, please refer to Figure 2d , and selectively etching the p-type NiOx material outside the gate region to expose the n-type β-Ga2O3 channel layer 4, forming a p-type NiOx cap layer 5, please refer to Figure 2e .

[0050] Specifically, a 50-150 nm thick p-type NiOx material is grown on the n-type β-Ga2O3 channel layer 4, the doping concentration of the p-type NiOx material is 1×10 14 cm -3 -1×10 18 cm -3 , and then the p-type NiOx material outside the gate region is selectively etched to a depth of 50-150 nm, exposing the n-type β-Ga2O3 channel layer 4, to form a p-type NiOx cap layer 5 located at the middle position of the n-type β-Ga2O3 channel layer 4.

[0051] S5, preparing source electrode 6 and drain electrode 7 on n-type β-Ga2O3 channel layer 4, so that source electrode 6 is located at one end of n-type β-Ga2O3 channel layer 4, drain electrode 7 is located at the other end of n-type β-Ga2O3 channel layer 4, and p-type NiOx cap layer 5 is located between source electrode 6 and drain electrode 7, please refer to Figure 2f .

[0052] Specifically, after depositing Ti / Au metal stack on the etched n-type β-Ga2O3 channel layer 4, annealing is performed to form an ohmic contact, obtaining source electrode 6 and drain electrode 7, wherein source electrode 6 is located at one end of n-type β-Ga2O3 channel layer 4, drain electrode 7 is located at the other end of n-type β-Ga2O3 channel layer 4, and p-type NiOx cap layer 5 is located between source electrode 6 and drain electrode 7.

[0053] S6, preparing gate electrode 8 on p-type NiOx cap layer 5, please refer to Figure 2g .

[0054] Specifically, depositing Ni / Au metal stack on p-type NiOx cap layer 5 to form gate electrode 8, obtaining the enhancement mode gallium oxide power transistor.

[0055] The manufacturing process of the enhancement mode gallium oxide power transistor of the embodiment is simple and controllable, compatible with existing processes, and has lower manufacturing cost.

[0056] Example Three

[0057] Based on example two, please refer to Figures 2a-2g , this embodiment takes preparing 200nm thick enhancement mode gallium oxide power transistor as an example for illustration.

[0058] The manufacturing method of the enhancement mode gallium oxide power transistor comprises the following steps:

[0059] S1, growing β-Ga2O3 unintentionally doped layer 2 on β-Ga2O3 substrate 1, please refer to Figure 2a .

[0060] Specifically, growing a layer of β-Ga2O3 unintentionally doped layer 2 on Fe-doped (010) crystal direction β-Ga2O3 substrate 1, with a thickness of 100nm and a carrier concentration of 1×10 14 cm -3 .

[0061] S2, growing p-type NiOx buffer layer 3 on β-Ga2O3 unintentionally doped layer 2, please refer to Figure 2b .

[0062] Specifically, a p-type NiOx buffer layer 3 with a thickness of 50 nm and a doping concentration of 1×10 14 cm -3 .

[0063] S3. Grow an n-type β-Ga2O3 channel layer 4 on the p-type NiOx buffer layer 3. Figure 2c .

[0064] Specifically, an n-type β-Ga2O3 channel layer 4 is grown on the p-type NiOx buffer layer 3, with a thickness of 200 nm and a doping concentration of 1×10 17 cm -3 .

[0065] S4. Prepare a p-type NiOx cap layer 5 on the n-type β-Ga2O3 channel layer 4. Figure 2d .

[0066] Specifically, a 50 nm thick p-type NiOx material is grown on the n-type β-Ga2O3 channel layer 4, and the doping concentration of the p-type NiOx material is 1×10 14 cm -3 Then, the p-type NiOx material outside the gate region is selectively etched to a depth of 50 nm to expose the n-type β-Ga2O3 channel layer 4, forming a p-type NiOx cap layer 5 located in the middle of the n-type β-Ga2O3 channel layer 4.

[0067] S5. Prepare a source electrode 6 and a drain electrode 7 on the n-type β-Ga2O3 channel layer 4. Figure 2f .

[0068] Specifically, a Ti / Au metal stack with a thickness of 20 / 200 nm, respectively, is deposited on the etched exposed n-type β-Ga2O3 channel layer 4, and then rapid thermal annealing is performed to alloy the ohmic metal to obtain a source electrode 6 and a drain electrode 7, wherein the source electrode 6 is located at one end of the n-type β-Ga2O3 channel layer 4, the drain electrode 7 is located at the other end of the n-type β-Ga2O3 channel layer 4, and the p-type NiOx cap layer 5 is located between the source electrode 6 and the drain electrode 7.

[0069] S6. Prepare a gate electrode 8 on the p-type NiOx cap layer 5. Figure 2g .

[0070] Specifically, a Ni / Au metal stack is evaporated on the p-type NiOx cap layer 5 with thicknesses of 45 / 400 nm, respectively, to obtain the gate electrode 8 .

[0071] Afterwards, interconnect metal is deposited on the surface of the device and electrodes are drawn out to complete the fabrication of the enhancement-mode gallium oxide power transistor.

[0072] Embodiment Four

[0073] Based on Embodiment Two, please combine Figures 2a-2g , this embodiment takes the preparation of a 400 nm thick enhanced gallium oxide power transistor as an example for illustration.

[0074] The method for manufacturing the enhanced gallium oxide power transistor comprises the following steps:

[0075] S1, growing a β-Ga2O3 unintentionally doped layer 2 on a β-Ga2O3 substrate 1, please refer to Figure 2a .

[0076] Specifically, a β-Ga2O3 unintentionally doped layer 2 is grown on a Fe-doped (010) crystal direction β-Ga2O3 substrate 1, with a thickness of 300 nm and a carrier concentration of 1×10 15 cm -3 .

[0077] S2, growing a p-type NiOx buffer layer 3 on the β-Ga2O3 unintentionally doped layer 2, please refer to Figure 2b .

[0078] Specifically, a p-type NiOx buffer layer 3 is sputtered on the β-Ga2O3 unintentionally doped layer 2, with a thickness of 100 nm and a doping concentration of 1×10 16 cm -3 .

[0079] S3, growing an n-type β-Ga2O3 channel layer 4 on the p-type NiOx buffer layer 3, please refer to Figure 2c .

[0080] Specifically, an n-type β-Ga2O3 channel layer 4 is grown on the p-type NiOx buffer layer 3, with a thickness of 400 nm and a doping concentration of 1×10 18 cm -3 .

[0081] S4, preparing a p-type NiOx cap layer 5 on the n-type β-Ga2O3 channel layer 4, please refer to Figure 2d .

[0082] Specifically, a 100 nm thick p-type NiOx material is sputtered on the n-type β-Ga2O3 channel layer 4, with a doping concentration of 1×10 16 cm -3 , and then the p-type NiOx material outside the gate region is selectively etched to a depth of 100 nm, exposing the n-type β-Ga2O3 channel layer 4, forming a p-type NiOx cap layer 5 located at the middle position of the n-type β-Ga2O3 channel layer 4.

[0083] S5, preparing source electrode 6 and drain electrode 7 on n-type β-Ga2O3 channel layer 4, please refer to Figure 2f .

[0084] Specifically, depositing Ti / Au metal stack on the etched n-type β-Ga2O3 channel layer 4, the thickness is 20 / 200 nm respectively, and then performing rapid thermal annealing to alloy the ohmic metal, obtaining source electrode 6 and drain electrode 7, wherein source electrode 6 is located at one end of n-type β-Ga2O3 channel layer 4, drain electrode 7 is located at the other end of n-type β-Ga2O3 channel layer 4, and p-type NiOx cap layer 5 is located between source electrode 6 and drain electrode 7.

[0085] S6, preparing gate electrode 8 on p-type NiOx cap layer 5, please refer to Figure 2g .

[0086] Specifically, evaporating Ni / Au metal stack on p-type NiOx cap layer 5, the thickness is 45 / 400 nm respectively, obtaining gate electrode 8.

[0087] After that, depositing interconnection metal on the surface of the device and leading out electrodes, completing the preparation of the enhancement mode gallium oxide power transistor.

[0088] Example five

[0089] On the basis of example two, please combine Figures 2a-2g , this example takes preparing 600 nm thick enhancement mode gallium oxide power transistor as an example to illustrate.

[0090] S1, growing β-Ga2O3 unintentionally doped layer 2 on β-Ga2O3 substrate 1, please refer to Figure 2a .

[0091] Specifically, growing a layer of β-Ga2O3 unintentionally doped layer 2 on Fe-doped (010) direction β-Ga2O3 substrate 1, the thickness is 500 nm, and the carrier concentration is 1×10 16 cm -3 .

[0092] S2, growing p-type NiOx buffer layer 3 on β-Ga2O3 unintentionally doped layer 2, please refer to Figure 2b .

[0093] Specifically, sputtering a layer of p-type NiOx buffer layer 3 on β-Ga2O3 unintentionally doped layer 2, the thickness is 150 nm, and the doping concentration is 1×10 18 cm -3 .

[0094] S3, growing n-type β-Ga2O3 channel layer 4 on p-type NiOx buffer layer 3, please refer to Figure 2c.

[0095] Specifically, an n-type β-Ga2O3 channel layer 4 is grown on the p-type NiOx buffer layer 3, with a thickness of 600 nm and a doping concentration of 1×10 19 cm -3 .

[0096] S4, a p-type NiOx cap layer 5 is prepared on the n-type β-Ga2O3 channel layer 4, please refer to Figure 2d .

[0097] Specifically, a 150 nm thick p-type NiOx material is grown on the n-type β-Ga2O3 channel layer 4, and the doping concentration of the p-type NiOx material is 1×10 18 cm -3 Then, the p-type NiOx material outside the gate region is selectively etched, with an etching depth of 150 nm, to expose the n-type β-Ga2O3 channel layer 4, thereby forming the p-type NiOx cap layer 5 located at the middle position of the n-type β-Ga2O3 channel layer 4.

[0098] S5, a source electrode 6 and a drain electrode 7 are prepared on the n-type β-Ga2O3 channel layer 4, please refer to Figure 2f .

[0099] Specifically, a Ti / Au metal stack is deposited on the exposed n-type β-Ga2O3 channel layer 4, with thicknesses of 20 / 200 nm, respectively, and then rapid thermal annealing is performed to alloy the ohmic metal, thereby obtaining the source electrode 6 and the drain electrode 7, wherein the source electrode 6 is located at one end of the n-type β-Ga2O3 channel layer 4, the drain electrode 7 is located at the other end of the n-type β-Ga2O3 channel layer 4, and the p-type NiOx cap layer 5 is located between the source electrode 6 and the drain electrode 7.

[0100] S6, a gate electrode 8 is prepared on the p-type NiOx cap layer 5, please refer to Figure 2g Figures 2a-2g .

[0101] Specifically, a Ni / Au metal stack is evaporated above the p-type NiOx cap layer 5, with thicknesses of 45 / 400 nm, respectively, thereby obtaining the gate electrode 8.

[0102] After that, an interconnection metal is deposited on the surface of the device and a lead electrode is led out, thereby completing the fabrication of the enhancement-mode gallium oxide power transistor.

[0103] The above is a further detailed description of the present application in combination with specific preferred embodiments, and the specific implementation of the present application should not be limited to these descriptions. For ordinary skilled persons in the technical field to which the present application belongs, a number of simple deductions or substitutions can be made without departing from the concept of the present application, and all of these should be considered as falling within the protection scope of the present application.

Claims

1. An enhanced gallium oxide power transistor comprising: A β-Ga2O3 substrate (1), a β-Ga2O3 unintentionally doped layer (2), a p-type NiOx buffer layer (3), an n-type β-Ga2O3 channel layer (4), a p-type NiOx cap layer (5), a source electrode (6), a drain electrode (7) and a gate electrode (8), wherein, The β-Ga2O3 substrate (1), the β-Ga2O3 unintentionally doped layer (2), the p-type NiOx buffer layer (3) and the n-type β-Ga2O3 channel layer (4) are sequentially stacked; The source electrode (6) is located at one end of the n-type β-Ga2O3 channel layer (4), and the drain electrode (7) is located at the other end of the n-type β-Ga2O3 channel layer (4); The p-type NiOx cap layer (5) is located on the n-type β-Ga2O3 channel layer (4) and between the source electrode (6) and the drain electrode (7); The gate electrode (8) is located on the p-type NiOx cap layer (5).

2. The enhanced gallium oxide power transistor of claim 1, wherein, The doping element of the β-Ga2O3 substrate (1) comprises Fe.

3. The enhanced gallium oxide power transistor of claim 1, wherein, The thickness of the β-Ga2O3 non-intentionally doped layer (2) is 100-500 nm, and the carrier concentration is 1 x 1010 14 cm -3 ~ 1 x 1012 16 cm -3 .

4. The enhanced gallium oxide power transistor of claim 1, wherein, The thickness of the p-type NiOx buffer layer (3) is 50-150 nm, and the p-type doping concentration is 1 x 1018-1 x 1020 cm-3. 14 cm -3 -1 x 1020 cm-3. 18 cm -3 -1 x 1020 cm-3.

5. The enhanced gallium oxide power transistor of claim 1, wherein, The thickness of the n-type β-Ga2O3 channel layer (4) is 200-600 nm, and the doping concentration is 1 x 1018-1 x 1020 cm-3. 17 cm -3 ~ 1 x 1020 cm-3. 19 cm -3 .

6. The enhanced gallium oxide power transistor of claim 1, wherein, The thickness of the p-type NiOx cap layer (5) is 50-150 nm, and the p-type doping concentration is 1 x 1018-1 x 1020 cm-3. 14 cm -3 ~ 1 x 1020 cm-3. 18 cm -3 .

7. A method of fabricating an enhanced gallium oxide power transistor, comprising: The method comprises the steps of: growing a β-Ga2O3 unintentionally doped layer (2) on a β-Ga2O3 substrate (1); growing a p-type NiOx buffer layer (3) on the β-Ga2O3 unintentionally doped layer (2); growing an n-type β-Ga2O3 channel layer (4) on the p-type NiOx buffer layer (3); growing a p-type NiOx material on the n-type β-Ga2O3 channel layer (4) and selectively etching the p-type NiOx material outside the gate region to expose the n-type β-Ga2O3 channel layer (4), thereby forming a p-type NiOx cap layer (5); preparing a source electrode (6) and a drain electrode (7) on the n-type β-Ga2O3 channel layer (4) such that the source electrode (6) is located at one end of the n-type β-Ga2O3 channel layer (4), the drain electrode (7) is located at the other end of the n-type β-Ga2O3 channel layer (4), and the p-type NiOx cap layer (5) is located between the source electrode (6) and the drain electrode (7); preparing a gate electrode (8) on the p-type NiOx cap layer (5). A β-Ga2O3 substrate (1), a β-Ga2O3 unintentionally doped layer (2), a p-type NiOx buffer layer (3), an n-type β-Ga2O3 channel layer (4), a p-type NiOx cap layer (5), a source electrode (6), a drain electrode (7) and a gate electrode (8), wherein, The β-Ga2O3 substrate (1), the β-Ga2O3 unintentionally doped layer (2), the p-type NiOx buffer layer (3) and the n-type β-Ga2O3 channel layer (4) are sequentially stacked; The source electrode (6) is located at one end of the n-type β-Ga2O3 channel layer (4), and the drain electrode (7) is located at the other end of the n-type β-Ga2O3 channel layer (4); The p-type NiOx cap layer (5) is located on the n-type β-Ga2O3 channel layer (4) and between the source electrode (6) and the drain electrode (7); The gate electrode (8) is located on the p-type NiOx cap layer (5). The doping element of the β-Ga2O3 substrate (1) comprises Fe. including the steps of: growing a β-Ga2O3 unintentionally doped layer (2) on a β-Ga2O3 substrate (1); growing a p-type NiOx buffer layer (3) on the β-Ga2O3 unintentionally doped layer (2); growing an n-type β-Ga2O3 channel layer (4) on the p-type NiOx buffer layer (3); growing a p-type NiOx material on the n-type β-Ga2O3 channel layer (4) and selectively etching the p-type NiOx material outside the gate region to expose the n-type β-Ga2O3 channel layer (4), thereby forming a p-type NiOx cap layer (5); preparing a source electrode (6) and a drain electrode (7) on the n-type β-Ga2O3 channel layer (4) such that the source electrode (6) is located at one end of the n-type β-Ga2O3 channel layer (4), the drain electrode (7) is located at the other end of the n-type β-Ga2O3 channel layer (4), and the p-type NiOx cap layer (5) is located between the source electrode (6) and the drain electrode (7); preparing a gate electrode (8) on the p-type NiOx cap layer (5).

8. The method of fabricating an enhanced gallium oxide power transistor according to claim 7, wherein The thickness of the β-Ga2O3 non-intentionally doped layer (2) is 100-500 nm, and the carrier concentration is 1 x 10 14 cm -3 -1 x 10 16 cm -3 .

9. The method of fabricating an enhanced gallium oxide power transistor according to claim 7, wherein The thickness of the p-type NiOx buffer layer (3) is 50-150 nm, and the p-type doping concentration is 1 x 1018-1 x 1020 cm-3. 14 cm -3 ~1 x 1020 cm-3. 18 cm -3 .

10. The method of fabricating an enhanced gallium oxide power transistor of claim 7, wherein, The thickness of the n-type β-Ga2O3 channel layer (4) is 200-600 nm, and the doping concentration is 1 x 1018-1 x 1020 cm-3. 17 cm -3 -1 x 1020 cm-3. 19 cm -3 .

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