Optical modulator and method of manufacturing an optical modulator

Abstract

A MOS capacitor type optical modulator includes a silicon-on-insulator (SOI) substrate, a first doped region in a silicon device layer of the SOI substrate, and a second doped region laterally separated from the first doped region by a vertically extending insulator layer to form a lateral MOS capacitor region. The first doped region, the second doped region, and the insulator layer are formed of different materials.

Description

Technical Field

[0001] One or more aspects of embodiments of the present invention relate to an optical modulator, and more specifically to a MOS capacitor-type optical modulator. Background Technology

[0002] Silicon MOS capacitor modulators can have high losses. III-V Si MOS capacitor modulators are a more efficient but potentially less suitable hybrid structure for high-volume manufacturing.

[0003] III-V Si MOS capacitor-type modulators can be fabricated by bonding III-V material sheets onto a silicon wafer. Besides being unsuitable for mass production, the bonding process also limits the possible geometric configurations of the modulator.

[0004] Some III-V Si MOS capacitor-type modulators use specialized transition layers, such as epitaxially grown crystalline rare earth oxides (REO). While these modulators are monolithic and therefore unsuitable for mass production, the fabrication steps required to create them are complex. Furthermore, the process requires Si(111) device layer orientation, which is less desirable compared to other Si device layers such as Si(100). Specifically, Si(111) is less common and more expensive than Si(100), and some etching techniques cannot be replicated on Si(111). Summary of the Invention

[0005] The embodiments of the present invention aim to solve the above-mentioned problems by providing a MOS capacitor-type optical modulator according to a first aspect, the MOS capacitor-type optical modulator comprising:

[0006] Silicon-on-Insulator (SOI) substrate;

[0007] A first doped region, wherein the first doped region is in the silicon device layer of the SOI substrate; and

[0008] The second doped region is laterally separated from the first doped region by a vertically extending insulating layer to form a lateral MOS capacitor region, wherein the first doped region, the second doped region, and the insulating layer are formed of different materials.

[0009] In this way, the modulator is monolithic, without requiring the silicon device layer of the SOI substrate to have a Si(111) device layer orientation. Furthermore, no special transition layer, such as a crystalline REO layer, is required.

[0010] The optical modulator may have any one or any combination of the optional features set forth below (provided they are compatible).

[0011] The SOI substrate may include a silicon substrate, a buried oxide (BOX) layer on top of the silicon substrate, and a silicon device layer (i.e., a top silicon layer) on top of the BOX layer.

[0012] As used herein, the terms “vertical” and “horizontal” should be understood relative to the BOX layer, such that “vertical” is perpendicular to the upper surface of the BOX layer, and “horizontal” refers to a direction located in any plane parallel to the plane along the upper surface of the BOX layer. As used herein, “lateral” can be understood to mean along a horizontal plane.

[0013] As used herein, the lateral MOS capacitor region can be the region of optical mode propagation of the device and is formed by a pin junction, wherein the pin junction includes a first doped region, an insulating layer, and a second doped region. The insulating layer can extend vertically to laterally separate the first and second doped regions, such that the pin junction of the lateral MOS capacitor region extends perpendicular to the BOX layer. The insulating layer can extend at an angle relative to the substrate to laterally separate the second doped region from the first doped region. For example, the insulating layer can extend at an angle greater than 0° and less than 90°.

[0014] The first doped region may contain a different type of dopant than the second doped region. Specifically, the first doped region may have the opposite doping type to the second doped region. For example, the first doped region may be a p-doped region and the second doped region may be an n-doped region. Alternatively, the first doped region may be an n-doped region and the second doped region may be a p-doped region.

[0015] The second doped region can be formed in the semiconductor region, and more particularly in the type III-V, type II-VI, or type IV semiconductor regions. The semiconductor region can be epitaxially grown from the silicon device layer of the SOI substrate.

[0016] In some implementations, the semiconductor region may extend from the silicon device layer at a region laterally offset from the MOS capacitor region.

[0017] In an implementation where the semiconductor region is a III-V type semiconductor region, the semiconductor region can be an InP, GaAs, InGaAs, or InGaAsP semiconductor region.

[0018] The insulating layer may include silicon nitride.

[0019] The silicon device layer of the SOI substrate may have (100) crystal orientation.

[0020] Optionally, a portion of the insulating layer may extend horizontally on top of the first doped region of the silicon device layer. Another portion of the insulating layer may extend horizontally below the second doped region of the semiconductor region. Thus, the insulating layer may be formed in a "Z" shape, wherein the vertically extending portion of the "Z" shape of the insulating layer forms the insulator of the pin junction of the MOS capacitor region between the first and second doped regions.

[0021] In some implementations, a portion of the silicon device layer may extend vertically away from the BOX layer. Specifically, a first doped region in the silicon device layer may extend vertically away from the BOX layer. A portion of the semiconductor region may also extend vertically. Specifically, a second doped region of the semiconductor region may extend vertically. Thus, the vertically extending insulating layer can laterally separate the vertically extending first doped region and the vertically extending second doped region.

[0022] In some embodiments, the upper horizontal portion of the semiconductor region may extend horizontally above a horizontally extending portion of the insulating layer, which itself extends horizontally above the first doped region of the silicon device layer. Therefore, the semiconductor region can be formed in a "Z" shape, such that the vertical portion and the upper horizontal portion of the "Z"-shaped insulating segment together form the insulator of the pin junction of the MOS capacitor region between the first and second doped regions. In these embodiments, the pin junction extends perpendicularly and parallel to the BOX layer.

[0023] The structure of a MOS capacitor-type optical modulator can be identified through cross-sectional imaging (such as FIB or SEM).

[0024] According to a second aspect of the present invention, a method for manufacturing a MOS capacitor-type optical modulator of the first aspect is provided.

[0025] Specifically, according to a second aspect, a method for manufacturing a MOS capacitor-type optical modulator is provided, the MOS capacitor-type optical modulator having a lateral MOS capacitor region, the lateral MOS capacitor region including a vertically extending insulating layer that laterally separates a first doped region and a second doped region, wherein the method includes the following steps:

[0026] A first doped region is provided in the silicon device layer of a silicon-on-insulator (SOI) substrate; and

[0027] A semiconductor region is epitaxially grown from the silicon device layer of the SOI substrate, wherein the semiconductor region includes the second doped region, and the first doped region, the second doped region, and the insulating layer are each formed of different materials.

[0028] The method may have any one or any combination of the optional features set forth below (provided they are compatible).

[0029] In some implementations, the semiconductor region may be epitaxially grown from a region of the silicon device layer that is laterally offset from the MOS capacitor region.

[0030] In this manner, the semiconductor region is grown from a region of the silicon device layer away from the MOS capacitor region. Therefore, any defects in the grown semiconductor region are confined to regions closely adjacent to the region from which the semiconductor region was epitaxially grown in the silicon device. Thus, any defects in the semiconductor region are positioned away from the MOS capacitor region, minimizing their impact on the modulator's performance. Furthermore, in some embodiments, regions of the semiconductor region adjacent to the region of the silicon device layer from which the semiconductor region was epitaxially grown can be selectively etched without removing the semiconductor region within the MOS capacitor region, resulting in high crystal quality throughout the semiconductor region.

[0031] In some embodiments, the semiconductor region is a type III-V semiconductor region. In other embodiments, the semiconductor region may be an InP, GaAs, InGaAs, or InGaAsP semiconductor region. However, in other embodiments, the semiconductor region may be a type II-VI semiconductor region or a type IV semiconductor region.

[0032] In some implementations, the insulating layer may include a dielectric material, such as silicon nitride.

[0033] Optionally, the silicon device layer of the SOI substrate has a (100) crystal orientation.

[0034] In some implementations, the method may also include the following steps:

[0035] A cavity is formed below the upper mask layer; and

[0036] In this cavity, a semiconductor region is epitaxially grown from the silicon device layer of the SOI substrate.

[0037] In this way, the growth of the semiconductor region can be contained within the cavity by the upper mask layer, making the resulting modulator monolithic without requiring a dedicated transition layer, such as a crystal REO. Therefore, the silicon device layer (i.e., the top silicon layer) of the SOI substrate does not require Si(111) device layer orientation and enables greater flexibility in device design.

[0038] A cavity is formed between the upper mask layer and the silicon device layer of the SOI substrate by forming a cavity below the upper mask layer.

[0039] Optionally, the upper mask layer may include a dielectric material. For example, the upper mask layer may include silicon nitride.

[0040] Optionally, the step of forming the cavity may include:

[0041] Provide a sacrifice layer;

[0042] The upper mask layer is deposited on top of the sacrificial layer; and

[0043] The sacrificial layer is selectively etched to form a cavity.

[0044] For example, a sacrificial layer can be provided by depositing a sacrificial layer.

[0045] Therefore, a sacrificial layer is used to form the shape of the cavity, thereby stacking the upper mask layer on top of the sacrificial layer before selectively etching the sacrificial layer from below to form the cavity. By selectively etching the sacrificial layer, the sacrificial layer is removed but the upper mask layer is retained, thereby forming the cavity below the upper mask layer.

[0046] The method may also include the following steps:

[0047] Trenches are etched in the silicon device layer of the SOI substrate;

[0048] The lower mask layer is deposited on top of the silicon device layer and in the trench;

[0049] In the lower mask layer, an opening in the silicon device layer is etched at a region laterally offset from the MOS capacitor region; and

[0050] The sacrificial layer is deposited on the lower mask layer and in the openings in the lower mask layer.

[0051] In some implementations, the lower mask layer may be formed of the same material as the upper mask layer. Therefore, the lower mask layer may include a dielectric material, such as silicon nitride.

[0052] The upper and lower mask layers can jointly define a cavity. Specifically, the cavity can be formed above the lower mask layer and below the upper mask layer.

[0053] Optionally, the method may further include the step of etching a portion of the sacrificial layer to reach the lower mask layer before depositing the upper mask layer.

[0054] Therefore, when the upper mask layer is deposited on top of the sacrificial layer, the upper and lower mask layers can surround the sacrificial layer. Thus, when the sacrificial layer is selectively etched between the upper and lower mask layers, the upper and lower mask layers are retained, and a cavity is formed below the upper mask layer.

[0055] According to some implementation schemes, the method may also include the step of planarizing the sacrificial layer by chemical mechanical planarization (CMP).

[0056] Specifically, the sacrificial layer can be planarized before the upper mask layer is deposited. Therefore, when the upper mask layer is deposited on top of the sacrificial layer, the upper and lower mask layers can surround the sacrificial layer, such that when the sacrificial layer is selectively etched from between the upper and lower mask layers, the upper and lower mask layers are retained, and a cavity is formed below the upper mask layer.

[0057] Optionally, the sacrificial layer may include alumina or amorphous silicon.

[0058] In some implementations, the method may further include the step of etching an opening in the upper mask layer that reaches the sacrificial layer before selectively etching the sacrificial layer to form a cavity.

[0059] Optionally, the method may further include the step of etching a portion of a semiconductor region to form a waveguide structure, the waveguide structure including a MOS capacitor region.

[0060] In this step, portions of the upper and lower mask layers, and optionally a portion of the silicon device layer, may also be etched to form a waveguide structure. The waveguide structure may include the remaining semiconductor regions and the remaining portions of the upper and lower mask layers.

[0061] The remaining portions of the upper and lower mask layers can form the insulating region of the pin junction of the MOS capacitor region, and the remaining semiconductor region can form the second doped region.

[0062] In some embodiments, the step of etching a portion of the semiconductor region to form the waveguide structure includes etching the portion of the semiconductor region in an opening in the lower mask layer and / or adjacent to that opening at a region of the silicon device layer laterally offset from the MOS capacitor region. Since any defects in the semiconductor region are confined to this region of the semiconductor, these defects can be removed by this etching without affecting the MOS capacitor region. Therefore, the entire remaining semiconductor region can have high crystal quality.

[0063] The method may also include the following steps:

[0064] An isolation layer is deposited on the waveguide structure;

[0065] The first electrical contact is applied to the silicon device layer (i.e., the first doped region) through the isolation layer; and

[0066] The second electrical contact is applied to the semiconductor region (i.e., the second doped region) through the isolation layer.

[0067] Optionally, the isolation layer can be an isolation oxide, such as silicon dioxide. Electrical contacts can be applied to the silicon device layer and the semiconductor region laterally offset from the MOS capacitor region.

[0068] Optionally, the method may include the step of planarizing the semiconductor region using CMP.

[0069] According to a third aspect of the present invention, a method for manufacturing a MOS capacitor-type optical modulator is provided, the MOS capacitor-type optical modulator having a MOS capacitor region comprising a semiconductor region, the method comprising the following steps:

[0070] A cavity is formed below the upper mask layer; and

[0071] The semiconductor region is epitaxially grown from the silicon device layer of the silicon-on-insulator (SOI) substrate within the cavity.

[0072] It should be noted that the method of the third aspect is not limited to manufacturing a MOS capacitor-type optical modulator with a lateral MOS capacitor region having a vertically extending insulating layer. In fact, in the method of the third aspect, dry etching or selective wet etching can be used to intentionally tilt the cavity etching (i.e., not vertical or horizontal).

[0073] In this way, the growth of the semiconductor region can be contained within the cavity by the upper mask layer, resulting in a monolithic modulator without requiring a dedicated transition layer, such as a crystal REO. Therefore, the silicon device layer on the SOI substrate does not require Si(111) device layer orientation and enables greater flexibility in device design.

[0074] A cavity is formed between the upper mask layer and the silicon device layer of the SOI substrate by forming a cavity below the upper mask layer.

[0075] This disclosure includes combinations of the foregoing aspects and optional features, unless such combinations are clearly not permitted or explicitly avoided. Attached Figure Description

[0076] Embodiments of the invention will now be described by way of example with reference to the accompanying drawings, in which:

[0077] Figure 1 This is a schematic cross-section of a MOS capacitor-type optical modulator according to a first embodiment of the present invention;

[0078] Figure 2 This is a schematic cross-section of a MOS capacitor-type optical modulator according to a second embodiment of the present invention;

[0079] Figures 3a to 3l Depicting manufacturing Figure 1 The steps of the modulator method;

[0080] Figures 4a to 4l Depicting manufacturing Figure 2 The steps of the modulator method; and

[0081] Figures 5a to 5g Depicting manufacturing Figure 2 The steps of a variant method for modulators. Detailed Implementation

[0082] The following detailed description, illustrated with reference to the accompanying drawings, is intended as a description of an exemplary embodiment of a MOS capacitor-type optical modulator and its manufacturing method provided according to the present invention, and is not intended to represent the only form in which the invention can be constructed or utilized. This description elucidates the features of the invention in conjunction with the illustrated embodiments. However, it should be understood that the same or equivalent functions and structures may be implemented by different embodiments also intended to be covered within the spirit and scope of the invention. As indicated elsewhere herein, similar element numbers are intended to indicate similar elements or features.

[0083] The following is for reference. Figure 1 and Figures 3a to 3l A MOS capacitor-type optical modulator 1 according to a first embodiment and a method for manufacturing the same are described. The modulator 1 includes an SOI substrate 20.

[0084] like Figure 3a As shown, a silicon-on-insulator substrate 20 is initially provided, which includes a silicon base layer 23, a buried silicon dioxide (BOX) layer 22, and a silicon device layer 21. The silicon device layer 21 has a Si (100) crystal structure. Trench 24 is etched in the silicon device layer 21 to reach the BOX layer 22. The trench is etched using standard patterning and etching techniques. Although Figure 3a Not shown, but the first doped region is formed using standard implantation techniques in the first silicon device layer 21.

[0085] Next, as Figure 3b As shown, a lower mask layer 25 comprising silicon nitride is deposited on top of the silicon device layer 21 and deposited in the trench 24.

[0086] Then, the opening 26 reaching the silicon device layer 21 is etched in the lower mask layer 25 (see, for example, see...). Figure 3c Similarly, standard patterning and etching techniques are used to etch opening 26. This opening 26 provides a point of exposed silicon from which the III-V type semiconductor layer will laterally grow. Opening 26 is etched in a region of the lower mask layer 25 that will be laterally offset from the region of the MOS capacitor with the pin junction of modulator 1.

[0087] like Figure 3d As shown, a sacrificial layer 27 is then deposited on top of the lower mask layer 25 and in the opening 26. For example, the sacrificial layer 27 may comprise alumina or amorphous silicon.

[0088] Next, a portion of the sacrificial layer 27 is etched down to the lower mask layer 25. Specifically, as... Figure 3e As shown, a portion of each side of the sacrificial layer 27 is etched to expose the underlying lower mask layer 25. Furthermore, a portion of the sacrificial layer 27 is etched into an opening 26 located in the lower mask layer 25 to expose a portion of the silicon device layer 21. In an alternative embodiment, this portion of the sacrificial layer 27 located in the opening 26 of the lower mask layer 25 is not etched, such that the sacrificial layer 27 extends across the opening 26 and does not expose the silicon device layer 21. Again, standard patterning and etching techniques are used.

[0089] like Figure 3f As shown, the upper mask layer 28 is then deposited on top of the sacrificial layer 27 and deposited in the opening 26. Thus, the upper mask layer 28 and the lower mask layer 25 surround the sacrificial layer 27.

[0090] Next, the opening 29 reaching the sacrificial layer 27 is etched in the upper mask layer 28 (see, for example, see...). Figure 3g Similarly, standard patterning and etching techniques are used.

[0091] The sacrificial layer 27 is then selectively etched while maintaining the upper mask layer 28 and the lower mask layer 25. Thus, a cavity 30 is formed between the upper mask layer 28 and the lower mask layer 25, below the upper mask layer 28 and above the lower mask layer 25 (see, for example, [link to relevant documentation]). Figure 3h The cavity 30 extends from the silicon device layer 21 between the upper mask layer 28 and the lower mask layer 25 at the opening 26 in the lower mask layer 25 to the opening 29 in the upper mask layer 28.

[0092] like Figure 3i As shown, a III-V type semiconductor region 31 is then epitaxially grown from the exposed silicon device layer 21 at an opening 26 in the lower mask layer 25 within the cavity 30. Standard epitaxial growth techniques are used. The III-V type semiconductor region 31 is grown to fill the shape of the cavity 30 and is thus confined by the upper mask layer 28 and the lower mask layer 25. In this example embodiment, the III-V type semiconductor region 31 is InP, GaAs, InGaAs, or InGaAsP, but other III-V type materials may also be used.

[0093] The second doped region of the III-V type semiconductor region 31 is formed by in-situ doping using standard doping techniques. In an alternative embodiment, standard implantation and / or diffusion techniques can be used to form the second doped region of the III-V type semiconductor region 31. If the first doped region is n-doped, the second doped region is p-doped, and vice versa.

[0094] Next, a waveguide structure 32 is formed by etching a portion of the unwanted III-V type semiconductor region 31, a portion of the upper mask layer 28, and a portion of the lower mask layer 25. The waveguide structure 32 includes a MOS capacitor region with a pin junction. Again, standard etching techniques are used. Figure 3j As shown, in this step, the portion of the Type III-V semiconductor region 31 adjacent to the silicon device layer 21 at the opening 26 is etched. Therefore, any defects in the Type II-V semiconductor region 31 are removed.

[0095] Then, an isolation layer 33 is deposited on top of the waveguide structure 32. Figure 3k In the example embodiment shown, the isolation layer 33 is an isolation oxide, such as silicon dioxide.

[0096] Finally, the isolation layer 33 is etched at the two openings reaching the silicon device layer 21 and the III-V type semiconductor region 31, respectively, and electrical contacts 34 are deposited through the isolation layer 33 (see, for example, see...). Figure 3l Electrical contacts 34 are applied to the region laterally offset from the MOS capacitor region of the waveguide structure 32 in the silicon device layer 21 and the III-V type semiconductor region 31. The remaining portion of the lower mask layer 25 forms the insulating layer of the pin junction in the MOS capacitor region.

[0097] exist Figure 1 The resulting modulator 1 is shown. The silicon device layer 21 of the SOI substrate 20 extends horizontally parallel to and adjacent to the BOX layer 22. The insulating layer 25 (formed by the lower mask layer) has a “Z” shape formed by a first upper horizontally extending portion 25a, a second vertically extending portion 25b, and a third lower horizontally extending portion 25c. Advantageously, this “Z” shape increases the surface area where charge can accumulate. This correspondingly increases the modulation efficiency without affecting the size of the optical mode.

[0098] A first horizontally extending portion 25a of the insulating layer 25 extends above and adjacent to the silicon device layer 21, and particularly above the first doped region of the silicon device layer 21. A second vertically extending portion 25b of the insulating layer 25 extends vertically away from the BOX layer 22 to the first upper horizontally extending portion 25a of the insulating layer 25. Therefore, the insulating layer 25 forms both a vertical junction (i.e., at the second vertically extending portion 25b) and a horizontal junction (i.e., at the first upper horizontally extending portion 25a) with the silicon device layer 21, and particularly the first doped region of the silicon device layer 21. In a variant not shown, the insulating layer 25 extends obliquely across the waveguide structure 32. For example, the insulating layer 25 may extend at an angle greater than 0° and less than 90°. Figure 1 Compared to the “Z”-shaped insulating layer shown, this extension could be linear.

[0099] The third lower horizontally extending portion 25c of the insulating layer 25 extends horizontally above and adjacent to the second vertically extending portion 25b of the insulating layer 25 on the top of the BOX layer 22.

[0100] Similar to the insulating layer 25, the III-V type semiconductor region 31 also has a “Z” shape formed by a first upper horizontally extending portion 31a, a second vertically extending portion 31b, and a third lower horizontally extending portion 31c.

[0101] The first upper horizontally extending portion 31a of the III-V type semiconductor region 31 extends on top of and adjacent to the first upper horizontally extending portion 25a of the insulating layer 25. The third lower horizontally extending portion 31c of the III-V type semiconductor region 31 extends on top of and adjacent to the third lower horizontally extending portion 25c of the insulating layer 25. The second vertically extending portion 31b of the III-V type semiconductor region 31 extends vertically between the first upper horizontally extending portion 31a and the third lower horizontally extending portion 31c of the III-V type semiconductor region 31.

[0102] Therefore, the first doped region of the silicon device layer 21 and the second vertically extending portion 31b of the III-V type semiconductor region 31 are laterally (i.e., horizontally) separated by the second vertically extending portion 25b of the insulating layer 25. This forms a lateral MOS capacitor region.

[0103] The first doped region of the silicon device layer 21 is also vertically spaced from the first upper horizontally extending portion 31a of the III-V type semiconductor region 31 by the first upper horizontally extending portion 25a of the insulating layer 25. Therefore, the modulator 1 has a pin junction that extends vertically and parallel to the BOX layer.

[0104] exist Figure 1 In the example embodiment shown, the insulating layer 25, the first doped region of the silicon device layer 21, and the second doped region of the III-V type semiconductor region 31 are formed of different materials. Specifically, the insulating layer 25 comprises silicon nitride, the silicon device layer 21 has a Si(100) crystal orientation, and the III-V type semiconductor region 31 comprises InP or InGaAsP.

[0105] The following is for reference. Figure 2 , Figures 4a to 4l and Figures 5a to 5g A MOS capacitor-type optical modulator 100 according to a second embodiment and a method for manufacturing the same are described. The modulator 100 includes an SOI substrate 120.

[0106] According to the first method for manufacturing a MOS capacitor-type optical modulator, and as Figure 4a As shown, a silicon-on-insulator (SiI) substrate 120 is initially provided, comprising a silicon base layer 123, a buried silicon dioxide (BOX) layer 122, and a silicon device layer 121. The silicon device layer 121 has a Si (100) crystal structure. Trench 124 is etched in the silicon device layer 121 to reach the BOX layer 122. The trench is etched using standard patterning and etching techniques. Although Figure 4a The first doped region is formed within the first silicon device layer 121 using a standard implantation technique, not shown in the diagram.

[0107] Next, as Figure 4b As shown (and similar to the first embodiment in) Figure 3b (as shown in the steps), a lower mask layer 125 comprising silicon nitride is deposited on top of the silicon device layer 121 and deposited in the trench 124.

[0108] An opening 126 is then etched in the lower mask layer 125. However, compared to the corresponding step in the first embodiment, the opening 126 in the lower mask layer 125 extends into the silicon device layer 121 and the BOX layer 122 within the trench 124. Similarly, the opening 126 is etched using standard patterning and etching techniques. This opening 126 provides a point of exposed silicon from which the III-V type layer will subsequently grow. The opening 126 is etched in a region of the lower mask layer 125 that will be laterally offset from the region of the MOS capacitor having the pin junction of the modulator 100.

[0109] like Figure 4d As shown, a sacrificial layer 127 is then deposited on top of the lower mask layer 125, in the trench 124, and in the opening 126. The sacrificial layer 127 may comprise alumina or amorphous silicon.

[0110] Next, the sacrificial layer 127 is planarized by chemical mechanical planarization (CMP) so that the sacrificial layer 127 exists only in the trenches 124 (e.g., see...). Figure 4e Therefore, the sacrificial layer 127 in the trench 124 is flush with the lower mask layer 125.

[0111] like Figure 4f As shown, an upper mask layer 128 is then deposited on top of a sacrificial layer 127, such that the upper mask layer 128 and the lower mask layer 125 surround the sacrificial layer 127.

[0112] Similar to the first implementation scheme Figure 3g The steps shown involve etching an opening 129 in the upper mask layer 128 that reaches the sacrificial layer 127. Similarly, standard patterning and etching techniques are used.

[0113] The sacrificial layer 127 is then selectively etched while maintaining the upper mask layer 128 and the lower mask layer 125. Thus, a cavity 130 is formed in the trench 124 between the upper mask layer 128 and the lower mask layer 125. The cavity 130 is formed below the upper mask layer 128.

[0114] like Figure 4i As shown, a III-V type semiconductor region 131 is then epitaxially grown from the exposed silicon device layer 121 at an opening 126 in the lower mask layer 125 within the cavity 130. Standard epitaxial growth techniques are used. The III-V type semiconductor region 131 is grown to fill the shape of the cavity 130 and is thus confined by the upper mask layer 128 and the lower mask layer 125. In this example embodiment, the III-V type semiconductor region 131 is InP or InGaAsP. A second doped region of the III-V type semiconductor region 131 is formed by in-situ doping using standard doping techniques. If the first doped region is n-doped, the second doped region is p-doped, and vice versa.

[0115] Next, a waveguide structure 132 is formed by etching a portion of the unwanted III-V type semiconductor region 131, a portion of the upper mask layer 128, and a portion of the lower mask layer 125. The waveguide structure 132 includes a MOS capacitor region with a pin junction. Standard etching techniques are used. The portion of the III-V type semiconductor region 131 adjacent to the silicon device layer 121 at the opening 126 is positioned away from the pin junction of the MOS capacitor region. Therefore, any defects in the III-V type semiconductor region 131 are positioned away from the pin junction, and thus their impact on the MOS capacitor region is reduced.

[0116] Similar to the first implementation scheme Figure 3k The steps shown in the diagram are followed by depositing an isolation layer 133 on top of the waveguide structure 132. Figure 4k In the example embodiment shown, the isolation layer 133 is an isolation oxide, such as silicon dioxide.

[0117] Finally, an isolation layer 133 is etched at the two openings reaching the silicon device layer 121 and the III-V semiconductor region 131, respectively, and electrical contacts 134 are deposited through the isolation layer 133 (see, for example, see...). Figure 4l Electrical contacts 134 are applied to the silicon device layer 121 and the region of the III-V type semiconductor region 131 that is laterally offset from the MOS capacitor region of the waveguide structure 132. The remaining portion of the lower mask layer 125 forms the insulating layer of the pin junction in the MOS capacitor region.

[0118] exist Figure 2 The resulting modulator 100 is shown in the figure. Similar to... Figure 1In the first embodiment shown, the insulating layer 125 of the modulator 2 (formed by the lower mask layer) has a “Z” shape formed by a first upper horizontally extending portion 125a, a second vertically extending portion 125b, and a third lower horizontally extending portion 125c.

[0119] Unlike Figure 1 The first implementation scheme shown, Figure 2 The silicon device layer 121 of the SOI substrate 120 shown includes a first horizontally extending portion 121a and a second vertically extending portion 121b. The first horizontally extending portion 121a is parallel to the BOX layer 122 and extends on top of the BOX layer, and the second vertically extending portion 121b extends vertically away from the BOX layer 122.

[0120] A first horizontally extending portion 125a of the insulating layer 125 extends horizontally above a vertically extending portion 121b of the silicon device layer 121. A second vertically extending portion 125b of the insulating layer 125 extends vertically and adjacent to the vertically extending portion 121b of the silicon device layer 121. A third lower horizontally extending portion 125c of the insulating layer 125 extends horizontally from the lower end of the second vertically extending portion 125b of the insulating layer 125 above the top of the BOX layer 122.

[0121] Unlike Figure 1 In the first embodiment shown, the III-V type semiconductor region 131 does not have a "Z" shape. Instead, the III-V type semiconductor region 131 includes a first vertically extending portion 131a, a second horizontally extending portion 131b, and a third vertically extending portion 131c. The first vertically extending portion 131a of the III-V type semiconductor region 131 extends vertically and adjacent to the vertically extending portion 125b of the insulating layer 125. Therefore, the second vertically extending portion 125b of the insulating layer 125 laterally (i.e., horizontally) separates the second vertically extending portion 121b of the silicon device layer 121 and the first vertically extending portion 131a of the III-V type semiconductor region 131. A first doped region is formed in the second vertically extending portion 121b of the silicon device layer 121, and a second doped region is formed in the first vertically extending portion 131a of the III-V type semiconductor region 131 to form a lateral MOS capacitor region having a pin junction extending parallel to the BOX layer.

[0122] exist Figure 2In the illustrated example embodiment, the insulating layer 125, the first doped region of the silicon device layer 121, and the second doped region of the III-V type semiconductor region 131 are formed of different materials. Specifically, the insulating layer 125 comprises silicon nitride, the silicon device layer has a Si(100) crystal orientation, and the III-V type semiconductor region 131 comprises InP, GaAs, InGaAs, or InGaAsP.

[0123] The following is for reference. Figures 5a to 5g describe Figure 2 An alternative manufacturing method for the MOS capacitor-type optical modulator 100 shown.

[0124] like Figure 5a As shown, a silicon-on-insulator (SiI) substrate 120 is initially provided, comprising a silicon base layer 123, a buried silicon dioxide (BOX) layer 122, and a silicon device layer 121. The silicon device layer 121 has a Si (100) crystal structure. Trench 124 is etched in the silicon device layer 121 to reach the BOX layer 122. The trench is etched using standard patterning and etching techniques. Although Figure 5a The first doped region is formed within the first silicon device layer 121 using a standard implantation technique, not shown in the diagram.

[0125] Next, as Figure 5b As shown, a lower mask layer 125 comprising silicon nitride is deposited on top of the silicon device layer 121 and in the trench 124. The lower mask layer 125 will form the insulating layer 125 of the MOS capacitor-type optical modulator 100 (in... Figure 2 (as shown in the image).

[0126] Then, opening 126 is etched in the lower mask layer 125. Similar to... Figure 4c As shown in the steps, the opening 126 in the lower mask layer 125 extends into the trench 124 to the silicon device layer 121 and the BOX layer 122. Similarly, the opening 126 is etched using standard patterning and etching techniques. This opening 126 provides a point of exposed silicon from which the III-V type layer will subsequently grow. The opening 126 is etched in a region of the lower mask layer 125 that will be laterally offset from the region of the MOS capacitor having the pin junction of the modulator 100.

[0127] and Figure 4d Compared to the method steps shown in the diagram for depositing the sacrificial layer, in... Figure 5d In the opening 126, a III-V type semiconductor region 131 is selectively and epitaxially grown from the exposed silicon device layer 121. The III-V type semiconductor region 131 grows outward from the opening 126 to at least fill the trench 124.

[0128] Then, the III-V type semiconductor region 131 is planarized by CMP so that the semiconductor region 131 exists only in the trench 124 (e.g., see...). Figure 5e In this way, the semiconductor region 131 in the trench 124 is flush with the lower mask layer 125.

[0129] The waveguide structure 132 is formed by etching a portion of the unwanted III-V type semiconductor region 131, a portion of the upper mask layer 125, and a portion of the silicon device layer 121. An isolation layer 133 is deposited on top of the waveguide structure 132. Figure 5f ).

[0130] Finally, an isolation layer 133 is etched at the two openings reaching the silicon device layer 121 and the III-V type semiconductor region 131, respectively, and electrical contacts 134 are deposited through the isolation layer. Figure 5g ).

[0131] Although the invention has been described in conjunction with the exemplary embodiments described above, many equivalent modifications and variations will be apparent to those skilled in the art when this disclosure is given. Therefore, the exemplary embodiments of the invention set forth above should be considered illustrative rather than restrictive. Various changes may be made to the described embodiments without departing from the spirit and scope of the invention.

Claims

1. A MOS capacitor-type optical modulator, the MOS capacitor-type optical modulator comprising: A silicon-on-insulator (SOI) substrate, the SOI substrate comprising a silicon base layer, a buried silicon dioxide layer, and a silicon device layer, wherein trenches are etched in the silicon device layer to reach the buried silicon dioxide layer; as well as A waveguide structure, comprising a lateral MOS capacitor region, wherein an optical mode propagates through the lateral MOS capacitor region, the lateral MOS capacitor region comprising: A first doped region, wherein the first doped region is located in the silicon device layer of the SOI substrate; and The second doped region, wherein the first doped region, the second doped region, and the insulating layer are formed of different materials. The insulating layer is located on top of the silicon device layer and within the trench of the silicon device layer. The insulating layer has a Z-shape formed by a first portion extending horizontally on top of the first doped region and adjacent to the silicon device layer, a second portion extending vertically, and a third portion extending horizontally below the second doped region, on top of the buried silicon dioxide layer, and adjacent to the buried silicon dioxide layer. The first doped region is vertically separated from the second doped region by the first portion of the insulating layer, and is laterally separated from the second doped region by the second portion of the insulating layer to form the lateral MOS capacitor region.

2. The MOS capacitor-type optical modulator as claimed in claim 1, wherein the second doped region is formed in a III-V type semiconductor region.

3. The MOS capacitor-type optical modulator as claimed in claim 1 or claim 2, wherein the insulating layer comprises silicon nitride.

4. The MOS capacitor-type optical modulator of claim 1, wherein the silicon device layer of the SOI substrate has a (100) crystal orientation.

5. A method for manufacturing a MOS capacitor-type optical modulator, the MOS capacitor-type optical modulator comprising a waveguide structure having a lateral MOS capacitor region, wherein an optical mode propagates in the lateral MOS capacitor region, the lateral MOS capacitor region comprising an insulating layer, wherein the method comprises the following steps: A first doped region is provided in a silicon device layer of a silicon-on-insulator (SOI) substrate, wherein the SOI substrate includes a silicon base layer, a buried silicon dioxide layer, and the silicon device layer, and wherein a trench is etched in the silicon device layer extending to the buried silicon dioxide layer; and A semiconductor region is epitaxially grown from the silicon device layer of the SOI substrate, wherein the semiconductor region includes a second doped region, and the first doped region, the second doped region, and the insulating layer are each formed of different materials. The insulating layer is located on top of the silicon device layer and within the trench of the silicon device layer. The insulating layer has a Z-shape formed by a first portion extending horizontally on top of the first doped region and adjacent to the silicon device layer, a second portion extending vertically, and a third portion extending horizontally below the second doped region, on top of the buried silicon dioxide layer, and adjacent to the buried silicon dioxide layer. The first doped region is vertically separated from the second doped region by the first portion of the insulating layer, and is laterally separated from the second doped region by the second portion of the insulating layer to form the lateral MOS capacitor region.

6. The method of claim 5, wherein the semiconductor region is epitaxially grown from a region of the silicon device layer that is laterally offset from the lateral MOS capacitor region.

7. The method of claim 5 or claim 6, wherein the semiconductor region is a III-V type semiconductor region.

8. The method of claim 5, wherein the silicon device layer of the SOI substrate has a (100) crystal structure.

9. The method of claim 5, wherein the method further comprises the following step: A portion of the semiconductor region is etched to form the waveguide structure.

10. The method of claim 9, further comprising the step of: An isolation layer is deposited on the waveguide structure; The first electrical contact is applied to the first doped region through the isolation layer; and The second electrical contact is applied to the second doped region through the isolation layer.

11. The method of claim 5, wherein the method further comprises the following step: A cavity is formed below the upper mask layer; as well as The semiconductor region is epitaxially grown from the silicon device layer of the SOI substrate within the cavity.

12. The method of claim 11, wherein the upper mask layer comprises silicon nitride.

13. The method of claim 11 or claim 12, wherein the step of forming the cavity comprises: Provide a sacrifice layer; The upper mask layer is deposited on top of the sacrificial layer; as well as The sacrificial layer is selectively etched to form the cavity.

14. The method of claim 13, wherein the method further comprises the following step: A lower mask layer is deposited on top of the silicon device layer and in the trench; In the lower mask layer, an opening in the silicon device layer is etched at a region laterally offset from the lateral MOS capacitor region. as well as The sacrificial layer is deposited on the lower mask layer and in the openings within the lower mask layer.

15. The method of claim 14, further comprising the step of: Before depositing the upper mask layer, a portion of the sacrificial layer is etched to reach the lower mask layer.

16. The method of claim 13, wherein the method further comprises the following step: The sacrificial layer is planarized using chemical mechanical planarization (CMP).

17. The method of claim 13, wherein the sacrificial layer comprises alumina or amorphous silicon.

18. The method of claim 13, further comprising the step of: Before selectively etching the sacrificial layer to form the cavity, an opening reaching the sacrificial layer is etched in the upper mask layer.

19. The method of claim 5, further comprising the following step: The semiconductor region is planarized using chemical mechanical planarization (CMP).

20. A method for manufacturing a MOS capacitor-type optical modulator, the MOS capacitor-type optical modulator comprising a waveguide structure having a lateral MOS capacitor region, an optical mode propagating in the lateral MOS capacitor region, and the lateral MOS capacitor region comprising a semiconductor region, the method comprising the following steps: A cavity is formed below the upper mask layer; as well as The semiconductor region is epitaxially grown from a silicon device layer on a silicon-on-insulator (SOI) substrate within the cavity, wherein the SOI substrate comprises a silicon base layer, a buried silicon dioxide layer, and the silicon device layer, and wherein trenches are etched in the silicon device layer to reach the buried silicon dioxide layer. The silicon device layer includes a first doped region, and the semiconductor region includes a second doped region. The insulating layer is located on top of the silicon device layer and within the trench of the silicon device layer. The insulating layer has a Z-shape formed by a first portion extending horizontally on top of the first doped region and adjacent to the silicon device layer, a second portion extending vertically, and a third portion extending horizontally below the second doped region, on top of the buried silicon dioxide layer, and adjacent to the buried silicon dioxide layer. The first doped region is vertically separated from the second doped region by the first portion of the insulating layer, and is laterally separated from the second doped region by the second portion of the insulating layer to form the lateral MOS capacitor region.

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