Loss leveling in non-volatile memory

Abstract

This invention provides a method, circuit, and system for managing wear leveling in non-volatile memory. First, a raw physical block address (PBA) for a logical block address (LBA) used for a write operation is received. The raw PBA is one of a set of PBAs for data blocks in a non-volatile memory array. Each of these PBAs is uniquely mapped to a specific LBA using a multi-level interconnect network (MIN). Next, a swapped PBA is determined for the LBA. The swapped PBA can be selected from the set of PBAs uniquely mapped using the MIN. Then, the MIN can be configured to map the LBA to the swapped PBA. Finally, data from a first data block stored at the raw PBA can be swapped with data from a second data block stored at the swapped PBA.

Description

[0001] Cross-citation of related applications

[0002] This application claims priority to U.S. Application No. 17 / 213,005, filed March 25, 2021, which claims priority and benefit to U.S. Provisional Patent Application Serial No. 63 / 075,462, filed September 8, 2020, both of which are incorporated herein by reference. Background Technology

[0003] Some data stored in a non-volatile memory device can be accessed and overwritten frequently, while other data can be written once and remain in that state for a relatively long period of time. Physical non-volatile memory structures that experience frequent access can be subjected to greater electromechanical stress than areas that are not frequently accessed, and therefore, if no action is taken to mitigate this unbalanced use, they can experience a greater level of wear and tear over the lifetime of the device.

[0004] "Damage level" refers to a measure of the condition under which a collection of memory cells performs its designed functions of storing, holding, and providing data. In some embodiments, the damage level is a measure of the amount of degradation that the collection of memory cells has undergone. The damage level can be expressed as a number of PE cycles relative to the total number of programming and erasing (PE) cycles that the memory cells are expected to complete before becoming defective / inoperable.

[0005] For example, suppose a set of memory cells is designed and manufactured to function properly for 5,000 PE cycles. Once an example set of memory cells reaches 2,000 PE cycles, the wear level can be expressed as the ratio of the number of completed PE cycles to the number of PE cycles the set is designed to complete. In this example, the wear level could be expressed as 2 / 5, 0.4, or 40% of the cells worn or used. The wear level can also be expressed in terms of how many PE cycles the set is expected to complete. In this example, the remaining wear or lifetime of the memory cell set could be 3 / 5, 0.6, or 60%. In other words, the wear level can represent the amount of wear or lifetime of the memory cells used, or it can represent the amount of wear or lifetime of the memory cells held until they become defective, inoperable, or unusable.

[0006] One way to prevent imbalances in wear leveling is to reallocate logical block addresses (LBAs) of frequently accessed data to different sets of physical block addresses (PBAs), allowing the re-access rate to be diffused across the physical device. A "logical block address" is a value associated with a logical address in a block storage device for each of n logical blocks that can be used to store user data across the storage medium. In some block storage devices, logical block addresses (LBAs) can range from 0 to n per volume or partition. In a block storage device, each LBA directly maps to a specific data block, and each data block maps to a specific set of physical sectors or physical data block addresses (PBAs) on the physical storage medium. A "physical block address" is address information that uniquely identifies the physical location of a data block relative to other data blocks in the non-volatile memory array. A common method for managing LBA-to-PBA allocation may involve rearranging entries in an indirection table based on entries in a frequency of use table.

[0007] For page-based nonvolatile memory, a table for usage frequency and an indirect table for logical pages can be maintained. The most frequently addressed logical addresses can be periodically mapped to physical word lines. For a driver with M pages / sectors, the indirect table can have M entries, and each entry can occupy N bits, where N is log2(M).

[0008] For a 2-terabyte drive with 512-byte data blocks,

[0009] M = (2x10) 12 ) / 512=3.9x10 9 ,and

[0010] N = 32

[0011] Therefore, the storage area required to store the indirect table of this driver will be

[0012] M x log2(M) = 125Gb (~15GB)

[0013] Using a frequency table consumes a similar amount of storage area as an indirect table, so the total storage area required for this metadata can be approximately 30 gigabytes. In some implementations, 2+1 redundancy can be used to replicate the metadata, increasing this value to up to 90 gigabytes, or approximately 4.5% of the total disk space. Therefore, as the size of page-based nonvolatile memory products increases, a more practical solution is needed that occupies less disk space for allocating and reallocating LBAs to PBAs to overcome device diffusion loss levels and thus extend device lifespan. Summary of the Invention

[0014] This disclosure relates to a method for managing wear leveling in non-volatile memory. First, a raw physical block address (PBA) for a logical block address (LBA) used for a write operation can be received. The raw PBA may include one of a set of PBAs for data blocks in a non-volatile memory array. Each of these PBAs can be uniquely mapped to a specific LBA using a multi-level interconnect network (MIN). Next, a swapped PBA can be determined for each LBA. The swapped PBA can be selected from the set of PBAs uniquely mapped using the MIN. Then, the MIN can be configured to map LBAs to swapped PBAs. Finally, data from a first data block stored at the raw PBA can be swapped with data from a second data block stored at the swapped PBA.

[0015] This disclosure further relates to circuitry for managing wear leveling in a non-volatile memory. The circuitry may include a write access monitor, path tracking circuitry configured to track LBAs to PBAs via a multilevel interconnect network (MIN), an address translation manager, a control state, an accumulated control state, a wear level manager, and a data mover. The write access monitor counts write accesses to the non-volatile memory array by read / write circuitry. The MIN may include multiple switching elements and may map each LBA of the non-volatile memory array to a unique PBA. The address translation manager may use the path tracking circuitry to translate the LBA of each write access to a PBA. The control state considers current changes to the MIN. The accumulated control state considers changes to the MIN over time. The wear level manager changes the mapping of the two LBAs and two corresponding PBAs of the MIN in response to a signal from the write access monitor. The data mover automatically swaps data stored in data blocks between the two swapped PBAs in response to a signal from the wear level manager.

[0016] Finally, this disclosure relates to a system for managing wear leveling in nonvolatile memory. The system may include a nonvolatile memory array and a nonvolatile memory controller. The nonvolatile memory array may store data in memory cells. The nonvolatile memory controller may further include a processor, volatile memory, a host interface manager, an address translation manager, a wear level manager, and a memory interface manager. The host interface manager may communicate between a host and the nonvolatile memory controller. The address translation manager may include a Benes network, control states, and cumulative control states. The Benes network maps each logical block address (LBA) of the nonvolatile memory array to a unique physical block address (PBA). The Benes network may include multiple switching elements. The control states may account for current changes made to the Benes network. The cumulative control states may account for changes to the Benes network over time. The wear level manager may include routers, selectors, and data movers. Routers may determine the path through the Benes network from the original PBA of the LBA used for write operations. The Benes network may include a set of levels. The selector can refer to the accumulated control state to identify the switching element as an unchanged switching element in the stage closest to the output of the Benedictine network. The selector can further select the switching element along the path in the stage closest to the output of the Benedictine network, such that the selected switching element is an unchanged switching element. The selector can then change the selected unchanged switching element into a changed switching element, such that the path through the selected switching element leads to the swapped PBA. The data mover can atomically swap the data of a first data block stored at the original PBA with the data of a second data block stored at the swapped PBA. Finally, the memory interface manager can be coupled to a non-volatile memory array for reading data and writing data to the non-volatile memory array. Attached Figure Description

[0017] To facilitate identification of a particular element or action, one or more of the most significant digits in the reference numerals refer to the reference numeral that first introduces the element.

[0018] Figure 1 A schematic block diagram illustrating one embodiment of a system 100 according to one embodiment.

[0019] Figure 2 A block diagram illustrating one embodiment of a non-volatile memory device 200 according to one embodiment.

[0020] Figure 3 A block diagram illustrating one embodiment of a non-volatile memory controller 300 according to one embodiment.

[0021] Figure 4An Omega multilevel interconnection network 400 according to one embodiment is shown.

[0022] Figure 5A An aspect of a switching element according to one embodiment is shown.

[0023] Figure 5B An aspect of a switching element according to one embodiment is shown.

[0024] Figure 5C An aspect of the control state of a switching element according to one embodiment is shown.

[0025] Figure 6 A Beneath multilevel interconnection network 600 according to one embodiment is shown.

[0026] Figure 7 Example 700 according to one embodiment is shown.

[0027] Figure 8 Example 800 according to one embodiment is shown.

[0028] Figure 9 A Benedictine multilevel interconnection network 900 according to one embodiment is shown.

[0029] Figure 10 Example 1000 according to one embodiment is shown.

[0030] Figure 11 A Benedictine multilevel interconnection network 1100 according to one embodiment is shown.

[0031] Figure 12 Example 1200 according to one embodiment is shown.

[0032] Figure 13 A Benedictine multilevel interconnection network 1300 according to one embodiment is shown.

[0033] Figure 14 Example 1400 according to one embodiment is shown.

[0034] Figure 15 A Beneath multilevel interconnection network 1500 according to one embodiment is shown.

[0035] Figure 16 A system 1600 according to one embodiment is shown.

[0036] Figure 17 A graph showing the metadata per page according to one embodiment is shown.

[0037] Figure 18 This is an example block diagram of a computing device 1800 that may be incorporated into certain embodiments. Detailed Implementation

[0038] Instead of using metadata in an address mapping table to direct data from an LBA indication for a write operation to a specific physical PBA and tracking the LBA / PBA mapping, this disclosure uses a multi-level interconnect network (MIN) to associate or map LBAs to PBAs. In one instance, an LBA indicated at a MIN input maps to a PBA indicated at a MIN output. Three alternative embodiments are presented for changing the MIN to swap the PBAs assigned to LBAs:

[0039] 1. PBAs can be randomly selected for allocation to LBAs experiencing high traffic volumes, and the non-blocking MIN can be adjusted accordingly to record this change in allocation.

[0040] 2. A random switching element within MIN, along a path through MIN representing a mapping from a certain PBA to an LBA, can switch from a first state, such as a through state, to a second state, such as a cross state, or vice versa.

[0041] 3. An algorithm can be used to select a switching element along the path to indicate correlation, and the switching can change its state.

[0042] These aspects of the disclosed solution are described in more detail below.

[0043] Figure 1 This is a block diagram of one embodiment of a system 100 including a non-volatile memory device 140 configured according to an embodiment of the claimed solution. The storage device 104 of the computing device 102 may include a processor 106, volatile memory 108, and a communication interface 110. The processor 106 may include one or more central processing units, one or more general-purpose processors, one or more dedicated processors, one or more virtual processors (e.g., the computing device 102 may be a virtual machine operating within a host), one or more processor cores, etc. The communication interface 110 may include one or more network interfaces configured to communicatively couple the computing device 102 and / or the non-volatile memory controller 138 to a communication network 114, such as an Internet Protocol (IP) network, a storage area network (SAN), a wireless network, a wired network, etc.

[0044] In various embodiments, the non-volatile memory device 140 may be located in one or more different locations relative to the computing device 102. In one embodiment, the non-volatile memory device 140 includes one or more non-volatile memory elements 132, such as semiconductor chips, memory dies, or packages, or other integrated circuit devices mounted on one or more printed circuit boards, memory housings, and / or other mechanical and / or electrical support structures. For example, the non-volatile memory device 140 may include one or more direct-access memory module (DIMM) cards, one or more expansion cards and / or daughter cards, solid-state drives (SSDs) or other hard disk drive devices, and / or may have another memory and / or storage form factor known to those skilled in the art. The non-volatile memory device 140 may be integrated with and / or mounted on the motherboard of the computing device 102, mounted in a port and / or slot of the computing device 102, mounted on a dedicated storage device on a different computing device 102 and / or network 114, or communicate with the computing device 102 via an external bus (e.g., an external hard disk drive), etc.

[0045] In one embodiment, the non-volatile memory device 140 may be located on the memory bus of the processor 106 (e.g., on the same memory bus as the volatile memory 108, on a different memory bus than the volatile memory 108, or in place of the volatile memory 108, etc.). In another embodiment, the non-volatile memory device 140 may be located on the peripheral bus of the computing device 102, such as a Peripheral Component Interconnect High Speed ​​(PCI High Speed ​​or PCie) bus, a Serial Advanced Technology Attachment (SATA) bus, a Parallel Advanced Technology Attachment (PATA) bus, a Small Computer System Interface (SCSI) bus, a FireWire bus, a Fibre Channel connection, a Universal Serial Bus (USB), a PCie-AS Advanced Switching (PCie-AS) bus, etc. In another embodiment, the non-volatile memory device 140 may be located on a data network 114, such as an Ethernet network, a wireless broadband network, a SCSI RDMA network on network 114, a Storage Area Network (SAN), a Local Area Network (LAN), a Wide Area Network (WAN) such as the Internet, another wired and / or wireless network 114, etc.

[0046] The computing device 102 may further include a non-transitory computer-readable storage medium 112. The computer-readable storage medium 112 may include executable instructions configured to cause the computing device 102 (e.g., processor 111) to perform one or more steps of the methods disclosed herein.

[0047] According to various embodiments, the non-volatile memory controller 138 may manage one or more non-volatile memory devices 140 and / or non-volatile memory elements 132. The non-volatile memory device 140 may include recording, memory, and / or storage devices, such as solid-state storage devices and / or semiconductor storage devices arranged and / or partitioned into multiple addressable storage locations. As used herein, a storage location refers to any physical unit of memory (e.g., any number of physical storage media on the non-volatile memory device 140). Memory units may include, but are not limited to, pages, physical page memory partitions, blocks, data blocks, erase blocks, sectors, series or sets of physical storage locations (e.g., logical pages, logical blocks, logical erase blocks), etc.

[0048] A "physical page" refers to the smallest physical unit or block of memory within a given memory die and / or plane (e.g., a memory die) that can be written to in a single operation. In some embodiments, a physical page comprises a word line of a row in a memory array that serves as a memory cell.

[0049] A "data block" refers to the smallest physical quantity of storage space on a physical storage medium that can be accessed and / or addressed using storage commands. Physical storage media can be volatile memory, non-volatile memory, persistent storage, flash memory, hard disk drives, etc. Some conventional storage devices divide the physical storage medium into volumes or logical partitions (also called partitions). Each volume or logical partition can contain multiple sectors. One or more sectors are organized into blocks (also called data blocks).

[0050] In, for example, those with In some storage systems that interface with an operating system, data blocks are called clusters. In other storage systems, such as those that interface with UNIX, Linux, or similar operating systems, data blocks are simply called blocks. A data block or cluster represents the smallest physical quantity of storage space on the storage medium managed by the storage controller. A block storage device associates n data blocks, numbered from 0 to n, with logical block addresses (LBAs) that can be used to store user data across the physical storage medium. In some block storage devices, logical block addresses can range from 0 to n per volume or logical partition. In conventional block storage devices, logical block addresses are directly mapped to a data block.

[0051] "Erase block" refers to either a logical erase block or a physical erase block. In one embodiment, a physical erase block represents the smallest memory cell within a given die that can be erased at a given time (e.g., due to wiring of memory cells on the die). In one embodiment, a logical erase block represents the smallest block that can be erased by a non-volatile memory controller in response to receiving an erase command. In this embodiment, when the non-volatile memory controller receives an erase command specifying a particular logical erase block, the non-volatile memory controller can erase every physical erase block within that block simultaneously. It should be noted that physical erase blocks within a given logical erase block can be considered contiguous in the physical address space, even if they reside on separate dies. Therefore, the term "contiguous" can be applied not only to data stored on the same physical medium but also to data stored on separate media.

[0052] In some embodiments, the device driver and / or non-volatile memory controller 138 may present a logical address space 122 to the storage client 116. As used herein, the logical address space 122 refers to a logical representation of a memory resource. The logical address space 122 may include multiple (e.g., a series) logical addresses. As used herein, a logical address refers to any identifier used to reference a memory resource (e.g., data), including but not limited to logical block addresses (LBAs), cylinder / head / sector (CHS) addresses, filenames, object identifiers, inodes, universally unique identifiers (UUIDs), globally unique identifiers (GUIDs), hash codes, signatures, index entries, ranges, degrees, etc.

[0053] The device driver of the non-volatile memory device 140 can maintain metadata 124, such as a logical-to-physical address mapping structure, to map logical addresses in the logical address space 122 to storage locations on the non-volatile memory device 140. The device driver can be configured to provide storage services to one or more storage clients 116. Storage clients 116 may include local storage clients 116 operating on the computing device 102 and / or remote storage clients 116 accessible via the network 114 and / or the communication interface 110. Storage clients 116 may include, but are not limited to, operating systems, file systems, database applications, server applications, kernel-level processes, user-level processes, applications, etc.

[0054] The device driver is communicatively coupled to one or more non-volatile memory devices 140. The one or more non-volatile memory devices 140 may comprise different types of non-volatile memory devices, including, but not limited to, solid-state storage devices, semiconductor storage devices, SAN storage resources, etc. The one or more non-volatile memory devices 140 may include one or more of a corresponding non-volatile memory controller 138 and / or non-volatile memory media 130. The device driver may provide write access to the one or more non-volatile memory devices 140 via a conventional block I / O interface 118. Additionally, the device driver may provide write access to other functionalities via a storage-class memory interface (SCM interface 120). Metadata 124 can be used to manage and / or track data operations performed through any of the block I / O interface 118, SCM interface 120, or other relevant interfaces.

[0055] In one embodiment, a user application, such as a software application operating on or in conjunction with storage client 116, uses storage device 104. Storage client 116 manages files and data and utilizes the functionality and features of non-volatile memory controller 138 and associated non-volatile memory media 130. Representative examples of storage clients include, but are not limited to, servers, file systems, operating systems, database management systems (“DBMS”), volume managers, etc. In one embodiment, storage client 116 performs write access to one or more non-volatile memory devices 140 via a conventional block I / O interface 118.

[0056] Some conventional block storage devices divide the storage medium into volumes or partitions. Each volume or partition can contain multiple sectors. One or more sectors are organized into blocks (also called data blocks). For example, those with... In some storage systems that interface with an operating system, a data block is called a cluster. In other storage systems, such as those that interface with UNIX, Linux, or similar operating systems, a data block is simply called a block. A data block or cluster represents the smallest physical quantity of storage space on the storage medium managed by the non-volatile memory controller 138. A block storage device associates n blocks, numbered from 0 to n, with logical block addresses that can be used to store user data across the non-volatile memory medium 130. In some block storage devices, logical block addresses can range from 0 to n per volume or partition. In conventional block storage devices, logical block addresses are directly mapped to specific logical blocks.

[0057] The device driver can present the logical address space 122 to the storage client 116 through one or more interfaces. As discussed above, the logical address space 122 may include multiple logical addresses, each corresponding to a corresponding storage location within one or more non-volatile memory devices 140. The device driver may maintain metadata 124, which includes any-to-any mappings between logical addresses and storage locations, etc.

[0058] The device driver may further include and / or communicate with a non-volatile memory device interface 126, the non-volatile memory device interface 126 being configured to transmit data, commands, and / or queries to one or more non-volatile memory devices 140 via a bus 136, the bus 136 including, but not limited to: the processor 106 memory bus, a peripheral component interconnect high-speed (PCI High Speed ​​or PCIe) bus, a Serial Advanced Technology Attachment (ATA) bus, a parallel ATA bus, a Small Computer System Interface (SCSI), FireWire, Fibre Channel, Universal Serial Bus (USB), a PCIe Advanced Switching (PCIe-AS) bus, a network 114, wireless broadband, SCSI RDMA, non-volatile memory high-speed (NVMe), etc. The non-volatile memory device interface 126 may communicate with one or more non-volatile memory devices 140 using input / output control (IO-CTL) commands, IO-CTL command extensions, remote direct memory write access, etc.

[0059] Communication interface 110 may include one or more network interfaces configured to communicatively couple computing device 102 and / or nonvolatile memory controller 138 to network 114 and / or one or more remote network-accessible storage clients 116. Storage clients 116 may include local storage clients 116 operating on computing device 102 and / or remote storage clients 116 accessible via network 114 and / or communication interface 110. Nonvolatile memory controller 138 is part of and / or communicates with one or more nonvolatile memory devices 140. Although Figure 1 A single nonvolatile memory device 140 is depicted, but this disclosure is not limited in this respect and can be adapted to incorporate any number of nonvolatile memory devices 140.

[0060] The non-volatile memory device 140 may include one or more non-volatile memory elements 132 of the non-volatile memory medium 130, which may include, but are not limited to: ReRAM, memristor memory, programmable metallized cell memory, phase-change memory (PCM, PCME, PRAM, PCRAM, bidirectional universal memory, chalcogenide RAM, or C-RAM), NAND flash memory (e.g., 2D NAND flash memory, 3D NAND flash memory), NOR flash memory, nanometer random write access memory (nanometer RAM or NRAM), nanowire-based memory, silicon-oxide-based sub-10 nanometer processing memory, graphene memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, programmable metallized cell (PMC), conductive bridged RAM (CBRAM), magnetoresistive RAM (MRAM), magnetic storage media (e.g., hard disk, magnetic tape), optical storage media, etc. In some embodiments, one or more non-volatile memory elements 132 of the non-volatile memory medium 130 include storage-class memory (SCM).

[0061] While conventional technologies, such as NAND flash memory, can be addressable blocks and / or pages, in one embodiment, storage-class memory (SCM) is addressable bytes. In other embodiments, storage-class memory may be faster and / or have a longer lifespan (e.g., durability) than NAND flash memory; may have lower cost, use less power, and / or have higher storage density than DRAM; or provide one or more other benefits or improvements when compared to other technologies. For example, storage-class memory may include one or more non-volatile memory elements 132 of ReRAM, memristor memory, programmable metallized cell memory, phase-change memory, nanoRAM, nanowire-based memory, silicon-oxide-semiconductor-based sub-10 nanometer processing memory, graphene memory, SONOS memory, PMC memory, CBRAM, MRAM, and / or variations thereof.

[0062] Although the non-volatile memory medium 130 is referred to herein as a "memory medium," in various embodiments, the non-volatile memory medium 130 may more generally include one or more non-volatile recording media capable of recording data, and may be referred to as a non-volatile memory medium, non-volatile storage medium, etc. Furthermore, in various embodiments, the non-volatile memory device 140 may include a non-volatile recording device, a non-volatile memory device, a non-volatile storage device, etc.

[0063] The non-volatile memory medium 130 may include one or more non-volatile memory elements 132, which may include, but are not limited to, chips, packages, planes, dies, etc. The non-volatile memory controller 138 may be configured to manage data operations on the non-volatile memory medium 130 and may include one or more processors, programmable processors (e.g., FPGAs), ASICs, microcontrollers, etc. In some embodiments, the non-volatile memory controller 138 is configured to store data on the non-volatile memory medium 130 and / or read data from the non-volatile memory medium 130, to transfer data to / from the non-volatile memory device 140, etc.

[0064] A nonvolatile memory controller 138 may be communicatively coupled to a nonvolatile memory medium 130 via a bus 134. The bus 134 may include a bus for transferring data to / from the nonvolatile memory element 132. In one embodiment, the bus 134 may further include a control bus for transmitting addressing and other command and control information to the nonvolatile memory element 132. In some embodiments, the bus 134 may communicatively couple the nonvolatile memory elements 132 to the nonvolatile memory controller 138 in parallel. This parallel write access may allow the nonvolatile memory elements 132 to be managed as groups, thereby forming logical memory elements 128. Logical memory elements 128 may be partitioned into corresponding logical memory cells (e.g., logical pages) and / or logical memory partitions (e.g., logical data blocks, logical blocks, logical erase blocks). Logical memory cells may be formed by logically combining the physical memory cells of each of the nonvolatile memory elements 132.

[0065] In some embodiments, the nonvolatile memory controller 138 may be configured to store data on one or more asymmetric write-once media (e.g., nonvolatile memory media 130). As used herein, a "write-once" storage medium is a storage medium that is reinitialized (e.g., erased) each time new data is written or programmed on it. As used herein, an "asymmetric" storage medium is a storage medium that has different latency for different storage operations. Many types of nonvolatile memory media 130 are asymmetric; for example, read operations may be much faster than write / program operations, and write / program operations may be much faster than erase operations (e.g., read media may be hundreds of times faster than erase and tens of times faster than program media).

[0066] In some embodiments, the non-volatile memory medium 130 may be partitioned into erasable groups (e.g., erase blocks) to accommodate memory partitioning, particularly considering the asymmetric nature of the medium. Thus, modifying a single data sector or block in situ may involve erasing the entire erase block containing the data and rewriting the modified data along with the original, unchanged data to the erase block. This can result in inefficient "write amplification," which may excessively wear down the non-volatile memory medium 130.

[0067] Therefore, in some embodiments, the non-volatile memory controller 138 may be configured to write data off-site. As used herein, "off-site" data writing means writing data to a different physical storage location, rather than "in-situ" overwriting data (e.g., overwriting data in the original physical location). Off-site data modification avoids write amplification because it is not necessary to erase and rewrite existing valid data on the erase block containing the data to be modified. Furthermore, off-site data writing can mitigate the latency effects of certain storage operations.

[0068] The non-volatile memory controller 138 may be organized into multiple erase blocks of word lines within the non-volatile memory element 132. In some embodiments, the addresses of the word lines are used such that the word lines are logically organized into a monotonically increasing sequence (e.g., decoding and / or converting the addresses of the word lines into a monotonically increasing sequence, etc.). In another embodiment, the word lines of the erase blocks within the non-volatile memory element 132 may be physically arranged in a monotonically increasing sequence of word line addresses, wherein consecutively addressed word lines are also physically adjacent (e.g., WL0, WL1, WL2...WLN).

[0069] The non-volatile memory controller 138 may include a device driver executing on the computing device 102 and / or communicate with the device driver. The device driver may provide storage services to the storage client 116 via one or more interfaces (block I / O interface 118, SCM interface 120, and / or others). In some embodiments, the device driver provides the computing device 102 block I / O interface 118, through which the storage client 116 performs block-level I / O operations. Alternatively or additionally, the device driver may provide the SCM interface 120, which may provide other storage services to the storage client 116. In some embodiments, the SCM interface 120 may include an extension to the block I / O interface 118 (e.g., the storage client 116 may write access to the SCM interface 120 by extending or adding to the block I / O interface 118). Alternatively or additionally, the SCM interface 120 may be provided as a separate API, service, and / or library.

[0070] The device driver may further include a non-volatile memory device interface 126 configured to transmit data, commands, and / or queries to a non-volatile memory controller 138 via a bus 136, as described above.

[0071] Figure 2 A non-volatile memory device 200 according to one embodiment is illustrated. The non-volatile memory device 200 includes a non-volatile memory controller 202 and a non-volatile memory array 204. The non-volatile memory array 204 is an array of non-volatile memories. "Non-volatile memory" is an abbreviation for non-volatile memory medium. In some embodiments, non-volatile memory medium refers to a non-volatile memory medium and logic, controllers, processors, state machines, and / or other peripheral circuitry that manages the non-volatile memory medium and provides write access to the non-volatile memory medium.

[0072] "Non-volatile memory media" refers to any hardware, device, component, element, or circuit configured to maintain changeable physical characteristics for representing binary values ​​of zero or one after the main power supply is removed. Examples of changeable physical characteristics include, but are not limited to, the threshold voltage of a transistor, the resistance level of a memory cell, the current level through the memory cell, magnetic pole orientation, spin-transfer torque, etc.

[0073] The variable physical characteristics ensure that, once set, they remain sufficiently fixed, allowing for the measurement, detection, or sensing of variable physical characteristics when reading, retrieving, or sensing binary values, even when the mains power supply for the non-volatile memory medium is unavailable. In other words, a non-volatile memory medium is a storage medium configured such that data stored on it can be retrieved after power to the non-volatile memory medium has been removed and subsequently restored.

[0074] Non-volatile memory media may include one or more non-volatile memory elements, which may include, but are not limited to, chips, packages, planes, memory dies, etc. Examples of non-volatile memory media include, but are not limited to: ReRAM, memristor memory, programmable metallized cell memory, phase-change memory (PCM, PCME, PRAM, PCRAM, bidirectional universal memory, chalcogenide RAM or C-RAM), NAND flash memory (e.g., 2D NAND flash memory, 3D NAND flash memory), NOR flash memory, nanometer random access memory (nanometer RAM or NRAM), nanowire-based memory, silicon-oxide-based sub-10 nanometer processing memory, graphene memory, silicon-oxide-nitride-oxide-silicon (SONOS), programmable metallized cell (PMC); conductive bridged RAM (CBRAM); magnetoresistive RAM (MRAM), magnetic storage media (e.g., hard disks, magnetic tapes), optical storage media, etc.

[0075] Although non-volatile memory media are referred to herein as "memory media," in various embodiments, non-volatile memory media may be more generally referred to as non-volatile memory. Because non-volatile memory media are capable of storing data when power is removed, they may also be referred to as recording media, non-volatile recording media, storage media, memory, non-volatile memory, volatile memory media, non-volatile memory medium, non-volatile memory, etc.

[0076] In some embodiments, data stored in a non-volatile memory medium can be addressed at the block level, meaning that the data in the non-volatile memory medium is organized into data blocks, each with a unique logical address (e.g., LBA). In other embodiments, data stored in a non-volatile memory medium can be addressed at the byte level, meaning that the data in the non-volatile memory medium is organized into data bytes (8 bits), each with a unique address (e.g., logical address). An example of a byte-addressable non-volatile memory medium is a storage-class memory (SCM).

[0077] A “non-volatile memory controller” refers to any hardware, device, component, element, or circuit configured to manage data operations on a non-volatile memory medium, and may include one or more processors, programmable processors (e.g., FPGAs), ASICs, microcontrollers, etc. In some embodiments, a non-volatile memory controller is configured to store data on and / or read data from a non-volatile memory medium to transfer data to / from a non-volatile memory device, etc.

[0078] A "non-volatile memory array" refers to a collection of non-volatile memory cells (also called memory cells or non-volatile memory units) organized into an array structure with rows and columns. Memory arrays can be addressed using row identifiers and column identifiers.

[0079] Those skilled in the art will recognize that a memory array may include an in-plane set of memory cells, an in-plane set of memory cells, an in-plane set of memory cells, an in-plane set of memory cells, an in-plane set of memory cells, an in-plane set of memory cells, an in-plane set of memory cells, an in-plane set of memory cells, an in-plane set of memory cells, an in-plane set of memory cells, or have other known memory cell configuration architectures and arrangements.

[0080] A non-volatile memory array may comprise a collection of memory cells at several levels of organization within a memory or memory system. In one embodiment, in-plane memory cells may be organized into a memory array. In one embodiment, multiple in-plane memory cells of a memory die may be organized into a memory array. In one embodiment, memory cells within multiple memory dies of a memory device may be organized into a memory array.

[0081] The non-volatile memory device 200 may belong to a family of memories referred to as storage-class memory (SCM) or persistent memory. "Storage-class memory" refers to a type of non-volatile memory configured for faster write access compared to NAND memory and configured to write access to data organized into sectors. In one embodiment, a sector is 512 bytes. Examples of storage-class memory may include ReRAM, memristor memory, programmable metallized cell memory, phase-change memory (PCM, PCME, PRAM, PCRAM, bidirectional universal memory, chalcogenide RAM, or C-RAM), etc.

[0082] The non-volatile memory array 204 can be divided into several subarrays 206. Each subarray 206 can be further divided into several partitions 208, as shown. Subarrays 206 and partitions 208 can be addressed independently within the non-volatile memory array 204 and can include data blocks with physical block addresses. Alternatively or additionally, subarrays 206 and partitions 208 can be addressed in logical cells or groups.

[0083] Figure 3A non-volatile memory controller 300 is shown as one embodiment that may include circuitry for managing wear leveling in non-volatile memory. The non-volatile memory controller 300 may be connected to a non-volatile memory array 204. The non-volatile memory controller 300 may include an address translation manager 302, path tracking circuitry 304 for navigating a multi-level interconnect network 306, a wear level manager 308, read / write circuitry 310, a write access monitor 312, a data mover 314, an accumulation control state 316, a switch setting 318, a control state 320, and a switch setting 322.

[0084] Read / write circuitry 310 directs storage commands to the non-volatile memory array 204. A "storage command" refers to any command related to a storage operation. Examples of storage commands include, but are not limited to, read commands, write commands, maintenance commands, configuration commands, management commands, diagnostic commands, test mode commands, countermeasure commands, and any other commands that the storage controller can receive from the host or issue to another component, device, or system. Generally, a storage command is a command issued from the host or another component or device to the memory or memory device. A storage command typically initiates one or more storage operations.

[0085] For example, a read or write operation may include a logical block address (LBA) identifying the location for storing or accessing data by the read / write circuitry 310. A "read operation" refers to an operation performed on a memory cell to obtain, sense, detect, or determine the value of data represented by the state characteristics of the memory cell. A "write operation" refers to a storage command or memory command configured to instruct a receiver to write or store one or more data blocks on a permanent storage medium, such as a hard disk drive, non-volatile memory medium, etc. A write command may include any storage command that results in data being written to the physical storage medium of the storage device. A write operation may include enough data to fill one or more data blocks, or a write operation may include enough data to fill a portion of one or more data blocks. In one embodiment, a write operation includes a start LBA and a count indicating the number of LBAs indicating the data written to the storage medium.

[0086] Address translation manager 302 translates the LBA (Logical Block Address) contained in a storage command for each write access into a physical block address (PBA). An "address translation manager" refers to logic in a non-volatile storage device, chip, or component (e.g., a storage-class memory device or flash memory device) that includes abstract logic-to-physical address translation to provide the physical block addresses of the logical block addresses used by storage clients (e.g., hosts) and the physical block addresses of the data stored by the storage controller. The logic-to-physical translation layer maps logical block addresses (LBAs) to the physical addresses of the data stored on the solid-state storage medium. This mapping allows data to be referenced in the logical block address space using logical identifiers, such as block addresses. The logical identifiers do not indicate the physical location of the data on the solid-state storage medium, but rather serve as an abstract reference to the data.

[0087] Address translation manager 302 can perform this translation using path tracing circuit 304. Path tracing circuit 304 uses a multilevel interconnect network 306 (MIN), also known as an access network, to map LBAs to PBAs. The mapping operation of path tracing circuit 304 can also be referred to as a lookup operation.

[0088] A "multistage interconnection network" refers to any hardware, software, firmware, circuit system, component, module, logic, logic and data structure, device, or equipment that is configured, programmed, designed, arranged, or engineered to implement a dynamic interconnection network, comprising a set of interconnected nodes, each node being a switching element. Connections between nodes are edges. In this dynamic interconnection network, the interconnections between nodes can be altered by changing the switching elements at the nodes, thus changing the path from one node to another in the interconnection network. (Search 'multistage interconnection networks' on Wikipedia.com, December 1, 2019. Modified. Accessed July 21, 2020.)

[0089] In one embodiment, a multi-level interconnect network may include a logical construct or structure implemented by a combination of firmware, software, logic, and / or data structures. A multi-level interconnect network may include one of a variety of configurations. In some multi-level interconnect networks, switching elements may be interconnected in levels or layers. A multi-level interconnect network may contain a set of inputs and a set of outputs, and each input to the multi-level interconnect network may be mapped to a single output of the multi-level interconnect network. The traversal of a multi-level interconnect network from a given input to a given output from node to node (e.g., from switching element to switching element) is called a path, and this traversal is called path tracing. Changing one or more switching elements alters the path between the input and the output.

[0090] Examples of different multilevel interconnection network configurations include Benedictine networks, inverse Benedictine networks, bitone networks, inverse bitone networks, omega networks, inverse omega networks, butterfly networks, and inverse butterfly networks. In one embodiment, the multilevel interconnection network may include block encryption.

[0091] "Path tracing circuit" refers to a device, component, element, module, system, subsystem, circuit system, logic, hardware, subcircuit, or circuit configured and / or operable to determine a path from an input value, port, or setting of a multilevel interconnected network (MIN) along each edge and through each node of the MIN to a corresponding output value, port, or setting.

[0092] In some embodiments, each node of the MIN may include a switching element having two inputs and two outputs. The switching element may include two different configuration modes: one that makes the switching element a through switching element, and another that makes the switching element a cross switching element.

[0093] The path tracing circuit is configured to follow, traverse, or trace a path through MIN by: iteratively navigating from the input, MIN input to the first node in the first stage, determining the node's configuration, mode, or type (e.g., a through-switch element or a cross-switch element), and determining the output of said node leading to subsequent nodes in subsequent stages or the MIN output after the final stage. In some embodiments, the path tracing circuit 304 may be implemented using software or firmware.

[0094] Advantageously, the path tracing circuit 304 is configured to map an LBA to a PBA or look up a PBA using an LBA using a multi-level interconnect network 306, the multi-level interconnect network 306 being a logic construct (shown using dashed lines) of potentially very large size compared to other hardware or circuit implementations of a multi-level interconnect network 306. For example, some hardware implementations of the multi-level interconnect network 306 may contain 32 inputs and 32 outputs (e.g., 2^5 × 2^5). In contrast, the path tracing circuit 304 is configured to use a multi-level interconnect network 306 having 4,294,967,296 inputs and 4,294,967,296 outputs (e.g., 2^32 × 2^32).

[0095] While a multi-level interconnect network 306 with 2^32 inputs and 2^23 outputs can be implemented using hardware and / or circuitry, hardware implementation is generally impractical due to the required complexity, circuitry size, memory, and processing power. The path tracing circuit 304 overcomes these technical inefficiencies by utilizing the configuration of the multi-level interconnect network 306, the logic of the path tracing circuit 304, and a set of iterative steps for navigating the multi-level interconnect network 306. In the illustrated embodiment, the multi-level interconnect network 306 is a logical construct for the path tracing circuit 304 to operate partially and / or partially in an iterative manner.

[0096] In one embodiment, path tracing circuitry 304 is configured to determine portions of a complete path through a multi-level interconnect network 306 having N inputs and N outputs by iteratively processing a set of levels through the multi-level interconnect network 306. In this way, a large multi-level interconnect network 306 (e.g., 2^32 inputs by 2^32 outputs) can be processed using minimal hardware, minimal storage, minimal memory, and minimal processing.

[0097] In one embodiment, for each iteration, path tracing circuitry 304 is configured to map a single input to one of 2^k outputs, where k is the number of levels. Path tracing circuitry 304 is configured to be implemented in hardware. The number of levels implemented varies based on product and / or design specifications. If an embodiment of path tracing circuitry 304 is configured to map for k = 4 levels in each iteration, then path tracing circuitry 304 can determine the mapping of subnetworks in multi-level interconnect network 306 through 15 nodes (1 for the start node, 2 for the next level, 4 for the next level, and 8 for the fourth level). In some embodiments, the outputs from each level in the subnetwork can be pre-computed for a given input or input node. In this iterative manner, a small portion of the entire multi-level interconnect network 306 is implemented.

[0098] For illustrative purposes, assume that the multi-level interconnect network 306 is a Benedictine network of size 2^N inputs by 2^N outputs (described in more detail below), with N*(N+1) / 2 levels, where each node has 2^(Nl) nodes (e.g., switching elements). Further assume N = 32 and k = 4, such that the multi-level interconnect network 306 has 528 levels, with each level having 2,147,483,648 nodes. In this example, the path tracing circuit 304 requires 132 iterations (# levels / k = 528 / 4) to completely traverse the multi-level interconnect network 306 and map an LBA to a PBA.

[0099] At the start of iteration 132, the path tracing circuit 304 is given an LBA as an input parameter. Using this input parameter, the output path for each node in k levels (e.g., four in this example) can be pre-calculated and loaded via the path tracing circuit 304. The path through k levels can be determined using a state machine or firmware configured according to the connectivity pattern for the multi-level interconnection network 306.

[0100] Continuing with the example of k=4, assume the starting node is Pl, Pout is the final level in this set, and Pl,0 indicates that the first node connected to Pl is a through-switching element, and P1,I indicates that the second node connected to Pl is a cross-switching element. The path from Pl to Pout in a single iteration can be represented as follows: Pl-->(Pl,0,Pl,l)-->(Pl,0,0,Pl,0,0,Pl,1,0,Pl,1,1)-->(Pl,0,0,0,Pl,0,0,1,Pl,0,1,0,Pl,0,1,1,Pl,1,0,0,Pl,1,0,1,Pl,1,1,0,Pl,l,1,1)-->Pout. Pout then becomes the starting node for subsequent iterations, and the path tracing circuit 304 repeats the path traversal for the subsequent k-level sets (here, level 4, i.e., 5 to 8). After 132 iterations, the path tracing circuit 304 has determined the PBA mapped to the original LBA.

[0101] The wear level manager 308 may be coupled to the address translation manager 302 to implement the methods disclosed herein to prevent or mitigate excessive wear in a portion or block of data in the non-volatile memory array 204. A “wear level manager” refers to any hardware, software, firmware, circuitry, component, module, logic, apparatus, or device configured, programmed, designed, arranged, or engineered to manage the wear level of a memory cell or storage unit. In some embodiments, the wear level manager performs certain functions and / or operations on the memory cells to mitigate excessive wear or degradation of the memory cells. In one embodiment, the wear level manager may operate to ‘uniform’ or ‘equalize’ the wear of the memory cells across the non-volatile memory array.

[0102] The loss level manager 308 may include a write access monitor 312 and a data mover 314. A "write access monitor" is any hardware, software, firmware, circuitry, component, module, logic, device, or apparatus that is configured, programmed, designed, arranged, or engineered to track, monitor, or measure write accesses, access requests, storage commands, write operations, read operations, etc., between a host and a storage device.

[0103] "Write access" refers to a write operation that has an associated LBA and data to be written to a non-volatile memory medium at a PBA that is uniquely mapped to an LBA, or a read operation that has an associated LBA and data to be read from a non-volatile memory medium at a PBA that is uniquely mapped to an LBA.

[0104] Write access monitor 312 can count write accesses to the non-volatile memory array 204 by read / write circuitry 310. In one embodiment, write access monitor 312 can signal to wear level manager 308 in response to a threshold number of write accesses performed by read / write circuitry 310. In another embodiment, write access monitor 312 can signal to wear level manager 308 in response to a pseudo-random number generated by write accesses performed by read / write circuitry 310. In this embodiment, write access monitor 312 may include random number generator 324.

[0105] Random number generator 324 may include a uniform random number generator (URNG) and a comparator. The seed for the URNG may be derived from a clock or serial number of the product, etc. A probability factor or rate for signaling used in swapping operations can be set. In one example embodiment, the probability factor / rate is 0.01. This probability rate establishes an average change in the LBA-to-PBA mapping once every 100 write accesses. In one embodiment, the probability rate may serve as a safety feature, causing the LBA-to-PBA allocation to change at an unpredictable rate, ensuring that certain locations on the non-volatile memory medium receive appropriate wear leveling.

[0106] In one example, the URNG can generate a 14-bit pseudo-random number between 0 and 16383, and if the random number generated by the URNG is equal to or less than 164 (since 0.01 of 16384 is approximately 164), then the comparator can signal an LBA / PBA swap operation. The random number generator 324 can generate a pseudo-random number for each write access. By applying a probability factor and using a comparator, the random number generator 324 determines the pseudo-random number for the write access. In one embodiment, the pseudo-random number for the write access may include the number of write accesses that, before the random number generator 324, are processed with the probability factor and comparator signal to trigger the LBA / PBA swap operation. In one embodiment, the pseudo-random number for the write access includes the number N of write accesses that occur on average once every D write accesses, where D > 10, before the random number generator 324, are processed with the probability factor and comparator signal to trigger the LBA / PBA swap operation.

[0107] In one embodiment, the pseudo-random number for write access may include a predefined pseudo-random number. The predefined pseudo-random number may be generated by a pseudo-random number generator. The write access monitor 312 may be configured to signal the loss level to change one or more LBA mappings when the pseudo-random number generator generates a predefined pseudo-random number. The write access monitor 312 may also signal the pseudo-random number generator to generate a new pseudo-random number each time a write access occurs.

[0108] Advantageously, the nonvolatile memory controller 300, featuring a wear level manager 308, a write access monitor 312, and a random number generator 324, can determine when to perform an LBA / PBA swap operation without any input, communication, or interaction with system-level drivers or applications. The independent determination of when to perform an LBA / PBA swap operation by the write access monitor 312 provides an additional level of security to ensure that the nonvolatile memory medium is not prematurely damaged or worn out.

[0109] The loss level manager 308 can change the mapping of two or more LBAs and two or more corresponding PBAs in response to a signal from the write access monitor 312. A “signal” refers to an electrical signal (wired or wireless), communication, or indication sent from one module, logic unit, component, circuit, driver, device, manager, or controller to another component, circuit, sub-circuit, driver, device, manager, or controller. In one embodiment, the signal includes an analog signal. In another embodiment, the signal includes a digital signal. In one embodiment, the signal includes a message sent using software and / or firmware.

[0110] In response to a change in the mapping of two or more LBAs and two or more corresponding PBAs by the loss level manager 308, the data mover 314 can atomically swap data stored in data blocks of two or more swapped PBAs. In one embodiment, the data mover 314 can perform the swap in response to a signal from the loss level manager 308. "Data mover" refers to any hardware, software, firmware, circuitry, component, module, logic, device, or apparatus configured, programmed, designed, or engineered to copy or move one or more data blocks from a source location to a destination location. Specifically, a data mover is configured to perform low-level operations to transfer copies of one or more data blocks from a source PBA to a destination PBA.

[0111] In some embodiments, the data mover deletes or erases the data block once it is properly stored at the destination location. In other embodiments, the data mover uses temporary storage space for the data block from the destination location and overwrites the data at the destination location. If the data mover swaps data between the destination and source locations, it may then store the data in temporary storage space at the source location.

[0112] The multilevel interconnect network 306 may include multiple switching elements and may map each LBA of the non-volatile memory array 204 to a unique PBA, as described below. The multilevel interconnect network 306 may include an omega network, a Benedictine network, or a bitone network. (About...) Figure 4 and Figure 6 An embodiment of the multi-level interconnection network 306 is described in more detail.

[0113] Control state 320 may take into account current changes to the switching settings 322 of the multilevel interconnection network 306. “Control state” refers to a state that is designed, engineered, configured, or arranged to represent the current state of the switching elements within the multilevel interconnection network (MIN) at a specific point in time.

[0114] Typically, a multilevel interconnect network has an initial state, which represents the state or configuration of each switching element when the multilevel interconnect network is first created or instantiated. This initial state is the control state at time point 0 when the MIN is first created. Over time, it may be necessary to change the state, configuration, or status of one or more switching elements within the MIN. Before the change, the control state represents the state of the switching elements in the MIN. After the change, a new control state is created, which represents the state of the MIN at the new time point after the change.

[0115] Various changes can be represented by control states. In one embodiment, the change is achieved by altering the path through MIN by changing the input-to-output mapping of one or more switching elements.

[0116] Control states can be represented in various ways, including using algorithms and / or data structures. In one example embodiment, the control state is represented by a matrix or array data structure configured such that each entry in the matrix represents a node in an m×n network, and the value of each entry indicates whether the path through the switching element at the node in the network has changed / switched from an initial state to a different state.

[0117] In an exemplary embodiment, the control state may represent a MIN of m×n switching elements, where each switching element is a switch with two inputs, each input mapped to two outputs. In an exemplary embodiment, changing the switching elements may change the mapped outputs and inputs. In this exemplary embodiment, each entry in the control state may be set to '0' or '1', where '0' means that the switching element has not changed since its initial state, and '1' means that the switching element has changed from its initial state.

[0118] "State" refers to the conditions, attributes, patterns, and / or characteristics of a device, apparatus, component, system, subsystem, circuit, subcircuit, machine, logic module, state machine, etc. In some embodiments, state may include models or representations, mappings, associations, functional transitions, permutations, etc., of logic modules. State may be represented and / or defined by a single value, parameter, setting, attribute, or condition, or by multiple values, parameters, settings, attributes, or conditions collectively or individually.

[0119] "Current change" refers to a change that is currently in progress, is in the process of being implemented, or will be implemented in the near future. The cumulative control state 316 may consider changes to the switch settings 318 of the multi-level interconnected network 306 over time. "Switch settings" refer to settings, parameters, configurations, values, etc., that identify, define, or determine how a switch is configured to operate. As an example, a switch setting may identify whether a switch is on or off. In another example, a switch setting may identify how one or more inputs are routed, mapped, or associated with one or more outputs.

[0120] For example, in one embodiment, the switch setting can identify whether the switching element is in a through configuration, such as a through switching element. Alternatively or additionally, the switch setting can identify whether the switching element is in a cross configuration, such as a cross switching element.

[0121] In one embodiment, a switch setting may indicate whether a switching element has changed from its initial or initial configuration or state. A switching element may include one or more switch settings. Therefore, switch setting 322 may represent the current state of the switching element, and switch setting 318 may represent the state of the switching element over time, or the historical state of the switching element.

[0122] The multi-level interconnection network 306 may include logic configured to map LBAs to their original PBAs based on cumulative control states 316. A “cumulative control state” refers to the control state at a given point in time, encompassing the effects or influences of one or more control states iteratively applied to the initial control state over several iterations. The cumulative control state represents an overview of the control states up to the current number of iterations.

[0123] Therefore, the control state represents the state of a system, model, network, or device at a given point in time, while the cumulative control state represents the state of the system, model, network, or device, which includes any effects from the initial control state to the given point in time. In other words, the cumulative control state tracks the history of the control state of a system, model, device, or network (e.g., a multi-level interconnected network).

[0124] Figure 4 An Omega multilevel interconnection network 400 according to one embodiment is shown. An "Omega network" or "Omega multilevel interconnection network 400" refers to a type of multilevel interconnection network with multiple levels having 2×2 switching elements. Each input has a dedicated connection to an output. An N*N Omega network has log(N) levels and N / 2 switching elements in each level for perfect shuffling between levels. Therefore, the network has a complexity of O(N log(N)). Each switching element can employ its own switching algorithm. Omega networks are blocking networks. (Search 'multilevel interconnection network' on Wikipedia.com, December 1, 2019. Modified. Accessed July 8, 2020.)

[0125] The Omega multilevel interconnect network 400 includes switching elements 402 arranged in three levels: level 404a, level 404b, and level 404c. The Omega multilevel interconnect network 400 can communicate with a data structure configured to store an accumulated control state 316 including a switch setting 410 and a control state 320 including a switch setting 412.

[0126] Switching element 402 may include 2×2 (two by two) switches, as per [reference to...] Figure 5A and Figure 5B A more detailed description follows. A "switching element" refers to a node within a multi-level interconnected network configured with 'm' input terminals or nodes and 'n' output terminals or nodes. A switching element routes signals, paths, trajectories, processes, routes, lines, or pathways from an input terminal or node to an output terminal or node. In some embodiments, 'm' = 'n' and 'm' = 2. Switching elements can be implemented in hardware, firmware, software, logic, state machines, etc.

[0127] The three levels of switching element 402 can provide a configurable path, trajectory, process, route, line, or pathway from the input of, for example, LBA 406 to the output of, for example, PBA 408 associated with LBA 406. A “level” or “layer” refers to a collection of switching elements within a multi-level interconnection network. The number of levels within a multi-level interconnection network and / or the number of switching elements within each level depends on the type of multi-level interconnection network used.

[0128] For example, an Omega network with N inputs and N outputs (N×N) has log2(N) stages, and each stage contains N / 2 switching elements. A Benedictine network with N inputs and N outputs (N×N) has (2*log2(N)-1) stages, and each stage contains N / 2 switching elements.

[0129] In some embodiments, each switching element in the stage has the same number of inputs as the outputs. In one embodiment, each switching element comprises two inputs and two outputs.

[0130] A “path,” “process,” “trajectory,” “line,” or “route” refers to a set of nodes within a multilevel interconnected network that traverses from the input to the output of the multilevel interconnected network, where each node in the multilevel interconnected network is directed to only one output node based on a given input to the node, and where each node defines how the input to the node maps to the output. A path can include a logical or physical path through the multilevel interconnected network.

[0131] Control state 320 may include a data structure, such as a 3x4 matrix, as shown, configured to store entries for mapping to each switching element currently changing within the Omega multilevel interconnect network 400. When the Omega multilevel interconnect network 400 is first initialized, both control state 320 and the cumulative control state 316 matrix may be initialized to an initial state, such as a random combination of zeros and ones, or all zeros. Whenever a change is made to the Omega multilevel interconnect network 400, control state 320 may start from an initialized state (e.g., all zeros), and the cumulative control state 316 may not be reinitialized, instead retaining the state of previous changes made to the Omega multilevel interconnect network 400.

[0132] The cumulative control state 316 may include a data structure, such as a 3x4 matrix, as shown, configured to store entries for each switching element (a node of the network) corresponding to or mapped to a changing switching element within the Omega multilevel interconnect network 400.

[0133] The cumulative control state 316 can be configured to identify switching elements 402 not considered in the data structure as unchanged switching elements. For example, in one embodiment, the cumulative control state 316 can be represented using a two-dimensional array, where empty or zero entries in the array represent unchanged switching elements, and entries with values ​​such as '1' represent changed switching elements. This two-dimensional array in such an example saves storage space because the data values ​​do not store entries for representing unchanged switching elements, and only data values ​​are used to represent entries for changing switching elements.

[0134] A "changed switching element" refers to a switching element that has been changed at least once since the initial startup, configuration, or instantiation of the multilevel interconnection network. A "unchanged switching element" refers to a switching element that has not been changed at least once since the initial startup, configuration, or instantiation of the multilevel interconnection network. Changing a switching element means that, after the change, the routing of one or more inputs of the switching element from a first output to a second output is changed.

[0135] In some embodiments, the address translation manager 302 and the loss level manager 308 use path tracing circuitry 304 and multi-level interconnect network 306 to access, manage, reference, and / or translate or map LBAs to PBAs. Advantageously, the path tracing circuitry 304 can navigate the nodes and levels of the multi-level interconnect network 306 using minimal logic or hardware and / or memory to increase performance. The address translation manager 302 and the loss level manager 308 may coordinate with the path tracing circuitry 304 to map LBAs to PBAs through a process referred to herein as “tracing,” “path tracing,” or “traversal.”

[0136] Next, examples illustrate how the path tracing circuit 304 navigates the multi-level interconnect network 306. Figure 4 In this example, assume the LBA to be mapped is '100'. First, obtain the path from input '100' along the edge between input '100' and node 'A1' in level 404a.

[0137] In some embodiments, the path tracing circuit 304 may be implemented using a state machine, hourly sequential circuitry, etc. The path tracing circuit 304 may have multiple input data values, which, together with logic, enable the path tracing circuit 304 to model and traverse multi-level interconnect networks with a large number of inputs and outputs (e.g., 32 or more). One of these inputs is an accumulated control state 316. The accumulated control state 316 identifies how to configure each switching element within the multi-level interconnect network (e.g., a pass-through indicated by '0' or a crossover indicated by '1').

[0138] Path tracing circuit 304 is configured to determine how to organize and configure a multi-level interconnect network. For this first step, path tracing circuit 304 accesses a single switching element in the first level 404a within the MIN. Path tracing circuit 304 identifies this node as having only two outputs. Accumulated control state 316 identifies which input maps to which output (through or cross). Because path tracing circuit 304 is configured to understand how the MIN is organized, it can determine which two nodes in the second level 404b can be accessed after a given node in the first level 404a. Similarly, path tracing circuit 304 can determine which four nodes in the third level 404c can be accessed after a node in the second level 404b. Therefore, path tracing circuit 304 can iterate through the MIN based on its current configuration, accumulated control state 316, and given input values ​​without loading all node data into memory at once. Furthermore, depending on available memory and / or processing resources, the path tracing circuit 304 can map multiple paths through MIN during a single iteration, then refine the iteration as it looks at the nodes of each level. In one embodiment, the path tracing circuit 304 can pre-compute up to five levels in a single clock cycle. This proactive computation can be helpful for a Benedictine network with 2^32 inputs by 2^32 outputs, since a Benedictine network can contain 63 levels (N = 2^32, # level = 2log2N-1).

[0139] Advantageously, the path tracing circuit 304 can save memory space by using an accumulated control state 316 that defaults to '0' for the pass-through switching elements, so that the path tracing circuit 304 only needs to load 'l' values ​​for nodes connected to the nodes of the stage being checked. In this way, the path tracing circuit 304 can use a compressed form when using the data of the accumulated control state 316, resulting in minimal memory space usage. In some embodiments, most nodes of the MIN retain their original initialization state '0' for the pass-through switching elements, and the path tracing circuit 304 works with a minimal amount of memory space for the accumulated control state 316 used for the cross-switching elements. For example, an embodiment of program 1200 may change the switching elements only in the last two or three stages of the MIN (the stages closest to the output of the MIN), resulting in minimal memory space requirements for the accumulated control state 316 of zero for all switching elements in other stages, and for the accumulated control state 316 of the switching elements (e.g., switching element configuration) in the last two or three stages.

[0140] Continuing with the path tracing example, next, examine node 'A1' to determine which output is connected to the edge from input '100'. In this example, and at the current cumulative control state 316, node 'A1' is in a pass-through configuration, causing input '100' to connect to the output edge from 'A1' to 'B2'. Therefore, the path is obtained from 'A1' to 'B2'.

[0141] If node 'A1' is in a cross configuration, then cumulative control state 316 may contain a value that causes node 'A1' to be in a cross configuration that connects input '100' to the output edge from 'A1' to 'B1'.

[0142] Next, examine node 'B2' to determine which output is connected to the edge from 'A1'. In this instance, and at the current cumulative control state 316, node 'B2' is in a pass-through configuration, causing the input edge from 'A1' to be connected to the output edge from 'B2' to 'C3'. Therefore, the edge is obtained from 'B2' to 'C3'.

[0143] Next, node 'C3' is examined to determine which output is connected to the edge from 'B2'. In this instance, and at the current cumulative control state 316, node 'C3' is in a pass-through configuration, such that the input edge from 'B2' is connected to the output edge from 'C3' to output '100' (PBA '100'). Therefore, an edge is obtained from 'C3' to output '100'. After reaching output '100', the entire path has been traversed, and path tracing circuit 304 has successfully traced the path, in this instance, mapping LBA '100' to PBA '100'. The entire path includes every edge traversed from the input LBA to the output PBA.

[0144] The path tracing circuit 304 can use path tracing to determine the PBA mapped to the LBA, for example in an LBA-to-PBA lookup, or in conjunction with the loss level manager 308 to determine how the MIN can be changed to implement a swap of the PBA between two LBAs.

[0145] Figure 5A A switching element, also referred to as a pass-through switching element 502 in a pass-through configuration or setup, is shown. The pass-through switching element 502 may be implemented as... Figure 4One of the switching elements 402 described herein. In this example, switching element 402 may be the switching element marked 'A1' in the figure. A "through switching element" refers to a switching element having a first input, a second input, and a first output and a second output, wherein the switching element is configured such that a signal, path, trajectory, process, route, traversal, line, or pathway entering at the first input passes through the switching element and exits at the first output, and a signal, path, trajectory, process, route, traversal, line, or pathway entering at the second input passes through the switching element and exits at the second output.

[0146] The pass-through switch element 502 can be a 2x2 switch, meaning that each of the two inputs can be routed to each of the two outputs, shown here as IN-1 and IN-2, and OUT-1 and OUT-2, respectively. In the pass-through configuration, as shown, IN-1 can be connected to OUT-1, and IN-2 can be connected to OUT-2. In this way, an input of '000' to IN-1 can be routed to OUT-1, which... Figure 4 The Omega multi-level interconnect network 400 is further connected to the IN-I input of switching element B1. Input '100' to IN-2 can be routed to OUT-2, which can then be connected to the IN-1 input of switching element B2, such as... Figure 4 As shown in the figure.

[0147] Figure 5B A switching element, also referred to as cross switch element 504 in a cross configuration or setup, is shown. Cross switch element 504 may be implemented as... Figure 4 One of the switching elements 402 described herein. In this example, switching element 402 may be the switching element marked 'A2' in the figure. A "cross-switch element" refers to a switching element having a first input, a second input, and a first output and a second output, wherein the switching element is configured such that a signal, path, trajectory, process, route, line, or pathway entering at the first input exits at the second output, and a signal, path, trajectory, process, route, traversal, line, or pathway entering at the second input exits at the first output.

[0148] The cross switch element 504 can be a two-to-two switch, such as... Figure 5A As shown in the diagram. However, in the cross-connect configuration shown, IN-1 can be connected to OUT-2, and IN-2 can be connected to OUT-1. In this way, '001' input to IN-1 can be routed to OUT-2, which... Figure 4 The Omega multi-level interconnect network 400 is further connected to the IN-1 input of switching element B3. Input '101' to IN-3 can be routed to OUT-1, which can then be connected to the IN-I input of switching element B4, such as... Figure 4 As shown in the figure.

[0149] Figure 5C Example data structures, according to certain embodiments, are shown that can be used to track and / or accumulate control states. A “data structure” refers to a data organization, management, and storage format that enables efficient write access and modification. More precisely, a data structure is a set of data values, the relationships between them, and the functions or operations that can be applied to the data. (Search 'data structure' on Wikipedia.com, July 4, 2020. Modified. Accessed July 24, 2020.) Instances of data structures include, but are not limited to, queues, linked lists, lists, arrays, matrices, stacks, etc. An “entry” refers to a position within another thing, such as a data structure. Entries are configured to hold, store, or retain values, levels, or settings.

[0150] Entries 512 of data structure 506 may correspond to the switching settings 318 of the previously described switching element 402. For example, the switching setting of A1 508 can be found in the first entry 512 at the top of the leftmost column of the matrix. This entry 512 may be '0', corresponding to the state or condition of the A1 switching element that has not yet been changed from its original through-switch element 502 configuration. The entry 512 of the switching setting of A2 510 can be found in the next value (next row) of the first column of data structure 506. This entry 512 may be '1', corresponding to the state or condition of the A2 switching element that has been changed to the cross-switch element 504 configuration.

[0151] The illustrated Omega multilevel interconnect network 400 is merely a simple example of mapping a three-bit LBA to a three-bit PBA. When implementing the Omega multilevel interconnect network 400 in some embodiments, the LBA may include 32 bits, and the PBA may be 32 bits. Each 32-bit input Omega multilevel interconnect network 400 will have 2^32 (or 4,294,967,296) inputs and 2^32 outputs, with each of the 32 stages having 2^3I (or 2,147,483,648) switching elements. In this embodiment, the Omega multilevel interconnect network 400 is extremely large, with each of the 32 stages having 2^3I switching elements. Using matrices to represent the cumulative control states 316 and / or 320 uses less memory than mapping the LBAs to PBAs in a lookup table.

[0152] In conventional modules, devices, systems, or controllers, multilevel interconnect networks can be used to represent nodes and paths in a processing or communication network. In such conventional systems, the size of the multilevel interconnect network can be limited by the amount of volatile memory available for the system, as such systems can load data representing the entire multilevel interconnect network into volatile memory. Using a multilevel interconnect network, as in the disclosed embodiments for mapping logical block addresses to physical block addresses, is impractical due to the number of mappings managed and the metadata required to manage such mappings.

[0153] Advantageously, embodiments of this disclosure overcome this technical limitation by representing the multi-level interconnect network as logic within the controller, firmware, circuitry, and / or software, and by using data structures (e.g., a switch setting matrix for accumulating control states and another switch setting matrix for control states). By using this logic and these data structures, embodiments of the disclosed and claimed solutions utilize a multi-level interconnect network to map the LBA to the PBA, while still using minimal volatile memory.

[0154] In some embodiments, data defining the structure, configuration, and state of a multilevel interconnect network may be stored on a non-volatile memory medium. Due to the size of the multilevel interconnect network, the non-volatile memory controller 300 may load portions of the data defining and representing the multilevel interconnect network into volatile memory to provide PBA lookup functionality and / or LBA-to-PBA mapping changes as needed. The loaded portions may be significantly smaller than the data required to represent the entire multilevel interconnect network, its control state, and its cumulative control state.

[0155] The loaded portion can be a row of a control state data structure or a column of a cumulative control state data structure, and / or a path through a multi-level interconnect network. In this way, the amount of volatile memory required or used by the non-volatile memory controller 300 can be reduced to save costs and increase performance.

[0156] This is a simple example demonstrating the technical efficiency of using matrix data structures to manage the control states and / or cumulative control states of a MIN. Figure 4 In the example shown, when the switching element 402 is in the through state, the input can correspond to the output shown in the table below.

[0157] enter Output 000 000 001 001 010 010 011 011 100 100 101 101 110 110 111 111

[0158] For example, if the switch element 402 marked "C1" switches to the cross state, then the input will be associated with the output shown in the table below.

[0159] enter Output 000 001 001 000 010 010 011 011 100 100 101 101 110 110 111 111

[0160] Based on this simplified example, the conventional method of associating LBA and PBA can rely on maintaining, for example, the lookup tables described above, each with sixteen entries of three bits, totaling forty-eight bits. However, using the Omega multilevel interconnect network 400, the setting of each switching element 402 can be represented as '0' or '1' and maintained in a matrix with a single entry in row 0, column 3 indicating that the switching element is now the changed switching element. As previously described, a single entry in the matrix uses far less memory and / or storage area than a sixteen-entry lookup table. The switch setting table 410 of the cumulative control state 316 can maintain the setting of the switching element 402 over time, while the switch setting 412 in the control state 320 structure can maintain the currently applied switch setting.

[0161] Figure 6 A Beneath multilevel interconnect network 600 according to one embodiment is shown. Switching elements 602 are arranged in five levels: levels 604a, 604b, 604c, 604d, and 604e, where inputs (LBA 606) and outputs (PBA 608) are connected to form a Beneath network configuration. A “Beneath network” or “Beneath Omega multilevel interconnect network 400” refers to a rearrangeable, non-blocking network derived from a Clos network by initializing n = m = 2. There are (2log(N)-1) levels, where each level contains N / 2 2*2 cross switches. An 8*8 Beneath network has five levels with switching elements, and each level has four switching elements. The three central levels have two 4*4 Beneath networks. The 4*4 Beneath networks can recursively connect any input to any output. (Search 'multilevel interconnected networks' on Wikipedia.com, December 1, 2019. Edited. Accessed July 8, 2020.)

[0162] A "reconfigurable, non-blocking multilevel interconnect" refers to a multilevel interconnect configured such that each input has a corresponding output, and changing the configuration of any switching element within the multilevel interconnect will still produce a path between each input and each output. A Beneathian network is an example of a reconfigurable, non-blocking multilevel interconnect.

[0163] The switch settings 612 of control state 320 can be modified to account for changes in the state of selected switching elements. For example, in control state switch settings 612, a switching element that changes from a through state to a cross state (or vice versa) can be assigned a '1' to indicate that the switching element is a changed switching element. A '0' in the matrix of switch settings 612 can indicate that the state of the switching element has not changed, and a '1' in the matrix of switch settings 612 can indicate that the state of the switching element has changed or is changing. The switch settings 610 of cumulative control state 316 can be updated, for example, by a loss level manager 308 or another component of the non-volatile memory controller 300 to account for modified control state switch settings.

[0164] Next, examples describe how one embodiment of the path tracing circuit 304 can navigate a multi-level interconnect network 306. The path tracing circuit 304 can implement the steps outlined in the following examples. Figure 6 In this example, assume the LBA to be mapped is '010'. First, obtain the path from input '010' along the edge between input '010' and node 'A2' in stage 604a. Next, examine node 'A2' to determine which output is connected to the edge from input '010'. In this instance, and at the current cumulative control state 316, node 'A2' is in a pass-through configuration, causing input '010' to be connected to the output edge from 'A2' to 'B1'. Therefore, obtain the path from 'A2' to 'B1'.

[0165] Next, examine node 'B1' to determine which output is connected to the edge from 'A2'. In this instance, and at the current cumulative control state 316, node 'B1' is in a pass-through configuration, causing the input edge from 'A2' to be connected to the output edge from 'B1' to 'C2'. Therefore, the edge is obtained from 'B1' to 'C2'.

[0166] Next, examine node 'C2' to determine which output is connected to the edge from 'B1'. In this instance, and at the current cumulative control state 316, node 'C2' is in a pass-through configuration, causing the input edge from 'B1' to be connected to the output edge from 'C2' to 'D1'. Therefore, the edge from 'C2' to 'D1' is obtained.

[0167] Next, examine node 'D1' to determine which output is connected to the edge from 'C2'. In this instance, and at the current cumulative control state 316, node 'D1' is in a pass-through configuration, causing the input edge from 'C2' to be connected to the output edge from 'D1' to 'E2'. Therefore, the edge is acquired / traversed from 'D1' to 'E2'.

[0168] Next, examine node 'E2' to determine which output is connected to the edge from 'D1'. In this instance, and at the current cumulative control state 316, node 'E2' is in a pass-through configuration, causing the input edge from 'D1' to be connected to the output edge from 'E2' to output '010' (PBA'010'). Therefore, the edge from 'E2' to output '010' is obtained.

[0169] After reaching output '010', the entire path has been traversed, and address translation manager 302 and / or loss level manager 308 have successfully tracked the path. In this example, LBA '010' is mapped to PBA '010'. As can be seen from this example, changing the switching element along the path will alter the path and result in a new mapping from the original LBA to a different PBA.

[0170] After reaching output '010', the entire path has been traversed, and the path tracing circuit 304 has successfully tracked the path. In this instance, LBA '010' is mapped to PBA '010'. The entire path may include every edge traversed from the input LBA to the output PBA.

[0171] Figure 7 A routine 700 for implementing the disclosed solution according to one embodiment is shown. In block 702, routine 700 receives a raw physical block address (PBA) for a logical block address (LBA) for a write operation, the raw PBA comprising one of a set of PBAs for data blocks in a non-volatile memory array, each PBA in the set of PBAs being uniquely mapped to a specific LBA in the set of LBAs by means of a multilevel interconnect network (MIN).

[0172] In block 704, routine 700 determines a swapped PBA for an LBA, the swapped PBA being determined from a set of PBAs uniquely mapped by means of a MIN. In block 706, routine 700 configures the MIN such that the LBA is mapped to a swapped PBA.

[0173] In box 708, routine 700 swaps the data of the first data block stored at the original PBA with the data of the second data block stored at the swapped PBA.

[0174] Figure 8Routine 800 for implementing the disclosed solution according to one embodiment is shown. Routine 800 begins at block 802 when a raw physical block address (PBA) is received from a set of PBAs. The raw PBA includes one of the PBAs in the set of PBAs for data blocks in a non-volatile memory array. A “raw physical block address” refers to a physical block address that is associated, mapped, or related to a logical block address of a write access request, such as a write operation and / or a read operation. The raw PBA can be determined using a multilevel interconnect network (MIN) that uniquely maps the raw PBA to a specific LBA from the set of LBAs. A specific LBA can be identified in a storage command, such as a write operation.

[0175] The MIN may include a rearrangeable, non-blocking multilevel interconnect network, such as a Benes network. In some embodiments, the non-volatile memory controller 300 or the loss level manager 308 may receive (box 802) the raw PBA.

[0176] At box 804, the loss level manager 308 may, for example, randomly select a swapped PBA for an LBA. "Swapd PBA" refers to a physical block address that is selected, chosen, or directed to be swapped with the original PBA. The swapped PBA can be selected from a set of PBAs mapped by means of a MIN map, where the set of PBAs does not contain the original PBA.

[0177] At box 806, MIN can be configured to map the LBA of a storage command to a swapped PBA. For example, the loss level manager 308 can determine a common switching element for the original PBA and the swapped PBA and change the switching element such that the LBA of a storage command, such as a write operation or other write access, is routed to the swapped PBA instead of the original PBA.

[0178] At box 808, data in the first data block stored in the original PBA can be swapped with data in the second data block stored in the swapped PBA. In some embodiments, the data can be swapped by the data mover 314 of the loss level manager 308.

[0179] Figure 9 A Benedictine multilevel interconnect network 900 according to one embodiment is shown. Specifically, Figure 9 Showing can be related to Figure 8 The described routine 800 is a Benedictine multilevel interconnect network 900 compatible with Benedictines. The switching elements 602 of the Benedictine multilevel interconnect network 900 are arranged in five levels: level 604a, level 604b, level 604c, level 604d, and level 604e. In the Benedictine network configuration shown, the input (LBA 606) is connected to the output (PBA 608) via the switching elements 602.

[0180] In one embodiment, a specific LBA 902'001' can be mapped to the original PBA 904'001' via a switching element 602, wherein the switching element 602, in a pass-through configuration, is as follows: Figure 5A As shown, the switch settings 318 indicated in the cumulative control state 316 can each be '0', indicating that the switch element is an unchanged switch element.

[0181] The '011' swap PBA 906 can be randomly selected via the loss level manager 308, as shown below. Figure 8 As described in routine 800. Next, loss level manager 308 can determine the common switching element of the original PBA 904 and the swapped PBA 906 and change the switching element such that the LBA for storing commands is routed to the swapped PBA 906 instead of the original PBA 904. Loss level manager 308 can determine the swapped PBA 906 output that can remap the '001' input to '011' by reconfiguring the switching element 'D3' (the changed switching element 908) from a through switching element to a cross switching element (see the thick dashed path), thus providing a path 910 from a specific LBA 902 to the swapped PBA 906, which changes at 'D3' to follow the new path 912.

[0182] The loss level manager 308 can update the switch setting 322 and the cumulative control state 316. The switch setting 322 of the control state 320 can be updated to include a '1' in the location associated with the 'D3' switch element 602, indicating that 'D3' is the changed switch element 908. In one embodiment, the cumulative control state 316 can be updated simultaneously with the control state 320. In another embodiment, immediately before the next update to the control state 320, the switch setting 318 of the cumulative control state 316 can be updated with the current control state 320, and therefore may not immediately reflect the current switch setting 322, as shown.

[0183] Figure 10 A routine 1000 for implementing the disclosed solution according to one embodiment is shown. Routine 1000 begins at block 1002 when a raw physical block address (PBA) is received from a set of PBAs. The raw PBA includes one of a set of PBAs for a data block of a non-volatile memory array. A multilevel interconnect network (MIN) is used to uniquely map the raw PBA to a specific LBA for a write operation. The specific LBA may be one of a set of LBAs.

[0184] At box 1004, the loss level manager 308 can determine the path 1106 from the specific LBA referenced in the storage command to the original PBA via MIN (see box 1004). Figure 11At box 1006, a switching element 602 along path 1106 can be randomly selected.

[0185] At block 1008, the MIN can be configured such that a specific LBA is mapped to a swapped PBA by changing the configuration of the selected switching element, such that the path through the switching element is changed to another output of the switching element, leading to the swapped PBA. In some embodiments, the loss level manager can be configured to track path 1106 from the selected switching element (e.g., randomly selected switching element 1112) through the MIN to the swapped PBA 1110.

[0186] Finally, at box 1010, the data of the first data block stored at the original PBA can be swapped with the data of the second data block stored at the swapped PBA.

[0187] Figure 11 A Benedictine multilevel interconnect network 1100 according to one embodiment is shown. Specifically, Figure 11 Showing can be related to Figure 10 The described routine 1000 is compatible with a Benedictine multilevel interconnect network 1100. The switching elements 602 of the Benedictine multilevel interconnect network 1100 are arranged in five levels: level 604a, level 604b, level 604c, level 604d, and level 604e. In the Benedictine network configuration shown, the input (LBA 606) is connected to the output (PBA 608) via the switching elements 602.

[0188] In one embodiment, the first LBA 1102'100' can be mapped to the original PBA 1104'100' via the switching element 602 of the Benes multilevel interconnect network 1100. According to... Figure 10 In routine 1000, the loss level manager 308 can determine that the original PBA 1104 may need to be swapped, and can therefore determine the path 1106 from the original PBA 1104 to the first LBA 1102. This path tracing can be called reverse path tracing because the path is traced from the physical block address to the corresponding logical block address.

[0189] As shown, the path 1106 from the first LBA 1102 to the original PBA 1104 may include switching elements 602'A3','B2','C1','D2', and'E3'. According to routine 1000, the loss level manager may randomly select one of these switching elements to be reconfigured, for example, from a through-type switching element to a cross-type switching element. In the illustrated example, the loss level manager 308 may randomly select switching element 602'E3'. Switching element 602'E3' becomes the selected switching element 1112. The loss level manager 308 may reconfigure or switch switching element 'E3'. In this way, the first LBA 1102 is now mapped to the swapped PBA 1110 instead of the original PBA 1104. In one embodiment, the loss level manager 308 may modify the selected switching element 1112 such that the path 1106 through the selected switching element 1112 is changed to another output of the selected switching element 1112 and leads to the swapped PBA 1110. In some embodiments, the loss level manager 308 may be configured to track the path 1106 from the selected switching element 1112 through MIN to the swapped PBA 1110.

[0190] The switch setting 1116 of control state 320 can be updated to include a "1" at the location associated with the 'E3' switch element. In one embodiment, the switch setting 1114 of cumulative control state 316 can be updated simultaneously with control state 320, as shown.

[0191] The second LBA 1108 can be associated with the data accessed at the swapped PBA prior to this change by the loss level manager. The data at the swapped PBA 1110 can be swapped with the data at the original PBA 1104 as part of routine 1000.

[0192] Figure 12 Routine 1200 for implementing the disclosed solution according to one embodiment is shown. Routine 1200 begins at block 1202 when a raw physical block address (PBA) is received from a set of PBAs. The raw PBA includes one of the PBAs in a set of PBAs for a data block of a non-volatile memory array. A multilevel interconnect network (MIN) is used to uniquely map the raw PBA to a specific LBA from a write operation. The specific LBA may be one of the LBA sets.

[0193] At box 1204, the loss level manager can determine the path 1310 from the specific LBA referenced in the storage command to the original PBA via MIN (see box 1204). Figure 13At block 1206, the loss level manager may refer to the cumulative control state to identify the switching element that is the unchanged switching element in the stage closest to the output of MIN. The unchanged switching element may include a through-type switching element, and the changed switching element may include a cross-type switching element. Alternatively, in one embodiment, the unchanged switching element may include a cross-type switching element, and the changed switching element may include a through-type switching element.

[0194] In box 1208, the loss level manager can then select the switching element along the path in the stage closest to the output of MIN, such that the selected switching element is an unchanged switching element.

[0195] At block 1210, the loss level manager can change the selected unchanged switching element to a changed switching element, such that the path through the selected switching element leads to the swapped PBA. In some embodiments, the loss level manager can be configured to track the path 1310 from the selected switching element in the stage closest to the output of MIN 1314, which is also on path 1310, to the swapped PBA 1318 via MIN.

[0196] At box 1212, the data of the first data block stored in the original PBA is swapped with the data of the second data block stored in the swapped PBA.

[0197] Figure 13 A Benedictine multilevel interconnect network 1300 according to one embodiment is shown. Specifically, Figure 13 Showing can be related to Figure 12 The described routine 1200 is compatible with a Benedictine multilevel interconnect network 1300. The switching elements 602 of the Benedictine multilevel interconnect network 1300 can be arranged in five levels: level 604a, level 604b, level 604c, level 604d, and level 604e. The connection of the input LBA 606 via the switching elements 602 is associated with the output PBA 608.

[0198] For reference regarding Figure 12As described in routine 1200, a first LBA 1302 may be associated with an original PBA 1304, wherein switching elements 602 are along path 1310 from the first LBA 1302 to the original PBA 1304, and each of the switching elements 602 along path 1310 is in a pass-through configuration. These switching elements 602 can be considered as unchanged switching elements 1312 and can be indicated as '0' in switch setting 1306 of cumulative control state 316. Both switching elements 602 'E1' and 'E4' have '0' in cumulative control state 316 because they are unchanged switching elements 1312. Note that switch setting 1308 of control state 320 indicates that switching element 602 'E4' is set to '1', which means that this switching element 602 is changing and becoming a changed switching element.

[0199] The loss level manager can detect the need to swap the first LBA 1302 to another PBA in order to manage loss on the first data block. The loss level manager can use or refer to the cumulative control state 316 to determine how to change the Benes multilevel interconnect network 1300 to swap the PBAs. In one embodiment, the loss level manager can examine a matrix of switch settings 1306 to identify the stage closest to the output of MIN 1314. Reading the rightmost column of the switch settings 1306 matrix from left to right indicates the stage closest to the output of MIN 1314. In one embodiment, a '0' in the switch settings 1306 matrix indicates an unchanged switch element 1312, and a '1' in the switch settings 1306 matrix indicates a changed switch element 1316.

[0200] In the illustrated example, because the last column of the switch setting matrix 1306 has at least one entry with '0', the last column corresponds to the stage closest to the output of MIN 1314, which also has at least one switching element, namely the unchanged switching element 1312. In one embodiment, for a given example, the loss level manager may identify switching elements 'E1' and 'E4' as the switching elements of unchanged switching element 1312 in the stage closest to the output of the MIN with the unchanged switching element.

[0201] Next, the loss level manager can select a switching element along path 1310 that is the same unchanging switching element 1312 in the stage closest to the output of MIN 1314. Therefore, in this example, the loss level manager selects switching element 'E4' because 'E4' meets these criteria.

[0202] The loss level manager can therefore change the switching element E4 to a modified switching element (indicated as '1' in switch setting 1308 of control state 320, and a cross path of 'E4'). Changing E4 to a cross switching element causes the first LBA 1302 of '100' to be mapped to the swapped PBA 1318 '111' instead of the original PBA 1304 '110' via the modified switching element ('E4').

[0203] The second LBA 1320'111' can be mapped to the original PBA 1304. The second data block stored at the swapped PBA 1318 can be swapped with the first data block stored at the original PBA 1304, such as... Figure 12 As described in routine 1200.

[0204] Figure 14 Routine 1400 for implementing the disclosed solution according to one embodiment is shown. Routine 1400 begins at block 1402 when a raw physical block address (PBA) is received from a set of PBAs. The raw PBA includes one of the PBAs in the set of PBAs for a data block of a non-volatile memory array. A multilevel interconnect network (MIN) is used to uniquely map the raw PBA to a specific LBA from a write operation. The specific LBA may be one of the LBA sets.

[0205] At box 1404, the loss level manager can determine the path 1502 from the specific LBA referenced in the storage command to the original PBA via MIN (see box 1404). Figure 15 The MIN includes a set of levels and a cumulative control state. Figure 15 In one example, the Benes multilevel interconnection network 1500 may contain five levels: level 1504, level 1506, level 1508, level 1510 and level 1512.

[0206] At block 1406, the loss level manager can refer to the cumulative control state to identify the switching element that is the unchanged switching element in the stage closest to the output of MIN. The switching element of MIN can be 2×2 switches. The unchanged switching element may include a through-type switching element, and the changed switching element may include a cross-type switching element. Alternatively, in one embodiment, the unchanged switching element may include a cross-type switching element, and the changed switching element may include a through-type switching element.

[0207] In block 1408, the loss level manager can then select the switching element along the path in the stage closest to the output of MIN, such that the selected switching element is an unchanged switching element. When the storage device operates and a particular switching element 602 switches to a changed switching element, the number of unchanged switching elements decreases. In a particular embodiment operating according to routine 1200, for example, eventually all the switching elements in the rightmost column of the Benedict multilevel interconnect network 1500 can become changed switching elements.

[0208] In one embodiment, such as routine 1400, and referring to Figure 15 If the stage closest to the output of MIN 1514 (e.g., stage 1504) has no unchanged switching element (E1 to E4 are changed switching elements), then at box 1410, the loss level manager can select a switching element from the stages between the inputs of MIN (e.g., LBA 606) and adjacent to the stage closest to the output of MIN with only changed switching elements (e.g., stage 1504).

[0209] exist Figure 14 and Figure 15 In an example, the loss level manager can select an unchanged switching element from one of stages 1506, 1508, 1510, or 1512. In one embodiment, the loss level manager searches for the unchanged switching element in the stage among stages 1506, 1508, 1510, and 1512 that is closest to the output of MIN. Therefore, in Figure 15 In this process, the loss level manager will begin with level 1506. If level 1506 contains unchanged switching elements, then the switching elements can be changed. If level 1506 contains only changed switching elements, then the loss level manager can check level 1508. The loss level manager can iteratively follow this same pattern until all levels between the MIN input and the level closest to the MIN output have been checked.

[0210] At box 1412, the loss level manager can change the selected unchanged switching element to a changed switching element, such that path 1502 through the selected switching element leads to the swapped PBA 1516. Finally, at box 1414, the data of the first data block stored in the original PBA 1518 can be swapped with the data of the second data block stored in the swapped PBA 1516.

[0211] Figure 15 A Benedictine multilevel interconnect network 1500 according to one embodiment is shown. Specifically, Figure 15 Showing can be related to Figure 14The described routine 1400 is compatible with a Benedictine multilevel interconnect network 1500. The input LBA 606 is associated with the output PBA 608 via a connection or path made through the switching element 602.

[0212] For reference Figure 14 As described in example 1400, the first LBA 1520'110' can be associated with the original PBA 1518'111', wherein, except for the switching element 602 in stage 1504, the switching element 602 along path 1502 from the first LBA 1520 to the original PBA 1518 is in a pass-through configuration. These can be regarded as unchanged switching elements 602 indicated as '0' in the switch setting 1522 data structure of cumulative control state 316, or as changed switching elements 1524 indicated as '1' in switch setting 1522.

[0213] The loss level manager can detect when the first LBA 1520 needs to be swapped to another PBA in order to manage the loss on the first data block. The loss level manager can use the cumulative control state 316 to determine whether the switching element 602 along path 1502 and within stage 1504 is an unchanged switching element.

[0214] In the illustrated case, the switching element 602 in stage 1504 (E1-4) is the changed switching element 1524. This is indicated by the '1' in the rightmost column of the switch setting 1522 matrix of the cumulative control state 316. The loss level manager can therefore check the stages adjacent to the rightmost stage (e.g., stage 1506) and iteratively check the unchanged switching element 602 along path 1502 in each stage between stage 1504 and the input (e.g., LBA 606).

[0215] Assume that switching element 1526 ('D2') is an unchanged switching element. The loss level manager can therefore change switching element 1526 ('D2') to a changed switching element (indicated as '1' in switch setting 1528 of control state 320). Changing switching element 1526 ('D2') to a cross-connect switching element results in the first LBA 1520 of '110' being mapped to swapped PBA 1516 '101' instead of the original PBA 1518 '111'.

[0216] The second LBA 1530'100' may have initially been mapped to swapped PBA 1516. The second data block stored at swapped PBA 1516 can be swapped with the first data block stored at the original PBA 1518, as follows: Figure 14 As described in routine 1400.

[0217] Figure 16A system 1600 according to one embodiment is shown. System 1600 may include a host 1602, for example... Figure 3 The non-volatile memory controller 1604 described herein and, for example, Figure 2 The non-volatile memory array 204 described in the article.

[0218] The host 1602 may incorporate read / write circuitry 1606, configured to issue storage commands using logical block addresses (LBAs) to perform read and write operations, as well as other activities. The logical block addresses used by the host 1602 may be associated with physical block addresses (PBAs) of data on the non-volatile memory array 204. "Read / write circuitry" refers to a device, component, element, module, system, subsystem, circuit system, logic, hardware, sub-circuit, or circuit configured and / or operated to read data from and write data to a storage medium (e.g., a memory cell of a storage array).

[0219] The non-volatile memory array 204 can store data in memory cells 1608. A "memory cell" refers to a type of storage medium configured to represent one or more binary values ​​by means of the determinable physical characteristics of the storage medium when sensing, reading, or detecting the storage medium to determine which binary value(s) will ultimately be stored in the memory cell(s). The terms "memory cell" and "storage unit" are used interchangeably herein.

[0220] The non-volatile memory controller 1604 may include logic and / or functional modules that facilitate the translation of LBAs from memory commands 1610 used by the host 1602 into PBAs for write access 1612 to request or transfer data within the non-volatile memory array 204. The non-volatile memory controller 1604 may include a processor 1614, volatile memory 1616, a host interface manager 1618 (HIM), and a memory interface manager 1620 (MIM).

[0221] The host interface manager 1618 is configurable to communicate between the host 1602 and the non-volatile memory controller 1604. "Host interface manager" refers to hardware, firmware, software, circuitry, components, modules, logic, devices, or apparatus that is configured, programmed, designed, arranged, or engineered to support communication between the host and peripheral devices (e.g., memory devices and / or non-volatile memory devices), and that interfaces with and performs said communication.

[0222] The memory interface manager 1620 can be coupled to the non-volatile memory array 204 for reading data and writing data to the non-volatile memory array 204. The host interface manager 1618, processor 1614, volatile memory 1616, and memory interface manager 1620 can communicate within the non-volatile memory controller 1604 via bus 1622. A "memory interface manager" or "flash interface manager" refers to any hardware, firmware, software, circuitry, component, module, logic, apparatus, or device that is configured, programmed, designed, arranged, or engineered to support communication between a storage device or memory controller and one or more memory dies or memory chips, interfaces with, and performs said communication.

[0223] The volatile memory 1616 may include an address translation manager 1624 and a wear level manager 1626, which may contain information about... Figure 3 The address translation manager 302 and loss level manager 308 described herein have the same or similar functionality. In one embodiment, the address translation manager 1624 may include a Benedictine multilevel interconnect network 600, a control state 320, and an accumulated control state 316, such as those discussed in detail above. The Benedictine multilevel interconnect network 600 may be configured to map each LBA of a store command 1610 received from the host 1602 of the non-volatile memory array 204 to a unique PBA for write access 1612 to data on the non-volatile memory array 204. The Benedictine multilevel interconnect network 600 may include a plurality of switching elements 1628. The control state 320 may take into account current changes made to the Benedictine multilevel interconnect network 600. The accumulated control state 316 may take into account changes to the Benedictine multilevel interconnect network 600 over time.

[0224] The loss level manager 1626 may include a router 1630, a selector 1632, and a data mover 1634. The router 1630 determines the path through the Benes multilevel interconnect network 600 from the raw PBA of the LBA used for write or read operations. The Benes multilevel interconnect network 600 may be arranged in the stages of the switching element 1628, as previously discussed in detail.

[0225] Selector 1632 may refer to cumulative control state 316 to identify the switching element 1628, which is the unchanging switching element in the stage closest to the output of Benedict's multi-stage interconnection network 600. "Selector" means any hardware, software, firmware, circuit, component, module, logic, device, or equipment that is configured, programmed, designed, or engineered to select, determine, or choose one or more items or options from a set of items or options.

[0226] Selector 1632 can select the switching element 1628 along the path in the stage closest to the output of the Benedictine multilevel interconnect network 600, such that the selected switching element 1628 is an unchanged switching element. Selector 1632 can then change the selected unchanged switching element to a changed switching element, such that the path through the selected switching element leads to the swapped PBA. Data mover 1634 can atomically swap the data of a first data block stored at the original PBA with the data of a second data block stored at the swapped PBA. Data mover 1634 may include information about Figure 3 The features, functions, and / or operations of the described data mover 314 are similar to those of other data movers.

[0227] In one embodiment, selector 1632 can be selected from inputs in the Benedict multilevel interconnect network 600 (e.g., ...). Figure 15 The stages between LBA 606 and the stages adjacent to the output of the MIN (which does not have unchanged switching elements) of the nearest Benedict multistage interconnection network 600 (e.g., Figure 15 Level 1504 in the instance (e.g., Figure 15 In the example of level 1506), the selected switching element is selected. Selector 1632 can search for switching elements to select in response to the level closest to the output of MIN which does not have an unchanged switching element.

[0228] In one embodiment, the LBA of the storage command 1610 (specifically, the write operation) may include an N-bit address. In some embodiments, the Benedictine multilevel interconnect network 600, which maps 2^N LBAs to 2^N PBAs, may be excessively large for hardware implementation or to provide the desired performance level. For example, suppose N = 32, such that the Benedictine multilevel interconnect network 600 would require 2^32 LBAs to 2^32 PBAs, i.e., 4,294,967,296 LBAs and 4,294,967,296 PBAs.

[0229] Therefore, instead of implementing each node, level, and edge of the Benedictine multilevel interconnect network 600 in hardware or software / firmware with volatile memory, embodiments of this solution implement logic and / or software / firmware, such as path tracing circuitry 304, configured to operate once on a portion of the Benedictine network and configured to deterministically traverse the Benedictine network with minimal processing, memory, and storage resources. For example, in one embodiment, the Benedictine multilevel interconnect network 600 may be implemented using sequential circuitry or a state machine such that the latency for traversing a path through the Benedictine multilevel interconnect network 600 directly relates to several levels within the Benedictine multilevel interconnect network 600.

[0230] The loss level manager 1626 and / or address translation manager 1624 can use a portion of the Benes multilevel interconnect network 600 in volatile memory 1616 (represented by Benes network metadata 1636 along with configuration information defining how the Benes multilevel interconnect network 600 is configured and organized) to determine paths and swap PBAs. By loading a portion of the Benes multilevel interconnect network 600 (e.g., Benes network metadata 1636), the address translation manager 1624 and / or loss level manager 1626 can use, access, monitor, manipulate, manage, navigate, and traverse the Benes multilevel interconnect network 600 or any multilevel interconnect network with a large number of inputs and outputs, where a large number is a value greater than five. Advantageously, the address translation manager 1624 and / or loss level manager 1626 loads and works only with the portion of the address translation manager 1624 and / or loss level manager 1626 that is in a position related to node navigation and operation in the multilevel interconnect network.

[0231] Benes network metadata 1636 may be stored wholly or partially in volatile memory 1616 and / or non-volatile memory array 204. For example, Benes network metadata 1636 may include a subset of switch settings from accumulated control states and / or control states, and address translation manager 1624 may contain logic for determining PBA for a specific LBA. Similarly, address translation manager 1624 and loss level manager 1626 may cooperate to load only enough Benes network metadata 1636 to swap the original PBA with the swapped PBA and coordinate with data mover 1634 to move associated data.

[0232] Figure 17 A graph 1700 illustrates the number of bits of metadata required to be stored per page of volatile memory based on the value of L, which is described in detail below. This graph 1700 relates to various routines described herein (e.g., Figure 12 The example 1200 and... Figure 14 The use of Benedictine networks is implemented using the example routine 1400 described herein. This graph 1700 also relates to systems using 32-bit addressing, such as those concerning… Figure 16 The system described is 1600.

[0233] The solutions disclosed in this article can be used to solve and manage, for example Figure 2 The loss leveling of the non-volatile memory array 204 described herein. Now refer to... Figure 2Several subarrays 206 can be divided into regions 208. For example, there can be two subarrays 206, each of which can be addressed using the most significant bit of the LBA. In this way, one bit of the LBA can be used to address the subarray 206 that can be considered a "global partition", and 31 bits can be used to address the region 208 that can be considered a "local partition". This is presented as an illustrative example and is not intended to limit this disclosure. Generally, N bits of address can be used to access G global partitions and L local partitions, where G + L = N.

[0234] In one embodiment, a common multilevel interconnect network can be used to implement the mapping between subarray 206 and partition 208. At the global level, a portion of the LBA identifies a specific partition 208, and the remaining bits of the LBA identify the PBA within that specific partition 208.

[0235] In one embodiment, a local partition can be a physical page of a non-volatile memory array. Using the above example, with a single most significant bit used to address a global partition (G=1) and 31 bits used to address a page (L=31), a 32-bit address can be used to address 2 pages within each global partition. G One global partition and 2 L Page 1 of 10.

[0236] Assuming it is used for 2 L ×2 L Time-varying Benedictine mapping of pages and 2 for global partitioning G ×2 G The time-varying Benedictine mapping, Figure 17 The graph shown illustrates how the metadata required per page for storage mapping, based on the number of bits used to address the page (L), approaches a minimum of 1.0 as L increases from 0 (representing 32-bit addressing in a conventional system) (where 2.0 bits of metadata are required per page). The required memory region can be mapped similarly to using an Omega network MIN.

[0237] Figure 18 Example block diagram of computing device 1800, which is an embodiment of a solution that can be incorporated into. Figure 18 The machine system shown is only an aspect of implementing the technical processes described herein and does not limit the scope of the claims. Those skilled in the art will recognize other variations, modifications, and alternatives. In some embodiments, the computing device 1800 includes a data processing system 1802, a communication network 1818, a communication network interface 1814, an input device 1810, an output device 1808, etc.

[0238] like Figure 18As described, the data processing system 1802 may include one or more processors 1806 and a storage subsystem 1804. Examples of processors may include, but are not limited to, central processing units, general-purpose processors, special-purpose processors, graphics processing units (GPUs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), systems-on-a-chip (SoCs), virtual processors, processor cores, etc.

[0239] The processor 1806 communicates with several peripheral devices via a bus subsystem 1822. These peripheral devices may include an input device 1810, an output device 1808, a communication network interface 1814, and a storage subsystem 1804. In one embodiment, the storage subsystem 1804 includes one or more storage devices and / or one or more memory devices.

[0240] In one embodiment, the storage subsystem 1804 includes volatile memory 1812 and non-volatile memory 1816. The volatile memory 1812 and / or the non-volatile memory 1816 may store computer-executable instructions, individually or together, forming logic 1820, which, when applied and executed by processor 1806, implements embodiments of the processes disclosed herein.

[0241] One or more input devices 1810 include means and mechanisms for inputting information into the data processing system 1802. These may include a keyboard, keypad, touchscreen incorporated into the graphical user interface, audio input devices such as a voice recognition system, a microphone, and other types of input devices. In various embodiments, the input device 1810 may be embodied as a computer mouse, trackball, trackpad, joystick, wireless remote control, drawing tablet, voice command system, eye-tracking system, etc. The input device 1810 typically allows the user to select objects, icons, control areas, text, etc., appearing on the graphical user interface via commands such as clicking buttons.

[0242] Output device 1808 includes means and mechanisms for outputting information from data processing system 1802. These may include graphical user interfaces, speakers, printers, infrared LEDs, etc., as is also known in the art. In some embodiments, the graphical user interface is directly coupled to bus subsystem 1822 via a wired connection. In other embodiments, the graphical user interface is coupled to data processing system 1802 via communication network interface 1814. For example, the graphical user interface may include a command-line interface on a separate computing device 1800 (e.g., a desktop computer, server, or mobile device).

[0243] Communication network interface 1814 provides an interface to communication networks (e.g., communication network 1818) and devices external to data processing system 1802. Communication network interface 1814 can act as an interface for receiving data from other systems and transmitting data to other systems. Embodiments of communication network interface 1814 may include an Ethernet interface, a modem (telephone, satellite, cable, ISDN), (asynchronous) digital subscriber line (DSL), FireWire, USB, a wireless communication interface such as Bluetooth or WiFi, a near-field communication wireless interface, a cellular interface, etc.

[0244] The communication network interface 1814 can be coupled to the communication network 1818 via an antenna, cable, or the like. In some embodiments, the communication network interface 1814 can be physically integrated on the circuit board of the data processing system 1802, or in some cases can be implemented in software or firmware (e.g., a "soft modem").

[0245] The computing device 1800 may include logic that allows communication over a network using protocols such as HTTP, TCP / IP, RTP / RTSP, IPX, UDP, etc.

[0246] Volatile memory 1812 and non-volatile memory 1816 are examples of tangible media configured to store computer-readable data and instructions to implement various embodiments of the processes described herein. Other types of tangible media include removable memory (e.g., pluggable USB memory devices, mobile device SIM cards), optical storage media such as CD-ROMs and DVDs, semiconductor memory such as flash memory, non-transitory read-only memory (ROM), volatile memory with a backup battery, networked storage devices, etc. Volatile memory 1812 and non-volatile memory 1816 may be configured to store basic programming and data constructs that provide functionality for the disclosed processes and other embodiments falling within the scope of this disclosure.

[0247] Logic 1820, comprising one or more portions of an embodiment of the solution, may be stored in volatile memory 1812 and / or non-volatile memory 1816. Logic 1820 may be read from volatile memory 1812 and / or non-volatile memory 1816 and executed by processor 1806. Volatile memory 1812 and non-volatile memory 1816 may also provide a repository for storing data used by logic 1820.

[0248] The volatile memory 1812 and non-volatile memory 1816 may include several memories, including main random-write access memory (RAM) for storing instructions and data during program execution and read-only memory (ROM) for storing read-only non-transitory instructions. The volatile memory 1812 and non-volatile memory 1816 may include a file storage subsystem that provides permanent (non-volatile) storage for program and data files. The volatile memory 1812 and non-volatile memory 1816 may include a removable storage system, such as removable flash memory.

[0249] Bus subsystem 1822 provides mechanisms for allowing various components and subsystems of data processing system 1802 to communicate with each other as needed. Although communication network interface 1814 is schematically depicted as a single bus, some embodiments of bus subsystem 1822 may utilize multiple dissimilar buses.

[0250] It will be readily apparent to those skilled in the art that computing device 1800 can be a device such as a smartphone, desktop computer, laptop computer, rack-mounted computer system, computer server, or tablet computer device. As is commonly known in the art, computing device 1800 can be implemented as a series of multiple networked computing devices. Furthermore, computing device 1800 will generally include operating system logic (not shown), the type and nature of which are well known in the art.

[0251] The terms used herein shall be given their common meaning in the relevant field, or the meaning indicated by their use in the context, unless otherwise specified.

[0252] Within this disclosure, various entities (which may be referred to differently as “units,” “circuits,” other components, etc.) may be described or required to be “configured” to perform one or more tasks or operations. This expression “configured to [perform one or more tasks]” is used herein to refer to a structure (i.e., a physical object such as an electronic circuit). More precisely, this expression is used to indicate that the structure is arranged to perform one or more tasks during operation. Even if the structure is not currently being operated, it may be referred to as being “configured” to perform some tasks. “Credit allocation circuit configured to allocate credits to multiple processor cores” is intended to cover, for example, an integrated circuit having a circuit system that performs this function during operation, even if the integrated circuit in question is not currently in use (e.g., not connected to a power source). Therefore, entities described or enumerated as being “configured” to perform some tasks refer to physical objects, such as devices, circuits, memories storing program instructions executable to perform tasks, etc. This phrase is not used herein to refer to intangible objects.

[0253] The term "configured as" does not mean "configurable as". For example, although an unprogrammed FPGA may be "configurable as" to perform certain functions after programming, the unprogrammed FPGA will not be considered "configured as" to perform those functions.

[0254] "Logic" refers to software, firmware, state machines, subcircuits, circuit systems, one or more electronic components, machine memory circuits, non-transitory machine-readable media, and / or the like, which, by means of their material and / or material-energy configuration, include control and / or program signals, and / or settings and values ​​(e.g., resistance, impedance, capacitance, inductance, current / voltage levels, etc.), which can be applied to affect the operation of a device. Magnetic media, electronic circuits, electrical and optical memories (both volatile and non-volatile), and firmware are examples of logic. Logic specifically excludes pure signals or software itself (however, it does not exclude machine memory that includes software and thus forms a material configuration).

[0255] As used herein, the term "based on" is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence the determination. That is, a determination may be based solely on the specified factor or on the specified factor plus other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies B as the factor used to determine A or the determination that influences A. This phrase does not exclude that the determination of A may also be based on another factor, such as C. This phrase is also intended to cover embodiments where A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "at least partially based on."

[0256] As used herein, the phrase "in response to" describes one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may affect or otherwise trigger the effect. That is, the effect may respond only to those factors, or it may respond to the specified factor as well as other unspecified factors. Consider the phrase "execute A in response to B." This phrase specifies B as the factor that triggers the execution of A. This phrase does not exclude the possibility that A may also be executed in response to another factor, such as C. This phrase is also intended to cover embodiments in which A is executed only in response to B.

[0257] As used herein, unless otherwise stated, the terms “first,” “second,” etc., are used as noun markers following them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). For example, in a register set with eight registers, the terms “first register” and “second register” can be used to refer to any two of the eight registers, rather than, for example, only logic registers 0 and 1.

[0258] When used in the claims, the term "or" is used as an inclusive "or," not an exclusive "or." For example, the phrase "at least one of x, y, or z" means any one of x, y, and z, and any combination thereof.

Claims

1. A method for managing a wear level, comprising: receiving an original physical block address (PBA) for a logical block address (LBA) of a write operation, the original PBA comprising one of a set of PBAs for a data block of a non-volatile memory array, each PBA of the set of PBAs uniquely mapped to one LBA of a set of LBAs by means of a multi-level interconnection network (MIN); determining a transposed PBA for the LBA, the transposed PBA determined from the set of PBAs uniquely mapped by means of the MIN, wherein a write access monitor is configured to signal a wear level manager in response to a pseudo-random number of write accesses, wherein a pseudo-random number of write accesses comprises a number N that occurs on average once for every D write accesses, where D > 10, and wherein a cumulative control state comprises switch settings for switch elements of the MIN, and the MIN comprises one of an omega network, a Benes network, and a double-tuned network; configuring the MIN such that the LBA maps to the transposed PBA; and transposing data of a first data block stored at the original PBA with data of a second data block stored at the transposed PBA.

2. The method of claim 1, wherein the multi-level interconnection network comprises a re-arrangeable, non-blocking multi-level interconnection network, and determining a transposed PBA further comprises randomly selecting a transposed PBA from the set of PBAs that does not include the original PBA.

3. The method of claim 2, wherein the multi-level interconnection network comprises a Benes network.

4. The method of claim 1, wherein determining a transposed PBA further comprises: determining a path through the MIN from the original PBA to the LBA; randomly selecting a switch element along the path; and changing the selected switch element such that the path through the selected switch element changes to another output of the selected switch element and leads to the transposed PBA.

5. The method of claim 1, wherein determining a transposed PBA further comprises: determining a path through the MIN from the original PBA to the LBA, the MIN comprising a set of levels and a cumulative control state; referencing the cumulative control state to identify a switch element in a level closest to an output of the MIN that is an unchanged switch element; selecting a switch element along the path in the level closest to the output of the MIN such that the selected switch element is an unchanged switch element; and changing the selected unchanged switch element to a changed switch element such that the path through the selected switch element leads to the transposed PBA.

6. The method of claim 5, further comprising selecting the selected switch element from a level between inputs of the MIN and adjacent to the level closest to the output of the MIN that does not have an unchanged switch element in response to the level closest to the output of the MIN not having an unchanged switch element.

7. The method of claim 5, further comprising: modify the control state of the MIN to account for changing the selected switch element to the changed switch element; and modify the cumulative control state to account for the modified control state.

8. The method of claim 7, wherein the cumulative control state comprises a data structure configured to store an entry for each changed switch element mapped to a changed switch element within the MIN, and the cumulative control state is configured to identify switch elements in the data structure not accounted for as the unchanged switch elements.

9. The method of claim 5, further comprising tracking the path from the selected switch element through the MIN to the swap PBA.

10. The method of claim 1, wherein the multi-level interconnection network comprises logic configured to map the LBA to the original PBA based on a cumulative control state.

11. A circuit for managing wear levels, comprising: a write access monitor configured to count write accesses to a non-volatile memory array by a read / write circuit; a path tracking circuit configured to map a logical block address (LBA) of a data block of the non-volatile memory array to a unique physical block address (PBA) by tracking a path through a multi-level interconnection network (MIN) from each LBA to the unique PBA, the MIN comprising a plurality of switch elements; an address translation manager configured to translate the LBA of each write access to the PBA by means of the path tracking circuit; a control state configured to account for a current change made to the MIN; a cumulative control state configured to account for changes to the MIN; a wear level manager configured to change a mapping of two LBAs and two corresponding PBAs of the MIN in response to a signal from the write access monitor; and a data mover configured to atomically swap data stored in data blocks of two swapped PBAs in response to a signal from the wear level manager; wherein the write access monitor is configured to signal the wear level manager in response to a pseudo-random number of write accesses made by the read / write circuit, wherein the pseudo-random number of write accesses comprises a number N that occurs on average once for every D write accesses, where D > 10, and wherein the cumulative control state comprises switch settings for the switch elements of the MIN, and the MIN comprises one of an omega network, a Benes network, and a double-tune network.

12. The circuit of claim 11, wherein the MIN comprises a re-arrangeable, non-blocking multi-level interconnection network, and wherein the wear level manager is configured to: randomly select a swap PBA to swap with an LBA of a write access to the non-volatile memory array by the read / write circuit; determine a switch element common to an original PBA associated with the LBA and the swap PBA associated with another LBA; and changing the switch elements so that the LBA of the write access is routed to the transposed PBA.

13. The circuit of claim 11, wherein the wear-leveling manager is configured to: determine a path from an LBA of a write access by the read / write circuit to a native PBA of the non-volatile memory array through the MIN; randomly select a switch element along the path; and change the selected switch element so that the path through the selected switch element changes to another output of the selected switch element and leads to a transposed PBA.

14. The circuit of claim 11, wherein the wear-leveling manager is configured to: determine a path from an LBA of a write access by the read / write circuit to a native PBA of the non-volatile memory array through the MIN, the MIN comprising a set of stages; refer to the cumulative control state to identify a switch element in a stage closest to an output of the MIN that is an unchanged switch element; select a switch element along the path in the stage closest to the output of the MIN so that the selected switch element is an unchanged switch element; and change the selected unchanged switch element to a changed switch element so that the path through the selected switch element leads to a transposed PBA.

15. The circuit of claim 14, wherein the wear-leveling manager is further configured to select the selected switch element from a stage between inputs of the MIN and adjacent to the stage closest to an output of the MIN that does not have an unchanged switch element in response to the stage closest to the output of the MIN not having an unchanged switch element; and wherein the switch elements of the MIN comprise 2x2 switches, and the unchanged switch element comprises a pass-through switch element, and the changed switch element comprises a cross switch element.

16. A system for managing a wear-level in a non-volatile memory, comprising: a non-volatile memory array configured to store data in its memory cells; and a non-volatile memory controller comprising: a processor; a volatile memory; a host interface manager configured to communicate between a host and the non-volatile memory controller; an address translation manager comprising: a write access monitor configured to signal a wear-leveling manager in response to a pseudo-random number of write accesses by a read / write circuit, wherein the pseudo-random number of write accesses comprises a number N that occurs on average once for every D write accesses, where D > 10, and wherein a cumulative control state comprises switch settings for switch elements of a multi-stage interconnection network, and the multi-stage interconnection network comprises a Banyan network; a Banyan network configured to map each logical block address (LBA) of the non-volatile memory array to a unique physical block address (PBA), the Banyan network comprising a plurality of switch elements; a control state configured to account for current changes made to the Banyan network; and a wear-leveling manager configured to: determine a path from an LBA of a write access by the read / write circuit to a native PBA of the non-volatile memory array through the MIN; randomly select a switch element along the path; and change the selected switch element so that the path through the selected switch element changes to another output of the selected switch element and leads to a transposed PBA. accumulation control state configured to account for changes to the Benes network over time; a wear-leveling manager including: a router configured to determine a path through the Benes network from an original PBA for a LBA of a write operation, the Benes network including a set of stages; a selector configured to: reference the accumulation control state to identify a switch element in a stage closest to an output of the Benes network that is an unchanged switch element; select a switch element along the path in the stage closest to the output of the Benes network such that the selected switch element is an unchanged switch element; and change the selected unchanged switch element to a changed switch element such that the path through the selected switch element leads to a remapped PBA; and a data mover configured to atomically remap data of a first data block stored at the original PBA with data of a second data block stored at the remapped PBA; and a memory interface manager coupled to the non-volatile memory array for reading data and writing data to the non-volatile memory array.

17. The system of claim 16, wherein the selector is further configured to select the selected switch element from a stage between inputs of the Benes network and adjacent to a stage closest to an output of the Benes network that does not have an unchanged switch element in response to the stage closest to the output of the Benes network not having an unchanged switch element.

18. The system of claim 17, wherein the LBA of the write operation includes an N-bit address, and the Benes network maps 2^N LBAs to 2^N PBAs, and wherein the wear-leveling manager is configured to determine the path and remap PBAs using a portion of the Benes network in the volatile memory.

19. Circuitry for managing wear-leveling in a non-volatile memory, comprising: a non-volatile memory array including data blocks addressable by logical block addresses; a processor including: read / write circuitry configured to read data blocks using logical block addresses and write data blocks to the non-volatile memory array; path tracking circuitry configured to map each logical block address (LBA) of the non-volatile memory array to a unique physical block address (PBA) by tracking a path through a multi-stage interconnection network (MIN) from each LBA to the unique PBA, the MIN including a plurality of switch elements; an address translation manager configured to translate the LBA of each write access to a PBA by means of the path tracking circuitry; and an accumulation control state configured to account for changes to the MIN.

20. The circuitry of claim 19, wherein the path tracking circuitry is configured to track the path through the MIN by tracking a path through a Benes network, the Benes network including a set of stages. wherein a number of write accesses tracked by the read / write circuit is pseudo-random, wherein a pseudo-random number of write accesses includes a number N that occurs on average once for every D write accesses, where D > 10, and wherein the cumulative control state includes a switch setting for the switch element of the MIN, and the MIN includes one of an omega network, a Banyes network, and a dual-ramp network.

20. The circuit of claim 19, wherein the path tracking circuit is configured to iteratively process a set of stages of the MIN to map the LBA to the unique PBA.

21. The circuit of claim 19, wherein the MIN includes N inputs by N outputs, where N > 10.

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