Using Partitioned Namespaces to Compress Logical-to-Physical Table Pointers in SSDs

Abstract

The present disclosure generally relates to methods of operating a storage device. The storage device includes a controller, a random access memory (RAM), and NVM cells, where the NVM cells include a plurality of partitions. The RAM unit includes a logical to physical address (L2P) table for the plurality of partitions. The L2P table includes pointers associated with logical block addresses (LBAs) and physical locations where data is stored in the NVM. The L2P table includes one pointer per erase block or partition. When a command to read data within the NVM is received, the controller reads the L2P table to determine the associated pointer for the LBA and the data. The controller can then determine in which partition or erase block the data is stored and calculate various offsets for word lines, pages, and page addresses to find the exact location of the data in the NVM.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to U.S. Application No. 16 / 861,068, filed on April 28, 2020, the entire disclosure of which is incorporated herein by reference. Background of the Invention Field of the Invention

[0004] Embodiments of the present disclosure generally relate to storage devices, such as solid - state drives (SSDs).

[0005] Description of Related Art

[0006] Storage devices such as SSDs can be used in computers for applications that require relatively low latency and high - capacity storage. For example, an SSD can exhibit lower latency than a hard disk drive (HDD), especially for random reads and writes. Generally, a controller of an SSD receives commands to read data from or write data to a memory device from a host device. The data is read and written to one or more erase blocks in the memory device. When a write command is received, the data associated with the write command has a logical block address (LBA). A logical - to - physical address (L2P) table stored in the volatile memory of the SSD associates one or more LBAs of the data to the physical addresses where the data is stored in the SSD when the data is written. The L2P table is updated whenever data is erased from the SSD, such as during a garbage collection operation, to point to a marker value (e.g., "null value").

[0007] To associate the LBA of data to the physical address where the data is stored in the SSD, the L2P table includes pointers that point to or identify each location in the memory device, or to a marker value indicating that the data is invalid. Since data is written to the memory device sequentially, any modification of the data requires a read - modify - write process, which can be a time - consuming and resource - intensive process. In the read - modify - write process, the data is read in segments of about 4 KiB or 8 KiB and then modified in segments of about 512 B. The modified data is written sequentially to available locations in the memory cells. Although the previous data corresponding to the modified data can be erased, the L2P table includes pointers to the physical locations of the existing data. Since a storage device typically includes a very limited amount of volatile memory, a large portion of the available volatile memory can be tied up storing the L2P table.

[0008] Accordingly, there is a need for a new method to improve data storage in storage devices. Summary of the Invention

[0009] The present disclosure as a whole relates to a method of operating a storage device. The storage device includes a controller, a random access memory (RAM), and a NVM unit, wherein the NVM unit includes multiple partitions. The RAM unit includes a logical to physical address (L2P) table of the multiple partitions. The L2P table includes pointers associated with a logical block address (LBA) and a physical location where data is stored in the NVM. The L2P table includes a pointer per erase block or partition. When a command to read data within the NVM is received, the controller reads the L2P table to determine the LBA and the associated pointer of the data. The controller can then determine in which partition or erase block the data is stored, and calculate various offsets of word lines, pages, and page addresses to find the exact location of the data in the NVM.

[0010] In one embodiment, a storage device includes a nonvolatile storage unit, wherein the capacity of the nonvolatile storage unit is divided into a plurality of partitions. The nonvolatile storage unit includes a plurality of dies, and each of the plurality of dies includes a plurality of erase blocks. The storage device also includes a volatile memory unit, wherein the volatile memory unit stores a first logical-to-physical address table, and the first logical-to-physical address table associates a logical block address of data to a physical address at which the data is stored in the nonvolatile storage unit. The storage device also includes a controller coupled to the nonvolatile storage unit and the volatile memory unit, wherein the controller is configured to: receive a first read command to read first data stored in the nonvolatile storage unit; and read a first pointer associated with the first data in the first logical-to-physical table to determine that the first data is stored in a first erase block of a first partition of the plurality of partitions. The controller is further configured to: determine a page and word line offset within the first erase block to find the first data, and read the first data.

[0011] In another embodiment, a storage device includes a nonvolatile storage unit, wherein the capacity of the nonvolatile storage unit is divided into a plurality of partitions. The nonvolatile storage unit includes a plurality of dies, and each of the plurality of dies includes a plurality of erase blocks. Each of the erase blocks includes a plurality of word lines and a plurality of pages. The storage device also includes a volatile memory unit, wherein the volatile memory unit stores a first logical-to-physical address table, and the first logical-to-physical address table associates a logical block address of data to a physical address at which the data is stored in the nonvolatile storage unit. The storage device also includes a controller coupled to the nonvolatile storage unit and the volatile memory unit, wherein the controller is configured to: write first data associated with one or more first commands to a first erase block in a first partition of the plurality of partitions; and update the first logical-to-physical address table stored in the volatile memory unit, wherein updating the first logical-to-physical table includes associating a pointer to the first partition and the first data. The controller is further configured to: receive a read command to read first data; identify a first logical block address of the first data; read a pointer associated with the first partition to determine that the first data is stored in the first partition; calculate an offset of an erase block to determine that the first data is in the first erase block; and calculate an offset of a page and a word line within the first erase block to find the first data.

[0012] In another embodiment, a storage device includes a nonvolatile storage unit, wherein the capacity of the nonvolatile storage unit is divided into a plurality of partitions. The nonvolatile storage unit includes a plurality of dies, and each of the plurality of dies includes a plurality of erase blocks. The storage device also includes a volatile memory unit, wherein the volatile memory unit stores a first logical-to-physical address table, and the first logical-to-physical address table associates a logical block address of data to a physical address at which the data is stored in the nonvolatile storage unit. The storage device also includes: means for receiving a first read command to read first data stored in the nonvolatile storage unit; means for identifying a first logical block address of the first data; and means for reading a pointer associated with a first partition in the first logical-to-physical table to determine that the first data is stored in a first partition of the plurality of partitions. The storage device also includes: means for calculating an erase block offset to determine that the first data is stored in a first erase block of the first partition; and means for calculating a page and word line offset within the first erase block to find the first data. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Thus, a detailed understanding of the manner in which the above-described features of the present disclosure are understood, a more particular description of the present disclosure, the above brief overview, may be obtained by reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only typical embodiments of the present disclosure and are therefore not to be considered limiting of its scope, as the present disclosure may admit to other equally effective embodiments.

[0014] Figure 1 is a schematic block diagram illustrating a storage system according to one embodiment.

[0015] Figure 2A A partitioned namespace utilized in a storage device is shown according to one embodiment.

[0016] Figure 2B According to one embodiment, Figure 2A A state diagram of the partition namespace of a storage device.

[0017] Figure 3A is an erase block of a partition according to one embodiment.

[0018] Figure 3B A partition including one or more erase blocks is shown according to one embodiment.

[0019] Figure 4 is a schematic block diagram illustrating a storage system according to another embodiment.

[0020] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation. DETAILED DESCRIPTION

[0021] Hereinafter, reference is made to the embodiments of the present disclosure. However, it should be understood that the present disclosure is not limited to the embodiments specifically described. On the contrary, any combination of the following features and elements (whether or not related to different embodiments) is considered to realize and practice the present disclosure. In addition, although the embodiments of the present disclosure can achieve advantages that are superior to other possible solutions and / or superior to the prior art, whether a specific advantage is achieved by a given embodiment is not a limitation to the present disclosure. Therefore, the following aspects, features, embodiments and advantages are merely illustrative, and are not considered to be elements or limitations of the appended claims, unless explicitly stated in the claims. Similarly, reference to "the present disclosure" should not be interpreted as a summary of any inventive subject matter disclosed herein, and should not be considered to be elements or limitations of the appended claims, unless explicitly stated in the claims.

[0022] The present disclosure generally relates to methods of operating a storage device. The storage device includes a controller, a random access memory (RAM), and NVM cells, where the NVM cells include a plurality of partitions. The RAM unit includes a logical-to-physical address (L2P) table for the plurality of partitions. The L2P table includes pointers associated with a logical block address (LBA) and a physical location where data is stored in the NVM. The L2P table includes one pointer per erase block or partition. When a command to read data within the NVM is received, the controller reads the L2P table to determine the LBA and the associated pointer for the data. The controller can then determine in which partition or erase block the data is stored and calculate various offsets for word lines, pages, and page addresses to find the exact location of the data in the NVM.

[0023] Figure 1 FIG. 4 is a schematic block diagram illustrating a storage system 100 in accordance with one or more techniques of the present disclosure, where a storage device 106 can be used as a storage device for a host device 104. For example, the host device 104 can utilize storage cells 110 included in the storage device 106, such as non-volatile memory, to store and retrieve data. For example, the storage cells 110 can be any type of non-volatile memory, such as MRAM, NAND, NOR, or HDD. In the following description, for simplicity and illustrative purposes, the storage cells 110 are referred to as non-volatile memory (NVM) 110. The host device 104 includes host DRAM 138. In some examples, the storage system 100 can include a plurality of storage devices that can operate as a storage array, such as the storage device 106. For example, the storage system 100 can include a plurality of storage devices 106 that are configured as a redundant array of inexpensive / independent disks (RAID) that collectively serve as a mass storage device for the host device 104.

[0024] The storage system 100 includes a host device 104 that can store data to and / or retrieve data from one or more storage devices, such as the storage device 106. As Figure 1 shown, the host device 104 can communicate with the storage device 106 via an interface 114. The host device 104 can include any one of a variety of devices, including computer servers, network-attached storage (NAS) units, desktop computers, notebook (i.e., laptop) computers, tablet computers, set-top boxes, cellular phones such as so-called "smart" phones, so-called "smart" tablets, televisions, cameras, display devices, digital media players, video game consoles, video streaming devices, and the like.

[0025] The storage device 106 includes a controller 108, a non-volatile memory 110 (NVM 110), a power supply 111, a volatile memory 112, and an interface 114. The controller 108 includes a partition management 120 and a buffer (not shown). In some examples, for clarity, the storage device 106 may include Figure 1 106. For example, the storage device 106 may include a printed circuit board (PCB) to which the components of the storage device 106 are mechanically attached, and the printed circuit board includes conductive traces that electrically interconnect the components of the storage device 106, etc. In some examples, the physical size and connector configuration of the storage device 106 may conform to one or more standard form factors. Some exemplary standard form factors include, but are not limited to, a 3.5" data storage device (e.g., an HDD or SSD), a 2.5" data storage device, a 1.8" data storage device, a peripheral component interconnect (PCI), a PCI extension (PCI-X), a PCI Express (PCIe) (e.g., PCIe x1, x4, x8, x16, PCIe Mini card, MiniPCI, etc.). In some examples, the storage device 106 can be directly coupled (e.g., directly soldered) to a motherboard of the host device 104.

[0026] The interface 114 of the storage device 106 may include one or both of a data bus for exchanging data with the host device 104 and a control bus for exchanging commands with the host device 104. The interface 114 may operate according to any suitable protocol. For example, the interface 114 may operate according to one or more of the following protocols: Advanced Technology Attachment (ATA) (e.g., Serial ATA (SATA) and Parallel ATA (PATA)), Fibre Channel Protocol (FCP), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), PCI, PCIe, Non-Volatile Memory Standard (NVMe), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), Compute Express Link (CXL), Open Channel SSD (OCSSD), etc. The electrical connection (e.g., data bus, control bus, or both) of the interface 114 is electrically connected to the controller 108, thereby providing an electrical connection between the host device 104 and the controller 108, allowing data to be exchanged between the host device 104 and the controller 108. In some examples, the electrical connection of interface 114 may also allow storage device 106 to receive power from host device 104. Figure 1 As shown, power supply 111 may receive power from host device 104 via interface 114 .

[0027] The storage device 106 includes an NVM 110, which may include multiple memory devices or memory cells. The NVM 110 may be configured to store and / or retrieve data. For example, a memory cell of the NVM 110 may receive data and receive a message from the controller 108 indicating that the memory cell stores data. Similarly, a memory cell of the NVM 110 may receive a message from the controller 108 indicating that the memory cell retrieves data. In some examples, each memory cell in the memory cell may be referred to as a die. In some examples, a single physical chip may include multiple dies (i.e., multiple memory cells). In some examples, each memory cell may be configured to store a relatively large amount of data (e.g., 128MB, 256MB, 512MB, 1GB, 2GB, 4GB, 8GB, 16GB, 32GB, 64GB, 128GB, 256GB, 512GB, 1TB, etc.).

[0028] In some examples, each memory cell of NVM 110 may include any type of nonvolatile memory device, such as a flash memory device, a phase change memory (PCM) device, a resistive random access memory (ReRAM) device, a magnetoresistive random access memory (MRAM) device, a ferroelectric random access memory (F-RAM), a holographic memory device, and any other type of nonvolatile memory device.

[0029] NVM 110 may include multiple flash memory devices or storage cells. Flash memory devices may include NAND or NOR-based flash memory devices, and data may be stored based on the charge contained in the floating gate of the transistor for each flash memory cell. In NAND flash memory devices, the flash memory devices may be divided into multiple blocks, which may be divided into multiple pages. Each block in a plurality of blocks within a particular memory device may include multiple NAND cells. The rows of NAND cells may be electrically connected using word lines to define pages in a plurality of pages. The corresponding cells in each of the plurality of pages may be electrically connected to the corresponding bit lines. In addition, the NAND flash memory device may be a 2D or 3D device, and may be a single-level cell (SLC), a multi-level cell (MLC), a three-level cell (TLC), or a four-level cell (QLC). The controller 108 may write data to and read data from the NAND flash memory device at the page level, and erase data from the NAND flash memory device at the block level.

[0030] The storage device 106 includes a power supply 111 that can provide power to one or more components of the storage device 106. When operating in standard mode, the power supply 111 can use power provided by an external device such as a host device 104 to power one or more components. For example, the power supply 111 can use power received from the host device 104 via the interface 114 to power one or more components. In some examples, the power supply 111 may include one or more power storage components that are configured to supply power to one or more components when operating in a shutdown mode, such as when power is stopped from being received from an external device. In this way, the power supply 111 can be used as an onboard backup power supply. Some examples of one or more power storage components include, but are not limited to, capacitors, supercapacitors, batteries, and the like. In some examples, the amount of power that can be stored by one or more power storage components can be a function of the cost and / or size (e.g., area / volume) of the one or more power storage components. In other words, as the amount of power stored by the one or more power storage components increases, the cost and / or size of the one or more power storage components also increases.

[0031] Storage device 106 also includes volatile memory 112, which can be used by controller 108 to store information. Volatile memory 112 can include one or more volatile memory devices. In some examples, controller 108 can use volatile memory 112 as a cache. For example, controller 108 can store cached information in volatile memory 112 until the cached information is written to non-volatile memory 110. Figure 1 As shown, the volatile memory 112 may consume power received from the power supply 111. Examples of the volatile memory 112 include, but are not limited to, random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, DDR5, LPDDR5, etc.)).

[0032] Various types of volatile memory may be used with different access characteristics. For example, DRAM 112 may be arranged for longer burst accesses to allow improved bandwidth (BW) of the same access bus. Alternatively, DRAM 112 may be used with smaller accesses so that random small accesses may have better latency. Controller 108 includes additional optional SRAM and / or embedded MRAM (not shown). Embedded MRAM (not shown) is another alternative memory that may be used in another embodiment. Similarly, access to MRAM (not shown) may be optimized for different design purposes, but the amount of embedded MRAM (not shown) in SSD controller 108 may be cost sensitive. Therefore, the choice of how much and which data goes into advanced non-volatile memory and advanced volatile memory will depend on system tradeoffs.

[0033] The storage device 106 includes a controller 108 that can manage one or more operations of the storage device 106. For example, the controller 108 can manage reading data from the NVM 110 and / or writing data to the NVM via a switch mode (TM) bus 128. The controller 108 may include a partition manager (ZM) 120 to manage reading and writing to partitions and relocating valid data to and from partitions for garbage collection purposes. Partition metadata 122 may be stored in the partition manager 120 or the controller 108. In some embodiments, when the storage device 106 receives a write command from the host device 104, the controller 108 may initiate a data storage command to store data to the NVM 110 and monitor the progress of the data storage command. The controller 108 may determine at least one operating characteristic of the storage system 100 and store the at least one operating characteristic to the NVM 110. In some embodiments, when the storage device 106 receives a write command from the host device 104, the controller 108 temporarily stores the data associated with the write command in a buffer before sending the data to the NVM 110.

[0034] Figure 2A A zoned name space (ZNS) 202 view is shown for use in a storage device 200 according to one embodiment. The storage device 200 can present the ZNS 202 view to a host device. Figure 2B A state diagram 250 of a ZNS 202 of a storage device 200 is shown according to one embodiment. The storage device 200 may be Figure 1The storage device 106 of the storage system 100 of the embodiment of the present invention. The storage device 200 may have one or more ZNS 202, and each ZNS 202 may have a different size. In addition to the one or more partition namespaces 202, the storage device 200 may also include one or more regular namespaces. In addition, the ZNS 202 may be a zone block command (ZBC) for SAS and / or a zone device ATA command set (ZAC) for SATA. Due to the relationship between possible logical and physical activities, host-side partition activities may be more directly related to media activities in the partition driver.

[0035] In storage device 200, ZNS 202 is the number of NVMs that can be formatted into logical blocks such that the capacity is divided into a plurality of partitions 206a-206n (collectively referred to as partitions 206). NVMs can be Figure 1 10. Each of the partitions 206 includes a plurality of physical blocks or erase blocks (not shown) of the memory cell or NVM 204, and each of the erase blocks is associated with a plurality of logical blocks (not shown). Each of the partitions 206 may have a size aligned with the capacity of one or more erase blocks of the NVM or NAND device. When the controller 208 receives a command from, for example, a host device (not shown) or a submission queue of the host device, the controller 208 may read data from and write data to a plurality of logical blocks associated with a plurality of erase blocks (EBs) of the ZNS 202. Each of the logical blocks is associated with a unique LBA or sector.

[0036] In one embodiment, NVM 204 is a NAND device. The NAND device includes one or more dies. Each of the one or more dies includes one or more planes. Each of the one or more planes includes one or more erase blocks. Each erase block in the one or more erase blocks includes one or more word lines (e.g., 256 word lines). Each word line in the one or more word lines can be addressed in one or more pages. For example, an MLC NAND die can use an upper page and a lower page to reach two bits in each cell of the entire word line (e.g., 16KiB per page). In addition, each page can be accessed with a granularity equal to or less than a complete page. The controller can frequently access the NAND with a user data granularity logical block address (LBA) size of 512 bytes. Therefore, as mentioned in the description below, the NAND position is equal to a granularity of 512 bytes. Therefore, the LBA size is 512 bytes and the page size of two pages of the MLC NAND is 16KiB, which results in 32 LBAs per word line. However, the NAND position size is not intended to be limited and is only used as an example.

[0037] When data is written to an erase block, one or more logical blocks are correspondingly updated within a partition 206 to track the location of the data within the NVM 204. Data may be written one partition 206 at a time until the partition 206 is full, or to multiple partitions 206 so that multiple partitions 206 may be partially full. Similarly, when data is written to a particular partition 206, the data may be written to multiple erase blocks one block at a time in the order of NAND locations, page by page, or word line by word line, until moving to an adjacent block (i.e., writing the first erase block until the first erase block is full before moving to the second erase block), or may be written to multiple erase blocks multiple blocks at a time in the order of NAND locations, page by page, or word line by word line to partially fill each block in a parallel manner (i.e., writing the first NAND location or page of each erase block before writing the second NAND location or page of each erase block). This sequential programming of each NAND location is a typical, non-limiting requirement of many NAND EBs.

[0038] When controller 208 selects the erase block that will store the data of each sub-region, controller 208 will be able to select erase block at the sub-region open time, or this controller can select erase block when reaching the needs of the first word line of filling this specific erase block.When utilizing the above-mentioned method of filling an erase block completely before starting the next erase block, this may be more different.Controller 208 can use this time difference to select more optimized erase block on an instant basis.The decision of which erase block to distribute and assign for each sub-region and its continuous LBA can occur in controller 208 for zero or more parallel sub-regions all the time.

[0039] Each partition in partitions 206 is associated with a partition starting logical block address (ZSLBA) or a partition starting sector. The ZSLBA is the first available LBA in partitions 206. For example, the first partition 206a is associated with ZSLBA. a SLBA is associated with the second partition 206b and Z b SLBA is associated with the third partition 206c and Z c SLBA is associated with the fourth partition 206d and Z d SLBA is associated, and the nth partition 206n (ie, the last partition) is associated with Z n Each partition 206 is identified by its ZSLBA and is configured to receive sequential writes (ie, write data to NVM 110 in the order in which the write commands are received).

[0040] When data is written to a partition 206, a write pointer 210 is advanced or updated to point to or indicate the next available block in the partition 206 to which the data is written, so as to keep track of the next write start point (i.e., the completion point of the previous write is equal to the start point of the subsequent write). Thus, the write pointer 210 indicates where the subsequent write to the partition 206 will begin. Subsequent write commands are "partition append" commands, in which the data associated with the subsequent write command is appended to the partition 206 at the location indicated by the write pointer 210 as the next start point. An ordered list of LBAs within the partition 206 may be stored for write ordering. Each partition 206 may have its own write pointer 210. Thus, when a write command is received, the partition is identified by its ZSLBA, and the write pointer 210 determines the location within the identified partition where the writing of the data begins.

[0041] Figure 2B Shows Figure 2A 202. In state diagram 250, each partition may be in a different state, such as empty, active, full, or offline. When a partition is empty, the partition contains no data (i.e., no erase blocks in the partition currently store data), and the write pointer is located at ZSLBA (i.e., WP=0). Once a write is scheduled to the partition or a partition open command is issued by the host, the empty partition will switch to an open and active partition. Partition management (ZM) commands can be used to move partitions between partition open and partition closed states (both are active states). If a partition is active, the partition includes open blocks that can be written to, and a description of the recommended time in the active state can be provided to the host. Controller 208 includes the ZM. Partition metadata can be stored in the ZM and / or controller 208.

[0042] The term "write" includes programming user data on 0 or more NAND locations in an erase block and / or partially filled NAND locations in an erase block when the user data has not yet filled all available NAND locations. The term "write" may also include moving a partition to full due to internal drive processing needs (open block data retention issues due to error bits accumulating faster on open erase blocks), the storage device 200 closing or filling a partition due to resource limitations (like too many open partitions to track or defective conditions discovered, etc.), or the host device closing a partition due to issues such as no more data to send to the drive, computer shutdown, error handling on the host, limited host resources for tracking, etc.

[0043] Active partitions can be open or closed. An open partition is an empty partition or partially filled partition that is ready for writing and has currently allocated resources. Data received from a host device using a write command or a partition append command can be programmed into an open erase block that is not currently filled with previous data. A closed partition is an empty partition or partially filled partition that is not currently receiving writes from the host continuously. Moving a partition from an open state to a closed state allows the controller 308 to reallocate resources to other tasks. These tasks may include, but are not limited to, other open partitions, other conventional non-partitioned areas, or other controller needs.

[0044] In open and closed partitions, the write pointer points to a location in the partition between the ZSLBA and the end of the last LBA of the partition (i.e., WP>0). An active partition can switch between open and closed states as specified by the ZM, or when a write is scheduled to the partition. In addition, the ZM can reset the active partition to clear or erase the data stored in the partition, causing the partition to switch back to an empty partition. Once the active partition is full, the partition switches to a full state. A full partition is a partition that is completely filled with data and has no more available sectors or LBAs for writing data (i.e., WP=Partition Capacity (ZCAP)). In a full partition, the write pointer points to the end of the writable capacity of the partition. Read commands for data stored in a full partition can still be executed.

[0045] The partitions may have any total capacity, such as 256MiB or 512MiB. However, a small portion of each partition may not be accessible to write data, but may still be read, such as the portion of each partition that stores parity data and one or more excluded erase blocks. For example, if the total capacity of partition 206 is 512MiB, the ZCAP may be 470MiB, which is the capacity available for writing data, while 42MiB is not available for writing data. The writable capacity (ZCAP) of the partition is equal to or less than the total partition storage capacity. The storage device 200 may determine the ZCAP of each partition when the partition is reset. For example, the controller 208 or ZM may determine the ZCAP of each partition. When a partition is reset, the storage device 200 may determine the ZCAP of the partition.

[0046] The ZM can reset a full partition, thereby scheduling the erasure of data stored in the partition so that the partition switches back to an empty partition. When resetting a full partition, although the partition may be marked as an empty partition available for writing, the data of the partition may not be cleared immediately. However, the reset partition must be erased before switching to an open and active partition. The partition can be erased at any time between the ZM reset and the ZM open. When resetting a partition, the storage device 200 can determine the new ZCAP of the reset partition and update the writable ZCAP attribute in the partition metadata. An offline partition is a partition to which data cannot be written. An offline partition can be in a full state, an empty state, or a partially full state without being in an active state.

[0047] Since resetting a partition can clear all data stored in a partition or schedule the erasure of all data stored in a partition, the need for garbage collection of each erase block is eliminated, thereby improving the overall garbage collection process of the storage device 200. The storage device 200 can mark one or more erase blocks for erasure. When a new partition is to be formed and the storage device 200 expects that the ZM is open, then the one or more erase blocks marked for erasure can be erased. The storage device 200 can also determine and create the physical support of the partition when erasing the erase block. Therefore, once the new partition is opened and the erase block is selected to form the partition, the erase block will be erased. In addition, each time the partition is reset, the LBA of the partition 206 and the new order of the write pointer 210 can be selected, so that the partition 206 can tolerate receiving commands out of order. The write pointer 210 can be optionally closed so that the command can be written to any starting LBA indicated by the command.

[0048] Re-reference Figure 2A , when the host sends a write command to write data to the partition 206, the controller 208 pulls in the write command and identifies the write command as a write to the newly opened partition 206. The controller 208 selects a set of EBs to store the data associated with the write command of the newly opened partition 206, and the newly opened partition 206 is switched to the active partition 206. The write command can be a command to write new data, or a command to move valid data to another partition for garbage collection purposes. The controller 208 is configured to DMA read new commands from the submission queue filled by the host device.

[0049] In the empty partition 206 that has just been switched to the active partition 206, data is assigned to the partition 206 and a set of associated sequential LBAs of the partition 206 starting at ZSLBA because the write pointer 210 indicates the logical block associated with ZSLBA as the first available logical block. The data can be written to one or more erase blocks or NAND locations that have been allocated for the physical location of the partition 206. After the data associated with the write command is written to the partition 206, the write pointer 210 is updated to point to the next LBA available for host writing (i.e., the completion point of the first write). The write data from the host write command is sequentially programmed into the next available NAND location in the erase block that is selected for the physical support of the partition.

[0050] For example, the controller 208 may receive a first write command to the third partition 206c, or a first partition append command. The host sequentially identifies which logical block of the partition 206 is used to write the data associated with the first command. The data associated with the first command is then written to the first or next one or more available LBAs in the third partition 206c as indicated by the write pointer 210, and the write pointer 210 is advanced or updated to point to the next available LBA (i.e., WP>0) available for host writing. If the controller 208 receives a second write command to the third partition 206c, or a second partition append command, the data associated with the second write command is written to the next available LBA identified by the write pointer 210 in the third partition 206c. Once the data associated with the second command is written to the third partition 206c, the write pointer 210 is again advanced or updated to point to the next available LBA available for host writing. Resetting the third partition 206c moves the write pointer 210 back to Z c SLBA (ie, WP=0), and the third partition 206c switches to an empty partition.

[0051] Figure 3A A partitioned erase block 300 is shown according to one embodiment. Figure 3A 310, WL1 320, WL2 330, and WLn 340. The letter "n" represents the value applicable to the last word line in the erase block 300. For example, the erase block 300 may include 256 word lines. However, the erase block 300 may include more than 256 word lines or less than 256 word lines.

[0052] Furthermore, each wordline contains multiple pages, where the number corresponds to the type of memory cell. For example, SLC memory has 1 page per wordline, MLC memory has 2 pages per wordline, TLC memory has 3 pages per wordline, and so on. Figure 3A 4, the erase block 300 is a TLC memory, and each word line includes an upper page (such as UP1 322), a middle page (such as MP1 324), and a lower page (such as LP1 476), as shown by WL1 470. Each page, such as UP1 322, includes four NAND locations or four time slots (e.g., page addresses), such as 95, 96, 97, and 98 of UP1 322, that can be used for data storage. In the following description, a TLC memory erase block including 256 word lines will be used as an example; however, such an example is for explanation purposes only and is not intended to be limiting.

[0053] A time slot can be considered as a data codeword, a page address, or a page offset, where the data codeword size is 4,096B + error detection code (EDC) + error correction code (ECC). EDC may have an 8B size, and ECC may have a 128B size. Therefore, the data codeword size is 4,232B. If the NAND page is 17,000B, four data codewords (i.e., 16,928B) may fit into the NAND page. A time slot is an offset to any data codeword by page address. For example, the second data codeword 96 of the upper page UP1 322 has a time slot offset. However, the second data codeword 96 may be addressed as the second time slot 96 of the upper page UP1 322. Therefore, for exemplary purposes, throughout the description, a time slot may be used interchangeably with a data codeword.

[0054] Due to the fact that the size of the original host data is 4,096B or 4KiB, and due to the fact that the EDC and ECC parts are optional and variable in size, the offset used to reach each codeword may be referred to herein as 4KiB. However, it should generally be understood that in the examples discussed herein, the size of 4KiB is actually 4,232B. In another example, the size of a NAND page may be referred to as 16KiB, but a NAND page is more accurately described as four data codewords in a 4,232B data codeword plus some unused space. In this example, the unused space is the area between 16,928B and 17,000B.

[0055] Data is written sequentially to each 4,232B (i.e., 4KiB) NAND location of the non-volatile memory cells in sizes that are multiples of the size of one or more wordlines (i.e., multiples of 48KiB). For example, data is written sequentially to each 4KiB NAND location of the upper page UP1 322, middle page MP1 324, and lower page LP1 326. Additionally, data is written sequentially from wordline to wordline such that data is written to WL0 310 before data is written to WL1 320. As discussed above, data can be written top-to-bottom through an erase block (i.e., WL0 to WL1 to WL2, etc.) before moving to the next available erase block, or data can be written to one wordline (e.g., WL0) in each erase block before writing to the next available wordline (e.g., WL1) in each erase block. Write commands that are smaller than the wordline size are saved in a controller buffer area such as a temporary SRAM location dedicated to holding in-flight data (i.e., host data and / or parity data that is not written to the NAND) until the aggregated size of the write commands equals or exceeds the wordline size.

[0056] In one embodiment, a partial write of data can be a 'fuzzy' write or program. The partial write can be the first pass programming of the data. The second pass programming of the data can be a 'fine' write where the data can be read from the storage device. For example, a first data can be 'fuzzily' written to WL1 320, a second data 'fuzzily' written to WL2 330, and then the first data finely rewritten to WL1 320. Data can be written to a NAND location or time slot, or read from a NAND location or time slot that is sized from approximately 4KiB to approximately 16KiB. However, erasing data occurs at the erase block level where an erase block can include 256 wordlines, 768 pages, or 3,072 NAND locations or 3,072 time slots. In a storage device utilizing ZNS, an erase block within a partition can only be erased if every erase block within the partition has been erased. In other words, erasing data in a partition occurs at the partition level.

[0057] Figure 3B A partition 350 including Figure 3A one or more erase blocks 300 is shown according to one embodiment. The partition 350 can be Figure 3A a partition 206 of the ZNS 202. The partition 350 can be Figure 1 a partition of the NVM 110 coupled to the controller 108. A storage device (such as Figure 1 the storage device 106) is coupled to a memory device (such as Figure 1The NVM 110 of FIG. 1 includes a plurality of partitions, each partition including a plurality of dies 370. Although 32 dies 370 are shown in the partition 350, any number of dies may be included. Each die 370 (such as D0 370a) includes a pair of planes 360, such as P0 360a and P1 360b, and each plane 360 ​​includes Figure 3A A plurality of erase blocks 300, such as EB0 300a.

[0058] Partition 350 is formed by selecting an erase block 300 for user data storage from each plane 360 ​​of 31 of the 32 dies 370 and assigning or associating the logical block address corresponding to the erase block 300 to the partition 350. In one embodiment, partition 350 may include 31 dies 370, 380b to be used for user data and 1 die 380a to be used for parity data. For example, RAID 4 uses 1 die for parity data. In another embodiment, partition 350 may include 30 dies 370 to be used for user data and 2 dies 380a, 380b to be used for parity data. For example, RAID 6 uses 2 dies for parity data. Such embodiments are not intended to be limiting or non-limiting, but are examples of possible configurations of partition 350. In addition, there may be other embodiments that are not listed or described.

[0059] Additionally, parity data for one word line of each erase block storing user data (e.g., word line 60 of each erase block of each plane of 30 or 31 dies) may be stored in a corresponding parity word line (e.g., word line 60) of any erase block in which user data is not stored in a parity word line (e.g., word line 60). In such an embodiment, the parity word lines may be stored in a plurality of different erase blocks or planes or dies within partition 350. Additionally, when programming to non-volatile memory cells, instead of two planes of a die, a single plane of a die may be programmed to the non-volatile memory cells. Additionally, while die 380a for storing parity data is shown as the last die 380a within partition 350, any die 370, 380a, 380b may be used to store parity data.

[0060] Within partition 350, parity die 380a is partitioned for storage of parity or parity data for die failure protection. Parity die 380a may store p parity data as standard parity data, or may store q parity data of the same size as p parity data. However, q parity data is calculated using Gaussian numbers on host data stored on a particular word line of each EB. Parity data includes erasure coding that can prevent one or more die failures and / or one or more plane failures. Erasure coding can also provide a certain amount of protection for plane loss failures.

[0061] In coding theory, an erasure code is a forward error correction (FEC) code under the assumption of bit erasures (rather than bit errors) that converts a message of k symbols into a longer message (codeword) of n symbols, such that the original message can be recovered from a subset of the n symbols. Examples of various classes of erasure codes are tornado codes, fountain (i.e., rateless erasure) codes, parity codes, and Reed-Solomon codes. For example, Reed-Solomon codes are a group of ECCs where these codes are able to detect and correct multiple symbol errors.

[0062] In one embodiment, the error correction information used by the ECC decoder to correct errors can refer to redundant and / or encoded bits generated by the encoder for the error correction code. In various embodiments, the error correction code can be one of various types of error correction codes, such as block codes, convolutional codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, low-density parity check (LDPC) codes, Hamming codes, Reed-Solomon codes, turbo codes, etc. The ECC may also include an EDC, where the EDC can be a tag value, a logical address, a cyclic redundancy code (CRC), or any other ECC miscorrection check that will follow the ECC decoding. The miscorrection check detects whether the ECC has corrected a value to an invalid result. The miscorrection check is needed because there are situations where the ECC decodes to an incorrect value, but the EDC within the codeword has a known result or value to detect these miscorrections.

[0063] In addition, data is written to the erase blocks from the first partition in order such that data is written to EB0 300a before data is written to EB1 300b. Data is also written to the partitions in order such that data is written to the first partition before data is written to the second partition. Partition 350 may have any writable capacity (ZCAP), such as 256 MiB or 512 MiB, as discussed above. Each of the multiple partitions, such as partition 350, has the same partition capacity. When, for example, Figure 1When a device of the data storage device 106 utilizes ZNS, data is erased in the size of the partition capacity. In other words, unless the entire partition is erased or moved to a partition empty state (i.e., partition empty), a separate erase block cannot be erased, such as Figure 2B However, if the data storage device 106 includes a non-volatile storage unit with partial ZNS capability, data is erased from the data storage device 106 in the ZNS-capable portion of the non-volatile storage unit by the partition capacity size. Data can be erased from the non-ZNS-capable non-volatile storage unit by the erase block size.

[0064] In addition, data is stored in NVM (such as Figure 1 The location of the ZNS-capable portion of the NVM 110 is recorded in a first logical-to-physical (L2P) table as an LBA in a volatile memory cell such as the volatile memory cell 112. Data is stored in the NVM such as Figure 1 The location in the non-ZNS-capable portion of NVM 110 of the present invention is recorded in the second L2P table as an LBA in a volatile memory cell (such as volatile memory cell 112). Volatile memory cell 112 may be a DRAM cell. In addition, NVM 110 includes a first L2P table that matches the first L2P table of volatile memory cell 112 and a second L2P table that matches the second L2P table of volatile memory cell 112. The L2P table in NVM 110 is updated to match the L2P table of volatile memory cell 112.

[0065] The L2P table includes pointers to each physical location of data within NVM 110. Figure 3A In a conventional or non-ZNS storage device, a pointer is associated with each NAND location or each slot (such as slot 99, slot 100, slot 101, and slot 102 of MP1 324). The physical location of the data is mapped in the logical array so that the pointer address array includes the location mapped from the tube core to the NAND location. In an erase block, the total number of pointers is calculated as follows: 256 WLs*3 pages / WLs*4 slots / page*1 pointer / slot=3,072 pointers. In a first partition with a capacity of 62 erase blocks, there may be 190,464 pointers (i.e., 3,072 pointers / erase block*62 erase blocks=190,464 pointers). Each pointer includes a certain amount of data using the available storage of DRAM 112 and NVM 110.

[0066] By merging pointers, more memory in DRAM 112 may be available because DRAM 112 is able to store smaller L2P tables. For example, in a conventional or non-ZNS storage device, an upper page (such as UP1 322) includes 4 pointers associated with 4 slots or 4 NAND locations. In contrast, in a storage device utilizing ZNS, if the pointers are associated only with the first NAND location or first slot 99 in MP1 324, the number of pointers for the page is reduced by 3, to 1. By utilizing a pointer to the first slot or first NAND location of the page, the pointer is associated with the beginning of the page. To access the second, third, or fourth slot or second, third, or fourth NAND location in MP1 324, an offset is calculated and utilized. For example, the second slot or second NAND location 100 of MP1 324 utilizes a pointer to the first slot or first NAND location slot 99 of MP1 324 with an offset of 1. The third time slot or third NAND location 100 of MP1 324 utilizes a pointer to the first time slot or first NAND location slot 99 of MP1 324 with an offset of 2. The fourth time slot or fourth NAND location 100 of MP1 324 utilizes a pointer to the first time slot or first NAND location slot 99 of MP1 324 with an offset of 3.

[0067] In addition, when searching for a NAND location or slot due to receiving a first read command such as reading data stored in the fourth slot 102, the controller 108 uses the L2P table to find the location of the relevant LBA associated with the physical address of the data to be read. Since the pointers are merged into each page, the pointer may reference slot 95 of UP1 322, slot 99 of MP1 324, or slot 103 of LP1 326. When the controller 108 searches for the LBA associated with slot 102, the controller 108 will determine that the pointer for slot 99 of MP1 324 is too low and the pointer for slot 103 of LP1 326 is too high. Therefore, the controller 108 determines that the LBA of the data to be read is between slot 99 and slot 103 (e.g., within MP1 324). The controller 108 then utilizes the pointer associated with slot 99 of MP1 324 in conjunction with NAND location slot offset 3 to obtain the target LBA associated with the first read command for data stored in the fourth slot 102 of MP1 324 .

[0068] Pointers may be further merged to combine pages of a word line. For example, an upper page (such as UP1 322, a middle page (such as MP1 324), and a lower page (such as 326LP1) each include a pointer to the first slot or first NAND position of the page (i.e., the start of the page) resulting from merging the NAND slots as previously described. The three pointers, each associated with a page, may be merged into one pointer to the start of a word line (such as slot 95 of UP1 322). To reference the middle page, the pointer associated with the upper page is utilized with a page offset of 1. Similarly, to reference the lower page, the pointer associated with the upper page is utilized with a page offset of 2. Thus, each word line will have one pointer that can be used to read data in any of the pages of the word line and in any of the NAND positions or slots of the page.

[0069] In addition, when searching for pages of word lines due to receiving a first read command such as reading data stored in the fourth time slot 102 of the middle page MP1 324, the controller 108 uses the L2P table to find the location of the relevant LBA associated with the physical address of the data to be read. Since the pointers are merged to each word line, the pointers may reference WL0 310, WL1 320, WL2 330, or WLn 340. When the controller 108 searches for the LBA associated within WL1 320, the controller 108 will determine that the pointer for WL1 320 is too low and the pointer for WL2 330 is too high. Therefore, the controller 108 determines that the LBA of the data to be read is between WL1 320 and WL2 330 (e.g., within WL1 320). The controller 108 then performs the same process as discussed above to first determine in which page the data is stored, and then determine in which time slot or NAND location the data is stored by calculating various offsets. The controller 108 then utilizes the pointer associated with WL1 320 in conjunction with Page Offset 1 and Slot or NAND Location Offset 3 to obtain the target LBA associated with the first read command in the fourth slot 102 of mid-page MP1 324 .

[0070] The pointers may be further merged to combine word lines of an erase block. For example, WL0 310, WL1 320, WL2 330, and WLn 340 each include a pointer to the first time slot or first NAND position of a word line (i.e., the beginning of a word line) resulting from merging pages as previously described. The pointers associated with each word line may be merged into one pointer to the beginning of an erase block (such as WL0 310 of erase block 300). In addition, to reference the second word line WL1 320, the pointer associated with the erase block is utilized with a word line offset of 1. Similarly, to reference the third word line WL2 330, the pointer associated with the erase block is utilized with a word line offset of 2. Thus, each erase block will have one pointer that can be used to read data in any one of the word lines of the erase block.

[0071] When searching word lines of erase blocks due to receiving a first read command such as reading data stored in third WL2 330 of erase block 300, controller 108 uses the L2P table to find the location of the relevant LBA associated with the physical address of the data to be read. Figure 3A The erase block 300 may be Figure 3B Since the pointer is incorporated into each erase block, the pointer can reference erase block EB0 300a or another erase block, such as Figure 3B The erase block EB1 300b is shown in FIG.

[0072] If the first erase block EB0 300a is the first erase block of the first partition 350 and the second erase block EB1 300b is the second erase block of the first partition 350, the controller 108 will determine that the pointer for the first erase block EB0 300a is too low and the pointer for the second erase block EB1 300b is too high. Therefore, the controller 108 determines that the LBA of the data to be read is between the first erase block EB0 300a and the second erase block EB1 300b (e.g., within the first erase block EB0 300a). Then, the controller 108 performs the same process as discussed above to first determine in which word line the data is stored, then determine in which page the data is stored, and then determine in which time slot or NAND position the data is stored by calculating various offsets. The controller 108 utilizes the pointer associated with the first erase block EB0 300a in conjunction with word line offset 2 and the appropriate page and slot or NAND location offset to obtain the target LBA associated with the first read command for the third word line WL2 330 .

[0073] In one embodiment, if each erase block of a partition has the same address in a plane (i.e., the third erase block of each plane of each die of a partition), the pointers may also be further merged to combine the erase blocks of the partition. For example, the first erase block 300a, the second erase block 300b, the third erase block 300c, and the fourth erase block 300n each include a pointer to the first time slot or the first NAND position (i.e., the start of the erase block) of the erase block resulting from the merging of word lines as previously described. In some embodiments, the pointers associated with the erase blocks may be merged into a pointer to the first physical position or the starting physical position (i.e., the first erase block of the partition, or the first NAND position or the first time slot of the first erase block of the partition) of the partition (such as the first partition 350 and the second partition (not shown)). In other words, since the partition includes a series of sequential LBAs, each partition may be associated with a pointer pointing to or indicating the first or starting physical position within the partition. In addition, in order to reference the second erase block EB1 300b, the pointer associated with the erase block is utilized when the erase block offset is 1. Likewise, to reference the third erase block EB2 300c, a pointer associated with the erase block is utilized where the erase block offset is 2.

[0074] When searching the erase blocks of a partition due to receiving a first read command such as reading data stored in the second erase block EB1 300b of the first partition 350, the controller 108 uses the L2P table to find the location of the relevant LBA associated with the physical address of the data to be read. Since the pointer is merged into each partition, the pointer may reference the first or starting physical address of the first partition, the first or starting physical address of the second partition, and so on. When the controller 108 searches for the LBA associated with the second erase block EB1 300b, the controller 108 will determine that the pointer for the first or starting physical address of the first partition is too low and the pointer for the first or starting physical address of the second partition is too high. Therefore, the controller 108 determines that the LBA of the data to be read is between the first partition and the second partition (e.g., within the first partition 350).

[0075] The controller 108 then performs the same process as discussed above to first determine in which erase block the data is stored, then in which word line the data is stored, then in which page the data is stored, and then in which slot or NAND location the data is stored by calculating the various offsets. The controller 108 utilizes the pointer associated with the first partition 350 and in conjunction with the erase block offset 1 and the appropriate word line, page, and slot or NAND location offset to obtain the target LBA associated with the first read command for the second erase block EB1 300b of the first partition 350. Thus, each partition will have one pointer that can be used to read data in any one of the erase blocks of the partition.

[0076] By incorporating pointers in a first L2P table configured for ZNS, the amount of pointers for a partition can be reduced from a value of approximately 190,464 pointers per partition including 62 erase blocks to a value much less than approximately 190,464 pointers. The first L2P table can associate one pointer per partition such that a first or starting physical address of a first partition is associated with a first pointer, a first or starting physical address of a second partition is associated with a second pointer, and so on. Data within each partition can be found, thereby calculating various offsets. By reducing the amount of pointers in the first L2P table, more storage space can be used to store other data rather than storing pointers. In addition, the controller 108 utilizes logic control to determine the location of data based on the pointers and various offsets.

[0077] Figure 4 4 is a schematic block diagram showing a storage system 400 according to another embodiment. The host 402 may be Figure 1 The host 104, SSD 406 may be Figure 1 The storage device 106, the controller 408 may be Figure 1 The controller 108, the first RAM or volatile memory 410 (ie, the first RAM1 memory) such as DRAM may be Figure 1 The volatile memory 112, and NVM 404 may be Figure 1 In the following description, for simplicity and exemplary purposes, the first volatile memory 112 may be referred to as a DRAM memory.

[0078] NVM 404 includes ZNS segments 440 and non-ZNS segments 448. ZNS segments 440 may include any number of partitions, such as a first partition 442, a second partition 444, and an nth partition 446. ZNS segments 440 may include partitions of different sizes or capacities. For example, first partition 442, second partition 444, and third partition 446 may have a first size or capacity, while fourth partition 460, fifth partition 462, and sixth partition 464 may have a second size or capacity different from the first size or capacity. DRAM 410 includes one or more first ZNS L2P tables (shown as first ZNS L2P table 420) and one or more non-ZNS L2P tables 428. First ZNS L2P table 420 includes a pointer to a first or starting physical address of each partition, such that the pointer is associated with each partition starting LBA (ZSLBA). ZSLBA may be Z 0 SLBA 422, Z 1 SLBA 424 or Z NSLBA 426, where "N" is an integer. DRAM 410 may also include one or more second ZNS L2P tables (second L2P table 430 is shown). Second ZNS L2P table 430 includes pointers to each erase block within each partition, as discussed further below. The partitions in the L2P table can be in any order, such that the second partition is listed before the first partition.

[0079] In addition, NVM 404 includes one or more ZNS L2P tables (not shown) and one or more non-ZNS L2P tables (not shown). The L2P tables in NVM 404 are periodically updated to match the L2P tables 420, 428, 430 of volatile memory unit 112. In one embodiment, controller 408 may access a section of the L2P tables residing in NVM 404 instead of the L2P tables 420, 428, 430 residing in DRAM 410.

[0080] DRAM 410 may have limited data storage space because DRAM 410 is smaller than NVM 404. The data storage space of DRAM 410 and NVM 404 may include a ZNS L2P table and a ZNS segment, a non-ZNS L2P table and a non-ZNS segment, or both a ZNS L2P table, a ZNS segment, a non-ZNS L2P table, and a non-ZNS segment. If the data storage space of DRAM 410 or NVM 404 includes a ZNS L2P table and a ZNS segment 440, the controller 408 may merge the pointers in each ZNS L2P table (i.e., a first pointer 452 pointing to the first or starting physical address of the first partition 442, a second pointer 454 pointing to the first or starting physical address of the second partition 444, and an nth pointer 456 pointing to the first or starting physical address of the nth partition 446). However, the non-ZNS L2P table is configured to operate in a conventional setting without ZNS.

[0081] In a DRAM 410 that includes both a first ZNS L2P table 420 and a second non-ZNS L2P table 428, the first ZNS L2P table 420 may include all partitions minus three partitions, where erase blocks in the three partitions are associated with the second non-ZNS L2P table 428. The second non-ZNS L2P table 428 may be only about 1% of the capacity of the DRAM 410, with a 4K L-page size. If the DRAM 410 includes only the second non-ZNS L2P table 428, such as conventional volatile memory operations, the capacity may be limited to a 128K L-page size. The preceding values ​​listed are not intended to be limiting, but rather provide examples of possible implementations.

[0082] DRAM 410 may include one or more ZNS L2P tables such that each ZNS L2P table may refer to partitions of different sizes. For example, a first ZNS L2P table 420 may refer to a partition that includes two erase blocks from each plane of each die, while a second ZNS L2P table 430 may refer to a partition that includes one erase block from each plane of each die. In one embodiment, the pointers point to the first or starting physical address of each partition. In another embodiment, the pointers point to each erase block of the partition. For example, in the first ZNS L2P table 420, pointer 452 points to the first or starting physical address of the first partition 442, pointer 454 points to the first or starting physical address of the second partition 444, and pointer 456 points to the first or starting physical address of the nth partition 456. However, in the second L2P table 430, pointer 472 points to the second erase block EB1 of the N+1 partition 460, and pointer 474 points to the nth erase block EBN of the N+M partition 464, where "M" is an integer. In embodiments where pointers point to each erase block of a partition, the various page and slot offsets are still calculated as discussed above.

[0083] In one embodiment, DRAM 410 includes both a first ZNS L2P table 420 and a second non-ZNS L2P table 428. First write data to NVM 404 associated with one or more first commands is received by the controller to write data to a fourth time slot or fourth NAND location of a fourth page of a third word line of a first erase block EB0 of a first partition 442. The physical location of the data is stored as an LBA in the first ZNS L2P table 420. Since the LBA is stored in the first ZNS L2P table 420, a first pointer 452 associated with the first partition 442 is associated with the location of the first write data.

[0084] However, when the controller receives a first read command associated with first write data to NVM 404, the first write data may be referenced by the first pointer 452 to the first partition 442, wherein the erase block offset of the first erase block EB0 is 0, as described above. The first write data may be further referenced by the first pointer 452 to the first erase block EB0, wherein the word line offset of the third word line is 2, as described above. The first write data may be referenced by the first pointer 452 to the third word line, wherein the page offset of the third page is 2, as described above. The first write data may be further referenced by the first pointer 452 to the third page, wherein the slot or NAND position offset of the fourth slot or fourth NAND position of the third page is 3.

[0085] If the controller receives one or more commands to write first data to NVM 404 to write the first data to a fourth time slot or a fourth NAND location of a third page of a third word line of a first erase block within a non-ZNS segment, there is a pointer in the non-ZNSL2P table 428 for each sub-location of the data (e.g., a pointer for each NAND location or time slot associated with the first write data or a pointer to a 4K or 8K data size within the erase block).

[0086] In order to save space in DRAM in the ZNS L2P table where LBAs of storage devices utilizing ZNS are stored, pointers may be merged to the first value of each sub-segment, such as the first partition, first erase block, first word line, first page, and first NAND location or first time slot. Various offsets may be used with the pointers associated with the first value to determine where the data is stored in the ZNS. The merging of pointers reduces the amount of memory dedicated to pointer data in DRAM, which reduces the need for larger DRAM units or allows other data to be stored in DRAM.

[0087] In one embodiment, a storage device includes a nonvolatile storage unit, wherein the capacity of the nonvolatile storage unit is divided into a plurality of partitions. The nonvolatile storage unit includes a plurality of dies, and each of the plurality of dies includes a plurality of erase blocks. The storage device also includes a volatile memory unit, wherein the volatile memory unit stores a first logical-to-physical address table, and the first logical-to-physical address table associates a logical block address of data to a physical address at which the data is stored in the nonvolatile storage unit. The storage device also includes a controller coupled to the nonvolatile storage unit and the volatile memory unit, wherein the controller is configured to: receive a first read command to read first data stored in the nonvolatile storage unit; and read a first pointer associated with the first data in the first logical-to-physical table to determine that the first data is stored in a first erase block of a first partition of the plurality of partitions. The controller is further configured to: determine a page and word line offset within the first erase block to find the first data, and read the first data.

[0088] The volatile memory unit stores a second logical-to-physical table. The first logical-to-physical table is for a plurality of partitions, and the second logical-to-physical table is for a non-partition namespace. The controller is configured to track which erase blocks are within each partition. The first logical-to-physical table includes a pointer to each erase block within each partition. Determining a page and word line offset within the first erase block includes scanning the logical block addresses stored in the first logical-to-physical table by page size and by word line size. Data for each partition is sequentially written to each erase block of the partition.

[0089] In another embodiment, a storage device includes a nonvolatile storage unit, wherein the capacity of the nonvolatile storage unit is divided into a plurality of partitions. The nonvolatile storage unit includes a plurality of dies, and each of the plurality of dies includes a plurality of erase blocks. Each of the erase blocks includes a plurality of word lines and a plurality of pages. The storage device also includes a volatile memory unit, wherein the volatile memory unit stores a first logical-to-physical address table, and the first logical-to-physical address table associates a logical block address of data to a physical address at which the data is stored in the nonvolatile storage unit. The storage device also includes a controller coupled to the nonvolatile storage unit and the volatile memory unit, wherein the controller is configured to: write first data associated with one or more first commands to a first erase block in a first partition of the plurality of partitions; and update the first logical-to-physical address table stored in the volatile memory unit, wherein updating the first logical-to-physical table includes associating a pointer to the first partition and the first data. The controller is further configured to: receive a read command to read first data; identify a first logical block address of the first data; read a pointer associated with the first partition to determine that the first data is stored in the first partition; calculate an offset of an erase block to determine that the first data is in the first erase block; and calculate an offset of a page and a word line within the first erase block to find the first data.

[0090] The controller is further configured to: write second data associated with one or more second commands to a second erase block in the first partition in sequence; update a first logical-to-physical address table stored in a volatile memory unit, wherein updating the logical-to-physical table includes associating a pointer to the first partition and the second data; and identifying a second logical block address of the second data. The controller is also configured to: read a pointer associated with the first partition to determine that the second data is stored in the first partition; calculate an offset of the erase block to determine that the second data is stored in the second erase block; and calculate a page and word line offset within the second erase block to find the second data. The first logical-to-physical table stores one pointer per partition. Each pointer points to or indicates a first or starting physical address of each partition. The non-volatile memory also includes a non-partition namespace. The volatile memory unit stores a second logical-to-physical address table for the non-partition namespace. Calculating the erase block offset includes scanning the logical block addresses stored in the first logical-to-physical table by erase block size, and wherein calculating the page and word line offset within the first erase block includes scanning the logical block addresses stored in the first logical-to-physical table by page size and by word line size. The volatile memory unit stores a third logical-to-physical table. The first logical-to-physical table includes pointers to a first partition and one or more first partitions having a first capacity, and the third logical-to-physical table includes pointers to one or more second partitions having a second capacity different from the first capacity.

[0091] In another embodiment, a storage device includes a nonvolatile storage unit, wherein the capacity of the nonvolatile storage unit is divided into a plurality of partitions. The nonvolatile storage unit includes a plurality of dies, and each of the plurality of dies includes a plurality of erase blocks. The storage device also includes a volatile memory unit, wherein the volatile memory unit stores a first logical-to-physical address table, and the first logical-to-physical address table associates a logical block address of data to a physical address at which the data is stored in the nonvolatile storage unit. The storage device also includes: means for receiving a first read command to read first data stored in the nonvolatile storage unit; means for identifying a first logical block address of the first data; and means for reading a pointer associated with a first partition in the first logical-to-physical table to determine that the first data is stored in a first partition of the plurality of partitions. The storage device also includes: means for calculating an erase block offset to determine that the first data is stored in a first erase block of the first partition; and means for calculating a page and word line offset within the first erase block to find the first data.

[0092] The device for calculating the erase block offset is configured to scan the logical block addresses stored in the first logical to physical table by erase block size. The device for calculating the page and word line offset is configured to scan the logical block addresses stored in the first logical to physical table by page size and by word line size. Data is written to each partition in sequence. A pointer associated with the first partition points to or indicates a first or starting physical address of the first partition. The non-volatile memory also includes a non-partition namespace. The volatile memory unit stores a second logical to physical address table for the non-partition namespace. The controller is configured to track which erase blocks are within each partition and how many logical block addresses are within each erase block.

[0093] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be envisaged without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the appended claims.

Claims

1. A storage device, comprising: Non-volatile storage cells, wherein the capacity of the non-volatile storage cells is divided into multiple partitions, and wherein the non-volatile storage cells include multiple die, and each die of the multiple die includes multiple erase blocks; Volatile memory cells, wherein the volatile memory cells store a first logical-to-physical address table and a second logical-to-physical address table, the first logical-to-physical address table associating a logical block address of data to a physical address where the data is stored in the non-volatile storage cells, wherein the first logical-to-physical address table is for the multiple partitions and the second logical-to-physical address table is for a non-partitioned namespace; and A controller, the controller being coupled to the non-volatile storage cells and the volatile memory cells, wherein the controller is configured to: Receive a first read command to read first data stored in the non-volatile storage cells; Read a first pointer associated with the first data in the first logical-to-physical address table to determine that the first data is stored in a first erase block of a first partition among the multiple partitions; Determine page and word line offsets within the first erase block to locate the first data; and Read the first data.

2. The storage device according to claim 1, wherein the controller is further configured to track which erase blocks are within each partition.

3. The storage device according to claim 1, wherein the first logical-to-physical address table includes pointers for each erase block within each partition.

4. The storage device according to claim 1, wherein determining the page and word line offsets within the first erase block includes scanning the logical block addresses stored in the first logical-to-physical address table by page size and by word line size.

5. The storage device according to claim 1, wherein data for each partition is written sequentially to each erase block of the partition.

6. The storage device according to claim 1, wherein reading the first pointer associated with the first data in the first logical-to-physical address table to determine that the first data is stored in the first erase block of the first partition further includes calculating an erase block offset to determine that the first data is stored in the first erase block.

7. The storage device according to claim 1, wherein the volatile memory cells store a third logical-to-physical address table, and wherein the first logical-to-physical address table includes pointers for the first partition and one or more first partitions having a first capacity, and the third logical-to-physical address table includes pointers for one or more second partitions having a second capacity different from the first capacity.

8. A storage device, comprising: Non-volatile storage cells, wherein the capacity of the non-volatile storage cells is divided into multiple partitions, and wherein the non-volatile storage cells include multiple die, and each die of the multiple die includes multiple erase blocks, and each of the erase blocks includes multiple word lines and multiple pages; A volatile memory cell, wherein the volatile memory cell stores a first logical-to-physical address table that associates a logical block address of data with a physical address where the data is stored in the non-volatile storage cell; and A controller coupled to the non-volatile storage cell and the volatile memory cell, wherein the controller is configured to: Write first data associated with one or more first commands to a first erase block in a first partition of the plurality of partitions; Update the first logical-to-physical address table stored in the volatile memory cell, wherein updating the first logical-to-physical address table includes associating a pointer to the first partition and the first data; Receive a read command to read the first data; Identify a first logical block address of the first data; Read the pointer associated with the first partition to determine that the first data is stored within the first partition; Calculate an erase block offset to determine that the first data is stored in the first erase block; and Calculate page and word line offsets within the first erase block to find the first data.

9. The storage device according to claim 8, wherein the controller is further configured to: Sequentially write second data associated with one or more second commands to a second erase block in the first partition; Update the first logical-to-physical address table stored in the volatile memory cell, wherein updating the first logical-to-physical address table includes associating the pointer to the first partition and the second data; Identify a second logical block address of the second data; Read the pointer associated with the first partition to determine that the second data is stored within the first partition; Calculate an erase block offset to determine that the second data is stored in the second erase block; and Calculate page and word line offsets within the second erase block to find the second data.

10. The storage device according to claim 8, wherein the first logical-to-physical address table stores one pointer per partition, and wherein each pointer points to or indicates a first or starting physical address of each partition.

11. The storage device according to claim 8, wherein the non-volatile storage cell further includes a non-partitioned namespace, and wherein the volatile memory cell stores a second logical-to-physical address table for the non-partitioned namespace.

12. The storage device according to claim 8, wherein calculating the erase block offset includes scanning the logical block addresses stored in the first logical-to-physical address table by erase block size, and wherein calculating the page and word line offsets within the first erase block includes scanning the logical block addresses stored in the first logical-to-physical address table by page size and by word line size.

13. The storage device according to claim 8, wherein the volatile memory cell stores a third logical-to-physical address table.

14. The storage device according to claim 13, wherein the first logical-to-physical address table includes pointers for the first partition and one or more first partitions having a first capacity, and the third logical-to-physical address table includes pointers for one or more second partitions having a second capacity different from the first capacity.

15. A storage device, the storage device comprises: Non-volatile storage cells, wherein the capacity of the non-volatile storage cells is divided into a plurality of partitions, and wherein the non-volatile storage cells include a plurality of dies, and each die of the plurality of dies includes a plurality of erase blocks; Volatile memory cells, wherein the volatile memory cells store a first logical-to-physical address table that associates a logical block address of data with a physical address where the data is stored in the non-volatile storage cells; Means for receiving a first read command for reading first data stored in the non-volatile storage cells; Means for identifying a first logical block address of the first data; Means for reading a pointer associated with a first partition among the plurality of partitions in the first logical-to-physical address table to determine that the first data is stored within the first partition among the plurality of partitions; Means for calculating an erase block offset to determine that the first data is stored in a first erase block of the first partition, wherein the means for calculating the erase block offset is configured to scan the logical block address stored in the first logical-to-physical address table by an erase block size; and Means for calculating a page and word line offset within the first erase block to find the first data.

16. The storage device according to claim 15, wherein the means for calculating the page and word line offset is configured to scan the logical block address stored in the first logical-to-physical address table by a page size and by a word line size.

17. The storage device according to claim 15, wherein the pointer associated with the first partition points to or indicates a first or starting physical address of the first partition.

18. The storage device according to claim 15, wherein the non-volatile storage cells further include a non-partitioned namespace, and wherein the volatile memory cells store a second logical-to-physical address table for the non-partitioned namespace.

19. The storage device according to claim 15, further comprising means for tracking which erase blocks are within each partition and how many logical block addresses are within each erase block.

20. The storage device according to claim 15, wherein the volatile memory cells store a third logical-to-physical address table, and wherein the first logical-to-physical address table includes pointers for the first partition and one or more first partitions having a first capacity, and the third logical-to-physical address table includes pointers for one or more second partitions having a second capacity different from the first capacity.

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