Control word line voltage to reduce read interference in memory devices

Abstract

Apparatus and techniques for reducing read interference in a memory device by reducing channel gradient and charge injection to memory cells are described. Before reading a memory cell in a selected NAND string, the channel of an unselected NAND string is boosted. This boosting involves simultaneously increasing the voltage signal of a non-adjacent word line of the selected word line WLn to the read pass voltage while selecting the gate transistor on the drain side to turn it on and off, and increasing the voltage signal of the non-adjacent word line of the selected word line WLn to the read pass voltage, while applying a positive voltage to the source and drain terminals of the unselected NAND string. The voltage signal of the adjacent word lines of WLn: increases to a peak level to enhance channel conductivity for faster reading, wherein the peak level is less than the read pass voltage; decreases to a lower level to reduce the channel gradient and thus reduce read interference; and then increases to the read pass voltage.

Description

Background Technology

[0001] This technology relates to the operation of memory devices.

[0002] Semiconductor memory devices have become increasingly common in a variety of electronic devices. For example, non-volatile semiconductor memories are used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices.

[0003] Charge storage materials (such as floating gates) or charge trapping materials can be used in such memory devices to store charges representing data states. Charge trapping materials can be arranged vertically in a three-dimensional (3D) stacked memory structure or horizontally in a two-dimensional (2D) memory structure. An example of a 3D memory structure is the Bit Cost Scalable (BiCS) architecture, which comprises a stack of alternating conductive and dielectric layers.

[0004] Memory devices include memory cells that can be arranged in series to form NAND strings, for example, where select-gate transistors are located at the ends of the NAND string to selectively connect the channels of the NAND string to source lines or bit lines. However, various challenges exist in operating such memory devices. Attached Figure Description

[0005] Figure 1A This is a block diagram of an example memory device.

[0006] Figure 1B yes Figure 1A A block diagram of the arrangement of the memory device 100, wherein the control circuitry 130 on the first die 130a communicates with the memory structure 126 on a separate second die 126b.

[0007] Figure 1C It shows Figure 1A Example of temperature sensing circuit 116.

[0008] Figure 2 It is shown Figure 1A A block diagram of one embodiment of the sensing block 51.

[0009] Figure 3 It shows Figure 1A An exemplary embodiment of the power control circuit 115 for supplying voltage to a block of memory cells.

[0010] Figure 4 This is a perspective view of an exemplary memory die 600, wherein blocks are disposed in corresponding planes P0 and P1, and... Figure 3 Consistent.

[0011] Figure 5 It shows Figure 4 An exemplary cross-sectional view of block B0-0, which includes a portion of NAND string 700n.

[0012] Figure 6 It shows Figure 5 An exemplary cross-sectional view of the block portion in the xy plane at the WLn level.

[0013] Figure 7 It shows Figure 4 Another exemplary cross-sectional view of block B0-0, which includes a portion of NAND string 600n, wherein the block comprises two layers.

[0014] Figure 8 It shows Figure 4 An exemplary view of block B0-0 and associated bit lines and sensing circuitry, wherein the corresponding NAND strings are arranged in the sub-block.

[0015] Figure 9 An exemplary NAND string in a 2D configuration is shown.

[0016] Figure 10 The threshold voltage (Vth) distribution of an eight-state memory device is shown.

[0017] Figure 11A An example of the channel voltage in an unselected NAND string is shown during the pre-charge phase of a read operation, when the SGD and SGS transistors are turned on and positive biases Vbl and Vcelsrc are applied to the drain and source terminals of the NAND string, respectively.

[0018] Figure 11B This illustrates the situation during the pre-charge phase of a read operation, where the SGD and SGS transistors are turned off, causing channel gradients in memory cells within the NAND string to be disturbed. Figure 11A An example of the channel voltage in an unselected NAND string.

[0019] Figure 11C This illustrates the situation during the pre-charge phase of a read operation, where the SGD and SGS transistors are turned off, causing channel gradients in memory cells within the NAND string to be disturbed. Figure 11A Another example of channel voltage in an unselected NAND string.

[0020] Figure 12A A flowchart is shown, which illustrates the relationship between... Figure 11B and Figure 11C An overview of a consistent exemplary process for reducing interference in read operations.

[0021] Figure 12B A flowchart is shown, in which... Figure 12A Exemplary details of the pre-charging phase of step 1201.

[0022] Figure 12C A flowchart is shown, in which... Figure 12A Exemplary details of the sensing phase of step 1202.

[0023] Figure 13A It shows the relationship with Figures 12A to 12C An example voltage signal in a consistent read operation.

[0024] Figure 13B It shows the relationship with Figure 12C Step 1223a is consistent with an exemplary voltage signal having a voltage over kick.

[0025] Figure 14A The curve is shown, where... Figure 13A How does Vread_low change with temperature, and... Figure 12B The steps 1213c are the same.

[0026] Figure 14B The curve is shown, where... Figure 13A How does Vread_low change with the risk of interference, and... Figure 12B The steps 1213c are the same. Detailed Implementation

[0027] This invention describes apparatus and techniques for reducing interference during read operations in memory devices.

[0028] In some memory devices, memory cells are interconnected, such as in NAND strings within a block or sub-block. Each NAND string includes: a plurality of memory cells connected in series between one or more drain-side select-gate transistors (called SGD transistors) at the drain end of the NAND string's connection bit line; and one or more source-side select-gate transistors (called SGS transistors) at the source end of the NAND string or other memory strings or connected groups of memory cells at the source end of the connection source line. The select-gate transistor is also called the select gate. Furthermore, memory cells may be arranged with a common control gate line (e.g., a word line) serving as the control gate. A set of word lines extends from the source side of the block to the drain side of the block. See, for example... Figure 8 Memory cells can also be connected in other ways.

[0029] In a 3D memory structure, memory cells can be arranged in stacked vertical NAND strings on a substrate, where the stack includes alternating conductive and dielectric layers. The conductive layers serve as word lines connecting to the memory cells. Each NAND string may have a pillar shape intersecting the word lines to form the memory cells. Furthermore, each NAND string includes various layers extending vertically within the stack, such as barrier oxide layers, charge trapping layers, tunnel layers, and channel layers. See, for example... Figure 5 and Figure 6 .

[0030] In a 2D memory structure, memory cells can be arranged in horizontal NAND strings on a substrate. See, for example... Figure 9 .

[0031] Memory cells can be programmed to have a threshold voltage (Vth) corresponding to the data state. See, for example... Figure 10 Vth is a function of the amount of charge in the charge storage material stored in the memory cell. A read operation can be performed to determine Vth, thus determining the data state of the memory cell. A read can also be performed in a verification test for a programming operation, where the Vth of the memory cell is compared to a verification voltage applied to the corresponding word line to determine whether programming of the memory cell is complete. Similarly, a read can be performed in a verification test for an erase operation, where the Vth of the memory cell is compared to a verification voltage applied to the corresponding word line to determine whether erasing of the memory cell is complete.

[0032] Typically, read operations are performed on memory cells within a selected sub-block of a block. The remaining sub-blocks of the block are unselected. However, applying a voltage to the word line used during NAND string reads in the selected sub-block can interfere with memory cells in NAND strings within the unselected sub-blocks, as the word line is shared by the NAND strings throughout the block. One type of read interference is caused by weak Fowler-Nordheim (FN) tunneling. In this case, a large voltage difference exists between the control gate and the cell's channel, which draws electrons from the channel into the charge trapping layer. For example, the control gate may be at a relatively high read pass voltage of 8-9V.

[0033] One approach is to precharge the channel of the NAND string in the unselected sub-block before reading it from the selected sub-block. This precharging may involve biasing the ends of the NAND string in the unselected sub-block when the memory cell is turned on. During this precharging phase of the read operation, the SGS transistor is turned on and held on, and the SGD transistor is turned on first and then turned off. The drain-side and source-side regions of the channel of the NAND string in the unselected sub-block are thus connected. In the subsequent sensing phase of the read operation, a read voltage is applied to the selected word line to read the NAND string in the selected sub-block.

[0034] Since the goal is to improve performance, the duration of the precharge phase should be minimized. However, if the duration is too short, a channel gradient can form in the NAND string within unselected sub-blocks, leading to hot electron injection (HEI) type read interference. In this case, the channel gradient generates electron-hole pairs, where electrons can be injected into the memory cell, thereby increasing its Vth. A boost in the channel voltage during the precharge phase can sometimes increase the likelihood of injection-type interference, such as when combined with… Figure 11B and Figure 11C This type of interference occurs when the SGD transistor is turned off, while the voltage on the unselected word line continues to increase to the read pass level. This sustained increase in voltage causes capacitive coupling of the channel, particularly on the drain side of the selected word line WLn, resulting in a large channel gradient. This type of interference is particularly prevalent on the memory cell of word line WLn+1, which is the word line adjacent to the drain side of WLn. Electrons generated by this channel gradient can be injected, especially, into the memory cell of word line WLn+1.

[0035] The technology provided in this paper solves the above and other problems. In one aspect, the read operation includes a precharge phase and a sensing phase. In the precharge phase, the voltage signal applied to the drain side of the selected word line adjacent to the word line increases from an initial level (at which time the associated memory cell is off) to a peak level (at which time the associated memory cell is on), and then decreases from the peak level to a lower level. This lower level can be a positive voltage. For example, see... Figure 13A Curves 1314 and 1315 in the diagram illustrate this. During the pre-charge phase from t0 to t9, the voltage signal increases from 0V at t0 to Vspike2 at t3, then decreases to Vread_low1 at t5 (curve 1314) or Vread_low2 at t4 (curve 1315). Simultaneously with this voltage signal, a voltage signal increasing from the initial level to the read pass level Vread is applied to non-adjacent word lines. See, for example, [link to relevant documentation]. Figure 13A Curves 1311 and 1312 in the diagram.

[0036] For NAND strings in unselected sub-blocks, the drain-side select-gate transistor (SGD transistor) is turned on first and then turned off. See, for example... Figure 13A Curves 1321 and 1323 for Vsg_unsel. When the SGD transistor is turned off, for example at t5, the voltage signal applied to the non-adjacent word line continues to increase from t5-t8 to Vread. This causes a channel gradient and associated interference. However, the magnitude of the channel gradient decreases as the voltage signal applied to the adjacent word line on the drain side decreases from its peak level to a lower level, contrasting with the case where this voltage signal increases to the read pass level. See also Figure 11B and Figure 11CBy preventing the voltage signal on the adjacent word line on the drain side from further increasing to Vread at this time, capacitive coupling in the corresponding channel region is avoided. Therefore, the possibility of channel gradient and interference is reduced.

[0037] Also during the precharge phase, the voltage signal used to select the word line can be increased from an initial level to a peak level, such as Vspike1 (curve 1301), and then decreased to a lower level, such as 0V. The source-side select-gate transistor (SGS transistor) can be turned on and remain on. See, for example, curves 1320 and 1322 and Vsgs. A positive voltage Vcelsrc1 (curve 1340) can be applied to the source terminal of the NAND string, while a positive voltage Vbl1 (curve 1330) can be applied to the drain terminal of the NAND string.

[0038] In one option, the reduced level of the voltage signal Vread_low applied to the adjacent word line on the drain side is adjusted based on factors that indicate the risk of read interference, such as the temperature or location of the selected word line.

[0039] In another option, the voltage signal applied to the drain side of the selected word line adjacent to the selected word line is also applied to the source side of the selected word line adjacent to the selected word line.

[0040] In another option, the voltage signal applied to the additional drain-side word line of the selected word line can be configured to reduce the likelihood of interference, similar to the voltage signal applied to the adjacent drain-side word line. For example, see the reduced level of the additional drain-side word line (…). Figure 13A Vread_low2 (see curve 1315). Vread_low2 can be greater than the level drop of the adjacent word line on the drain side (see...). Figure 13A Vread_low1 (curve 1314) in the image.

[0041] These and other features will be discussed further below.

[0042] Figure 1AThis is a block diagram of an exemplary storage device. Memory device 100, such as a non-volatile memory system, may include one or more memory dies 108. Memory die 108 or a chip includes a memory structure 126 of memory cells, such as an array of memory cells, control circuitry 110, and read / write circuitry 128. Memory structure 126 is addressable via word lines through row decoder 124 and via bit lines through column decoder 132. Read / write circuitry 128 includes a plurality of sensing blocks 51, 52, ..., 53 (sensing circuitry) and allows for parallel reading or programming of pages of memory cells. Typically, a controller 122 is included in the same memory device 100 (e.g., a removable memory card) as one or more memory dies 108. The controller may reside on a die 127 separate from the memory dies 108. Commands and data are transmitted between host 140 and controller 122 via data bus 120 and between controller and one or more memory dies 108 via line 118.

[0043] The memory structure can be a 2D memory structure or a 3D memory structure. The memory structure may include one or more memory cell arrays, including 3D arrays. The memory structure may include a monolithic 3D memory structure in which multiple memory stages are formed on (but not in) a single substrate (such as a wafer), without intermediate substrates. The memory structure may include any type of non-volatile memory, which is monolithically formed in one or more physical stages of memory cell arrays having active regions disposed on a silicon substrate. The memory structure may be in a non-volatile memory device having circuitry associated with the operation of the memory cells, whether the associated circuitry is on or within the substrate.

[0044] Control circuitry 110 cooperates with read / write circuitry 128 to perform memory operations on memory structure 126 and includes a state machine, on-chip address decoder 114, power control circuitry 115, and temperature sensing circuitry 116. Storage area 113 may be provided, for example, for operating parameters and software / code. In one embodiment, the state machine is software-programmed. In other embodiments, the state machine does not use software and is implemented entirely in hardware (e.g., electrical circuitry).

[0045] On-chip address decoder 114 provides an address interface between the hardware addresses used by the host or memory controller and the hardware addresses used by decoders 124 and 132. Power control circuitry 115 controls the power and voltage supplied to the word lines, select gate lines, bit lines, and source lines during memory operations. This power control module may include drivers for word lines, SGS and SGD transistors, and source lines. See also... Figure 3In one method, the sensing block may include a bit line driver. Temperature sensing circuitry 116 can detect the temperature of the memory device during programming operations. See [link to specific implementation of temperature sensing circuitry] for an exemplary embodiment. Figure 1C The temperature sensing circuit, the programming loop tracking circuit, and the verification test-setup circuit may include hardware, software, and / or firmware for performing the processes described herein.

[0046] In some specific implementations, some components of the components may be combined. In various designs, one or more components (alone or in combination) other than memory structure 126 may be considered as at least one control circuit configured to perform the techniques described herein, including the steps of the processes described herein. For example, the control circuit may include any or a combination of control circuit 110, state machine 112, decoders 114 and 132, power control circuit 115, temperature sensing circuit 116, sensing blocks 51, 52...53, read / write circuit 128, controller 122, etc. A state machine is a circuit that controls the operation of control circuit 110. In some implementations, the state machine is implemented or replaced by a microprocessor, microcontroller, and / or RISC processor.

[0047] The off-chip controller 122 (in one embodiment, circuitry) may include a processor 122e, memories such as ROM 122a and RAM 122b, and an error correction code (ECC) engine 245. The ECC engine can correct numerous read errors. RAM 122b may be, for example, DRAM storing uncommitted data. During programming, a copy of the data to be programmed is stored in RAM 122b until programming is successfully completed. In response to successful completion, the data is erased from RAM 122b and committed or released to a memory cell block. RAM 122b may store data for one or more word lines.

[0048] A memory interface 122d may also be provided. The memory interface, which communicates with the ROM, RAM, and processor, is a circuit that provides an electrical interface between the controller and the memory die. For example, the memory interface can change the format or timing of signals, provide buffers, isolate surges, latch I / O, etc. The processor can issue commands to the control circuitry 110 (or any other component of the memory die) via the memory interface 122d.

[0049] The memories in controller 122, such as ROM 122a and RAM 122b, include code such as a set of instructions, and the processor is operable to execute that set of instructions to provide the functionality described herein. Alternatively or otherwise, the processor may access the code from a subgroup 126a of the memory structure, such as reserved areas of memory cells in one or more word lines.

[0050] For example, the controller can use code to access memory structures, such as for programming, reading, and erasing operations. The code may include boot code and control code (e.g., a set of instructions). Boot code is the software that initializes the controller during boot or startup and enables it to access memory structures. The controller can use the code to control one or more memory structures. Upon power-up, processor 122e fetches boot code from ROM 122a or subgroup 126a for execution, and the boot code initializes system components and loads control code into RAM 122b. Once the control code is loaded into RAM, it is executed by the processor. The control code includes drivers that perform basic tasks such as controlling and allocating memory, prioritizing instruction processing, and controlling input and output ports.

[0051] The controller, such as RAM 122b and / or control circuitry 110, may store parameters indicating the expected number of failed bits in the block. These parameters may include, for example, the number of bits per cell stored in the memory cell, a portion of the word line programmed in the block or sub-block, a portion of the sub-block programmed in the block, the strength of the ECC processing used to store and read data in the block, the duration of the pre-read voltage pulse (if used), and read accuracy, such as bit line or word line voltage settling time and the number of sense passes.

[0052] Generally, control code may include instructions to perform the functions described herein, including the steps of the flowcharts discussed further below, and provide voltage waveforms, including those discussed further below. Control circuitry may be configured to execute instructions for performing the functions described herein.

[0053] In one embodiment, the host is a computing device (e.g., a laptop computer, desktop computer, smartphone, tablet computer, digital camera) that includes one or more processors and one or more processor-readable storage devices (RAM, ROM, flash memory, hard disk drive, solid-state memory) storing processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices that communicate with the one or more processors.

[0054] In addition to NAND flash memory, other types of non-volatile memory can also be used.

[0055] Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (DRAM) or static random access memory (SRAM) devices; non-volatile memory devices, such as resistive random access memory (ReRAM), electrically erasable programmable read-only memory (EEPROM), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (FRAM), and magnetoresistive random access memory (MRAM); and other semiconductor elements capable of storing information. Each type of memory device can have different configurations. For example, flash memory devices can be configured with NAND or NOR.

[0056] The memory device can be formed from passive and / or active components in any combination. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity-switching storage elements, such as antifuse or phase-change materials, and optional steering elements, such as diodes or transistors. Furthermore, by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements comprising charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0057] Multiple memory elements can be configured such that they are connected in series or that each element can be accessed individually. By way of non-limiting example, a flash memory device (NAND memory) in a NAND configuration typically contains memory elements connected in series. A NAND string is an example of a group of transistors connected in series, comprising memory cells and SG transistors.

[0058] NAND memory arrays can be configured such that the array consists of multiple strings of memory, where a string consists of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements can be configured such that each element can be accessed individually, such as in a NOR memory array. NAND memory configurations and NOR memory configurations are examples, and memory elements can be configured in other ways.

[0059] Semiconductor memory elements located within and / or on a substrate can be arranged in two or three dimensions, such as 2D memory structures or 3D memory structures.

[0060] In 2D memory architectures, semiconductor memory elements are arranged on a single plane or in a single memory device level. For example, see... Figure 9Typically, in a 2D memory structure, memory elements are arranged in a plane (e.g., in an xy-direction plane) that extends substantially parallel to the main surface of the substrate supporting the memory elements. The substrate can be a wafer on which layers of the memory elements are formed, or it can be a carrier substrate attached to the memory elements after they have been formed. As a non-limiting example, the substrate may include semiconductors, such as silicon.

[0061] Memory elements can be arranged in a single memory device level in an ordered array (such as in multiple rows and / or columns). However, memory elements can be arranged in unconventional or non-orthogonal configurations. Each memory element may have two or more electrodes or contact lines, such as bit lines and word lines.

[0062] Arrange a 3D memory array such that the memory elements occupy multiple planes or multiple memory device levels to form a three-dimensional structure (i.e., in the x, y and z directions, where the z direction is substantially perpendicular to the main surface of the substrate and the x and y directions are substantially parallel to the main surface of the substrate).

[0063] As a non-limiting example, a 3D memory structure can be vertically arranged as a stack of multiple 2D memory device levels. As another non-limiting example, a 3D memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate, i.e., in the y-direction), where each column has multiple memory elements. See, for example, [link to relevant documentation]. Figure 5 These columns can be arranged in a 2D configuration, for example, in the xy plane, resulting in a 3D arrangement of memory elements, where the elements are located on multiple vertically stacked memory planes. Other configurations of the three-dimensional memory elements can also constitute a 3D memory array.

[0064] By way of non-limiting example, in a 3D NAND memory array, memory elements may be coupled together to form NAND strings within a single horizontal (e.g., xy) memory device level. Alternatively, memory elements may be coupled together to form vertical NAND strings spanning multiple horizontal memory device levels. Other 3D configurations are conceivable, where some NAND strings contain memory elements within a single memory level, while others contain memory elements spanning multiple memory levels. The 3D memory array can also be designed in both NOR and ReRAM configurations.

[0065] Typically, in a monolithic 3D memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic 3D memory array may also have one or more memory layers located at least partially within a single substrate. As a non-limiting example, the substrate may include a semiconductor, such as silicon. In a monolithic 3D array, the layer constituting each memory device level of the array is typically formed on the layer of the lower memory device level of the array. However, the layers of adjacent memory device levels in a monolithic 3D memory array may be shared between memory device levels or there may be intermediate layers between memory device levels.

[0066] 2D arrays can be formed individually and then packaged together to form a non-monolithic memory device with multi-layered memory. For example, a non-monolithic stacked memory can be constructed by forming memory stages on separate substrates and then stacking the memory stages on top of each other. The substrates can be thinned or removed from the memory device stages before stacking, but since the memory device stages are initially formed on separate substrates, the resulting memory array is not a monolithic 3D memory array. Furthermore, multiple 2D or 3D memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

[0067] Typically, associated circuitry is required to operate and communicate with the memory element. As a non-limiting example, a memory device may have circuitry for controlling and driving the memory element to perform functions such as programming and reading. This associated circuitry may be located on the same substrate as the memory element and / or on a separate substrate. For example, a controller for memory read-write operations may be located on a separate controller chip and / or on the same substrate as the memory element.

[0068] Those skilled in the art will recognize that this technology is not limited to the described 2D and 3D exemplary structures, but encompasses all relevant memory structures as described herein and as understood by those skilled in the art in terms of their nature and scope.

[0069] Figure 1B yes Figure 1AA block diagram of the arrangement of a memory device 100, wherein control circuitry 130 on a first die 130a communicates with a memory structure 126 on a separate second die 126b. The control circuitry may communicate with the memory structure and die 126b via a memory interface 131 (e.g., similar to memory interface 122d). Examples of memory interfaces (I / F) include JEDEC's Common Flash Memory Interface. The techniques described herein can be implemented using a control die 130a incorporated into one or more memory dies 126b, wherein the memory die includes the memory structure 126, and the control die includes control circuitry 130 representing all or a subset of the peripheral circuitry of the memory structure. The control circuitry may be located on the same die as the plurality of memory cells or on a different die than the plurality of memory cells.

[0070] For example, the memory structure may include non-volatile memory cells. In some embodiments, the memory die and control die are combined. Control circuitry 130 may include a set of circuitry that performs memory operations (e.g., write, read, erase, etc.) on the memory structure. The control circuitry may include a state machine 112, a memory area 113, an on-chip address decoder 114, and power control circuitry 115. In another embodiment, a portion of the read / write circuitry 128 is located on the control die 130a, while another portion of the read / write circuitry is located on the memory die 126b. For example, the read / write circuitry may include a sense amplifier. This sense amplifier may be located on the control die and / or the memory die.

[0071] In an exemplary embodiment, control circuitry 130 is configured to connect to the NAND string and the substrate, and memory interface 131 is connected to the control circuitry. This circuitry can be configured, for example, to issue commands via the memory interface to apply different voltage signals to bit lines, word lines, select gate lines, and CELSRC lines (source lines). For example, the control circuitry can send commands to… Figure 3 The voltage driver in the middle issues commands to... Figures 12A-12C The flowchart in Figure 13 provides the voltage signal.

[0072] The term "memory die" can refer to a semiconductor die containing non-volatile memory cells for storing data. The term "control circuit die" can refer to a semiconductor die containing control circuitry for performing memory operations on the non-volatile memory cells on the memory die. Typically, many semiconductor dies are formed from a single semiconductor wafer.

[0073] Figure 1C It shows Figure 1AAn example of a temperature sensing circuit 116. This circuit includes pMOSFETs 131a, 131b, and 134, bipolar transistors 133a and 133b, and resistors R1, R2, and R3. I1, I2, and I3 represent currents. Voutput is the temperature-based output voltage supplied to the analog-to-digital converter (ADC) 129. Vbg is a temperature-independent voltage. A voltage level generation circuit 135 uses Vbg to set multiple voltage levels. For example, a reference voltage can be divided into several levels using a resistor divider circuit.

[0074] The ADC compares Voutput with the voltage level and selects the closest match, outputting the corresponding digital value (VTemp) to the processor 122e. This is data indicating the temperature of the memory device. In one approach, the ROM fuse 123 stores data that correlates the matched voltage level with the temperature. The temperature can be used, for example, to set temperature-based locking conditions in the memory device.

[0075] Vbg is obtained by applying a base-emitter voltage (Vbe) and a voltage drop across resistor R2 across transistor 131b. Bipolar transistor 133a has a larger area (factor N) than transistor 133b. PMOS transistors 131a and 131b are of equal size and arranged in a current mirror configuration, such that currents I1 and I2 are approximately equal. Therefore, Vbg = Vbe + R2 × I2 and I1 = Ve / R1, thus I2 = Ve / R1. Therefore, Vbg = Vbe + R2 × kT ln(N) / R1 × q, where T is temperature, k is the Boltzmann constant, and q is the unit of charge. The source of transistor 134 is connected to the supply voltage Vdd, and the node between the transistor's drain and resistor R3 is the output voltage Voutput. The gate of transistor 134 is connected to the same terminal as the gates of transistors 131a and 131b, and the current through transistor 134 mirrors the current through transistors 131a and 131b.

[0076] Temperature indication from the temperature sensing circuit can, for example, be found in... Figure 14B The curve is used to set the level of Vread_low. This temperature can be the ambient temperature of the memory device.

[0077] Figure 2 It is shown Figure 1A A block diagram of one embodiment of sensing block 51. The individual sensing block 51 is divided into one or more core portions called sensing circuits 60-63 or sensing amplifiers and a common portion called management circuitry 190. In one embodiment, each sensing circuit is connected to a corresponding bit line, which in turn is connected to one or more NAND strings. For example, in... Figure 8In the consistent configuration, each bit line is connected to four NAND strings, and each sub-block has one NAND string. A common management circuit 190 is connected to a group of multiple (e.g., four or eight) sensing circuits. Each sensing circuit in the group communicates with its associated management circuit via a data bus 176. Therefore, there are one or more management circuits communicating with the sensing circuits of a group of memory elements (memory cells).

[0078] For example, sensing circuit 60 operates during a programming cycle to provide a precharge / programming-suppression voltage to an unselected positioning line or a programming-enable voltage to a selected positioning line. The unselected positioning line is connected to an unselected NAND string and an unselected memory cell therein. An unselected memory cell can be a memory cell within an unselected NAND string, where the memory cell is connected to a selected or unselected word line. An unselected memory cell can also be a memory cell within a selected NAND string, where the memory cell is connected to an unselected word line. The selected positioning line is connected to a selected NAND string and a selected memory cell therein.

[0079] The sensing circuit 60 also operates during a verification test in the programming cycle to sense memory cells, thereby determining whether they have been programmed by reaching an assigned data state (e.g., as indicated by a verification voltage Vth exceeding the assigned data state). The sensing circuit 60 also operates during a read operation to determine the data state to which the memory cell has been programmed. The sensing circuit 60 also operates during an erase operation during the verification test to determine whether multiple memory cells have a Vth below the verification voltage. As further described below, verification tests can be performed on memory cells connected to all word lines in a block or on memory cells connected to odd or even number lines. The sensing circuit performs sensing by determining whether the conduction current in the connected bit lines is above or below a predetermined threshold level. This indicates whether the Vth of the memory cell is below or above the word line voltage, respectively.

[0080] The sensing circuit may include a selector 56 or a switch connected to transistor 55 (e.g., nMOS). Based on the voltage at the control gate 58 and drain 57 of transistor 55, the transistor may operate as a pass-gate or bit-line clamp. When the voltage at the control gate is sufficiently higher than the voltage at the drain, the transistor operates as a pass-gate to pass the voltage at the drain to the bit line (BL) at the source 59 of the transistor. For example, a programming-suppression voltage of, for example, 1-2V may be passed when pre-charging and suppressing an unselected NAND string. Alternatively, a programming-enable voltage such as 0V may be passed to allow programming in a selected NAND string. Selector 56 may pass a supply voltage Vdd (e.g., 3-4V) to the control gate of transistor 55 to cause the transistor to operate as a pass-gate.

[0081] When the voltage at the control gate is lower than the voltage at the drain, transistor 55 operates as a source follower to set or clamp the bit line voltage at Vcg - Vth, where Vcg is the voltage at the control gate 58 and Vth (e.g., 0.7V) is the threshold voltage of transistor 55. This assumes the source line is at 0V. If Vcelsrc is non-zero, the bit line voltage is clamped at Vcg - Vcelsrc - Vth. Therefore, this transistor is sometimes referred to as a bit line clamp (BLC) transistor, and the voltage Vcg at the control gate 58 is referred to as the bit line clamp voltage Vblc. This mode can be used during sensing operations, such as read and verification operations. The bit line voltage is thus set by transistor 55 based on the voltage output by selector 56. For example, selector 56 can pass Vbl_sense + Vth (e.g., 1.5V) to the control gate of transistor 55 to provide Vbl_sense, for example, 0.8V, on the bit line. Vbl selector 173 can pass a relatively high voltage, such as Vdd, to drain 57 to provide source follower mode during sensing operation, which is higher than the control gate voltage on transistor 55. Vbl refers to the bit line voltage.

[0082] Vbl selector 173 can transmit one of a plurality of voltage signals. For example, for a corresponding bit line of a NAND string that is not selected during a programming cycle, the Vbl selector can transmit a program-suppress voltage signal that increases from an initial voltage (e.g., 0V) to a programming suppress voltage (e.g., Vbl_inh). For a corresponding bit line of a selected NAND string during a programming cycle, Vbl selector 173 can transmit a programming-enable voltage signal, such as 0V. For example, the Vbl selector can select a bit line from a processor 192 based on a command from the processor 192. Figure 3 The voltage signal of the BL voltage driver 340 in the middle.

[0083] In one approach, the selector 56 of each sensing circuit can be controlled separately from the selectors of other sensing circuits. The Vbl selector 173 of each sensing circuit can also be controlled separately from the Vbl selectors of other sensing circuits.

[0084] During sensing, sensing node 171 is charged up to an initial voltage Vsense_init (such as 3V). The sensing node is then passed to a bitline via transistor 55, and the amount of decay of the sensing node is used to determine whether the memory cell is in a conductive or non-conductive state. The amount of decay of the sensing node also indicates whether the current Icell in the memory cell exceeds a reference current Iref. If Icell <= Iref, the memory cell is in a conductive state; if Icell > Iref, the memory cell is in a non-conductive state.

[0085] Specifically, comparator circuit 175 determines the attenuation amount by comparing the sense node voltage with the trip voltage during sensing. If the sense node voltage attenuates below the trip voltage Vtrip, the memory cell is in a conductive state and its Vth is at or below the verification voltage. If the sense node voltage does not attenuate below Vtrip, the memory cell is in a non-conductive state and its Vth is above the verification voltage. For example, comparator circuit 175 sets sense node latch 172 to 0 or 1 based on whether the memory cell is in a conductive or non-conductive state. Data in the sense node latch can be read by processor 192 and used to update bits in trip latch 174. Subsequently, for the next programming cycle, the processor can use the bits in the trip latch and the allocated data state in latches 194-197 to determine whether the memory cell and NAND string are selected for or not selected for programming in the programming cycle, thereby passing the appropriate enable or suppress bit line voltage to the bit line respectively. Latches 194-197 can be considered as data latches or user data latches because they store the data to be programmed into the memory cell.

[0086] The management circuitry 190 includes a processor 192, four exemplary data latches 194-197 for the sensing circuits 60-63 respectively, and an I / O interface 196 coupled between the data latch groups and the data bus 120. Each sensing circuit may be provided with a set of three data latches, for example, including individual latches LDL, MDL, and UDL. In some cases, different numbers of data latches may be used. In a three-bit implementation per unit, the LDL stores bits for the next page of data, the MDL stores bits for intermediate page data, and the UDL stores bits for the previous page of data.

[0087] Processor 192 performs calculations to determine the data stored in the sensed memory cells and stores the determined data in the set of data latches. Each set of data latches 194-197 stores data bits determined by processor 192 during a read operation and data bits imported from data bus 120 during a programming operation; these data bits represent write data to be programmed into memory. I / O interface 196 provides an interface between data latches 194-197 and data bus 120.

[0088] During a read operation, the system operates under the control of state machine 112, which controls the supply of different control gate voltages to the addressed memory cell. As it progresses through various predefined control gate voltages corresponding to different memory states supported by the memory, a sensing circuit can trip at one of these voltages, and the corresponding output is provided from the sensing circuit to the processor 192 via data bus 176. The processor 192 then determines the resulting memory state by considering the tripping event of the sensing circuit and information about the control gate voltages applied via input line 193 from the state machine. It then calculates the binary code of the memory state and stores the resulting data bits in data latches 194-197.

[0089] Some specific implementations may include multiple processors 192. In one implementation, each processor 192 will include output lines (not shown) such that each output line is connected via a wire or line connection. A wire or line connection or line connection can be provided by connecting multiple lines together at a node, where each line carries a high or low input signal from the corresponding processor, and the node's output is high if any of the input signals is high. In some implementations, the output lines are inverted before being connected to the wire or line. This configuration allows for rapid determination of when the programming process is complete during programming verification testing, as the state machine receiving the wire or line can determine when all programmed bits have reached the desired level. For example, when each bit reaches its desired level, a logic zero for that bit is sent to the wire or line (or data one is inverted). When all bits output data 0 (or data one is inverted), the state machine knows to terminate the programming process. Because each processor communicates with eight sensing circuits, the state machine needs to read the wire or line eight times, or logic can be added to the processor 192 to accumulate the results of the relevant bit lines, so that the state machine only needs to read the wire or line once. Similarly, by correctly selecting the logic level, the global state machine can detect when the first bit changes its state and adjust the algorithm accordingly.

[0090] During the programming or verification operation of a memory cell, the data to be programmed (written data) is stored in data latch groups 194-197 from the data bus 120. During reprogramming, the corresponding set of data latches for the memory cell can store data indicating when the memory cell can be reprogrammed based on the programming pulse magnitude value.

[0091] Under the control of the state machine, the programming operation applies a series of programming voltage pulses to the control gate of the addressed memory cell. The amplitude of each voltage pulse can be incrementally increased by one step from the previous programming pulse during the process, a process known as incremental step pulse programming. Each programming voltage is followed by a verification operation to determine whether the memory cell has been programmed to the desired memory state. In some cases, the processor 192 monitors the read-back memory state relative to the desired memory state. When both are consistent, the processor 192 sets the bit line to a programming-inhibited mode, such as by updating its latch. This prevents further programming of the memory cell coupled to the bit line, even if additional programming pulses are applied to its control gate.

[0092] Each set of data latches 194-197 can be implemented as a stack of data latches for each sensing circuit. In one embodiment, each sensing circuit 60 has three data latches. In some specific implementations, the data latches are implemented as shift registers, such that parallel data stored therein is converted into serial data on the data bus 120 and vice versa. All data latches corresponding to read / write blocks of memory cells can be connected together to form a block shift register, thereby enabling the serial transfer of input or output data blocks. Specifically, the read / write circuit module group is adjusted such that its data latch group shifts data sequentially into or out of the data bus as if they were part of a shift register for the entire read / write block.

[0093] Data latches indicate when an associated memory cell has reached certain milestones in a programming operation. For example, a latch might identify when the Vth of a memory cell is below a specific verification voltage. Data latches also indicate whether a memory cell is currently storing one or more bits from a page of data. For example, an LDL latch can be used to store the next page of data. An LDL latch is toggled (e.g., from 0 to 1) when the next page bit is stored in the associated memory cell. An MDL or UDL latch is toggled for each three-bit cell when the middle or previous page bit is stored in the associated memory cell, respectively. This occurs when the associated memory cell has completed programming.

[0094] Figure 3 It shows Figure 1A An exemplary specific implementation of power control circuitry 115 for supplying voltage to blocks of memory cells is provided. In one approach, the circuitry shown may be repeated for each plane of the die. In this example, memory structure 126 includes a set of four blocks B0-0 to B0-3 in one plane P0, and another set of four blocks B1-0 to B1-3 in another plane P1, and... Figure 4 Consistent. Generally speaking, these blocks can be in one or more planes. Figure 1AThe line decoder 124 provides voltage to the word lines and the select gate control lines for each block via the transmission transistor 322. In one method, a separate line decoder is provided for each block. The line decoder may be provided on one side of the block, such as... Figure 8 As shown in the diagram, the line decoder provides control signals to the transfer transistors, which connect blocks to the line decoder. In one method, the transfer transistors for each block are controlled by a common control gate voltage. Therefore, all transfer transistors in a block are either on or off at a given time. If a transfer transistor is on, a voltage from the line decoder is provided to the corresponding control gate line or word line. If a transfer transistor is off, the line decoder is disconnected from the corresponding control gate line or word line, causing the voltage to float on the corresponding control gate line or word line.

[0095] For example, control gate line 312 is connected to transmission transistor groups 313-316, which are in turn connected to control gate lines B1-0 to B1-3, respectively. Control gate line 317 is connected to transmission transistor groups 318-321, which are in turn connected to control gate lines B0-0 to B0-3, respectively.

[0096] Typically, programming or reading operations are performed on a selected block at a time within a block. Erasing operations can be performed on a selected block or a sub-block. The line decoder connects global control line 302 to local control line 303. Control lines represent conductive paths. Voltage is provided on the global control lines of many voltage drivers. Some voltage drivers can provide voltage to switch 350 connected to the global control line. Control transfer transistor 324 is used to transfer voltage from the voltage driver to switch 350.

[0097] Multiple voltage drivers connected to the transmission transistor can be provided. For example, the selected data word line driver WL_sel driver 347 provides a voltage signal on the selected data word line during programming or read operations. The WL_adj. driver 348 provides a voltage signal on unselected data word lines adjacent to the selected word line WLn. These unselected data word lines include the drain-side adjacent word line WLn+1 and the source-side adjacent word line WLn-1. In one option, the voltage driver for WLn+1 is separate from the voltage driver for WLn-1. Separate voltage drivers can also be provided for, for example, WLn+2 and / or WLn-2, ​​as well as for other word lines. The WL_non-adj. driver 348a provides a voltage signal on unselected data word lines not adjacent to the selected word line WLn. These are non-adjacent word lines of the selected word line, and when there are 96 word lines, they can include, for example, WL0 to WLn-2 and WLn+2 to WL95.

[0098] A dummy word line driver is also provided. The WLDD driver 349 provides a voltage signal on the drain-side dummy word line WLDD, and the WLDS driver 349a provides a voltage signal on the source-side dummy word line WLDS.

[0099] In one example, the voltage driver may also include an SGS driver 345 common to the different sub-blocks within the block. This driver provides a voltage signal to a control line connected to the control gate of the SGS transistor (source-side selected gate transistor). In another option, a separate SGS driver is provided for each sub-block.

[0100] The voltage driver may also include an SGD_sel driver 346 for SGD transistors of selected sub-blocks of the block involved in operation, and an SGD_unsel driver 346a for SGD transistors of unselected sub-blocks of the block. Alternatively, a separate SGD driver may be provided for each sub-block. The SGD driver provides voltage to a control line connected to the control gate of the SGD transistor (drain-side selected gate transistor).

[0101] Various components, including the line decoder, can receive commands from a controller, such as state machine 112 or controller 122, to perform the functions described herein.

[0102] The p-well voltage driver 330 provides a voltage Vp-well to the p+ contact 524 in the p-well region 592, for example, via conductive path 524a. See also Figure 5 In one approach, the p-well region 592 is common to a set of blocks. These blocks also share a set of bit lines 342. A source line voltage driver (referred to as CELSRC driver 331) provides a voltage Vcelsrc to the source terminals of the NAND string. For example, this can be achieved via, for instance, via... Figure 5 The local interconnect 523a in the p well region provides Vcelsrc to the n+ contact 523 in the p well region 592.

[0103] Bit line voltage driver 340 includes a voltage source that supplies voltage to bit line 342. The bit line voltage used for sensing may be, for example, 0.5V.

[0104] Figure 4 This is a perspective view of an exemplary memory die 400, wherein blocks are disposed in corresponding planes P0 and P1, and... Figure 3Consistent. The memory die includes a substrate 401, an intermediate region 402 in which memory cell blocks are formed, and an upper region 403 in which one or more upper metal layers are patterned to form bit lines. Planes P0 and P1 represent corresponding isolation regions formed in the substrate 401. Additionally, a first block sequence 405 (labeled B0-0 to B0-n-1) of n blocks is formed in P0, and a second block sequence 415 (labeled B1-0 to B1-n-1) of n blocks is formed in P1. Each plane may have associated row and column control circuitry, such as... Figure 1A The row decoder 124, the read / write circuit 128, and the column decoder 132.

[0105] In one approach, control circuitry 110, which can be located in a peripheral region of the die, can be shared between planes. Each plane may have a separate set of bit lines.

[0106] By providing memory cell blocks in multiple planes, parallel operations can be performed in the planes. For example, blocks in different planes can be erased simultaneously.

[0107] The substrate 401 may also carry circuitry below the block, as well as one or more lower metal layers that are patterned in the conductive path to carry signals of the circuitry.

[0108] In this example, memory cells are formed in vertical NAND strings within a block, and... Figure 5 Consistent. Each block comprises a stacked area of ​​memory cells, where alternating stacked layers represent word lines. In one possible approach, each block has opposing layered sides from which vertical contacts extend upwards to an upper metal layer to form connections with conductive paths. While two planes are shown as an example, other examples may use four or more planes. One plane per die is also possible.

[0109] While the examples above relate to 3D memory devices with vertically extending NAND strings, the techniques presented herein are also applicable to 2D memory devices in which the NAND strings extend horizontally on a substrate. Figure 9 Consistent.

[0110] Figure 5 It shows Figure 4An exemplary cross-sectional view of block B0-0, including a portion of NAND string 700n. The block comprises a stack 500 of alternating conductive layers (e.g., select gate layer and word line layer) and dielectric layers. These layers may be rectangular plates having a height in the z-direction, a width in the y-direction, and a length in the x-direction. Exemplary conductive layers include SGS, WLDS, WL0, WL1, WL2...WLn-1, WLn, WLn+1...WL94, WL95, WLDD, and SGD. WLn represents a selected word line used for read or program operations. The dielectric layers are shown by a dotted pattern and include an exemplary dielectric layer DL. The conductive layers extend within memory vias MH (see also...). Figure 6 ).

[0111] The stack is described as comprising one, but optionally one or more, alternating conductive and dielectric layers. See, for example, [link to relevant documentation]. Figure 7 The stack consists of a bottom layer (BT) and a top layer (TT). The stack comprises a set of alternating conductive and dielectric layers, in which memory holes are formed during the manufacturing process.

[0112] In addition to the 96 data word lines in this example, the conductive layers include SGS, WLDS, WL0-WL95, WLDD, and SGD(0), although the number of data word lines may be greater than or less than 96.

[0113] The conductive layer connected to the control gate of a memory cell is called a word line, and the conductive layers connected to the control gates of the source-side select-gate transistor and the drain-side select-gate transistor are called source-side control lines and drain-side control lines, respectively. WLDS and WLDD are dummy word lines or conductive layers connected to dummy memory cells. A dummy memory cell can have the same structure as a data memory cell, but the controller considers that the memory cell unqualified to store any type of data, including user data. One or more dummy memory cells can be provided at the drain and / or source terminals of the NAND string of the memory cell to provide a gradual transition of the channel voltage gradient. WL0-WL95 are data word lines connected to the data memory cell, which are qualified to store user data.

[0114] The top 510t and bottom 510b of the stack are shown. WL95 is the topmost data word line, and WL0 is the bottommost data word line.

[0115] NAND strings are formed by etching memory vias in a stack and then depositing multiple thin layers of material along the sidewalls of the memory vias. Memory cells are formed in regions where word lines intersect with the multiple thin layers, and select gate transistors are formed in regions where SGS and SGD control lines intersect with the multiple thin layers. For example, drain-side select gate transistor 516 is formed at the intersection of the SGD control line and the multiple thin layers, source-side select gate transistor 501 is formed at the intersection of the SGS control line and the multiple thin layers, and selected memory cell 514 is formed at the intersection of WLn and the multiple thin layers.

[0116] These multiple thin annular layers can be deposited, for example, using atomic layer deposition. These layers may include, for example, a barrier oxide layer 563, a charge trapping layer 564 or film (such as silicon nitride (Si3N4) or other nitrides), a tunnel layer 565 (e.g., gate oxide), and a channel layer 566 (e.g., comprising polysilicon). A dielectric core 593 (e.g., comprising silicon dioxide) may also be provided. In this example, all layers are disposed within memory vias. In other methods, some of the layers may be disposed within word line or control line layers. The multiple thin layers form columnar active regions of the NAND string. The word lines or control lines may contain metals, such as tungsten.

[0117] Stacked on substrate 401. In one method, the substrate includes a p-well region 592 connected to the source end of the NAND string (see also...). Figure 3 The p-well region may include an epitaxial region 592a that extends upward adjacent to the SGS layer. The p-well region may include an n+ contact 523 connected to a local interconnect 523a (conductive path or source line) to receive Vcelsrc, and a p+ contact 524 connected to a conductive path 524a to receive Vp-well. The local interconnect and conductive path may contain a conductive material, such as a metal surrounded by an insulating material, to prevent conduction with the metal of adjacent word lines. In one possible embodiment, the p-well region 592 may be formed in an n-well 591, which in turn is formed in a p-type semiconductor region 520 of the substrate.

[0118] The NAND string 700n has a source end 500s connected to the p-well at the bottom 510b of the stack 500. The NAND string 500n also has a drain end 500d connected to the bit line BL0 via a bit line contact 540 containing n-type material at the top 510t of the stack.

[0119] NAND strings using this 3D configuration are considered to have floating channels because the length of the channels is not formed on the substrate.

[0120] When a memory cell is programmed, electrons are stored in a portion of the charge trapping layer associated with the memory cell. These electrons are attracted from the channel into the charge trapping layer and then through the tunnel layer. The Vth of the memory cell increases proportionally to the amount of charge stored. During an erase operation, the channel of the NAND string is charged, such as by applying a positive erase pulse to the substrate, causing electrons to return from the charge trapping layer to the channel.

[0121] Figure 6 It shows Figure 5 An exemplary cross-sectional view of the block portion in the xy plane at the WLn level is shown. The layers of the NAND string 700n are shown, including a barrier oxide layer 563, a charge trapping layer 564, a tunnel layer 565, and a channel layer 566. A dielectric core 593 is also shown.

[0122] Figure 7 It shows Figure 4 Another exemplary cross-sectional view of block B0-0, including a portion of NAND string 600n, where the block comprises two layers. Element numbered similarly corresponds to... Figure 5 The components in the array. Multilayer stacks can be taller and have more layers than single-layer stacks, which is limited by the ability to accurately etch memory vias through multiple layers. In a multilayer stack, a bottom layer is formed and memory vias are etched. A top layer is then formed on the bottom layer, and memory vias aligned with the memory vias in the bottom layer are etched in the top layer, thus forming a continuous array of memory vias extending through both layers. Two or more layers can be used. The top of the memory vias in the first layer tends to be widened in the IF to form a base for alignment with memory vias formed later in the top layer. A NAND string 600n is formed, which includes a barrier oxide layer 663, a charge trapping layer 664, a tunnel layer 665, a channel layer 666, and a dielectric core 693.

[0123] In this example, the block comprises a stack of alternating conductive and dielectric layers in two layers (a bottom layer BT and a top layer TT). Interface (IF) regions formed of dielectric material separate the layers. Word lines include, for example, WL0 to WLIF-1 in BT and WLIF+1 to WL95 in TT, where WLIF-1 is a word line adjacent to and below the IF, and WLIF+1 is a word line adjacent to and above the IF. Optionally, word lines adjacent to the IF are assigned as dummy word lines.

[0124] Additionally, the height of the IF layer is greater than the height of the remaining dielectric layers between word lines. Therefore, there is reduced conductivity in the interface, making it more difficult for electrons to move through. This configuration can make memory cells in the top or bottom layers more susceptible to read interference. In some cases, the location of the memory cell within the layer (e.g., the location of the selected word line) affects the risk of interference.

[0125] Figure 8 It shows Figure 4 An exemplary view of block B0-0 and its associated bit lines and sensing circuitry, wherein the corresponding NAND strings are arranged in sub-blocks. The NAND strings are arranged in a 3D configuration within the sub-blocks of the block. This block is related to... Figures 5 to 7 Consistent. Each sub-block SB0-SB3 includes multiple NAND strings. Three exemplary NAND strings are shown for simplification. For example, SB0 includes NAND strings 700n, 700n1, and 700n2, SB1 includes NAND strings 710n, 710n1, and 710n2, SB2 includes NAND strings 720n, 720n1, and 720n2, and SB3 includes NAND strings 730n, 730n1, and 730n2. The NAND strings have data word lines, dummy word lines, and select gate lines. Each sub-block includes a set of NAND strings that extend in the x-direction and have a common SGD line or control gate layer. Specifically, SGD(0)-SGD(3) are located in SB0-SB3, respectively.

[0126] Block programming can be performed based on word line programming order. One option is to program memory cells in different word line portions within different sub-blocks, one sub-block at a time, before programming memory cells in the next word line. For example, this could involve programming WL0 in SB0, SB1, SB2, and SB3, then programming WL1 in SB0, SB1, SB2, and SB3, and so on. For example, the word line programming order could start with WL0 (source extreme word line) and end with WL95 (drain extreme word line).

[0127] A read can occur for a memory cell connected to a selected word line within a selected subblock. Reads can occur one subblock at a time.

[0128] In an erase operation, the entire block is usually erased, but partial erasure is also possible.

[0129] In this example, each NAND string includes multiple memory cells between SGS transistors and SGD transistors. In other examples, more than one SGD transistor and / or SGS transistor may be provided for each NAND string. The number of dummy memory cells can also vary. For example, NAND string 700n includes SGS transistor 701, dummy memory cells 702, data memory cells 703-710, dummy memory cells 711, and SGD transistor 712. NAND string 710n includes SGS transistor 721, dummy memory cells 722, data memory cells 723-730, dummy memory cells 731, and SGD transistor 732. NAND string 720n includes SGS transistor 741, dummy memory cells 742, data memory cells 743-750, dummy memory cells 751, and SGD transistor 752. The NAND string 730n includes an SGS transistor 761, a dummy memory cell 762, data memory cells 763-770, a dummy memory cell 771, and an SGD transistor 772.

[0130] This example illustrates one SGD transistor at the drain terminal of each NAND string and one SGS transistor at the source terminal of each NAND string. In one approach, the SGD transistors in SB0, SB1, SB2, and SB3 can be driven by separate control lines SGD(0), SGD(1), SGD(2), and SGD(3), respectively. In another approach, multiple SGD and / or SGS transistors can be provided in the NAND string.

[0131] A set of bit lines, including exemplary bit lines BL0-BL2, are connected to NAND strings. Each bit line is connected to a corresponding set of NAND strings, including one NAND string in each sub-block. For example, BL0 is connected to NAND strings 700n, 710n, 720n, and 730n in SB0-SB3, respectively; BL1 is connected to NAND strings 700n1, 710n1, 720n1, and 730n1 in SB0-SB3, respectively; and BL2 is connected to NAND strings 700n2, 710n2, 720n2, and 730n2 in SB0-SB3, respectively. Each bit line is also connected to a corresponding sensing circuit, and... Figure 2 The sensing circuits are identical. For example, BL0-BL2 are connected to sensing circuits 60-62 respectively.

[0132] In this example, the line decoder 124 is located on one side of the block, in the peripheral region of the substrate, and... Figure 4The control circuit 110 shown is consistent with this. The line decoder routes the voltage signal to the word line via conductive path 810. In one approach, the conductive path extends vertically to the upper region 403 in the z-direction, then horizontally in the y-direction, and then vertically downward in the -z-direction through-holes contacting the word line. The sides of the block may have a stepped shape, where the through-holes contact the edge of each word line. In this example, it is assumed that the stepped shape is closest to SB0. Therefore, the RC delay of the word line voltage signal will be minimal for SB0 and maximum for SB3. The distance between the line decoder and the sub-block is assumed to gradually increase from SB0 to SB3.

[0133] Figure 9 An exemplary NAND string in a 2D configuration is shown. The techniques discussed herein can be used in both 2D memory devices and the aforementioned 3D memory devices. In the 2D memory device, the channels extend horizontally in the substrate rather than in a vertically extending channel layer. In this example, substrate 900 includes a p-well 903 located within an n-well 902, which in turn is located in a p-substrate 901. Vp-well and Vcelsrc are provided to the p-well via contacts 910 and 911, respectively. A NAND string 919 is disposed on the substrate and includes a select gate transistor and memory cells. For example, the NAND string includes an SGS transistor 920, memory cells 921, 922, and 923 connected to WLDS, WL0, and WL1, memory cells 924, 925, and 926 connected to WLn-1, WLn, and WLn+1, memory cells 927 and 928 connected to WL95 and WLDD, and an SGD transistor 929. The doped regions in the substrate (e.g., doped regions 911-917) serve as the source and drain of the transistor. Vbl is supplied to the doped regions 917. When an appropriate voltage is supplied to the NAND string, an inversion layer or channel 940 is formed in the p-well. The remainder 903a of the p-well is biased with Vp-well.

[0134] An exemplary memory cell 924 includes a tunnel layer 930, a floating gate layer 931, a barrier oxide layer 932, and a control gate 933.

[0135] Figure 10 The threshold voltage (Vth) distribution of an eight-state memory device is shown. As an example, eight data states, or three bits per cell, are shown. The techniques described herein can be applied to other modes, including one or more bits per cell. The vertical axis depicts the number of memory cells on a logarithmic scale, and the horizontal axis depicts the threshold voltage on a linear scale. The Vth distribution can represent all memory cells connected to a word line or in a block. After erasing the block, a Vth distribution 1000 representing the erase state is obtained. The erase operation is complete when the Vth of all or nearly all memory cells is below the verification voltage VvEr.

[0136] The memory cells then undergo programming operations. Each memory cell will have an assigned data state. Some memory cells are assigned to an erase state and are not programmed. In this example, most memory cells are programmed to higher states, such as AF, which are represented by Vth distributions 1001-1007 respectively. These memory cells undergo verification testing using verification voltages VvA-VvG.

[0137] In a read operation, memory cells are read by applying read voltages VrA-VrG to selected word lines. In one method, one page of data is read at a time. For example, VrA and VrE can be used to read the lower page data (and...). Figure 13A (Consistent), VrB, VrD, and VrF can be used to read intermediate page data, and VrC and VrG can be used to read upper page data.

[0138] The widened Vth distribution 1000a used for erase states represents a memory cell that has experienced read disturbances as described herein. Read disturbances increase the upward tail of the Vth distribution, especially for erase-state memory cells, but may also affect other states. Some erase-state memory cells may have their Vth increased to above VrA and will be incorrectly read as being in state A, or even a state higher than A.

[0139] Figures 11A to 11C A graph showing the channel voltage Vch relative to its position along the length of the NAND string is provided. The position along the length of the NAND string is represented by the source-side select gate (SGS), word lines WLDS-WLDD, and drain-side select gate (SGD). The on / off states or voltages of the select gate transistors and word lines are also shown. This applies to unselected NAND strings during read operations on selected NAND strings, where the two NAND strings share a common set of word lines. The selected NAND string may be located in a selected sub-block, while the unselected NAND string is located in an unselected sub-block.

[0140] Figure 11A An example of the channel voltage in an unselected NAND string is shown during the pre-charge phase of a read operation, when the SGD and SGS transistors are turned on and positive biases Vbl and Vcelsrc are applied to the drain and source terminals of the NAND string, respectively.

[0141] Channel voltage corresponds to Figure 13AThe time t3 in the process. As mentioned, the goal of the precharge phase is to increase the channel voltage of the unselected NAND string to reduce the possibility of read interference of the weak Fowler-Nordheim (FN) tunneling type. During this phase, the SGS transistor is turned on, as indicated by SGS(on). The select gate transistor or memory cell transistor is turned on or off when it is in a conductive or non-conductive state, respectively. Turning on the transistor means changing it from the off state to the on (conductive) state, and turning off the transistor means changing it from the on state to the off (non-conductive) state. Turning on or off can be achieved by changing the control gate voltage.

[0142] The SGD transistor is turned on, as indicated by SGD(on). Memory cells connected to WLDS to WLn-2 and WLn+2 to WLDD are also turned on because Vread is applied to these word lines. Vread is the nominal read pass voltage, such as 8-9V, which is high enough to provide the associated memory cell in a strongly conductive state. Memory cells connected to WLn-1 and WLn+1 are also turned on because VreadK is applied to these word lines. VreadK is higher than Vread and high enough to provide the associated memory cell in a strongly conductive state. VreadK can be applied to adjacent word lines of WLn to provide sufficient enhancement to the channel region adjacent to WLn, where WLn receives a voltage lower than the read pass voltage.

[0143] WLn receives a voltage signal that spikes upwards to level Vspike1, causing an unselected memory cell to be briefly turned on or provided in a conductive state, provided that Vspike > Vth for that memory cell. Vspike1 is sufficient to turn on a memory cell in, for example, an erase state or other low state, and is high enough to be in the highest state (e.g., Figure 10 The memory cell in the G state is turned on.

[0144] When the SGS transistor is turned on and a positive voltage Vcelsrc1 (e.g., 1-2V) is applied to the source terminal of the NAND string (such as at the substrate), the channel voltage will be equal to Vcelsrc1 for the channel region adjacent to SGS to WLn-1 (curve 1101). When the SGD transistor is turned on and a positive voltage Vbl (e.g., 1-2V) is applied to the drain terminal of the NAND string (at the bit line), the channel voltage will be equal to Vbl + Vcelsrc1 for the channel region adjacent to WLn+1 to SGD (curve 1103). A relatively small channel gradient is formed in the channel region adjacent to WLn (curve 1102). When the SGD and SGS transistors are turned on, this channel gradient is unlikely to cause interference in this part of the precharge phase of the read operation.

[0145] Figure 11BThis illustrates the situation during the pre-charge phase of a read operation, where the SGD and SGS transistors are turned off, causing channel gradients in memory cells within the NAND string to be disturbed. Figure 11A An example of the channel voltage in an unselected NAND string. The channel voltage corresponds to... Figure 13A The time t7 in the middle. And Figure 11A The difference is that the memory cell of WLn is turned off due to (e.g., 0V applied to WLn), and the SGD transistor is turned off due to (e.g., 0V applied to the SGD line). The SGS transistor remains on, and Vcelsrc1 continues on the source line, such that for the channel region adjacent to SGS to WLn-1, the channel voltage will continue to be equal to Vcelsrc1 (curve 1101). However, because the memory cell of WLn and the SGD transistor are turned off, the channel region from WLn+1 to SGD is boosted to a voltage higher than... Figure 11A The level Vboost in Vbl+Vcelsrc (curve 1103a) is caused by the capacitive coupling between the unselected word line and the channel, because the voltage signal of the unselected word line is... Figure 13A The Vread increases to t5-t7. Figure 13A In the example, the voltage signal of the unselected word line increases from Vcutoff to Vread at t5-t7, while the memory cell of WLn and the SGD transistor are turned off.

[0146] Figure 11B Two options for the voltages on WLn-1 and WLn+1 are shown. In the first option, VreadK is applied. This results in a channel gradient of curve 1103 between WLn-1 and WLn, and a channel gradient of curve 1102a between WLn and WLn+1. The larger channel gradient of curve 1102 may interfere with the memory cells of WLn+1 due to electron injection.

[0147] In the second option providing read interference countermeasures, Vread_low1 is applied to WLn-1 and WLn+1. Figure 13A In this context, Vread_low1 is lower than Vread or VreadK, and also lower than Vspike2. This results in a channel gradient for curve 1103a between WLn-1 and WLn, and a channel gradient for curve 1102b between WLn and WLn+1. The channel gradient of curve 1102b is smaller than that of curve 1102a (because the former has a smaller slope), which advantageously reduces the risk of interference. In particular, before increasing Vboost in the channel region adjacent to WLn+2 to SGD, Vch is at level Vboost1 for the channel region adjacent to WLn+1.

[0148] The slope of curve 1102b indicates the strength of the electric field that generates electrons. As the slope decreases, the number of electrons decreases. Furthermore, by applying a reduced voltage to WLn+1, the attraction that draws electrons in the channel to the charge trapping layer is reduced. Therefore, the risk of interference is reduced for memory cells connected to WLn+1. Typically, the timing and magnitude of the voltage signal can be optimized based on a trade-off between read performance (e.g., read time) and read interference (e.g., as measured by the number of read errors).

[0149] Similarly, the channel gradient of curve 1103a is smaller than that of curve 1103, which also helps to reduce the risk of interference for memory cells connected to WLn-1.

[0150] Figure 11C This illustrates the situation during the pre-charge phase of a read operation, where the SGD and SGS transistors are turned off, causing channel gradients in memory cells within the NAND string to be disturbed. Figure 11A Another example of the channel voltage in an unselected NAND string. The channel voltage corresponds to... Figure 13A The time t7 in the middle. And Figure 11B The difference is that WLn-2 and WLn+2 include options for voltage Vread_low2 instead of Vread or VreadK. Figure 13A In this context, Vread_low2 is greater than Vread_low1 and lower than Vread, VreadK, or Vspike2. In the first option, Vread is applied to WLn-2 and WLn+2. This results in the channel gradient of curve 1103 between WLn-1 and WLn, and the channel gradient of curve 1102a between WLn and WLn+1, as combined with... Figure 11B The subject of discussion.

[0151] In the second option providing read interference countermeasures, Vread_low2 is applied to WLn-2 and WLn+2, while Vread_low1 is applied to WLn-1 and WLn+1. This results in a channel gradient for curve 1103b between WLn-2 and WLn, and a channel gradient for curve 1102c between WLn and WLn+2. The risk of interference is advantageously reduced for both memory cells of WLn+1 and WLn+2. Specifically, Vch is at level Vboost1 for the channel region adjacent to WLn+3 to SGD before increasing Vboost, and at level Vboost2 for the channel region adjacent to WLn+2.

[0152] Due to the SGD transistor being off, the read interference risk for memory cells on the drain side of WLn is generally greater than that for memory cells on the source side of WLn. Furthermore, on the drain side of WLn, the read interference risk gradually decreases for memory cells moving further away from WLn. For example, the risk is highest for memory cell WLn+1, followed by WLn+2, and so on. Therefore, read interference countermeasures can be implemented with an intensity proportional to the read interference risk, where a higher intensity corresponds to a lower voltage Vread_low. When, for example, the voltage on WLn+1 is... Figure 13A When Vread_low1 is set from t5-t7, capacitive coupling is avoided for the associated channel region because the voltage does not increase after the SGD transistor is turned off. Figure 11B and Figure 11C The read interference countermeasures shown can be further understood in conjunction with the flowcharts discussed below.

[0153] Figures 11A to 11C The NAND string in the text refers to the unselected NAND string in a read operation involving a selected NAND string. For example, in... Figure 8 In this context, assume that the NAND string in SB0 is the selected NAND string in the selected sub-block, and the NAND strings in SB1-SB3 are the unselected NAND strings in the unselected sub-block. Furthermore, assume... Figures 11A to 11C The NAND string in SB1 is the unselected NAND string 710n, and the NAND string 700n in SB0 is an example of the selected NAND string.

[0154] The unselected NAND string 710n includes memory cells 725-729 connected to WLn-2 through WLn+2, respectively. Memory cell 727 is an unselected memory cell connected to the selected word line WLn. Memory cell 728 is a drain-side adjacent memory cell of the unselected memory cell 727, and WLn+1 is a drain-side adjacent word line of WLn. Memory cell 729 is an additional drain-side non-adjacent memory cell of the unselected memory cell 727, and WLn+2 is an additional drain-side non-adjacent word line of WLn. Similarly, memory cell 726 is a source-side adjacent memory cell of the unselected memory cell 727, and WLn-1 is a source-side adjacent word line of WLn. Memory cell 725 is an additional source-side non-adjacent memory cell of the unselected memory cell 727, and WLn-2 is an additional source-side non-adjacent word line of WLn.

[0155] WLn+1 and WLn-1 are adjacent word lines of WLn, and WL0 to WLn-2 and WLn+2 to WL95 are non-adjacent word lines of WLn. WL0 to WLn-2 are source-side non-adjacent word lines of WLn, and WLn+2 to WL95 are drain-side non-adjacent word lines of WLn. Similarly, memory cells connected to WLn+1 and WLn-1 are adjacent memory cells connected to memory cells of WLn, and memory cells connected to WL0 to WLn-2 and WLn+2 to WL95 are non-adjacent memory cells connected to memory cells of WLn.

[0156] In the unselected NAND string 710n, memory cell 728 is most susceptible to read interference, and memory cell 729 is the second most susceptible. Figure 11B and Figure 11C Consistent. Similarly, among the other unselected NAND strings 710n1 and 710n2 in SB1, the memory cell connected to WLn+1 is most susceptible to read interference. The above discussion regarding the unselected NAND strings in SB1 also applies to the unselected NAND strings in SB2 and SB3, which are also susceptible to read interference.

[0157] During a read operation, a selected memory cell 707 in a selected NAND string 700n is read. Memory cells in other selected NAND strings of SB0, such as NAND strings 700n1 and 700n2, can also be read simultaneously.

[0158] Figure 12A A flowchart is shown, which illustrates the relationship between... Figure 11B and Figure 11C An overview of a consistent exemplary process for reducing interference during read operations. Step 1200 initiates a read operation on selected memory cells in selected NAND strings within a set of NAND strings. For example, the selected NAND strings may be located in selected sub-blocks, and the set of NAND strings may be located in a block. The selected memory cells may be connected to selected word lines. Step 1201 performs a precharge phase that reduces the likelihood of read interference occurring in unselected memory cells within unselected NAND strings in the set of NAND strings. For example, unselected NAND strings may be located in unselected sub-blocks. Figure 13A Examples of voltage signals during the precharge phase are provided in t0-t9. Step 1202 performs a sensing phase that senses selected memory cells relative to the read voltage. For example, the read voltage may be connected to a selected word line. Figure 13A Examples of voltage signals during the sensing phase are provided in t9-t15.

[0159] Step 1203 determines whether a next read voltage needs to be applied during the sensing phase. If this determination step is true, the next read voltage is applied in step 1202. If this determination step is false, a read operation is performed at step 1204.

[0160] Figure 12B A flowchart is shown, in which... Figure 12A Exemplary details of the precharge phase of step 1201. Step 1210 is the precharge phase for performing the read operation. Step 1211 includes applying a voltage signal to a non-adjacent word line of the selected word line, which increases from an initial (off) level to the nominal read pass level Vread and is maintained at Vread. For example, see... Figure 13A The curves 1310 and 1311, from t0 to t7, illustrate the voltage signal increasing from 0V to Vread. Step 1212 involves applying a voltage signal to a selected word line, which increases from an initial (off) level to a peak (on) level and then decreases to a reduced (off) level. See, for example, [link to relevant documentation]. Figure 13A Curve 1301 in the diagram shows the voltage signal increasing from 0V to Vspike1 during t0-t3, and then decreasing from Vspike1 back to 0V during t3-t6. Additionally, the memory cell is conductive when the word line voltage exceeds the on / off level of t1-t5, and is non-conductive from t0-t1 and t5-t6.

[0161] Step 1213 includes applying a voltage signal to adjacent word lines of the selected word line, the voltage signal increasing from an initial (off) level to a peak (on) level, and then decreasing to a lower (positive) level. See, for example, [link to relevant documentation]. Figure 13A In curve 1310, spanning t0-t3, it increases from 0V to Vspike2, and see curve 1314, it decreases from Vspike2 to Vread_low1. Step 1213 can be implemented using various options. For example, step 1213a includes applying a voltage signal to the adjacent word line (WLn+1) on the drain side but not to the adjacent word line (WLn-1) on the source side. Step 1213b includes applying this voltage signal to a group of multiple word lines (e.g., WLn+1 and WLn+2) adjacent to the selected word line. Step 1213c includes the option to set the reduced level (Vread_low) of the voltage signal applied to the adjacent word lines as a function of temperature or other interference risks. See also Figure 14A and Figure 14B .

[0162] Step 1214 includes applying a voltage signal to the SGD transistor of the unselected NAND string, the voltage signal increasing from an initial (off) level to a peak (on) level, and then decreasing to a lowered (off) level. See, for example, [link to relevant documentation]. Figure 13ACurve 1322 shows that V increases from 0V to Vspike3 during t0-t3, and curve 1323 shows that for Vsgd_unsel, it decreases from Vspike3 to 0V during t3-t6. Additionally, the SGD transistor conducts when the word line voltage exceeds the on / off level of t1-t5, and is non-conductive from t0-t1 and t5-t6.

[0163] Step 1215 includes applying a voltage signal to the SGD transistors of the selected NAND string, the voltage signal increasing from an initial (off) level to a peak (on) level, and maintaining at that peak level. See, for example, [link to relevant documentation]. Figure 13A Curve 1322 for Vsgd_sel shows, for example, an increase from 0V to 6V from t0 to t4, and curve 1320 shows a hold at 6V. The SGD transistor conducts when the word line voltage exceeds the on / off level from t1 to t14, and is non-conductive from t0 to t1.

[0164] Step 1216 includes applying a voltage signal to the SGS transistors of the selected and unselected NAND strings, the voltage signal increasing from an initial (off) level to a peak (on) level and maintaining at that peak level. See, for example, [link to relevant documentation]. Figure 13A The curve 1322 for Vsgs shows, for example, that increases from 0V to 6V from t0 to t4, and curve 1320 shows that it remains at 6V. The SGS transistor conducts when the word line voltage exceeds the on / off level from t1 to t14, and is non-conductive from t0 to t1.

[0165] Steps 1212 to 1216 may occur when the voltage signal applied to the non-adjacent word line is increased in step 1211.

[0166] Figure 12C A flowchart is shown, in which... Figure 12A Exemplary details of the sensing phase of step 1202. Step 1220 initiates the sensing phase of the read operation. Step 1221 includes maintaining the voltage signal applied to the non-adjacent word line of the selected word line at the nominal read pass level Vread. See, for example, curves 1312 and 1313 at t9-t15. Step 1222 includes transitioning the voltage signal applied to the selected word line from its decreasing level to the read voltage. See, for example, curves 1302-1304 at t9-t15, which increases from 0V to VrA and then to VrE. Step 1223 includes increasing the voltage signal applied to the adjacent word line of the selected word line from its decreasing level to the read pass level VreadK. See, for example, curves 1314 and 1316, where the voltage increases from Vread_low1 to VreadK. This step includes options for voltage overshoot, such as... Figure 13B As shown in the image.

[0167] Step 1224 includes maintaining the voltage signal applied to the SGD transistor of the unselected NAND string at a reduced (off) level. For example, see curve 1321, where the voltage is maintained at 0V. Step 1225 includes maintaining the voltage signal applied to the SGD transistor of the selected NAND string at a peak (on) level. For example, see curve 1320, where the voltage is maintained at 6V. Step 1226 includes maintaining the voltage signal applied to the SGS transistor of both the selected and unselected NAND strings at a peak (on) level. For example, see curve 1320, where the voltage is maintained at 6V. Step 1227 includes sensing the selected memory cell.

[0168] Figure 13A It shows the relationship with Figures 12A to 12C Exemplary voltage signals during a consistent read operation. As mentioned, the precharge phase extends from t0 to t9, and the sensing phase extends from t9 to t15. Curves 1301-1304 illustrate, for example, for a selected word line WLn, how the voltage Vwl_sel spikes upward from 0V to a peak level Vspike1, and then decreases to 0V. This voltage then increases to a first read voltage VrA, and then to a second read voltage VrE. These voltages are exemplary read voltages used to read data pages. Sensing can occur between t12-t13 and t13-t4 when VrA and VrE are applied, respectively. See also Figure 2 Select memory cells are connected at t1-t5.

[0169] Curves 1310-1316 are used for unselected word lines. Specifically, curves 1310-1313 are used for non-adjacent word lines of WLn. For example, this could include WL0-WLn-1 and WLn+1-WL95, or WL0-WLn-2 and WLn+2-WL95. Curves 1310, 1314, and 1316 are used for adjacent word lines of WLn. For example, this could include WLn-1 and WLn+1. The voltage signal increases from 0V to Vspike2 in t0-t3, and decreases from Vspike2 to Vread_low1 in t3-t5. Then, from t9-t11, the voltage signal increases from Vread_low1 to VreadK. Curves 1310, 1315, and 1316 are used for additional non-adjacent word lines of WLn. This could include, for example, WLn-2 and WLn+2, which are two word lines far from WLn. The voltage signal increases from 0V to Vspike2 during t0-t3, and decreases from Vspike2 to Vread_low2 during t3-t4. Then, from t9-t11, the voltage signal increases from Vread_low2 to VreadK.

[0170] Curves 1322 and 1320 are for the SGD transistors of the selected NAND strings and for the SGS transistors. Curves 1322, 1323, and 1321 are for the SGD transistors of the unselected NAND strings. The unselected SGD transistors are turned on at t1 - t5. The selected SGD transistors and SGS transistors are turned on at t1 - t14.

[0171] Regarding the spiking or peak voltage in question, for example, in the case where the voltage signal reaches the levels of Vspike1 - Vspike3, the control circuit can request the voltage driver to output a first voltage, and then output a second lower voltage before reaching the first voltage to obtain this type of waveform. For example, the control circuit 130 can make such a request to the voltage driver via the interface 131. The control circuit can request the voltage driver for Vwl_sel to output a voltage greater than Vspike1 at t0 - t3. For example, this voltage greater than Vspike1 can be Vread. It takes some time for the voltage driver to ramp its output from 0V to Vread. At t3, when the output voltage is Vspike1 < Vread, such that the output voltage has not reached the requested level Vread, the control circuit can request the voltage driver to output a voltage lower than Vspike1, such as 0V. The requested outputs are VrA for t12 - t13, VrE for t13 - t14, and 0V for t14 - t15.

[0172] Again, for example, the control circuit can request the voltage driver for Vwl_unsel to output a voltage greater than Vspike2 at t0 - t3. For example, this voltage greater than Vspike2 can be Vread or VreadK. At t3, when the output voltage is Vspike2 < Vread, such that the output voltage has not reached the requested level VreadK, the control circuit can request the voltage driver to output a voltage lower than Vspike2 from t3 - t9, such as Vread_low1 (curve 1314) or Vread_low2 (curve 1315). For curves 1314 and 1315, the requested output can be VreadK for t9 - t14.

[0173] For example, the control circuit can request the voltage driver for Vsgd_unsel to output a voltage greater than Vspike3 at t0-t3. For instance, this voltage greater than Vspike3 could be 6V, i.e., the peak voltage of Vsgd_sel and Vsgs. At t3, when the output voltage is Vspike3 < 6V, the control circuit can request the voltage driver to output a voltage lower than Vspike3, such as 0V. Vspike3 can be similar to or less than Vspike1 and Vspike2. The spike voltages Vspike1-Vspike3 represent the peak voltages of the voltage signal when the voltage driver is requested to reduce its output. In one approach, the request to change the voltage driver's output can be a step change request. In another approach, when the control circuit requests a step decrease in the voltage driver's output, the peak level or spike is reached simultaneously, for example, at t3.

[0174] Curve 1330 represents the bit line voltage Vbl. This voltage signal increases from 0V to a first positive level Vbl1, such as 1.3V, between t2 and t4, and remains at the first level between t4 and t8. The voltage signal then increases from Vbl1 to Vbl2 at t8, for example, 1.5V, and remains at Vbl2 until t14. Vbl thus increases in two steps. Alternatively, Vbl can be increased in a single step.

[0175] Curve 1340 is used for the source line voltage Vcelsrc. This voltage signal increases from 0V to Vcelsrc1, such as 1.3V, from t2 to t4, and is maintained at Vcelsrc1 from t4 to t14. In one approach, the voltage signals for Vbl and Vcelsrc begin to increase, for example, at t2. Furthermore, this start time can be after the start time, for example, t0, when the voltage signals of the word line and select gate transistor begin to increase from their respective initial levels to their respective peak levels. In other words, the start of the increase in Vbl and Vcelsrc can be delayed relative to the start of the increase in the voltage signals of the word line and select gate transistor. By keeping Vcelsrc grounded from t0 to t2, the memory cell will have a larger gate-to-source voltage, which allows its voltage signal to ramp up more quickly. The increase in Vbl can be simultaneous with the increase in Vcelsrc, such that the drain and source terminals of the NAND string are simultaneously biased with positive voltages of Vbl1 and Vcelsrc1, respectively.

[0176] Figure 13A The read operation shown involves applying multiple read voltages to WLn sequentially, with these voltages gradually increasing. For example, VrA could be applied first, followed by a higher voltage, VrE. Also in this example, Vwl_sel is set to a shutdown level, such as 0V, then increased to VrA, and then to VrE. Other options are possible.

[0177] It should also be noted that when the voltage signal of adjacent word lines increases from Vread_low1 to VreadK during the sensing phase at t9-t11, this can produce something similar to Figure 11B and Figure 11C The channel gradient during the precharge phase is shown in the diagram. However, this channel gradient during the sensing phase is expected to be smaller than that during the precharge phase. One factor is the higher voltage on WLn (e.g., the read voltage such as VrA compared to 0V). Another factor is that non-adjacent word lines are fixed at Vread and do not ramp up. However, to reduce the potential channel gradient during the sensing phase, adjacent word lines can be increased to Vread instead of a higher VreadK, for example, even increased to a level below Vread. In another option, the read pass voltage can be lower on the drain-side adjacent word line than on the source-side adjacent word line, since a worse channel gradient can be located on the drain side. In any case, read interference countermeasures implemented during the precharge phase will reduce the overall likelihood of read interference.

[0178] Figure 13B It shows the relationship with Figure 12C Step 1223a is consistent with an exemplary voltage signal featuring a voltage over-kick. A voltage over-kick refers to a voltage signal intentionally driven above a target level to provide a faster ramp-up from the initial level to the target level. This technique helps save time to compensate for the potential increase in time due to read interference countermeasures when transitioning to Vread_low1 and Vread_low2. The voltage signal increases from 0V to Vspike2 and then decreases to Vread_low1, as... Figure 13A As shown. The comparison involves... Figure 13A Curve 1316 shows the voltage signal increasing from Vread_low1 to VreadK in t9-t11 without any overshoot. Curve 1317 shows the case with an overshoot, where the voltage signal increases from Vread_low1 to Vspike4 in t9-t9a, and then decreases from Vspike4 to VreadK in t9a-t9b. Therefore, the voltage signal reaches VreadK earlier by the amount in t11-t9b. Time points t9 and t11 are compared with... Figure 13A Consistent.

[0179] In one approach, the control circuitry may request the voltage driver for Vwl_unsel to output a voltage greater than Vspike4 at t9-t9a. For example, this voltage greater than Vspike4 could be Vspike4 + an increment, where Vspike4 > VreadK. At t9a, when the output voltage is Vspike4 > VreadK, the control circuitry may request the voltage driver to output VreadK.

[0180] Figure 14A The curve is shown, where... Figure 13A How does Vread_low change with temperature, and... Figure 12B This is consistent with steps 1213c. For example, this could refer to Vread_low1 and / or Vread_low2. Generally, the risk of read interference is higher at lower temperatures. That is, the risk of read interference is a decreasing function of temperature. This is because channel leakage increases and therefore channel boost decreases at lower temperatures. In one approach, read interference countermeasures are made stronger when the risk of interference is higher. For example, a stronger countermeasure can be implemented by using a lower Vread_low. Therefore, Vread_low may be lower when the temperature is lower and therefore when the risk of read interference is higher. In other words, Vread_low can be relatively low when the temperature is relatively low and the risk of read interference is relatively high.

[0181] Figure 14B The curve is shown, where... Figure 13A How does Vread_low change with the risk of interference, and... Figure 12B The steps are consistent with 1213c. As mentioned, Vread_low can be lower when the risk of read interference is high. The risk of read interference can be based on various factors present during read operations. As mentioned, one factor is temperature. Another possible factor is the location of selected word lines in the stack. Testing the memory device can reveal a higher risk of read interference at certain locations of selected word lines. For example, a higher number of read errors can indicate a higher risk of read interference. Figure 7 In multi-layered stacking, the risk of read interference is higher when the selected word line is located in one of the layers (e.g., the bottom layer and the top layer). Another possible factor is the location of the selected sub-block within the block and its distance from the line decoder. For example, in Figure 8 In the sequence, SB0 is closest to the line decoder, and SB3 is furthest. Due to RC delay, the propagation time of the voltage signal can be longer when the distance is greater. This can lead to different levels of read interference in different sub-blocks. Another possible factor is the time elapsed since the last read operation or other operation (such as programming or erasing).

[0182] Therefore, it can be seen that in one specific embodiment, an apparatus includes: a control circuit configured to be connected to an unselected NAND string and a selected NAND string, the unselected NAND string including a plurality of memory cells between a drain-side select gate transistor and a source-side select gate transistor, the plurality of memory cells including unselected memory cells connected to a selected word line, drain-side adjacent memory cells of the unselected memory cells, and non-adjacent memory cells of the unselected memory cells, the selected NAND string including selected memory cells connected to the selected word line; and a memory interface connected to the control circuit, the control circuit being configured to issue commands via the memory interface to perform a precharge phase in a read operation of the selected memory cell, and then perform a sensing phase.

[0183] During the precharge phase, when the voltage signal applied to the non-adjacent memory cell increases from an initial level to the nominal read pass level (Vread), the control circuit is configured to: apply a voltage signal to the selected word line, which increases from an initial level when the non-selected memory cell is off to a peak level when the non-selected memory cell is on, and then decreases to a lower level when the non-selected memory cell is off; apply a voltage signal to the drain-side select gate transistor, which increases from an initial level when the drain-side select gate transistor is off to a peak level when the drain-side select gate transistor is on, and then decreases to a lower level when the drain-side select gate transistor is off; and apply a voltage signal to the drain-side adjacent memory cell, which increases from an initial level when the drain-side adjacent memory cell is off to a peak level when the drain-side adjacent memory cell is on, and then decreases to a lower level (Vread_low).

[0184] During the sensing phase, the control circuit is configured to maintain the voltage signal applied to the non-adjacent memory cell at the nominal read pass level, increase the voltage signal applied to the adjacent memory cell on the drain side from its decreased level to the read pass level (VreadK), and apply a read voltage to the selected word line when sensing the selected memory cell.

[0185] In another specific embodiment, a method includes boosting the channel of an unselected NAND string, the unselected NAND string including a plurality of memory cells between a drain-side select-gate transistor and a source-side select-gate transistor, the plurality of memory cells including unselected memory cells connected to a selected word line, drain-side adjacent memory cells of the unselected memory cells, and non-adjacent memory cells of the unselected memory cells. The boost includes: simultaneously applying a voltage signal that increases from an initial level to a read-through level (Vread) to the non-adjacent memory cell and a voltage signal that increases from an initial level to a peak level and then decreases to a lower level to the drain-side adjacent memory cell, turning on and then off the unselected memory cell and the drain-side select-gate transistor, and turning on the source-side select-gate transistor; and simultaneously applying a positive bias voltage to the source and drain terminals of the unselected NAND string while the unselected memory cell, the drain-side select-gate transistor, and the source-side select-gate transistor are turned on. After boosting the voltage in the channel, the method further includes: sensing a selected memory cell connected to the selected word line in the selected NAND string while the voltage signal applied to the non-adjacent memory cell is at its read pass level, the voltage signal applied to the adjacent memory cell on the drain side is at the read pass level, and the read voltage is applied to the selected word line.

[0186] In another embodiment, an apparatus includes: a control circuit configured to be connected to a set of memory cells arranged in NAND strings and connected to a set of word lines, the NAND strings including NAND strings in unselected sub-blocks and NAND strings in selected sub-blocks, each NAND string including a drain-side select-gate transistor at the drain end and a source-side select-gate transistor at the source end, the set of word lines including a selected word line, a drain-side adjacent word line of the selected word line, and a non-adjacent word line of the selected word line.

[0187] The control circuitry for performing a read operation involving the selected word line is configured to: increase the voltage signal applied to the non-adjacent word line from an initial level to a read pass level (Vread); during the increase of the voltage signal applied to the non-adjacent word line, turn on and then turn off the drain-side select gate transistor of the NAND string in the non-selected sub-block, turn on but not turn off the drain-side select gate transistor of the NAND string in the selected sub-block, and increase the voltage signal applied to the drain-side adjacent word line from an initial level to a peak level, and then decrease the voltage signal applied to the drain-side adjacent word line from the peak level to a lower level; increase the voltage signal applied to the drain-side adjacent word line from the lower level to a read pass level; and when the voltage signal applied to the non-adjacent word line is at its read pass level and the voltage signal applied to the drain-side adjacent word line is at its read pass level, apply a read voltage to the selected word line and sense the memory cells connected to the selected word line in the selected sub-block.

[0188] The specific embodiments of the invention described above have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the foregoing teachings. The described embodiments were chosen to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to best utilize the invention in various embodiments and various modifications suitable for the intended particular use. The scope of the invention is intended to be defined by the appended claims.

Claims

1. A memory device, comprising: Control circuitry (110, 122) configured to connect to an unselected NAND string (710n) and selected NAND strings (700n, 700n1, 700n2; 710n1, 710n2; 720n, 720n1, 720n2; 730n, 730n1, 730n2), the unselected NAND string comprising a plurality of memory cells (703-710) located between drain-side gate select transistors (712, 732, 752, 772) and source-side gate select transistors (701, 721, 741, 761). 723-730; 743-750; 763-770), the plurality of memory cells include unselected memory cells (727) connected to the selected word line (WLn), drain-side adjacent memory cells (728) of the unselected memory cells, and non-adjacent memory cells (722-726, 729, 730) of the unselected memory cells, the selected NAND string including selected memory cells connected to the selected word line; and A memory interface (131) is connected to the control circuit, which is configured to issue commands via the memory interface to perform a pre-charge phase during a read operation of the selected memory cell, and then perform a sensing phase. During the pre-charge phase, when the voltage signal applied to the non-adjacent memory cell increases from the initial level to the nominal read pass level (Vread), the control circuit is configured to: A voltage signal is applied to the selected word line, the voltage signal increasing from an initial level when the unselected memory cell is turned off to a peak level when the unselected memory cell is turned on, and then decreasing to a lower level when the unselected memory cell is turned off; A voltage signal is applied to the drain-side gate selector transistor, the voltage signal increasing from an initial level when the drain-side gate selector transistor is turned off to a peak level when the drain-side gate selector transistor is turned on, and then decreasing to a lower level when the drain-side gate selector transistor is turned off. as well as A voltage signal is applied to the adjacent memory cell on the drain side, the voltage signal increasing from an initial level when the adjacent memory cell on the drain side is turned off to a peak level when the adjacent memory cell on the drain side is turned on, and then decreasing to a lower level (Vread_low1); as well as During the sensing phase, the control circuit is configured to maintain the voltage signal applied to the non-adjacent memory cell at the nominal read pass level (Vread), increase the voltage signal applied to the adjacent memory cell on the drain side from its decreased level to the read pass level (VreadK), and apply a read voltage (VrA-VrG) to the selected word line when sensing the selected memory cell.

2. The memory device according to claim 1, wherein: The peak level of the voltage signal applied to the adjacent memory cell on the drain side is less than the nominal read pass level (Vread).

3. The memory device according to claim 1, wherein: During the sensing phase, a voltage overshoot (Vspike4) is used to increase the voltage signal applied to the adjacent memory cell on the drain side from its decreased level to its read pass level.

4. The memory device according to claim 1, wherein: The peak level of the voltage signal applied to the drain-side selected gate transistor and the peak level of the voltage signal applied to the selected word line are reached simultaneously.

5. The memory device according to claim 1, wherein: The reduced level of the voltage signal applied to the adjacent memory cell on the drain side is a positive voltage.

6. The memory device according to claim 1, wherein: The read pass level (VreadK) of the voltage signal applied to the adjacent memory cell on the drain side is greater than the nominal read pass level (Vread).

7. The memory device according to claim 1, wherein: During the pre-charge phase, when the voltage signal applied to the non-adjacent memory cell increases from its initial level to the nominal read pass level, the control circuit is configured to: apply a voltage signal to the additional drain-side memory cell of the unselected memory cell, the voltage signal increasing from an initial level when the additional drain-side memory cell is off to a peak level when the additional drain-side memory cell is on, and then decreasing to a lower level (Vread_low2); and The reduced level (Vread_low2) of the additional drain-side memory cell is greater than the reduced level (Vread_low1) of the adjacent drain-side memory cell.

8. The memory device according to claim 1, wherein: The plurality of memory cells include the source-side adjacent memory cells (726) of the unselected memory cells; and During the pre-charging phase and the sensing phase, the voltage signal applied to the adjacent memory cell on the drain side is also applied to the adjacent memory cell on the source side.

9. The memory device according to claim 1, wherein: The plurality of memory cells include the drain-side non-adjacent memory cells and source-side non-adjacent memory cells (723-726) of the unselected memory cell (727); and During the pre-charging phase and the sensing phase, the voltage signal applied to the non-adjacent memory cell is applied to both the drain-side non-adjacent memory cell and the source-side non-adjacent memory cell.

10. The memory device according to claim 1, wherein: After the voltage signal applied to the non-adjacent memory cell is increased (t0), the control circuit is configured to begin increasing the voltage applied to the drain and source terminals of the unselected NAND string (t2).

11. The memory device according to claim 1, wherein: The selected NAND string includes drain-side gate select transistors (712, 732, 752, 772); and During the precharge phase, when the voltage signal applied to the non-adjacent memory cell increases from its initial level to the nominal read pass level, the control circuit is configured to turn on the drain-side select gate transistor of the selected NAND string and keep it on.

12. A method of operating a memory device, comprising: The channel (666) of an unselected NAND string (710n) is boosted, the unselected NAND string comprising a plurality of memory cells (703-710) between drain-side gate select transistors (712, 732, 752, 772) and source-side gate select transistors (701, 721, 741, 761). 723-730; 743-750; 763-770), the plurality of memory cells includes an unselected memory cell (727) connected to a selected word line (WLn), a drain-side adjacent memory cell (728) of the unselected memory cell, and non-adjacent memory cells (722-726, 729, 730) of the unselected memory cell, the boost converter including: While the voltage signal applied to the non-adjacent memory cell increases from an initial level to a read pass level (Vread) and the voltage signal applied to the adjacent drain-side memory cell increases from an initial level to a peak level and then decreases to a lower level (Vread_low1), the unselected memory cell and the drain-side select gate transistor are turned on and then off, and the source-side select gate transistor is turned on; and While the unselected memory cell, the drain-side gate select transistor, and the source-side gate select transistor are turned on, a positive bias voltage (Vcelsrc1) is applied to the source and drain terminals of the unselected NAND string; and After the boost in the channel, while the voltage signal applied to the non-adjacent memory cell is at its read pass level (Vread), the voltage signal applied to the adjacent memory cell on the drain side is at its read pass level (VreadK), and the read voltage (VrA-VrG) is applied to the selected word line, the selected memory cell connected to the selected word line in the selected NAND string is sensed.

13. The method of claim 12, further comprising: The reduced level of the adjacent memory cell on the drain side is set as an increasing function of temperature.

14. The method of claim 12, further comprising: The reduced level of the adjacent memory cell on the drain side is set as a decreasing function of the read interference risk on the unselected memory cell.

15. The method according to claim 12, wherein: By increasing the voltage signal applied to the non-adjacent memory cell when the gate transistor is turned off on the drain side, the channel voltage (Vch) of the unselected NAND string is more coupled.

16. A memory device, comprising: A control circuit is configured to be connected to a set of memory cells arranged in NAND strings and connected to a set of word lines. The NAND strings include NAND strings in selected sub-blocks and NAND strings in unselected sub-blocks. Each NAND string includes a drain-side select-gate transistor at the drain terminal and a source-side select-gate transistor at the source terminal. The set of word lines includes a selected word line, drain-side adjacent word lines of the selected word line, and non-adjacent word lines of the selected word line. The control circuit for performing read operations involving the selected word line is configured to: The voltage signal applied to the non-adjacent word line is increased from the initial level to the read-through level; During the increase of the voltage signal applied to the non-adjacent word line, the drain-side select gate transistor of the NAND string in the unselected sub-block is turned on and then turned off, the drain-side select gate transistor of the NAND string in the selected sub-block is turned on without turning off, and the voltage signal applied to the adjacent word line on the drain side is increased from an initial level to a peak level, and then the voltage signal applied to the adjacent word line on the drain side is decreased from the peak level to a lower level; The voltage signal applied to the adjacent word line on the drain side is increased from the decreased level to the read-through level; Furthermore, when the voltage signal applied to the non-adjacent word line is at its read pass level and the voltage signal applied to the adjacent word line on the drain side is at its read pass level, a read voltage is applied to the selected word line and the memory cell connected to the selected word line in the selected sub-block is sensed.

17. The memory device according to claim 16, wherein: The control circuit is configured to turn on, without turning off, the source-side select gate transistor of the NAND string in the unselected sub-block during the increase of the voltage signal applied to the non-adjacent word line.

18. The memory device according to claim 17, wherein: The control circuit is configured to apply a positive bias to the drain and source terminals of the NAND string in the unselected sub-block when the drain-side gate select transistor and the source-side gate select transistor in the unselected sub-block are turned on.

19. The memory device according to claim 16, wherein: By increasing the voltage signal applied to the non-adjacent word line when the gate transistor on the drain side of the NAND string in the unselected sub-block is turned off, the channel voltage of the NAND string in the unselected sub-block is more coupled.

20. The memory device of claim 16, wherein: When the voltage signal applied to the adjacent word line on the drain side is at the reduced level, the adjacent memory cell on the drain side connected to the adjacent word line on the drain side in the unselected sub-block is turned on.

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