Burst data recovery circuit, integrated circuit, equipment and method

Abstract

The embodiment of the invention provides a burst data recovery circuit, an integrated circuit, equipment and a method. The burst data recovery circuit comprises a first voltage-controlled oscillator and a second voltage-controlled oscillator, a first charge injection circuit of the first voltage-controlled oscillator is used for receiving recovered data; the positive output end of the first voltage-controlled oscillator is connected with the positive input end of the second charge injection circuit of the second voltage-controlled oscillator, and the negative output end of the first voltage-controlled oscillator is connected with the negative input end of the second charge injection circuit; the positive output end of the first voltage-controlled oscillator is connected with the negative input end of the third charge injection circuit of the second voltage-controlled oscillator, and the negative output end of the first voltage-controlled oscillator is connected with the positive input end of the third charge injection circuit; and the differential output end of the second voltage-controlled oscillator is used for outputting a clock signal corresponding to the recovered data. Since the polarities of the two pairs of injection signals of the second voltage-controlled oscillator are opposite, the phase noise can be counteracted, so that the phase noise of the clock can be effectively suppressed, the clock jitter can be reduced, and the clock of the data can be accurately recovered.

Description

Technical Field

[0001] This application relates to the field of optical communication technology, and in particular to a burst data recovery circuit, integrated circuit, device and method. Background Technology

[0002] In applications of optoelectronic hybrid systems and passive optical networks (PONs) based on optical switching chips, the physical connection between the transmitter and receiver is not fixed. The receiver can receive signals transmitted from any transmitter through different physical channels. Because the signals originate from different physical channels, their amplitude and phase may differ. Therefore, the receiver needs to quickly lock the phase and recover the clock signal when receiving signals from different physical channels. A clock data recovery (CDR) circuit with this burst processing capability is called a burst data recovery circuit.

[0003] Since the data received by the receiver also includes noise, the burst data recovery circuit needs to be able to effectively suppress the phase noise of the clock. Currently, the clock recovered by burst data recovery circuits has large jitter. Summary of the Invention

[0004] This application provides a burst data recovery circuit, integrated circuit, device, and method that can effectively suppress clock phase noise, reduce clock jitter, and accurately recover the clock of the data.

[0005] The technical solution provided in this application includes the following aspects.

[0006] In a first aspect, embodiments of this application provide a burst clock data recovery circuit, comprising: a first voltage-controlled oscillator (VCO) and a second VCO; a first charge injection circuit of the first VCO for receiving recovered data; the positive output terminal of the first VCO connected to the positive input terminal of the second charge injection circuit of the second VCO, and the negative output terminal of the first VCO connected to the negative input terminal of the second charge injection circuit; the positive output terminal of the first VCO connected to the negative input terminal of the third charge injection circuit of the second VCO, and the negative output terminal of the first VCO connected to the positive input terminal of the third charge injection circuit; and the differential output terminal of the second VCO for outputting a clock signal corresponding to the recovered data. The burst data recovery circuit provided in this application includes two VCOs connected in series. The output signal of the first VCO serves as the injection signal of the second VCO. The second VCO includes two charge injection circuits, meaning the output signal of the first VCO is directly input to the first charge injection circuit of the second VCO, and the output signal of the first VCO is injected into the second charge injection circuit after the polarity of the positive and negative poles are crossed. In other words, the polarities of the signals injected by the two charge injection circuits of the second VCO are opposite. Since the two pairs of injected signals have opposite polarities, they can cancel out phase noise. Therefore, they can effectively suppress clock phase noise, reduce clock jitter, and accurately recover the clock data.

[0007] One possible implementation further includes: a continuous-time linear equalizer, a delay circuit, and an XOR gate; the input of the continuous-time linear equalizer is used to receive the recovered data, the output of the continuous-time linear equalizer is connected to the first input of the XOR gate, the output of the continuous-time linear equalizer is connected to the second input of the XOR gate through the delay circuit, and the output of the XOR gate is connected to the input of the first charge injection circuit. A continuous-time linear equalizer is a device used in high-speed serial signal receivers to improve the performance of the receiver's eye diagram, especially when signal transmission loss is high. By adjusting the frequency response, the continuous-time linear equalizer forms a high-pass filter effect that attenuates to a constant at low frequencies and gradually attenuates at high frequencies, thereby opening and closing the eye diagram. To compensate for the attenuation and degradation of the recovered data due to channel insertion loss, the continuous-time linear equalizer is used in the first stage of a burst clock data recovery circuit to reduce jitter in the recovered data and ensure that the correct data path enters the XOR gate.

[0008] In one possible implementation, the first voltage-controlled oscillator includes: a first voltage-controlled oscillator circuit and a first charge injection circuit; the positive and negative input terminals of the first charge injection circuit are respectively connected to the positive and negative output terminals of the XOR gate; the positive and negative output terminals of the first charge injection circuit are respectively connected to the positive and negative input terminals of the first voltage-controlled oscillator circuit; the positive output terminal of the first voltage-controlled oscillator circuit serves as the positive output terminal of the first voltage-controlled oscillator, and the negative output terminal of the first voltage-controlled oscillator circuit serves as the negative output terminal of the first voltage-controlled oscillator. The first charge injection circuit is used to lock onto the input differential signal. The first voltage-controlled oscillator circuit is used to recover the clock signal.

[0009] In one possible implementation, the second voltage-controlled oscillator includes: a second voltage-controlled oscillator circuit, a second charge injection circuit, and a third charge injection circuit; the positive output terminals of the second and third charge injection circuits are connected to the positive input terminal of the second voltage-controlled oscillator circuit, and the negative output terminals of the second and third charge injection circuits are connected to the negative input terminal of the second voltage-controlled oscillator circuit; the positive and negative output terminals of the second voltage-controlled oscillator circuit serve as the differential output terminals of the second voltage-controlled oscillator. The function of the second charge injection circuit is to receive the differential signal from the first voltage-controlled oscillator, achieving signal isolation and adjustable delay; the function of the third charge injection circuit is to receive the differential signal output from the first voltage-controlled oscillator, performing signal isolation and adjustable delay.

[0010] In one possible implementation, the second voltage-controlled oscillator further includes: an adjustable current source; the source terminal of the third charge injection circuit is connected to the adjustable current source; the adjustable current source is used to adjust the current according to the clock signal output by the second voltage-controlled oscillator. The adjustable current source is used to adjust the magnitude of the current injected into the third charge injection circuit, thereby changing the amplitude of the signal injected into the third charge injection circuit.

[0011] One possible implementation includes the adjustable current source comprising: a current source transistor, N mirror transistors, and N switches; the N mirror transistors and the N switches are in one-to-one correspondence; N is an integer greater than or equal to 2; the drain and gate of the current source transistor are connected to a preset current source, each mirror transistor is connected to the gate of the current source transistor through a corresponding switch, and the drains of the N mirror transistors are connected together as the output terminal of the adjustable current source; the sources of the N mirror transistors are all grounded; the adjustable current source is used to adjust the switching states of the N switches according to the clock signal output by the second voltage-controlled oscillator, thereby changing the current of the adjustable current source. The larger the value of N, the more current levels are corresponding to it. The value of N can be selected according to actual needs. This application embodiment does not impose specific limitations, and different switch combinations can be set according to actual needs to obtain different current magnitudes.

[0012] In one possible implementation, the second voltage-controlled oscillator further includes: a phase adjustment circuit; the negative input terminal of the phase adjustment circuit is connected to the positive output terminal of the first voltage-controlled oscillator, and the positive input terminal of the phase adjustment circuit is connected to the negative output terminal of the first voltage-controlled oscillator; the first output terminal of the phase adjustment circuit is connected to the positive input terminal of the third charge injection circuit, and the second output terminal of the phase adjustment circuit is connected to the negative input terminal of the third charge injection circuit; the phase adjustment circuit is used to adjust the phase of the differential signal output by the phase adjustment circuit according to the clock signal output by the second voltage-controlled oscillator. Specifically, the phase adjustment circuit changes the phase of the injection signal of the third charge injection circuit; specifically, the phase adjustment circuit can change the phase difference between the injection signal of the second charge injection circuit and the injection signal of the third charge injection circuit.

[0013] In one possible implementation, the phase adjustment circuit includes: a main path differential input circuit, a delay path differential input circuit, a main path adjustable tail current source, and a delay path adjustable tail current source; the positive terminal of the main path differential input circuit is connected to the negative output terminal of the first voltage-controlled oscillator, and the negative terminal of the main path differential input circuit is connected to the positive output terminal of the first voltage-controlled oscillator; the positive terminal of the delay path differential input circuit is connected to the negative output terminal of the first voltage-controlled oscillator, and the negative terminal of the delay path differential input circuit is connected to the positive output terminal of the first voltage-controlled oscillator; the positive output terminal of the main path differential input circuit and the delay path differential input circuit are connected to the negative output terminal of the first voltage-controlled oscillator; the negative terminal of the delay path differential input circuit is .... The positive output terminal of the sub-circuit is connected to the first output terminal of the phase adjustment circuit, and the negative output terminals of the main path differential input circuit and the delay path differential circuit are connected to the second output terminal of the phase adjustment circuit. The source terminal of the main path differential input circuit is connected to the main path adjustable tail current source, and the source terminal of the delay path differential input circuit is connected to the delay path adjustable tail current source. The main path adjustable tail current source is used to adjust the current magnitude according to the clock signal output by the second voltage-controlled oscillator. The delay path adjustable tail current source is used to adjust the current magnitude according to the clock signal output by the second voltage-controlled oscillator.

[0014] In one possible implementation, the phase adjustment circuit further includes: a first delay network and a second delay network; the positive input terminal of the delay path differential input circuit is connected to the negative input terminal of the phase adjustment circuit via the first delay network, and the negative input terminal of the delay path differential input circuit is connected to the positive input terminal of the phase adjustment circuit via the second delay network. The first delay network and the second delay network are used to delay the differential signal output from the first voltage-controlled oscillator before inputting it to the delay path differential input circuit. Specifically, the delay time can be adjusted by adjusting the parameters of the first delay network and the second delay network. For example, both the first delay network and the second delay network can be resistor-capacitor delay networks.

[0015] In one possible implementation, the phase adjustment circuit further includes: a controller; the main path adjustable tail current source includes a first bias transistor, and the delay path adjustable tail current source includes a second bias transistor; the sources of the first bias transistor and the second bias transistor are connected to the tail current source; the drain of the first bias transistor is connected to the source terminal of the main path differential input circuit, and the drain of the second bias transistor is connected to the source terminal of the delay differential input circuit; the controller is used to adjust the gate voltage of the first bias transistor and the gate voltage of the second bias transistor according to the clock signal output by the second voltage-controlled oscillator. The controller can perform closed-loop control, controlling the bias voltage according to the comparison signal fed back by the eye diagram monitor, and then controlling the bias current to achieve phase difference adjustment. For example, the phase adjustment circuit provided in this application embodiment can achieve a maximum phase difference adjustment of 65°.

[0016] In one possible implementation, both the first voltage-controlled oscillator circuit and the second voltage-controlled oscillator circuit are inductor-capacitor voltage-controlled oscillator circuits. For example, they can be negative resistance inductor-capacitor voltage-controlled oscillator circuits or current multiplexing negative resistance inductor-capacitor voltage-controlled oscillator circuits. The embodiments of this application do not specifically limit the specific implementation form of the voltage-controlled oscillator circuit.

[0017] One possible implementation further includes: a retiming circuit and an eye diagram monitor; the first input terminal of the retiming circuit is connected to the differential output terminal of the second voltage-controlled oscillator, and the second input terminal of the retiming circuit is connected to the output terminal of the delay circuit; the output terminal of the retiming circuit is connected to the input terminal of the eye diagram monitor; the retiming circuit is used to retime the data signal output by the delay circuit according to the clock signal output by the second voltage-controlled oscillator; the eye diagram monitor is used to acquire the retimed data signal output by the retiming circuit, compare the retimed data signal with a reference signal, and feed back the comparison result to the adjustable current source and the phase adjustment circuit of the second voltage-controlled oscillator. The eye diagram monitor can perform closed-loop control to achieve adjustable phase and adjustable amplitude of the input signal of the second voltage-controlled oscillator, thereby achieving greater efficiency in reducing clock jitter by adjusting the amplitude and phase.

[0018] Secondly, embodiments of this application also provide an integrated circuit, including: a burst transimpedance amplifier and the burst clock data recovery circuit described above; the input terminal of the burst clock data recovery circuit is used to connect to the output terminal of the burst transimpedance amplifier.

[0019] Thirdly, embodiments of this application also provide a device including the integrated circuit described above; the integrated circuit is used to obtain the clock of the received data signal.

[0020] One possible implementation is that the device is an optical module or a host chip.

[0021] Fourthly, embodiments of this application also provide a method for burst clock data recovery, comprising: receiving the data to be recovered using a first voltage-controlled oscillator; receiving the differential signal output by the first voltage-controlled oscillator using a first differential input terminal of a second voltage-controlled oscillator; receiving the cross signal of the differential signal output by the second voltage-controlled oscillator using a second differential input terminal of the second voltage-controlled oscillator; and outputting the clock signal of the recovered data using the second voltage-controlled oscillator.

[0022] It should be understood that the technical effects achieved by the technical solutions provided by the second to fourth aspects of this application and their corresponding possible implementations can be found in the above description of the technical effects achieved by the technical solutions provided by the first aspect and their corresponding possible implementations, and will not be repeated here. Attached Figure Description

[0023] Figure 1 A schematic diagram of a communication system provided in an embodiment of this application;

[0024] Figure 2 A schematic diagram of another communication system provided in the embodiments of this application;

[0025] Figure 3 A schematic diagram of an optoelectronic switching network provided in an embodiment of this application;

[0026] Figure 4 To and Figure 3 A schematic diagram of the corresponding optoelectronic switching network;

[0027] Figure 5 This is a schematic diagram illustrating an application scenario of a burst data recovery circuit provided in an embodiment of this application.

[0028] Figure 6 A schematic diagram of a burst clock data recovery circuit provided in an embodiment of this application;

[0029] Figure 7 A schematic diagram of another burst clock data recovery circuit provided in an embodiment of this application;

[0030] Figure 8 A schematic diagram of a first voltage-controlled oscillator provided in an embodiment of this application;

[0031] Figure 9 A schematic diagram of a first voltage-controlled oscillator and a second voltage-controlled oscillator provided in the embodiments of this application;

[0032] Figure 10 A schematic diagram of a phase adjustment circuit provided in an embodiment of this application;

[0033] Figure 11 A circuit diagram of a phase adjustment circuit provided in an embodiment of this application;

[0034] Figure 12 A schematic diagram of an adjustable current source provided in an embodiment of this application;

[0035] Figure 13 A schematic diagram of another voltage-controlled oscillator circuit provided in an embodiment of this application;

[0036] Figure 14A schematic diagram of an integrated circuit provided for an embodiment of this application;

[0037] Figure 15 A flowchart illustrating a method for recovering burst clock data provided in an embodiment of this application. Detailed Implementation

[0038] This application does not specifically limit whether the burst clock recovery circuit is located in the receiver (RX) or the transmitter (TX). In exemplary embodiments, the devices in the communication system provided in this application include, but are not limited to, the following.

[0039] The first type of device is the host chip, also known as the host chip within a device, which is connected to other devices via telecommunications channels. For example, host chips include, but are not limited to, switch chips or physical layer (PHY) chips, such as application-specific integrated circuit (ASIC) chips.

[0040] The second type of device is an electrical interconnect device, which connects to other devices via telecommunication channels. Exemplarily, electrical interconnect devices include direct attach cables (DACs), which include, but are not limited to, active electrical cables (AEC) modules, active copper cables (ACC) modules, or passive direct attach cable DAC modules. Optionally, the electrical interconnect device can be linear (L). For example, the AEC module is an LAEC module, and the ACC module is a LAC module.

[0041] The third type of device is the optoelectronic interconnect device, which is used for optoelectronic conversion and is connected to other devices through optical channels, or to other devices through optical channels and telecommunication channels.

[0042] In some implementations, the optoelectronic interconnect device includes an optical module. Exemplarily, the types of optical modules include, but are not limited to, the following.

[0043] (1) Normal optical module.

[0044] (2) Optical digital signal processor (oDSP) module, also known as oDSP optical module.

[0045] (3) LPO module, also known as LPO optical module.

[0046] (4) Co-packaged optics (CPO) modules, also known as CPO optical modules. CPO modules are obtained by assembling optical engines (OE) and host chips together, for example, by assembling them together on a substrate to form a co-package of OE and host chip.

[0047] (5) Near package optics (NPO) modules, also known as NPO optical modules. By assembling the OE and the host chip on the same printed circuit board (PCB) respectively, a near package of OE and host chip can be formed, thus obtaining an NPO module.

[0048] (6) Half retimed optics (HRO) module, also known as HRO optical module. HRO module refers to retimed transmitter linear receiver.

[0049] (7) Linear receive optics (LRO) module, also known as LRO optical module.

[0050] (8) Transmitter retimed optics (TRO) module, also known as TRO optical module.

[0051] In communication systems, the devices described above can be located in different equipment, such as switches or network interface cards (NICs). For ease of understanding, the following are some exemplary communication systems.

[0052] The first type of communication system, such as Figure 1 As shown, the first device includes a host chip 1 and an LPO optical module 1 connected via a telecommunications channel, and the second device includes a host chip 2 and an LPO optical module 2 connected via a telecommunications channel. The LPO optical module 1 and the LPO optical module 2 are connected via an optical channel. Figure 1 The examples shown are merely illustrative. For instance, at least one of the LPO optical modules 1 or LPO optical module 2 can be replaced with the HRO optical module described above.

[0053] The second type of communication system, such as Figure 2As shown, the first device includes a host chip 1 and an oDSP optical module connected via a telecommunications channel, and the second device includes a host chip 2 and an LPO optical module connected via a telecommunications channel. The oDSP optical module and the LPO optical module are connected via an optical channel, which is also referred to as mixed insertion of oDSP optical modules and LPO optical modules.

[0054] The oDSP optical module includes an oDSP. A first side of the oDSP is used to connect to the host chip 1; this first side can be referred to as the hostside. A second side of the oDSP is used to connect to the transmitter optical sub-assembly (TOSA) and / or the receiver optical sub-assembly (ROSA); this second side can be referred to as the mediaside. This application does not limit the devices included in the hostside and mediaside. The first side is used to communicate with the host chip 1 via a telecommunications channel. For example, the serializer / deserializer (serdes) located on the first side of the oDSP communicates with the serdes located on the host chip 1. Figure 2 The second side (not shown) communicates via a telecommunications channel. The second side is used to communicate with the TOSA / ROSA via the telecommunications channel. In one implementation, the TOSA / ROSA is located in the oDSP optical module. The TOSA / ROSA communicates with the LPO optical module of the second device via an optical channel. Compared to the oDSP optical module, the LPO optical module eliminates the oDSP; therefore, the host chip 2 is required to perform optoelectronic channel compensation because the LPO optical module eliminates the oDSP.

[0055] The internal structures of the first and second devices provided in this application embodiment can be the same or different, and no specific limitation is made. The burst data recovery circuit provided in this application embodiment can be located in the optical module or in the host chip. The burst data recovery circuit provided in this application embodiment can be an independent chip or integrated with other chips, and no specific limitation is made. For example, the burst data recovery circuit provided in this application embodiment can be located in the receiver's SERDES.

[0056] The following example uses the application scenario of optical communication.

[0057] The physical relationship between transmitters and receivers is not one-to-one; switching may occur during application, and the receiver may receive signals transmitted by any transmitter through different physical channels. For example, see... Figure 3 This figure is a schematic diagram of an optoelectronic switching network provided in an embodiment of this application. At time t1, receiver 2 corresponds to transmitter 1. See also... Figure 4At time t2, receiver 2 corresponds to transmitter 3. When the receiver receives signals that have passed through different physical channels, it needs to readjust the parameter configuration of the burst data recovery circuit, quickly lock the phase, and recover the data clock.

[0058] See Figure 5 The figure is a schematic diagram of an application scenario of a burst data recovery circuit provided in an embodiment of this application.

[0059] This application uses an optical communication application scenario as an example. Interface 10 is used to receive optical signals. A photoelectric conversion circuit 20 converts the optical signal into an electrical signal and provides it to the input of an amplifier circuit 30. For example, the photoelectric conversion circuit 20 can be implemented using a photodiode. The amplifier circuit 30 amplifies and isolates the electrical signal. The amplifier circuit 30 can utilize a burst mode transimpedance amplifier (BMTIA) to process burst data. A burst data recovery circuit 40 is used to quickly lock the phase of the output signal of the amplifier circuit 30 and recover the data clock. In one possible product form, the CDR circuit and BMTIA can be integrated into an optical line terminal (OLT).

[0060] In related technologies, burst data recovery circuits utilize digital circuits for phase locking, requiring simultaneous acquisition of data and edge information. This necessitates comparators for both data and edge information, resulting in a relatively large circuit. Alternatively, burst data recovery circuits can also utilize analog circuits for phase locking, employing a two-stage series voltage-controlled oscillator (VCO). The output of the first-stage VCO is directly connected to the input of the second-stage VCO. However, this phase-locked clock scheme is significantly affected by data jitter, especially for high-speed data transmissions where high jitter tolerance is crucial.

[0061] Therefore, in order to achieve phase-locked loop (PLL) for data using analog circuits, and to achieve strong jitter suppression so that the recovered clock is less affected by data jitter, this application provides a burst data recovery circuit. The two voltage-controlled oscillators (VCOs) are not simply connected in series; instead, the input signal of the second-stage VCO includes two pairs of differential signals. The first pair of differential signals is directly the differential signal output from the first-stage VCO, and the second pair of differential signals is a cross-polled differential signal from the first-stage VCO output. That is, the polarities of the second pair of differential signals are crossed; the positive polarity signal is input to the negative input terminal of the second-stage VCO, and the negative polarity signal is input to the positive input terminal. Because the polarities of the two pairs of injected signals are opposite, they can cancel out phase noise. Therefore, clock phase noise can be effectively suppressed, clock jitter reduced, and the data clock can be accurately recovered.

[0062] See Figure 6 The figure is a schematic diagram of a sudden clock data recovery circuit provided in an embodiment of this application.

[0063] The burst clock data recovery circuit provided in this application includes: a first voltage-controlled oscillator VCO1 and a second voltage-controlled oscillator VCO2; as the name suggests, a voltage-controlled oscillator (VCO) is simply understood as a voltage-controlled oscillation frequency, that is, a voltage-controlled oscillator is an oscillation circuit in which the output frequency corresponds to the input control voltage, the output frequency is a function of the control voltage, and the working state of the voltage-controlled oscillator or the component parameters of the oscillation circuit are controlled by the control voltage.

[0064] The recovered data includes frequency and phase information, which are used to lock the frequency and phase of the clock, respectively.

[0065] The first voltage-controlled oscillator (VCO1) provided in this application embodiment includes a pair of differential input interfaces and a pair of differential output interfaces. The second voltage-controlled oscillator (VCO2) includes two pairs of differential input interfaces and a pair of differential output interfaces.

[0066] The first charge injection circuit of the first voltage-controlled oscillator VCO1 is used to receive the recovered data. Figure 6 The first charge injection circuit is not shown in the diagram. The first charge injection circuit includes a pair of differential interfaces, which can be implemented using two semiconductor transistors to form a differential interface. For example... Figure 6 As shown, the differential interface of the first voltage-controlled oscillator (VCO1) includes a positive input terminal VP and a negative input terminal VN. This embodiment does not specifically limit the type of data to be recovered; any data received by VCO1 can be used for clock recovery.

[0067] The positive output terminal OUTP1 of the first voltage-controlled oscillator VCO1 is connected to the positive input terminal PinA of the second charge injection circuit of the second voltage-controlled oscillator VCO2, and the negative output terminal OUTN1 of the first voltage-controlled oscillator VCO1 is connected to the negative input terminal NinA of the second charge injection circuit. Figure 6 The second charge injection circuit is not shown; only the differential interfaces PinA and NinA included in the second charge injection circuit are illustrated. The second charge injection circuit can be implemented by using two semiconductor transistors to form a differential interface.

[0068] The positive output terminal of the first voltage-controlled oscillator VCO1 is connected to the negative input terminal NinB of the third charge injection circuit of the second voltage-controlled oscillator VCO2, and the negative output terminal of the first voltage-controlled oscillator VCO1 is connected to the positive input terminal PinB of the third charge injection circuit. Figure 6The third charge injection circuit is not shown; only the differential interfaces PinB and NinB included in the third charge injection circuit are illustrated. The third charge injection circuit can be implemented by using two semiconductor transistors to form a differential interface.

[0069] The differential output of the second voltage-controlled oscillator VCO2 is used to output the clock signal corresponding to the recovered data. The differential output of the second voltage-controlled oscillator VCO2 includes a positive output terminal OUTP2 and a negative output terminal OUTN2.

[0070] The embodiments of this application do not specifically limit the specific structure of the first voltage-controlled oscillator VCO1 and the second voltage-controlled oscillator VCO2. For example, the voltage-controlled oscillation circuits included in the first voltage-controlled oscillator VCO1 and the second voltage-controlled oscillator VCO2 are both inductor-capacitor LC voltage-controlled oscillator circuits. One possible implementation is to use an NMOS negative resistance LC voltage-controlled oscillator circuit; other types of voltage-controlled oscillator circuits can also be used.

[0071] For example, the working principle of a voltage-controlled oscillator is that the capacitance value of a variable capacitor can be adjusted by adjusting the control voltage, which in turn adjusts the self-oscillation frequency of the voltage-controlled oscillator, ensuring that the self-oscillation frequency of the voltage-controlled oscillator is within the clock-locked range of the recovered data.

[0072] In this embodiment, the clock signal output by the first voltage-controlled oscillator (VCO1) is directly affected by the data being recovered. This recovered data exhibits irregular data variations, such as consecutive 0s or consecutive 1s. Therefore, the clock signal output by VCO1 experiences significant jitter and uneven amplitude. To reduce clock signal jitter, the burst clock data recovery circuit provided in this application injects the clock signal output by VCO1 into a second voltage-controlled oscillator (VCO2) via cross-injection. VCO2, with its two cross-input interfaces, utilizes the opposite polarities of the two injected signals to cancel out phase noise. This effectively suppresses clock phase noise, reduces clock jitter, and accurately recovers the data clock.

[0073] To enable those skilled in the art to better understand and implement the technical solutions provided in the embodiments of this application, the working principle of the burst clock data recovery circuit is described below in conjunction with the accompanying drawings.

[0074] See Figure 7 The figure is a schematic diagram of another burst clock data recovery circuit provided in an embodiment of this application.

[0075] The burst clock data recovery circuit provided in this application embodiment further includes: a continuous time linear equalizer (CTLE) 41, a delay circuit 42, and an XOR gate 43.

[0076] The input of CTLE41 is used to receive the recovered data. The output of CTLE41 is connected to the first input of XOR gate 43, and the output of CTLE41 is connected to the second input of XOR gate 43 through delay circuit 42. CTLE is a device used in high-speed serial signal receivers to improve the performance of the receiver's eye diagram, especially when signal transmission loss is high. CTLE41 adjusts its frequency response to form a high-pass filter effect that attenuates constantly at low frequencies and gradually attenuates at high frequencies, thus opening and closing the eye diagram. To compensate for the attenuation and degradation of the recovered data due to channel insertion loss, CTLE41 is used in the first stage of a burst clock data recovery circuit to reduce jitter in the recovered data and ensure that the correct data edge information enters XOR gate 43.

[0077] The delay circuit 42 is used to delay the output signal of CTLE41 and output it to the second input terminal of XOR gate 43. This application does not specifically limit the delay time. To allow XOR gate 43 to better obtain spectral information, the delay circuit 42 can delay by 0.5 units of time (UI). Furthermore, it can ensure that the recovered data achieves a burst response time of 1UI, i.e., less than 1ns, with low burst overhead, making it suitable for clock recovery in high-speed signal transmission scenarios. The main function of the delay circuit 42 is to ensure that the input signal of XOR gate 43 is a signal with a time interval between the two paths, thus suppressing noise in the input signal. The delay circuit 42 can be implemented using a buffer.

[0078] The output of XOR gate 43 is connected to the input of the first charge injection circuit of the first voltage-controlled oscillator VCO1.

[0079] The XOR gate 43 can be implemented using a high-speed XOR gate. The function of the XOR gate 43 is to obtain the spectral information from the recovered data, and then extract the frequency information of the corresponding rate to help the first voltage-controlled oscillator VCO1 achieve frequency locking.

[0080] The burst clock data recovery circuit provided in this application embodiment further includes: a retiming circuit 44 and an eye diagram monitor 45.

[0081] Additionally, the second voltage-controlled oscillator VCO2 may also include an adjustment circuit. The adjustment circuit can be at least one of an adjustable current source or a phase adjustment circuit. The adjustable current source is used to adjust the magnitude of the current, thereby changing the amplitude of the signal injected by the third charge injection circuit. The phase adjustment circuit changes the phase of the signal injected by the third charge injection circuit; specifically, the phase adjustment circuit can change the phase difference between the injection signals of the second and third charge injection circuits. This application does not specifically limit the degree of phase difference that the phase adjustment circuit can adjust; for example, a phase shift of up to 65° can be achieved.

[0082] The source terminal of the third charge injection circuit is connected to an adjustable current source. The differential interface of the third charge injection circuit is connected to the output terminal of the first voltage-controlled oscillator VCO1 through a phase adjustment circuit.

[0083] The first input terminal of the retiming circuit 44 is connected to the differential output terminal of the second voltage-controlled oscillator VCO1, the second input terminal of the retiming circuit 44 is connected to the output terminal of the delay circuit 42, and the output terminal of the retiming circuit 44 is connected to the input terminal of the eye diagram monitor 45.

[0084] The retiming circuit 44 is used to retime the data signal output by the delay circuit 42 according to the clock signal output by the second voltage-controlled oscillator VCO2.

[0085] The eye diagram monitor 45 is used to acquire the retiming data signal output by the retiming circuit, compare the retiming data signal with the reference signal, and feed the comparison result back to the adjustable current source and phase adjustment circuit of the second voltage-controlled oscillator VCO2.

[0086] The retiming circuit can be implemented using a D flip-flop.

[0087] The eye diagram monitor 45 is used to obtain the eye diagram of the data, and the jitter of the eye diagram reflects the jitter of the clock. The eye diagram monitor 45 can be configured as an on-chip eye diagram monitor. Alternatively, the eye diagram detector 45 can be implemented using other circuits to detect bit errors or eye diagram quality. This application does not specifically limit the specific implementation of the eye diagram monitor.

[0088] The burst clock data recovery circuit provided in this embodiment also includes a delay adjustment circuit 46. The delay adjustment circuit 46 can adjust the delay time of the delay circuit 42 according to the comparison result fed back by the eye diagram monitor 45, so that the delay time of the delay circuit 42 is stabilized at 0.5UI. Specifically, the delay adjustment circuit 46 can adjust the duty cycle of the resistor-capacitor network and the buffer in the delay circuit 42 to adjust the delay time.

[0089] The burst clock data recovery circuit provided in this application embodiment injects the output signal of a first voltage-controlled oscillator (VCO) into a second VCO after cross-injection. The second VCO outputs a low-jitter clock signal, and the relationship between the phase of this clock signal and the phase of the recovered data remains constant. A retimer circuit samples and retimes the clock signal output by the second VCO, mainly to clear the jitter accumulation caused by channel insertion loss during data transmission. The recovered data after retime is sent to an eye diagram monitor. The eye diagram monitor feeds back the comparison result to the delay adjustment circuit and the second VCO to achieve the best cross-injection effect. Specifically, the second VCO also includes an adjustment circuit, which can adjust at least one of the phase or amplitude of the injected signal from the second VCO based on the comparison result fed back by the eye diagram monitor. For example, the adjustment circuit can achieve phase adjustment and amplitude adjustment. When the relationship between the phase output of the second voltage-controlled oscillator and the phase of the recovered data changes, the clock signal output by the second voltage-controlled oscillator is quickly adjusted by the phase adjustment circuit, so that the phase of the clock signal output by the second voltage-controlled oscillator follows the phase change of the recovered data, and the phase of the output clock signal is shifted forward or backward to fix the phase relationship.

[0090] The burst clock data recovery circuit provided in this application embodiment uses analog circuitry for implementation, resulting in shorter burst times, simpler circuitry, and lower requirements for manufacturing processes. Furthermore, it employs a two-stage voltage-controlled oscillator (VCO). The differential signals of the second-stage VCO use a cross-injection method, which can solve the jitter problem of high-speed clock lock-in, enabling its application in higher-speed scenarios with less jitter.

[0091] The following section, with reference to the accompanying drawings, describes a specific first voltage-controlled oscillator.

[0092] See Figure 8 The figure is a schematic diagram of a first voltage-controlled oscillator provided in an embodiment of this application.

[0093] The first voltage-controlled oscillator provided in this application embodiment includes: a first charge injection circuit 101 and a first voltage-controlled oscillator circuit 102; the first voltage-controlled oscillator formed by the first voltage-controlled oscillator circuit 102 and the first charge injection circuit 101 is called an input-locked voltage-controlled oscillator.

[0094] In this embodiment, the first charge injection circuit 101 includes a pair of metal-oxide-semiconductor field-effect transistors (MOSFETs) forming a differential input, but other types of semiconductor transistors can also be used. For ease of description, they will be referred to as the first MOSFET M1 and the second MOSFET M2 below.

[0095] The gates of the first MOS transistor M1 and the second MOS transistor M2 in the first charge injection circuit 101 are respectively connected to the two output terminals of the XOR gate, that is, the gate of M1 serves as the positive input terminal VP of the first voltage-controlled oscillator, and the gate of M2 serves as the negative input terminal VN of the first voltage-controlled oscillator; the drains of the first MOS transistor M1 and the second MOS transistor M2 are respectively connected to the differential pair input terminals of the first voltage-controlled oscillator circuit 102; the positive output terminal OUTP1 of the first voltage-controlled oscillator circuit 102 serves as the positive output terminal of the first voltage-controlled oscillator, and the negative output terminal OUTN1 of the first voltage-controlled oscillator circuit 102 serves as the negative output terminal of the first voltage-controlled oscillator.

[0096] Figure 8 The first voltage-controlled oscillator is an inductor-capacitor voltage-controlled oscillator, wherein the tap of the inductor L is connected to the power supply VDD, and the first and second ends of the inductor L are connected to OUTP1 and OUTN1 respectively. The variable capacitors include a first variable capacitor C11 and a second variable capacitor C12. The first end of the first variable capacitor C11 is connected to the voltage-controlled voltage VCtrl, and the second end of the first variable capacitor C11 is connected to OUTN1. The first end of the second variable capacitor C12 is connected to the voltage-controlled voltage VCtrl, and the second end of the second variable capacitor C12 is connected to OUTP1.

[0097] Figure 8 This is just one type of LC negative resistance voltage-controlled oscillator circuit. It should be understood that other structures can also be used for voltage-controlled oscillator circuits. Since the structure of voltage-controlled oscillator circuits is relatively mature, it will not be described in detail here.

[0098] See Figure 9 The figure is a schematic diagram of a first voltage-controlled oscillator and a second voltage-controlled oscillator provided in an embodiment of this application.

[0099] The second voltage-controlled oscillator VCO2 provided in this application embodiment includes: a second voltage-controlled oscillator circuit 201, a second charge injection circuit, and a third charge injection circuit; the second charge injection circuit includes a pair of differential MOSFETs, hereinafter referred to as the third MOSFET M3 and the fourth MOSFET M4.

[0100] The gate of the fourth MOSFET M4 serves as the positive input terminal PinA of the second charge injection circuit, and the gate of the third MOSFET M3 serves as the negative input terminal NinA of the second charge injection circuit.

[0101] The gate of the fourth MOSFET M4 is connected to the positive output terminal OUTP1 of the first voltage-controlled oscillator VCO1; the gate of the third MOSFET M3 is connected to the negative output terminal OUTN1 of the first voltage-controlled oscillator.

[0102] The positive output terminals of the second charge injection circuit and the third charge injection circuit are connected to the positive input terminal INP of the second voltage-controlled oscillator circuit, and the negative output terminals of the second charge injection circuit and the third charge injection circuit are connected to the negative input terminal INN of the second voltage-controlled oscillator circuit.

[0103] The third charge injection circuit includes a pair of differential MOSFETs, hereinafter referred to as the fifth MOSFET M5 and the sixth MOSFET M6.

[0104] The gate of the fifth MOSFET M5 serves as the positive input terminal PinB of the third charge injection circuit, and the gate of the sixth MOSFET M6 serves as the negative input terminal NinB of the third charge injection circuit.

[0105] The gate of the sixth MOSFET M6 is connected to the positive output terminal OUTP1 of the first voltage-controlled oscillator VCO1; the gate of the fifth MOSFET M5 is connected to the negative output terminal OUTN1 of the first voltage-controlled oscillator. Figure 10 It can be seen that the positive output terminal of the first voltage-controlled oscillator is connected to the negative input terminal of the third charge injection circuit, and the negative output terminal of the first voltage-controlled oscillator is connected to the positive input terminal of the third charge injection circuit, thus realizing that the output terminal of the first voltage-controlled oscillator is connected to the input terminal of the third charge injection circuit after the polarity of the output terminal is crossed.

[0106] The positive output terminal OUTP2 and the negative output terminal OUTN2 of the second voltage-controlled oscillator circuit serve as the differential output terminals of the second voltage-controlled oscillator.

[0107] It should be understood that the second voltage-controlled oscillator is of the same type as the first voltage-controlled oscillator, also employing an inductor-capacitor voltage-controlled oscillator, with the connection method of the inductor and adjustable capacitor being the same. Figure 8 The first voltage-controlled oscillator shown is the same, and the parameters are also the same, so it will not be described again here. Figure 9 The voltage control voltage VCtrl of the first voltage-controlled oscillator and the voltage control voltage VCtrl of the second voltage-controlled oscillator are equal.

[0108] The burst time recovery circuit provided in this application embodiment further includes an adjustable current source 202 as the second voltage-controlled oscillator.

[0109] The source of the third charge injection circuit is connected to an adjustable current source 202.

[0110] The adjustable current source 202 is used to adjust the current according to the clock signal output by the second voltage-controlled oscillator.

[0111] The burst time recovery circuit provided in this application embodiment further includes a phase adjustment circuit 203 for the second voltage-controlled oscillator.

[0112] The negative input terminal of the phase adjustment circuit 203 is connected to the positive output terminal of the first voltage-controlled oscillator, and the positive input terminal of the phase adjustment circuit 203 is connected to the negative output terminal of the first voltage-controlled oscillator; the first output terminal of the phase adjustment circuit 203 is connected to the positive input terminal of the third charge injection circuit, and the second output terminal of the phase adjustment circuit 203 is connected to the negative input terminal of the third charge injection circuit.

[0113] The phase adjustment circuit 203 is used to adjust the phase of the differential signal output by the phase adjustment circuit 203 according to the clock signal output by the second voltage-controlled oscillator.

[0114] from Figure 9 As can be seen, the first and second voltage-controlled oscillators (VCOs) are not directly connected in series. The input signal of the second VCO includes two pairs of differential signals. One pair of differential signals comes directly from the differential output of the first VCO, and the other pair comes from the crossover signal at the differential output of the first VCO. The phase difference between the two pairs of differential signals of the second VCO can be adjusted by a phase adjustment circuit, and the amplitude between the differential signals at both ends of the second VCO can be adjusted by an adjustable current source. This allows both the amplitude and phase of the two pairs of differential signals input to the second VCO to be adjustable. Furthermore, closed-loop feedback can be formed based on the differential signal output by the second VCO for adjustment, making the control more flexible and thus better reducing clock jitter.

[0115] The embodiments of this application do not specifically limit the implementation method of the phase adjustment circuit, as long as closed-loop phase adjustment can be achieved. The following describes a specific implementation method of the phase adjustment circuit with reference to the accompanying drawings.

[0116] See Figure 10 The figure is a schematic diagram of a phase adjustment circuit provided in an embodiment of this application.

[0117] The phase adjustment circuit provided in this application embodiment includes: a main path differential input circuit 21, a delay path differential input circuit 22, a main path adjustable tail current source 23, and a delay path adjustable tail current source 24.

[0118] The positive terminal of the main path differential input circuit 21 is connected to the negative output terminal OUTN1 of the first voltage-controlled oscillator VCO1, and the negative terminal of the main path differential input circuit 21 is connected to the positive output terminal OUTP1 of the first voltage-controlled oscillator.

[0119] The positive terminal of the delay path differential input circuit 22 is connected to the negative output terminal OUTN1 of the first voltage-controlled oscillator VCO1, and the negative terminal of the delay path differential input circuit 22 is connected to the positive output terminal OUTP1 of the first voltage-controlled oscillator VCO1.

[0120] The positive output terminal of the main path differential input circuit 21 and the positive output terminal of the delay path differential input circuit 22 are connected to the first output terminal VoutP of the phase adjustment circuit, and the negative output terminal of the main path differential input circuit 21 and the negative output terminal of the delay path differential input circuit 22 are connected to the second output terminal VoutN of the phase adjustment circuit.

[0121] The source end of the main path differential input circuit 21 is connected to the main path adjustable tail current source 23, and the source end of the delay path differential input circuit 22 is connected to the delay path adjustable tail current source 24.

[0122] The main path adjustable tail current source 23 is used to adjust the current magnitude according to the clock signal output by the second voltage-controlled oscillator.

[0123] The adjustable tail current source 24 of the delay path is used to adjust the current magnitude according to the clock signal output by the second voltage-controlled oscillator.

[0124] The phase adjustment circuit provided in this application adjusts the delay time according to the clock signal output by the second voltage-controlled oscillator. Specifically, it adjusts the current of the adjustable tail current source in the main path according to the clock signal output by the second voltage-controlled oscillator, thereby adjusting the current flowing through the differential input circuit of the main path. Adjusting the current of the adjustable tail current source in the delay path, thereby adjusting the current flowing through the differential input circuit of the delay path, achieves phase adjustment of the phase adjustment circuit.

[0125] The main function of the main path differential input circuit 21 and the delay path differential input circuit 22 is to shift the phase of the input signal, thereby creating a phase difference between the output signal and the input signal. The specific circuit of a phase adjustment circuit is described below with reference to the accompanying drawings.

[0126] See Figure 11 The figure is a circuit diagram of a phase adjustment circuit provided in an embodiment of this application.

[0127] The phase adjustment circuit provided in this application embodiment includes a main path differential input circuit comprising a seventh MOSFET M7 and an eighth MOSFET M8; and a delay path differential input circuit 22 comprising a ninth MOSFET M9 and a tenth MOSFET M10.

[0128] The drains of the seventh MOSFET M7 and the ninth MOSFET M9 serve as the first output terminal VoutP of the phase adjustment circuit. The drains of the eighth MOSFET M8 and the tenth MOSFET M10 serve as the second output terminal VoutN of the phase adjustment circuit.

[0129] The gate of the seventh MOSFET M7 is connected to VinP, and the gate of the eighth MOSFET M8 is connected to VinN.

[0130] The phase adjustment circuit also includes a first resistor R1 and a second resistor R2. The first end of the first resistor R1 and the first end of the second resistor R2 are connected to the power supply VDD. The second end of the first resistor R1 is connected to the drain of M7 and the drain of M9. The second end of the second resistor R2 is connected to the drain of M8 and the drain of M10.

[0131] The positive output signals of the main path differential input circuit and the delay path differential input circuit are superimposed through a common load resistor R1. The negative output signals of the main path differential input circuit and the delay path differential input circuit are superimposed through a common load resistor R2.

[0132] The phase adjustment circuit provided in this application embodiment further includes: a first delay network and a second delay network;

[0133] The gate of the ninth MOSFET M9 is connected to the gate of the eighth MOSFET M8 via the first delay network. The gate of the tenth MOSFET M10 is connected to the gate of the seventh MOSFET M7 via the second delay network.

[0134] This application does not specifically limit the specific structure of the first delay network and the second delay network. For example, the first delay network and the second delay network can be delay networks formed by resistors and capacitors. Figure 11 As shown, the first delay network includes a third resistor R3 and a third capacitor C3, and the second delay network includes a fourth resistor R4 and a fourth capacitor C4. Specifically, the gate of the ninth MOSFET M9 is connected to the gate of the eighth MOSFET M8 via the third resistor R3. The gate of M8 is connected to VinN, and the gate of M9 is connected to VinN via R3. That is, VinN reaches the gate of M9 after the delay of the first delay network. The gate of the tenth MOSFET M10 is connected to the gate of the seventh MOSFET M7 via the fourth resistor R4. The gate of M7 is connected to VinP, and the gate of M10 is connected to VinP via R4. That is, VinP reaches the gate of M10 after the delay of the second delay network. The gate of the ninth MOSFET M9 is grounded via the third capacitor C3. The gate of the tenth MOSFET M10 is grounded via the fourth capacitor C4. Adjusting the parameters of R3 and C3 can adjust the delay time of the first delay network, and adjusting the parameters of R4 and C4 can adjust the delay time of the second delay network.

[0135] The main path adjustable tail current source includes a first bias transistor M11, and the delay path adjustable tail current source includes a second bias transistor M12. The source of the first bias transistor M11 and the source of the second bias transistor M12 are connected to the tail current source. The drain of the first bias transistor M11 is connected to the source of the main path differential input circuit, that is, the drain of M11 is connected to the source of M7. The drain of the second bias transistor M12 is connected to the source of the delay differential input circuit, that is, the drain of M12 is connected to the source of M9.

[0136] The main path adjustable tail current source includes a first bias transistor M11, and the delay path adjustable tail current source includes a second bias transistor M12; the source of the first bias transistor M11 and the source of the second bias transistor M12 are connected to the tail current source; the drain of the first bias transistor M11 is connected to the source of the seventh MOSFET M7 and the source of the eighth MOSFET M8, and the drain of the second bias transistor M12 is connected to the source of the ninth MOSFET M9 and the source of the tenth MOSFET M10.

[0137] The burst clock recovery circuit provided in this application embodiment further includes a controller (not shown in the figure). The controller is used to adjust the gate voltage Sp of the first bias transistor M11 and the gate voltage Sn of the second bias transistor M12 according to the clock signal output by the second voltage-controlled oscillator. Adjusting the gate voltage Sp of the first bias transistor M11 by the controller can change the current IDC flowing through the first bias transistor M11, and adjusting the gate voltage Sn of the second bias transistor M12 by the controller can change the current IDCdelay flowing through the second bias transistor M12. This application embodiment does not specifically limit the specific form of the controller; for example, it can be a chip or an integrated circuit.

[0138] The phase adjustment circuit provided in this application embodiment can adjust the delay phase by controlling the ratio of IDC and IDCdelay. When the phase adjustment circuit is in the reference delay phase state, for example, Sp is set to 0.9V and Sn is set to 0V. When it is necessary to adjust the delay phase, the bias voltage value of Sp can be decreased by increasing Sn, and the current flowing through M11 and M12 can be adjusted to increase the delay phase of the phase adjustment circuit, so that a maximum phase shift of 65° can be achieved between the two pairs of differential input signals of the second voltage-controlled oscillator.

[0139] The following section, with reference to the accompanying diagram, describes a specific implementation method for an adjustable current source.

[0140] See Figure 12 The figure is a schematic diagram of an adjustable current source provided in an embodiment of this application.

[0141] The adjustable current source provided in this application includes: a current source transistor M11, N mirror transistors and N switches; the N mirror transistors and N switches correspond one-to-one; N is an integer greater than or equal to 2.

[0142] Figure 12 Taking N=3 as an example, the adjustable current source provided in this embodiment includes three image transistors, namely M14, M15 and M16. The three image transistors correspond to three switches, namely S1, S2 and S3. S1-S3 can also be MOSFETs, and this embodiment does not make a specific limitation.

[0143] The controller adjusts the switching states of N switches based on the clock signal output from the second voltage-controlled oscillator to change the current of the adjustable current source. Specifically, the controller can control the switching states of the N switches based on the comparison results fed back by the eye diagram monitor. For example, when the eye diagram quality is poor, the amplitude of the adjustment current may change significantly. This can be achieved through pre-testing, with the test results compiled into a table and stored in the controller. The table shows the correspondence between the comparison results and the N switches. The controller can directly look up the state of the N switches based on the comparison results and directly output drive signals to control the operation of the N switches.

[0144] The drain and gate of current source transistor M11 are connected to a preset current source. Each mirror transistor is connected to the gate of current source transistor M11 through a corresponding switch. The drains of N mirror transistors are connected together as the output terminal of the adjustable current source. The sources of all N mirror transistors are grounded. Specifically, the gate of M14 is connected to the gate of M13 through S1, the gate of M15 is connected to the gate of M13 through S2, and the gate of M16 is connected to the gate of M13 through S3. The source of M14 is connected to the source of M13, the source of M15 is connected to the source of M13, and the source of M16 is connected to the source of M13. The drains of M14, M15, and M16 together serve as the output terminal of the adjustable current source. When S1, S2, and S3 are all closed, the output current is the sum of the output currents of M14, M15, and M16.

[0145] This application does not specifically limit the switching states of S1, S2, and S3. The switching combinations of S1-S3 can be set as needed. For example, S1 can be open, and both S2 and S3 can be closed. Alternatively, S1 can be closed, and both S2 and S3 can be open. Or, S1 and S3 can be closed, and S2 can be open. Different switching combinations correspond to different output currents, which will not be listed here.

[0146] This application adjusts the magnitude of the tail current source by controlling the opening and closing combinations of three switches S1, S2, and S3, thereby regulating the amplitude of the injection signal of the second voltage-controlled oscillator.

[0147] Specifically, the dimensions of the tail current sources of the three MOSFETs M14-M16 can be set, where the dimensions are the aspect ratio of the MOSFETs. For example, the aspect ratio of M16:M15:M16 is 4:2:1. Correspondingly, assuming a unit current of I, when S1 is closed alone, the current is 1I; when S2 is closed alone, the current is 2I; and when S3 is closed alone, the current is 4I. When S1, S2, and S3 are all closed, the current is 7I. The above is just an example; different switch combinations can be set according to actual needs to obtain different current values.

[0148] It should be understood that the larger the value of N is, the more current levels there are. The value of N can be selected according to actual needs, and this application does not impose specific limitations on the embodiments.

[0149] Figure 8 and Figure 9 The voltage-controlled oscillator circuit shown is only one example. In addition, voltage-controlled oscillator circuits can also employ... Figure 13 The diagram shows an LC voltage-controlled oscillator circuit that reuses current. Since the structure of voltage-controlled oscillator circuits is relatively mature, it will not be described in detail here.

[0150] The burst clock data recovery circuit provided in this application embodiment can be a standalone chip or integrated with other circuits. One possible implementation is described below.

[0151] Based on the burst clock data recovery circuit provided in the above embodiments, this application also provides an integrated circuit, which will be described in detail below with reference to the accompanying drawings.

[0152] See Figure 14 This figure is a schematic diagram of an integrated circuit provided in an embodiment of this application.

[0153] The integrated circuit IC provided in this application includes: a burst transimpedance amplifier 1000 and a burst clock data recovery circuit 2000 described in the above embodiments;

[0154] The input terminal of the burst clock data recovery circuit 2000 is used to connect to the output terminal of the burst transimpedance amplifier 1000.

[0155] Because the integrated circuit provided in this application includes the burst data recovery circuit described above, the burst data recovery circuit includes two voltage-controlled oscillators connected in series. The output signal of the first voltage-controlled oscillator serves as the injection signal for the second voltage-controlled oscillator. Furthermore, the second voltage-controlled oscillator includes two charge injection circuits. Specifically, the output signal of the first voltage-controlled oscillator is directly input to the first charge injection circuit of the second voltage-controlled oscillator. The output signal of the first voltage-controlled oscillator is injected into the second charge injection circuit after the positive and negative poles are crossed. In other words, the polarities of the signals injected by the two charge injection circuits of the second voltage-controlled oscillator are opposite. Since the polarities of the two pairs of injected signals are opposite, they can cancel out phase noise. Therefore, clock phase noise can be effectively suppressed, clock jitter reduced, and the clock of the data accurately recovered.

[0156] Based on the burst clock data recovery circuit and integrated circuit provided in the above embodiments, this application also provides a device that includes the integrated circuit IC described above.

[0157] An integrated circuit (IC) is used to obtain the clock signal for the received data signal. The data received by the integrated circuit IC can be an electrical signal converted from a photoelectric conversion circuit, or an electrical signal that does not undergo photoelectric conversion.

[0158] One possible implementation involves using an optical module or a host chip; see [link to relevant documentation] for details. Figure 1 and Figure 2 The details of its introduction will not be repeated here.

[0159] Based on the burst clock data recovery circuit, integrated circuit and device provided in the above embodiments, this application also provides a burst clock data recovery method, which will be described in detail below with reference to the accompanying drawings.

[0160] See Figure 15 The figure is a flowchart of a method for recovering burst clock data provided in an embodiment of this application.

[0161] The method for recovering burst clock data provided in this application includes:

[0162] S1501: Receive the recovered data using the first voltage-controlled oscillator;

[0163] The recovered data received by the first voltage-controlled oscillator can be an electrical signal converted by a photoelectric conversion circuit, or it can be an electrical signal that has not undergone photoelectric conversion.

[0164] S1502: Receive the differential signal output by the first voltage-controlled oscillator using the first differential input terminal of the second voltage-controlled oscillator, and receive the cross signal of the differential signal output by the second voltage-controlled oscillator using the second differential input terminal of the second voltage-controlled oscillator.

[0165] S1503: The clock signal for the recovered data output by the second voltage-controlled oscillator.

[0166] The burst clock data recovery method provided in this application does not involve a simple series connection of two voltage-controlled oscillators (VCOs). Instead, the input signal of the second-stage VCO includes two pairs of differential signals. The first pair of differential signals is directly the differential signal output from the first-stage VCO, while the second pair of differential signals is a cross-polled differential signal from the first-stage VCO output. Specifically, the polarities of the second pair of differential signals are crossed, with the positive polarity signal input to the negative input terminal of the second-stage VCO and the negative polarity signal input to the positive input terminal. Because the polarities of the two pairs of injected signals are opposite, they can cancel out phase noise, thus effectively suppressing clock phase noise, reducing clock jitter, and accurately recovering the clock data.

[0167] One possible implementation further includes: retiming the data signal output by the delay circuit according to the clock signal output by the second voltage-controlled oscillator; comparing the retimed data signal with a reference signal, and feeding the comparison result back to the second voltage-controlled oscillator, so that the second voltage-controlled oscillator adjusts the amplitude and phase of the signal at the second differential input terminal according to the comparison result.

[0168] When the relationship between the phase output of the second voltage-controlled oscillator and the phase of the recovered data changes, the clock signal output by the second voltage-controlled oscillator is quickly adjusted by the phase adjustment circuit, so that the phase of the clock signal output by the second voltage-controlled oscillator follows the phase change of the recovered data, and the phase of the output clock signal is shifted forward or backward to fix the phase relationship.

[0169] The phase difference between the two pairs of differential signals of the second voltage-controlled oscillator can be adjusted by a phase adjustment circuit, and the amplitude between the differential signals at both ends of the second voltage-controlled oscillator can be adjusted by an adjustable current source. Thus, the amplitude and phase of the two pairs of differential signals input to the second voltage-controlled oscillator are adjustable, and the control can be adjusted by forming a closed-loop feedback based on the differential signal output by the second voltage-controlled oscillator. This makes the control more flexible and can better reduce clock jitter.

[0170] In this application, the terms "first," "second," etc., are used to distinguish identical or similar items that have essentially the same function. It should be understood that there is no logical or temporal dependency between "first," "second," and "nth," nor does it limit the quantity or order of execution. It should also be understood that although the following description uses the terms "first," "second," etc., to describe various elements, these elements should not be limited by the terms. These terms are merely used to distinguish one element from another.

[0171] It should also be understood that, in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0172] In this application, the term "at least one" means one or more, and the term "multiple" means two or more; for example, multiple devices means two or more devices. The terms "system" and "network" are often used interchangeably herein.

[0173] It should be understood that the terminology used in the description of the various examples herein is for the purpose of describing the particular examples only and is not intended to be limiting. As used in the description of the various examples and in the appended claims, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0174] It should also be understood that the term "and / or" as used herein refers to and covers any and all possible combinations of one or more of the associated listed items. The term "and / or" describes an association between related objects, indicating that three relationships can exist; for example, A and / or B can represent: A alone, A and B simultaneously, or B alone. Additionally, the character " / " in this application generally indicates that the preceding and following related objects are in an "or" relationship.

[0175] It should also be understood that the terms “if” and “if” can be interpreted as meaning “when” or “upon”, or “in response to determination” or “in response to detection”. Similarly, depending on the context, the phrases “if determination…” or “if detection [the stated condition or event]” can be interpreted as meaning “when determination…”, or “in response to determination…”, or “when detection [the stated condition or event]” or “in response to detection [the stated condition or event]”.

[0176] The above description is merely an embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A burst clock data recovery circuit, characterized in that, include: First voltage-controlled oscillator and second voltage-controlled oscillator; The first charge injection circuit of the first voltage-controlled oscillator is used to receive the recovered data; The positive output terminal of the first voltage-controlled oscillator is connected to the positive input terminal of the second charge injection circuit of the second voltage-controlled oscillator, and the negative output terminal of the first voltage-controlled oscillator is connected to the negative input terminal of the second charge injection circuit; The positive output terminal of the first voltage-controlled oscillator is connected to the negative input terminal of the third charge injection circuit of the second voltage-controlled oscillator, and the negative output terminal of the first voltage-controlled oscillator is connected to the positive input terminal of the third charge injection circuit. The differential output terminal of the second voltage-controlled oscillator is used to output the clock signal corresponding to the recovered data.

2. The circuit according to claim 1, characterized in that, Also includes: Continuous-time linear equalizers, delay circuits, and XOR gates; The input terminal of the continuous-time linear equalizer is used to receive the recovered data, the output terminal of the continuous-time linear equalizer is connected to the first input terminal of the XOR gate, and the output terminal of the continuous-time linear equalizer is connected to the second input terminal of the XOR gate through the delay circuit. The output of the XOR gate is connected to the input of the first charge injection circuit.

3. The circuit according to claim 1, characterized in that, The first voltage-controlled oscillator includes: a first voltage-controlled oscillator circuit and a first charge injection circuit; The positive and negative input terminals of the first charge injection circuit are respectively connected to the positive and negative output terminals of the XOR gate; The positive and negative output terminals of the first charge injection circuit are respectively connected to the positive and negative input terminals of the first voltage-controlled oscillator circuit. The positive output terminal of the first voltage-controlled oscillator circuit serves as the positive output terminal of the first voltage-controlled oscillator, and the negative output terminal of the first voltage-controlled oscillator circuit serves as the negative output terminal of the first voltage-controlled oscillator.

4. The circuit according to claim 2, characterized in that, The second voltage-controlled oscillator includes: a second voltage-controlled oscillator circuit, a second charge injection circuit, and the third charge injection circuit; The positive output terminal of the second charge injection circuit and the positive output terminal of the third charge injection circuit are connected to the positive input terminal of the second voltage-controlled oscillator circuit, and the negative output terminal of the second charge injection circuit and the negative output terminal of the third charge injection circuit are connected to the negative input terminal of the second voltage-controlled oscillator circuit. The positive and negative output terminals of the second voltage-controlled oscillator circuit serve as the differential output terminals of the second voltage-controlled oscillator.

5. The circuit according to claim 3, characterized in that, The second voltage-controlled oscillator further includes: an adjustable current source; The source terminal of the third charge injection circuit is connected to the adjustable current source; The adjustable current source is used to adjust the current according to the clock signal output by the second voltage-controlled oscillator.

6. The circuit according to claim 5, characterized in that, The adjustable current source includes: a current source transistor, N mirror transistors, and N switches; the N mirror transistors and the N switches correspond one-to-one; N is an integer greater than or equal to 2. The drain and gate of the current source transistor are connected to a preset current source. Each mirror transistor is connected to the gate of the current source transistor through a corresponding switch. The drains of N mirror transistors are connected together as the output terminal of the adjustable current source. The sources of N mirror transistors are all grounded. The adjustable current source is used to adjust the switching state of the N switches according to the clock signal output by the second voltage-controlled oscillator, so as to change the current of the adjustable current source.

7. The circuit according to claim 4, characterized in that, The second voltage-controlled oscillator further includes: a phase adjustment circuit; The negative input terminal of the phase adjustment circuit is connected to the positive output terminal of the first voltage-controlled oscillator, and the positive input terminal of the phase adjustment circuit is connected to the negative output terminal of the first voltage-controlled oscillator; the first output terminal of the phase adjustment circuit is connected to the positive input terminal of the third charge injection circuit, and the second output terminal of the phase adjustment circuit is connected to the negative input terminal of the third charge injection circuit. The phase adjustment circuit is used to adjust the phase of the differential signal output by the phase adjustment circuit according to the clock signal output by the second voltage-controlled oscillator.

8. The circuit according to claim 7, characterized in that, The phase adjustment circuit includes: a main path differential input circuit, a delay path differential input circuit, a main path adjustable tail current source, and a delay path adjustable tail current source; The positive terminal of the main path differential input circuit is connected to the negative output terminal of the first voltage-controlled oscillator, and the negative terminal of the main path differential input circuit is connected to the positive output terminal of the first voltage-controlled oscillator. The positive terminal of the delay path differential input circuit is connected to the negative output terminal of the first voltage-controlled oscillator, and the negative terminal of the delay path differential input circuit is connected to the positive output terminal of the first voltage-controlled oscillator. The positive output terminal of the main path differential input circuit and the positive output terminal of the delay path differential circuit are connected to the first output terminal of the phase adjustment circuit, and the negative output terminal of the main path differential input circuit and the negative output terminal of the delay path differential circuit are connected to the second output terminal of the phase adjustment circuit. The source terminal of the main path differential input circuit is connected to the main path adjustable tail current source, and the source terminal of the delay path differential input circuit is connected to the delay path adjustable tail current source. The main path adjustable tail current source is used to adjust the current magnitude according to the clock signal output by the second voltage-controlled oscillator. The adjustable tail current source of the delay path is used to adjust the magnitude of the current according to the clock signal output by the second voltage-controlled oscillator.

9. The circuit according to claim 8, characterized in that, The phase adjustment circuit further includes: a first delay network and a second delay network; The positive input terminal of the delay path differential input circuit is connected to the negative input terminal of the phase adjustment circuit through the first delay network, and the negative input terminal of the delay path differential input circuit is connected to the positive input terminal of the phase adjustment circuit through the second delay network.

10. The circuit according to claim 8, characterized in that, The phase adjustment circuit further includes: a controller; The main path adjustable tail current source includes a first bias transistor, and the delay path adjustable tail current source includes a second bias transistor; the source of the first bias transistor and the source of the second bias transistor are connected to the tail current source; the drain of the first bias transistor is connected to the source terminal of the main path differential input circuit, and the drain of the second bias transistor is connected to the source terminal of the delay differential input circuit. The controller is used to adjust the gate voltage of the first bias transistor and the gate voltage of the second bias transistor according to the clock signal output by the second voltage-controlled oscillator.

11. The circuit according to any one of claims 3-10, characterized in that, Both the first voltage-controlled oscillator circuit and the second voltage-controlled oscillator circuit are inductor-capacitor voltage-controlled oscillator circuits.

12. The circuit according to any one of claims 4-10, characterized in that, Also includes: Retiming circuit and eye diagram monitor; The first input terminal of the retiming circuit is connected to the differential output terminal of the second voltage-controlled oscillator, and the second input terminal of the retiming circuit is connected to the output terminal of the delay circuit; the output terminal of the retiming circuit is connected to the input terminal of the eye diagram monitor. The retiming circuit is used to retime the data signal output by the delay circuit according to the clock signal output by the second voltage-controlled oscillator. The eye diagram monitor is used to acquire the retiming data signal output by the retiming circuit, compare the retiming data signal with the reference signal, and feed the comparison result back to the adjustable current source and the phase adjustment circuit of the second voltage-controlled oscillator.

13. An integrated circuit, characterized in that, include: A burst transimpedance amplifier and a burst clock data recovery circuit as described in any one of claims 1-12; The input terminal of the burst clock data recovery circuit is used to connect to the output terminal of the burst transimpedance amplifier.

14. A device, characterized in that, Including the integrated circuit as described in claim 13; The integrated circuit is used to obtain the clock of the received data signal.

15. The device according to claim 14, characterized in that, The device is an optical module or a host chip.

16. A method for recovering burst clock data, characterized in that, include: The recovered data is received using the first voltage-controlled oscillator; The differential signal output by the first voltage-controlled oscillator is received at the first differential input terminal of the second voltage-controlled oscillator, and the cross signal of the differential signal output by the second voltage-controlled oscillator is received at the second differential input terminal of the second voltage-controlled oscillator. The second voltage-controlled oscillator outputs a clock signal for the recovered data.

17. The method according to claim 16, characterized in that, Also includes: The data signal output by the delay circuit is retimed according to the clock signal output by the second voltage-controlled oscillator; The retiming data signal is compared with the reference signal, and the comparison result is fed back to the second voltage-controlled oscillator, so that the second voltage-controlled oscillator adjusts the amplitude and phase of the signal at the second differential input terminal according to the comparison result.

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