Method for producing a composite structure comprising a single-crystalline SiC thin layer on a carrier substrate made of SiC

Abstract

The invention relates to a method for manufacturing a composite structure comprising a thin layer of monocrystalline silicon carbide arranged on a carrier substrate made of silicon carbide, the method comprising the following steps: a) providing an initial substrate made of monocrystalline silicon carbide, b) epitaxially growing a monocrystalline silicon carbide donor layer on the initial substrate to form the donor substrate, c) implanting light species ions into the donor layer to form a buried brittle plane, d) performing direct liquid injection chemical vapor deposition at a temperature below 1000° C. to form the carrier layer directly on the free surface of the donor layer, e) performing separation along the buried brittle plane to form an intermediate composite structure comprising the thin layer located on the carrier layer on the one hand and forming the remainder of the donor substrate on the other hand, f) applying a heat treatment to the intermediate composite structure at a temperature between 1000° C. and 1800° C., g) mechanically and / or chemically treating the composite structure.

Description

Technical Field

[0001] The invention relates to the field of semiconductor materials for microelectronic components. The invention relates in particular to a method for producing a composite structure comprising a thin layer of monocrystalline silicon carbide on a carrier substrate made of silicon carbide. Background Art

[0002] Interest in silicon carbide (SiC) has increased significantly over the past few years because of the semiconductor material's ability to improve energy processing capabilities. SiC is increasingly being used to make innovative power devices to meet the needs of emerging areas of electronics, especially such as electric vehicles.

[0003] Power devices and integrated power systems based on single crystal silicon carbide are able to manage much higher power densities than their conventional silicon counterparts, and do so with smaller active area sizes. To further limit the size of power devices on SiC, it is advantageous to fabricate vertical components rather than lateral components. To do this, the structure must allow vertical conduction between electrodes arranged on the front side of the SiC structure and electrodes arranged on the back side.

[0004] However, single-crystal SiC substrates intended for use in the microelectronics industry are more expensive and difficult to supply in large sizes. Therefore, it is advantageous to utilize thin layer transfer solutions to manufacture composite structures that typically include single-crystal SiC thin layers located on cheaper carrier substrates. One well-known thin layer transfer solution is Smart Cut TM Process, which is based on the implantation of light ions and assembly by direct bonding. Such a process makes it possible, for example, to manufacture a composite structure comprising a thin layer of single-crystalline SiC (c-SiC), taken from a c-SiC donor substrate, in direct contact with a carrier substrate made of polycrystalline SiC (p-SiC), allowing vertical conduction. However, achieving high-quality direct bonding by molecular adhesion between two substrates made of c-SiC and p-SiC remains difficult, as managing the surface state and roughness of these substrates is complex.

[0005] Various methods derived from this method are also known according to the prior art. For example, F. Mu et al. (ECS Transactions, 86 (5) 3-21, 2018) realized direct bonding after activating the surface to be assembled by bombarding with argon (SAB: "surface active bonding"): this treatment before bonding produces a very high density of side bonds, which promotes the formation of covalent bonds at the assembly interface and thus produces a high binding energy. However, this method has the disadvantage of producing an amorphous layer at the surface of the single-crystalline SiC donor substrate, which can have an adverse effect on the vertical conduction between the c-SiC thin layer and the carrier substrate made of p-SiC.

[0006] A solution to this problem has been proposed, in particular in EP 3 168 862, which consists in implanting dopant species into the amorphous layer in order to restore its electrical properties. The main drawbacks of this method are its complexity and cost.

[0007] Also known is US Pat. No. 8,436,363, which describes a method for manufacturing a composite structure comprising a thin layer of c-SiC arranged on a metal carrier substrate, the thermal expansion coefficient of which matches the thermal expansion coefficient of the thin layer. The manufacturing method comprises the following steps:

[0008] - forming a buried brittle plane in the c-SiC donor substrate, defining the thin layer between the buried brittle plane and the front surface of the donor substrate;

[0009] - depositing a metal layer, for example a tungsten layer or a molybdenum layer, on the front surface of the donor substrate to form a carrier substrate having a sufficient thickness to act as a stiffener;

[0010] - Separation along the buried brittle plane to form a composite structure comprising the metal carrier substrate and the c-SiC thin layer on the one hand and the remainder of the c-SiC donor substrate on the other hand.

[0011] However, this manufacturing method is incompatible when the material forming the carrier substrate is p-SiC which needs to be deposited at temperatures higher than 1200° C. (the usual temperature for manufacturing p-SiC). In particular, at these high temperatures, the growth kinetics of the cavities present in the buried brittle planes are faster than those of the p-SiC layer and the thickness required for the strengthening effect is not reached before blistering begins to occur (which is associated with deformation of the layer vertically aligned with the cavities).

[0012] Independently of the layer transfer technique used, the additional problem arises of providing a composite structure comprising a thin c-SiC layer which is of very high quality, in particular free from extended defects (or has a very low extended defect density) which are liable to affect the performance quality and reliability of the power devices to be manufactured on said thin layer.

[0013] Purpose of the Invention

[0014] The present invention relates to an alternative solution to the solutions in the prior art and aims to completely or partially overcome the above-mentioned disadvantages. The present invention relates in particular to a method for manufacturing a composite structure comprising a high-quality c-SiC thin layer on a carrier substrate made of SiC. Summary of the invention

[0015] The invention relates to a method for producing a composite structure comprising a thin layer of monocrystalline silicon carbide arranged on a carrier substrate made of silicon carbide. The method comprises the following steps:

[0016] a) providing an initial substrate made of single-crystalline silicon carbide,

[0017] b) epitaxially growing a donor layer of single-crystal silicon carbide on the initial substrate to form a donor substrate, the donor layer having a crystal defect density less than the crystal defect density of the initial substrate,

[0018] c) implanting light species ions into the donor layer to form a buried brittle plane that defines the thin layer between the buried brittle plane and a free surface of the donor layer,

[0019] d) performing direct liquid injection-chemical vapor deposition at a temperature below 1000° C. to form a support layer directly on the free surface of the donor layer, the support layer being formed of an at least partially amorphous SiC matrix,

[0020] e) separating along said buried brittle plane to form, on the one hand, an intermediate composite structure comprising said thin layer on said carrier layer and, on the other hand, the remainder of said donor substrate,

[0021] f) applying a heat treatment to the intermediate composite structure at a temperature between 1000° C. and 1800° C. to crystallize the carrier layer and form a polycrystalline carrier substrate,

[0022] g) subjecting the composite structure to a mechanical and / or chemical treatment, the treatment being applied to the free side of the carrier substrate being the back side of the composite structure, and / or to the free side of the thin layer being the front side of the composite structure.

[0023] Other advantageous and non-limiting features according to the invention alone or in any technically feasible combination:

[0024] said deposition step d) is carried out at a temperature between 100° C. and 700° C. or even preferably between 200° C. and 600° C.;

[0025] The deposition step d) is performed at a pressure between 1 Torr and 500 Torr;

[0026] The precursor used during said deposition step d) is selected from polysilylethylene and disilabutane;

[0027] at the end of said deposition step d), said support layer has a thickness greater than or equal to 10 micrometers, or even a thickness greater than or equal to 50 micrometers, or even a thickness greater than or equal to 100 micrometers, or even a thickness greater than or equal to 200 micrometers;

[0028] Between step d) and step e), applying chemical etching, mechanical grinding and / or mechanochemical polishing to the free surface of the carrier layer;

[0029] Step a) comprises forming a single crystal conversion layer on the initial substrate to convert basal plane dislocation defects of the initial substrate into thread edge dislocation defects;

[0030] The epitaxial growth step b) is carried out at a temperature higher than 1200°C and preferably between 1500°C and 1650°C;

[0031] The separation step e) is carried out at a temperature higher than the deposition temperature of step d);

[0032] The separation step e) is carried out during the deposition step d), and preferably at the end of step d);

[0033] The separation step e) and the crystallization step f) are carried out during the same thermal treatment;

[0034] Step g) comprises simultaneously performing mechanical chemical polishing on the front and back sides of the composite structure;

[0035] The method comprises the step of repairing the remaining portion of the donor substrate for the purpose of reuse as an initial substrate or as a donor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Other features and advantages of the present invention will become apparent from the following detailed description of the invention given with reference to the accompanying drawings, in which:

[0037] Figure 1 A composite structure manufactured according to the manufacturing method of the present invention is shown;

[0038] Figure 2a to Figure 2g The steps of the manufacturing method according to the present invention are shown;

[0039] Figure 3a and Figure 3b The steps of the manufacturing method according to the present invention are shown. DETAILED DESCRIPTION

[0040] In the specification, the same reference numerals may be used for the same type of elements in the drawings. The drawings are schematic representations and are not drawn to scale for clarity. Specifically, the thickness of a layer along the z-axis is not proportional to the lateral dimensions along the x-axis and y-axis; and the relative thickness of the layers relative to each other are not necessarily relative in the drawings.

[0041] The present invention relates to a method for manufacturing a composite structure 1( Figure 1 ), the composite structure comprising a thin layer 10 of monocrystalline silicon carbide arranged on a carrier substrate 20 made of silicon carbide. The carrier substrate 20 is advantageously polycrystalline ("p-SiC" will be used to refer to polycrystalline SiC).

[0042] The method first comprises step a) ( Figure 2a ): An initial substrate 11 made of single-crystal silicon carbide is provided. In the remainder of the specification, "c-SiC" will be used to refer to single-crystal silicon carbide.

[0043] The initial substrate 11 is preferably in the form of a wafer having a diameter of 100 mm, 150 mm or 200 mm, or even 300 mm or even 450 mm, and a thickness typically between 300 and 800 microns. The initial substrate 11 has a front side 11 a and a back side 11 b. The surface roughness of the front side 11 a is advantageously chosen to be less than 1 nm Ra (average roughness), as measured by an atomic force microscope (AFM) in a scan of 20 microns by 20 microns.

[0044] Then, the method comprises step b) ( Figure 2b ): epitaxially growing a single-crystal silicon carbide donor layer 110 on an initial substrate 11 to form a donor substrate 111. The epitaxial growth step is performed in such a way that the crystal defect density of the donor layer 110 is smaller than that of the initial substrate 11.

[0045] Typically, the initial substrate 11 made of c-SiC has a 4H or 6H polytype, a cut angle of less than 4.0° relative to the <11-20> crystal axis ±0.5°, and a micropipe density less than or equal to 5 / cm 2 , or even less than 1 / cm 2 For example, when doped with N (nitrogen), it preferably has a resistivity between 0.015 ohm.cm and 0.030 ohm.cm. It can be selected to have a resistivity of generally less than or equal to 3000 / cm 2 The initial substrate 11 has a low density of basal plane dislocation (BPD) defects. 2 C-SiC substrates with BPD densities of orders of magnitude are reasonably available, which facilitates their supply.

[0046] It is desirable that the crystal quality of the donor layer 110 of the c-SiC thin layer 10 that will form the composite structure 1 at the end of the method of the invention is greater than that of the initial substrate 11, in order to meet the specifications required for the vertical component to be manufactured on said thin layer 10. Various types of extension defects exist in the c-SiC layer or substrate. These extension defects can affect the performance and reliability of the component. In particular, for bipolar components, defects of the BPD type are fatal: in particular, Schottky stacking faults (or SSFs) extend from dislocations when the recombination energy of electron-hole pairs is available. The extension of SSF stacking faults within the active region of the component causes an increase in the through-state resistance of the component.

[0047] The c-SiC donor layer 110 is thus manufactured so as to have a relative humidity less than or equal to 1 / cm 2 BPD defect density.

[0048] To this end, the epitaxial growth step b) is carried out at a temperature higher than 1200° C. and preferably between 1500° C. and 1650° C. The precursors used are silane (SiH4), propane (C3H8) or ethylene (C2H4); and the carrier gas can be hydrogen with or without argon.

[0049] The low content of BPD defects in the donor layer 110 is obtained by promoting the conversion of BPD defects present in the initial substrate 11 into screw edge dislocations (TEDs).

[0050] According to a particular embodiment, step a) comprises forming a single-crystalline conversion layer 13 ( Figure 3a ), preferably a single-crystal conversion layer based on c-SiC, in order to maximize the conversion of BPD defects into TED defects of the initial substrate 11. To this end, it is advantageous to choose a low offcut angle close to 4° for the initial c-SiC substrate 11, to increase the in-situ etching performed before the epitaxial growth, to target a large growth rate (typically greater than 5 μm / h), and finally to choose growth conditions for the single-crystal conversion layer 13, in which the C / Si ratio in the precursor flow is close to 1.

[0051] Then step b) comprises performing an epitaxial growth of a donor layer 110 on said conversion layer 13 ( Figure 3b According to this particular embodiment, a BPD defect density less than or equal to 1 / cm 2 Or even less than 0.1 / cm 2 c-SiC donor layer 110. Moreover, the probability of bipolar degradation (probability of holes reaching the BPD / TED transition point) at the end of the method according to the invention is negligible (<0.1%), and the single-crystalline conversion layer 13 is not intended to be transferred into the composite structure 1. Prior art techniques intended to reduce bipolar degradation include incorporating a composite layer (nitrogen doped with more than 1E 18 at / cm 3 ). This layer can be 10 μm thick and greater than 5 E 18 / cm 3 The probability of the existence of holes is reduced to 0.1% relative to the substrate structure not including the composite layer at the expense of the concentration of . In the present invention, since the single crystal conversion layer 13 is not transferred, the probability of holes reaching the nucleation point of bipolar degradation (BPD-TED conversion point or any BPD point) is at least less than 0.1%, or even very close to 0%.

[0052] It should be noted that, before the epitaxial growth step b), a conventional sequence of cleaning or etching of the initial substrate 11 may be performed, which aims to eliminate all or some particles, metallic or organic contaminants or native oxide layers that may be present on the front side 11 a of the initial substrate 11 .

[0053] The manufacturing method according to the invention also comprises a step c) of implanting light species ions into the donor layer 110, up to a given depth representing the desired thickness of the thin layer 10, and in all cases without reaching the initial substrate 11 (and / or the conversion layer 13, when this layer is present). This implantation generates in the donor layer 110 a buried brittle plane 12 which delimits the thin layer 10 between said buried brittle plane 12 and the free surface 11a of said donor layer 110 ( Figure 2c ).

[0054] The light material injected is preferably hydrogen, helium or both of them. TM As is well known in the art, these light substances will form microcavities around a given depth, distributed in a thin layer parallel to the free surface 11a of the donor layer 110 (ie parallel to the plane (x, y) in the figure). For simplicity, this thin layer is called a buried brittle plane 12.

[0055] The energy used to implant the light species is selected to reach a given depth in the donor layer 110 .

[0056] Typically, the energy is between 10keV and 250keV and between 5 E 16 / cm 2 to 1 E 17 / cm 2 Hydrogen ions are implanted at a dose between 100 nm and 1500 nm to define a thin layer 10 having a thickness of about 100 nm to 1500 nm.

[0057] It should be noted that, prior to the ion implantation step, a protective layer may be deposited on the free face of the donor layer 110. For example, the protective layer may be composed of a material such as silicon oxide or silicon nitride.

[0058] The method according to the invention then comprises step d) Figure 2d ): Direct liquid injection-chemical vapor deposition (DLI-CVD) is performed at a temperature below 1000° C. and preferably below 900° C. to form the support layer 20 ′ directly on the free surface of the donor layer 110. The deposition step d) can be performed at a temperature between 100° C. and 800° C., between 100° C. and 700° C. or even advantageously between 200° C. and 600° C. The pressure in the deposition chamber is preferably defined between 1 Torr and 500 Torr.

[0059] The DLI-CVD deposition technique provides a good yield between supplied material (precursors) and achieved deposition thickness without requiring the use of chlorinated precursors which are limiting due to cost and environmental constraints.

[0060] Preferably, the DLI-CVD deposition involves a disilabutane precursor or a polysilylethylene precursor, either pure or diluted. Other precursors such as trichloromethylsilane, ethylenetrichlorosilane, dichloromethylvinylsilane, tetraethylsilane, tetramethylsilane, diethylmethylsilane, bistrimethylsilylmethane or hexamethyldisilane may alternatively be used.

[0061] In Guilhaume Boisselier's paper (2013, " Such a technique is described in "Pulsed liquid injection - chemical vapor deposition of chromium, silicon and hafnium carbides" ("Pulsed liquid injection - chemical vapor deposition of chromium, silicon and hafnium carbides") which is directed to the application of depositing ceramic coatings onto parts to protect them during very high temperature processing of, for example, steel or alloy metal parts.

[0062] The Applicant has developed a DLI-CVD deposition step d) for a completely different application, namely the formation of a carrier layer 20 ′ on a c-SiC donor layer 110 , in order to obtain, at the end of the manufacturing method, a composite structure 1 intended for use in the microelectronics field.

[0063] The deposited support layer 20' forms a SiC matrix comprising amorphous SiC and reaction byproducts derived from the precursors used during deposition and formed from carbon chains. In addition, the SiC matrix may optionally include crystalline SiC grains.

[0064] The DLI-CVD technique can provide a deposition rate greater than or equal to 10 micrometers / hour or even greater than 50 micrometers / hour or even greater than 100 micrometers / hour. Given the average deposition temperature, the deposition rate does not need to be very high (beyond obvious economic reasons), because the thermally activated growth of the cavities of the buried brittle plane 12 remains slow in these temperature ranges, making it easy to obtain a thickness of the carrier layer 20 ′ that ensures a reinforcing effect relative to the buried brittle plane 12.

[0065] At the end of step d), the carrier layer 20 ′ has a thickness greater than or equal to 10 microns, 50 microns, 100 microns or even greater than or equal to 200 microns. The stack 211 obtained from step d) comprises the carrier layer 20 ′ arranged on a donor layer 110 , itself arranged on an initial substrate 11 .

[0066] Then, the method according to the invention comprises step e) Figure 2e ): separation is carried out along the buried brittle plane 12 to form, on the one hand, the intermediate composite structure 1 ′ and, on the other hand, the remaining part 111 ′ of the donor substrate.

[0067] According to an advantageous embodiment, the separation step e) is performed by applying a thermal treatment to the stack 211 at a separation temperature higher than the deposition temperature of step d). In particular, the microcavities present in the buried brittle plane 12 follow the growth kinetics until the start of a rupture wave which will propagate across the entire extent of the buried brittle plane 12 and cause the separation between the intermediate composite structure 1 'and the rest 111 ' of the initial substrate. In practice, the temperature may be between 950°C and 1200°C and preferably between 1000°C and 1200°C, depending on the implantation conditions of step c).

[0068] According to an alternative embodiment, the separation step e) is performed by applying a mechanical stress to the stack 211, optionally preceded by a heat treatment to embrittle the buried brittle plane 12. For example, the stress may be applied by inserting a tool (e.g. a razor blade) close to the buried brittle plane 12. By way of example, the separation stress may be of the order of a few GPa, preferably greater than 2 GPa.

[0069] According to yet another embodiment, step e) of separating along the buried brittle plane 12 is performed during or directly at the end of the DLI-CVD deposition step d), in particular when the deposition temperature is in the range of 900-1000°C.

[0070] The manufacturing method according to the invention then comprises a step f) of applying a heat treatment at a temperature between 1000° C. and 1800° C. to the intermediate composite structure 1 ′ in order to crystallize the carrier layer 20 ′ and form a polycrystalline carrier substrate 20 .

[0071] The annealing atmosphere may in particular comprise a gas such as argon, nitrogen, hydrogen, helium or a mixture of these gases.

[0072] This annealing has the effect of eliminating hydrogen from the carrier layer 20 ′ and crystallizing the SiC matrix in the form of polycrystalline SiC.

[0073] Conventional furnaces for processing multiple structures simultaneously (batch annealing) can be used for the crystallization heat treatment. The typical duration of the treatment is between a few minutes and a few hours.

[0074] It is optionally possible to envisage an in-situ crystallization heat treatment in the DLI deposition chamber, with a typical duration of the order of several minutes.

[0075] Advantageously, the temperature increase and decrease ramps will be limited, for example, to less than 20° C. / minute, less than 5° C. / minute or even less than 1° C. / minute, in order to limit the appearance of cracks or structural defects in the crystalline layer.

[0076] After step f), a composite structure 1 is obtained which comprises a thin layer 10 of monocrystalline silicon carbide arranged on a carrier substrate 20 made of polycrystalline silicon carbide.

[0077] The deposition parameters (step d) and the crystallization annealing parameters (step f) are determined so that the carrier substrate 20 has:

[0078] - good electrical conductivity, ie less than or equal to 0.03 ohm.cm, or even less than or equal to 0.01 ohm.cm,

[0079] - High thermal conductivity, i.e. greater than or equal to 150 W.m -1 .K -1 , or even greater than or equal to 200W.m -1 .K -1 ,

[0080] - and a coefficient of thermal expansion close to that of the thin layer 10, ie, at room temperature, typically between 3.8 E -6 / K to 4.2 E -6 / K.

[0081] In order to obtain these properties, the carrier substrate 20 preferably has the following structural features: polycrystalline structure, 3C SiC type grains,

[111] orientation, an average size of 1 μm to 50 μm in the main plane of the substrate, N-type doping with a final resistivity less than or equal to 0.03 ohm.cm or even less than or equal to 0.01 ohm.cm.

[0082] Furthermore, a non-insulated interface between the donor layer 110 and the carrier substrate 20 is a preferred target. It is generally expected that the specific resistance of the interface is typically less than 1 mohm.cm 2 . In order to ensure the conductivity of the interface, the native oxide present on the free face of the donor layer 110 is removed by HF (hydrofluoric acid) deoxidation, either wet or dry, before the deposition step d). Alternatively, the overdoping of at least the first deposited nanometers of the carrier layer 20 ′ can be performed by introducing dopant substances during the DLI-CVD deposition step d). It should be noted that, in general, dopant substances can be introduced during the deposition step d) (in various doses) according to the doping level and the target conductivity of the carrier substrate 20, which conductivity will take effect at the end of the crystallization annealing in step f).

[0083] It is also advantageous to apply a cleaning sequence to the donor substrate 111 prior to deoxidation and / or forming the carrier layer 20 ′ in order to remove all or some of the particles, metals or organic contaminants that may be present on the free face of the donor substrate 111 .

[0084] As known per se, at the end of separation step e), the free face 10a of the thin layer 10 of the composite structure 1 has a surface roughness comprised between 5 nm RMS and 100 nm RMS (measured with an atomic force microscope (AFM) on a scan of 20 microns x 20 microns).

[0085] Thus, a step g) of mechanical and / or chemical treatment of the composite structure 1 is envisaged ( Figure 2f ) to smooth the free surface 10a of the thin layer 10 and / or to correct the thickness uniformity of the composite structure 1.

[0086] Step g) may include mechanical chemical polishing (MCP) of the free surface 10a of the thin layer 10, typically removing material of the order of 50nm to 1000nm, to obtain a final roughness of less than 0.5nm RMS (on an AFM field of 20×20μm), or even less than 0.3nm. Step g) may also include chemical or plasma treatment (cleaning or etching), for example, SC1 / SC2 type cleaning (standard cleaning 1, standard cleaning 2) and / or HF (hydrofluoric acid), and / or N2, Ar, CF4 plasma, to further improve the quality of the free surface 10a of the thin layer 10.

[0087] It is important to note that crystallization of the carrier layer 20 ′ often results in cracks or structural defects in the crystallized layer (which forms the carrier substrate 20 ), which has an impact on its mechanical and electrical qualities.

[0088] Therefore, step g) may include mechanical chemical polishing (MCP) and / or chemical treatment (etching or cleaning) and / or mechanical treatment (straightening) of the back side 20b of the carrier substrate 20 to eliminate all or some cracks and structural defects, thereby improving the thickness uniformity of the carrier substrate 20 and the roughness on the back side 20b. The thickness removed at the back side may be between about 100 microns and several microns.

[0089] A roughness of less than 0.5 nm RMS (measured with an atomic force microscope (AFM) over a 20 micron x 20 micron field) is desired to produce a vertical component for which at least one metal electrode will be present on the back side 20b of the composite substrate 1 .

[0090] Polishing or straightening of the edges of the composite structure 1 may also be carried out during this step g) in order to make the shape of its rounded contour and the cut edge waste compatible with the requirements of the microelectronic manufacturing process.

[0091] It should be noted that the treatment applied to the back side 20b of the carrier substrate 20 can optionally be applied to the free face of the carrier layer 20' just before the separation step e) (i.e. before the front side 10a of the composite structure 1 is exposed) in order to limit its contamination, in particular during contaminating or restrictive treatments such as chemical etching or mechanical grinding (straightening).

[0092] According to an advantageous embodiment, the mechanochemical treatment step g) comprises simultaneously polishing (MCP) the front side 10a and the back side 20b of the composite structure 1 in order to smooth said structure 1 and improve its thickness uniformity. The polishing parameters may differ between the front side and the back side, the smoothing of c-SiC surfaces and p-SiC surfaces generally requiring different consumables. When the carrier substrate 20 is made of p-SiC, in particular for the back side 20b, the mechanical component of the polishing is advantageous in order to limit the preferential attack of the chemical component of the polishing on the grain bonds. By way of example, the polishing parameters such as the rotation speed (polishing head and plate), the pressure, the concentration and the physical properties of the abrasive (i.e. the diamond nanoparticles having a diameter between about 10 nm and 1 μm) may be modified in order to strengthen the mechanical component.

[0093] Optionally, step g) is followed by a step g′) of heat treatment at a temperature between 1000° C. and 1800° C. for about 1 hour and at most a few hours. The purpose of this step is to stabilize the composite structure 1 by ensuring that structural or surface defects are still present in and / or on the thin layer 10 and, where appropriate, by substantially evolving the crystalline structure of the carrier substrate 20 so that the structure 1 is compatible with subsequent high-temperature heat treatments required for manufacturing components on the thin layer 10.

[0094] The method according to the invention may comprise a second step h)( Figure 2g ): epitaxial growth of an additional layer 10' of monocrystalline silicon carbide on the thin layer 10 of the composite structure 1. This step is applied when the production of the component requires a working layer 100 of relatively large thickness (typically about 5 to 50 microns).

[0095] The temperature applied during this step h) may be limited so as to limit the stresses induced in the working layer 100 (corresponding to the combination of the thin layer 10 and the additional layer 10 ′) by the composite structure 1 .

[0096] Finally, the manufacturing method may include the step of repairing the remaining portion 111' of the donor substrate for the purpose of reusing it as the initial substrate 1 or as the donor substrate 111. This repair step is based on the surface 110'a ( Figure 2e ), by surface or edge mechanochemical polishing and / or by mechanical straightening and / or by wet chemical etching or dry chemical etching.

[0097] Preferably, the thickness of the donor layer 110 formed in step b) is defined so that the remaining portion 111 ′ of the donor substrate 111 can be reused as the donor substrate 111 at least twice.

[0098] Preferably, when the conversion layer 13 is present, care will be taken to keep said layer intact, i.e. always keep a portion of the donor layer 10 on the rest 111 ' of the donor substrate. Thus, when said portion of the donor layer 10 is not sufficient to manufacture the composite structure 1, only an epitaxial growth step of the donor layer 10 is required, without a previous growth step of the conversion layer 13.

[0099] Example:

[0100] According to a non-limiting implementation example, the initial substrate 11 provided in step a) of the manufacturing method is a wafer made of c-SiC of 4H polytype, with an orientation of 4.0° relative to the <11-20> crystal axis ±0.5°, a diameter of 150 mm and a thickness of 350 μm.

[0101] Prior to step b) of epitaxial growth of the c-SiC donor layer 110 , a conventional RCA cleaning sequence (Standard Clean 1 + Standard Clean 2) is performed on the initial substrate 11 , followed by Caro's acid (a mixture of sulfuric acid and hydrogen peroxide) and then HF (hydrofluoric acid).

[0102] In an epitaxial chamber, growth is performed at a temperature of 1650° C. using precursors such as silane (SiH4) and propane (C3H8) or ethylene (C2H4) to produce a c-SiC donor layer 110 with a thickness of 30 μm (growth rate: 10 μm / hour). The donor layer has a 1 / cm 2 BPD defect density of the order of magnitude.

[0103] At 150 keV energy and 6 E 16 H+ / cm 2 Hydrogen ions are implanted at a dose of 100 nm through the free surface of the donor layer 110. Thus, a buried brittle plane 12 is created in the initial substrate 11 at a depth of about 800 nm.

[0104] A cleaning sequence of RCA+Caro's acid is performed on the donor substrate 111 to remove potential contaminants from the free surface of the donor layer 110 .

[0105] DLI-CVD deposition is performed on the donor layer 110 at a temperature of 800° C. using a disilabutane (DSB) precursor at a pressure of 50 Torr for 60 minutes to achieve a thickness of at least 150 microns for the support layer 20′. Under these conditions, the support layer 20′ is deposited in the form of an amorphous SiC matrix including reaction byproducts originating from the deposited precursors.

[0106] The stack 211 is then annealed at 1000° C. for 50 minutes and separation is carried out during said annealing on the buried brittle plane 12. At the end of this separation step e), the intermediate composite structure 1 ′ formed by the thin layer 10 and the carrier layer 20 ′ is separated from the remainder 111 ′ of the donor substrate.

[0107] Then, the intermediate composite structure 1 ′ is subjected to a crystallization heat treatment at 1200° C. for 1 hour in an argon atmosphere to form a polycrystalline SiC carrier substrate 20 of the composite structure 1 .

[0108] Alternatively, separation and crystallization can be performed during the same heat treatment, for example, at 1200° C. under a neutral atmosphere.

[0109] Mechanical correction of the rear face of the carrier substrate 20 by removing approximately 15 to 30 micrometers makes it possible to eliminate cracks and structural defects resulting from the crystallization of the SiC matrix.

[0110] Then, one or more mechanochemical polishing operations are performed to restore the surface roughness of the thin layer 10 and the back side of the carrier substrate 20, followed by a conventional cleaning sequence.

[0111] It goes without saying that the invention is not limited to the described embodiments and examples, and that implementation variations thereof may be conceived without departing from the scope of the invention as defined by the claims.

Claims

1. A method for producing a composite structure (1), comprising a thin layer (10) of single-crystalline silicon carbide arranged on a carrier substrate (20) made of silicon carbide, the method comprising the following steps: a) providing an initial substrate (11) made of single-crystalline silicon carbide, b) epitaxially growing a donor layer (110) of single-crystal silicon carbide on the initial substrate (11) to form a donor substrate (111), wherein the crystal defect density of the donor layer (110) is less than the crystal defect density of the initial substrate (11), c) implanting light material ions into the donor layer (110) to form a buried brittle plane (12), wherein the buried brittle plane (12) defines the thin layer (10) between the buried brittle plane (12) and a free surface of the donor layer (110), d) performing direct liquid injection-chemical vapor deposition at a temperature below 1000° C. to form a support layer (20′) directly on the free surface of the donor layer (110), the support layer (20′) being formed of an at least partially amorphous SiC matrix, e) separating along the buried brittle plane (12) to form, on the one hand, an intermediate composite structure (1') comprising the thin layer (10) on the carrier layer (20') and, on the other hand, the remainder (111') of the donor substrate, f) applying a heat treatment to the intermediate composite structure (1') at a temperature between 1000°C and 1800°C in order to crystallize the carrier layer (20') and form a polycrystalline carrier substrate (20), g) subjecting the composite structure (1) to a mechanical and / or chemical treatment, wherein the mechanical and / or chemical treatment is applied to the free surface of the carrier substrate (20) and / or to the free surface of the thin layer (10), the free surface of the carrier substrate (20) being the back surface of the composite structure (1) and the free surface of the thin layer (10) being the front surface of the composite structure (1).

2. The manufacturing method according to claim 1, wherein: The deposition step d) is performed at a temperature between 100°C and 700°C.

3. The manufacturing method according to claim 1, wherein: The deposition step d) is performed at a temperature between 200°C and 600°C.

4. The manufacturing method according to any one of claims 1 to 3, wherein: The deposition step d) is performed at a pressure between 1 Torr and 500 Torr.

5. The manufacturing method according to any one of claims 1 to 3, wherein: The precursor used during said deposition step d) is chosen from polysilylethylene and disilabutane.

6. The manufacturing method according to any one of claims 1 to 3, wherein: At the end of said deposition step d), said support layer (20') has a thickness greater than or equal to 10 micrometers.

7. The manufacturing method according to any one of claims 1 to 3, wherein: At the end of said deposition step d), said support layer (20') has a thickness greater than or equal to 50 micrometers.

8. The manufacturing method according to any one of claims 1 to 3, wherein: At the end of said deposition step d), said support layer (20') has a thickness greater than or equal to 100 micrometers.

9. The manufacturing method according to any one of claims 1 to 3, wherein: At the end of said deposition step d), said support layer (20') has a thickness greater than or equal to 200 micrometers.

10. The manufacturing method according to claim 1, wherein: Between step d) and step e), chemical etching, mechanical grinding and / or mechanochemical polishing are applied to the free surface of the carrier layer (20').

11. The manufacturing method according to claim 1, wherein: Step a) comprises forming a single crystal conversion layer (13) on the initial substrate (11) to convert basal plane dislocation defects of the initial substrate (11) into thread edge dislocation defects.

12. The manufacturing method according to claim 1, wherein: The epitaxial growth step b) is carried out at a temperature above 1200°C.

13. The manufacturing method according to claim 1, wherein: The epitaxial growth step b) is performed at a temperature between 1500°C and 1650°C.

14. The manufacturing method according to claim 1, wherein: The separation step e) is carried out at a temperature higher than the deposition temperature of step d).

15. The manufacturing method according to claim 1, wherein: The separation step e) is performed during the deposition step d).

16. The manufacturing method according to claim 1, wherein: The separation step e) is carried out at the end of step d).

17. The manufacturing method according to claim 1, wherein: Said separation step e) and said crystallization step f) are carried out during the same thermal treatment.

18. The manufacturing method according to claim 1, wherein: Step g) comprises simultaneously performing mechanical chemical polishing on the front side and the back side of the composite structure (1).

19. The manufacturing method according to claim 1, comprising the following steps: The remaining portion (111') of the donor substrate is repaired for the purpose of being reused as an initial substrate or as a donor substrate.

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