Semiconductor Structure and Method of Manufacturing the Same

Abstract

A semiconductor structure and a manufacturing method thereof, providing a P-type semiconductor layer (11), the P-type semiconductor layer comprising a GaN-based material, and an upper surface (11a) being a Ga surface; forming a first N-type semiconductor layer (12) on the P-type semiconductor layer, the first N-type semiconductor layer comprising a GaN-based material, and an upper surface (12a) being an N surface; wet etching to remove the first N-type semiconductor layer in a partial region, exposing the P-type semiconductor layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] III-nitrides are the third-generation new semiconductor materials following the first- and second-generation semiconductor materials such as Si and GaAs. Among them, GaN, as a wide-bandgap semiconductor material, has many advantages, such as high saturation drift velocity, large breakdown voltage, excellent carrier transport performance, and the ability to form ternary alloys such as AlGaN and InGaN and quaternary alloys such as AlInGaN, and it is easy to fabricate PN junctions based on GaN. In view of this, in recent years, GaN-based materials and semiconductor devices have been widely and deeply studied, and the MOCVD technology for growing GaN-based materials has become increasingly mature; in the research of semiconductor devices, remarkable achievements and great developments have been made in the research of optoelectronic devices such as GaN-based LEDs and LDs, and microelectronic devices such as GaN-based HEMTs.

[0003] Currently, there is still room for improvement in GaN-based semiconductor devices. One of the problems lies in that it is difficult to fabricate the contact electrodes on the P-type GaN-based semiconductor layer.

[0004] In view of this, it is necessary to provide a new semiconductor structure and a manufacturing method thereof to solve the above technical problems. Summary of the Invention

[0005] The object of the present invention is to provide a semiconductor structure and a manufacturing method thereof to improve the performance of GaN-based semiconductor devices.

[0006] To achieve the above object, on the one hand, the present invention provides a manufacturing method of a semiconductor structure, including:

[0007] Providing a P-type semiconductor layer, the P-type semiconductor layer includes a GaN-based material, and the upper surface is a Ga surface;

[0008] Forming a first N-type semiconductor layer on the P-type semiconductor layer, the first N-type semiconductor layer includes a GaN-based material, and the upper surface is an N surface;

[0009] Wet etching to remove the first N-type semiconductor layer in some regions, exposing the P-type semiconductor layer.

[0010] The GaN crystal has a wurtzite structure, in which the Ga and N atomic layers are stacked in a hexagonal layer of ABABAB. Each Ga (N) atom forms a bond with the surrounding 4 N (Ga) atoms in a diamond-like tetrahedral structure. It should be noted that, taking the Ga-N bond parallel to the C axis (

[0001] crystal orientation) as a reference, if the Ga atom in each Ga-N bond is farther from the lower surface, the upper surface is the Ga surface; if the N atom in each Ga-N bond is farther from the lower surface, the upper surface is the N surface.

[0011] Optionally, before forming the first N-type semiconductor layer on the P-type semiconductor layer, activate the P-type doping ions in the P-type semiconductor layer.

[0012] Optionally, the P-type semiconductor layer is located on the second N-type semiconductor layer; the first N-type semiconductor layer in the base region is wet-etched.

[0013] The manufacturing method further includes: dry-etching to remove the first N-type semiconductor layer and the P-type semiconductor layer in the collector region, exposing the second N-type semiconductor layer.

[0014] Optionally, providing the P-type semiconductor layer includes: providing a semiconductor substrate, forming a second N-type semiconductor layer on the semiconductor substrate; forming the P-type semiconductor layer on the second N-type semiconductor layer.

[0015] Or it includes: providing a second N-type semiconductor layer; forming the P-type semiconductor layer on the second N-type semiconductor layer.

[0016] Optionally, form a collector on the second N-type semiconductor layer in the collector region, form a base on the P-type semiconductor layer in the base region, and form an emitter on the first N-type semiconductor layer in the emitter region.

[0017] Optionally, forming a first N-type semiconductor layer with an N surface on the P-type semiconductor layer is achieved by: directly bonding the Ga surface of the first N-type semiconductor layer to the Ga surface of the P-type semiconductor layer.

[0018] Optionally, forming a first N-type semiconductor layer with an N surface on the P-type semiconductor layer is achieved by: during the process of forming the first N-type semiconductor layer, making the N surface of the first N-type semiconductor layer face upward through the way of polarity inversion.

[0019] On the other hand, the present invention provides a semiconductor structure, including:

[0020] A P-type semiconductor layer and a first N-type semiconductor layer distributed from bottom to top; wherein:

[0021] The P-type semiconductor layer comprises a GaN-based material, and its upper surface is a Ga plane; the first N-type semiconductor layer comprises a GaN-based material, and its upper surface is an N plane; a partial area of the Ga plane of the P-type semiconductor layer is exposed.

[0022] Optionally, it further comprises a second N-type semiconductor layer, and the P-type semiconductor layer is located on the second N-type semiconductor layer; the second N-type semiconductor layer in the collector region and the P-type semiconductor layer in the base region are exposed.

[0023] A collector is provided on the exposed second N-type semiconductor layer, a base is provided on the P-type semiconductor layer, and an emitter is provided on the first N-type semiconductor layer.

[0024] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0025] 1) In the method for manufacturing the semiconductor structure of the present invention, first a P-type semiconductor layer is provided, and the P-type semiconductor layer comprises a GaN-based material; then a first N-type semiconductor layer is formed on the P-type semiconductor layer, and the first N-type semiconductor layer comprises a GaN-based material; wherein, in the provided P-type semiconductor layer, the upper surface is controlled to be a Ga plane; when forming the first N-type semiconductor layer, the upper surface is controlled to be an N plane. Utilizing the directionality of wet etching, etching starts from the N plane of the first N-type semiconductor layer and automatically stops at the Ga plane of the P-type semiconductor layer, thereby avoiding over-etching. If dry etching is used, when dry etching stops, over-etching of the P-type semiconductor layer will occur; during the dry etching process, nitrogen atoms in the GaN-based material preferentially escape, resulting in an increase in the number of electron carriers. For the P-type semiconductor layer, some hole carriers will be neutralized, causing a decrease in the hole carrier concentration and even surface inversion; thus, compared with dry etching, wet etching can avoid the above problems in the process of forming the electrical connection structure of the P-type semiconductor layer.

[0026] 2) In the optional solution, before forming the first N-type semiconductor layer on the P-type semiconductor layer, the P-type doping ions in the P-type semiconductor layer are activated. This solution can provide an escape path for the released H atoms and improve the quality of the PN junction. The reason is as follows: When growing P-type GaN-based materials by MOCVD (Metal-organic Chemical Vapor Deposition) technology, there are a large number of H atoms in the MOCVD growth environment. If not removed, the acceptor dopant Mg in GaN will be passivated by a large number of H atoms and no holes will be generated; in addition, a large number of passivated and unbonded Mg ions will enter the N-type GaN-based material layer grown thereon, causing the PN junction interface to be blurred and some N-type GaN-based material layers to be compensated and the electron concentration to decrease, and in severe cases, the PN junction will fail.

[0027] 3) In an alternative embodiment, the P-type semiconductor layer is located on the second N-type semiconductor layer; the first N-type semiconductor layer in the base region is wet-etched.

[0028] The manufacturing method further includes: dry-etching to remove the first N-type semiconductor layer and the P-type semiconductor layer in the collector region, exposing the second N-type semiconductor layer. In other words, the semiconductor structure fabricated by the present invention can be a PN junction or an NPN bipolar transistor.

[0029] 4) In an alternative embodiment, forming a first N-type semiconductor layer with an N-face on the upper surface on the P-type semiconductor layer is achieved by: a) directly bonding the Ga-face of the first N-type semiconductor layer to the Ga-face of the P-type semiconductor layer; or b) during the formation of the first N-type semiconductor layer, making the N-face of the first N-type semiconductor layer face upward through a polarity inversion method. Research shows that the above two methods have reliable processes. Description of the Drawings

[0030] Figure 1 is a schematic structural diagram of the semiconductor structure according to the first embodiment of the present invention;

[0031] Figure 2 is Figure 1 a flowchart of the manufacturing method of the semiconductor structure in

[0032] Figure 3 is a schematic structural diagram of the semiconductor structure according to the second embodiment of the present invention;

[0033] Figure 4 is Figure 3 a flowchart of the manufacturing method of the semiconductor structure in

[0034] Figure 5 is a flowchart of the manufacturing method of the semiconductor structure according to the third embodiment of the present invention;

[0035] Figure 6 is a schematic structural diagram of the semiconductor structure according to the fourth embodiment of the present invention;

[0036] Figure 7 is a schematic structural diagram of the semiconductor structure according to the fifth embodiment of the present invention;

[0037] Figure 8 is Figure 7 a flowchart of the manufacturing method of the semiconductor structure in

[0038] Figure 9 is a schematic structural diagram of the semiconductor structure according to the sixth embodiment of the present invention;

[0039] Figure 10 is a schematic structural diagram of the semiconductor structure according to the seventh embodiment of the present invention.

[0040] For the convenience of understanding the present invention, all the reference numerals appearing in the present invention are listed below:

[0041] Semiconductor structures 1, 2, 3, 4, 5, 6; semiconductor substrate 10

[0042] P-type semiconductor layer 11; upper surface 11a of the P-type semiconductor layer

[0043] First N-type semiconductor layer 12; upper surface 12a of the first N-type semiconductor layer

[0044] Positive electrode 131; negative electrode 132

[0045] Second N-type semiconductor layer 14; collector region 1a

[0046] Base region 1b; emitter region 1c

[0047] Collector C; base B

[0048] Emitter E Detailed implementation manners

[0049] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following detailed description of specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0050] Figure 1 It is a schematic structural diagram of the semiconductor structure according to the first embodiment of the present invention.

[0051] Referring to Figure 1 as shown, the semiconductor structure 1 includes:

[0052] A semiconductor substrate 10, a P-type semiconductor layer 11, and a first N-type semiconductor layer 12 distributed from bottom to top; wherein:

[0053] The P-type semiconductor layer 11 includes a GaN-based material, and the upper surface 11a is a Ga surface; the first N-type semiconductor layer 12 includes a GaN-based material, and the upper surface 12a is an N surface; a partial region of the Ga surface of the P-type semiconductor layer 11 is exposed.

[0054] It can be seen that a PN junction is formed between the P-type semiconductor layer 11 and the first N-type semiconductor layer 12 in this embodiment.

[0055] The semiconductor substrate 10 can be sapphire, silicon carbide, silicon, GaN, or diamond.

[0056] The GaN-based material can be at least one of GaN, AlGaN, InGaN, and AlInGaN.

[0057] The upper surface 11a of the P-type semiconductor layer 11 being a Ga plane means that, with the Ga-N bond parallel to the C axis (

[0001] crystal orientation) as a reference, the Ga atom in each Ga-N bond is farther from the semiconductor substrate 10. It can be understood that, at this time, the lower surface of the P-type semiconductor layer 11 is an N plane.

[0058] The upper surface 12a of the first N-type semiconductor layer 12 being an N plane means that, with the Ga-N bond parallel to the C axis (

[0001] crystal orientation) as a reference, the N atom in each Ga-N bond is farther from the semiconductor substrate 10. It can be understood that, at this time, the lower surface of the first N-type semiconductor layer 12 is a Ga plane.

[0059] The exposed area of the upper surface 11a of the P-type semiconductor layer 11 and the upper surface 12a of the first N-type semiconductor layer 12 can form an electrical connection structure, such as a metal interconnection structure, to lead out the electrical signals of the P-type semiconductor layer 11 and the first N-type semiconductor layer 12 respectively.

[0060] For Figure 1 the semiconductor structure 1 in Figure 2 a corresponding manufacturing method is provided in an embodiment of the present invention.

[0061] First, step S1: Referring to Figure 2 and Figure 1 as shown, a P-type semiconductor layer 11 is formed on the semiconductor substrate 10. The P-type semiconductor layer 11 includes a GaN-based material, and the upper surface 11a is a Ga plane.

[0062] The semiconductor substrate 10 can be sapphire, silicon carbide, silicon, GaN, diamond, etc., and this embodiment does not limit this.

[0063] The GaN-based material of the P-type semiconductor layer 11 can be at least one of GaN, AlGaN, InGaN, AlInGaN, and this embodiment does not limit this either.

[0064] Taking the material of the P-type semiconductor layer 11 as GaN as an example, it can be grown by MOCVD technology. Exemplarily, NH 3 , TMGa are respectively the N source and the Ga source, and H 2 is the carrier gas. Specifically, GaN can be grown while performing P-type ion doping. The P-type ion can be Mg, and the Mg source can be CP 2 Mg. In other alternative solutions, the P-type doping ion can be at least one of calcium, carbon, beryllium, yttrium, and zinc.

[0065] In an alternative embodiment, a buffer layer may be grown on the semiconductor substrate 10 first, and then a P-type semiconductor layer 11 may be grown on the buffer layer. The buffer layer can reduce the screw dislocation (TD) density in the P-type semiconductor layer 11 and the TD bending caused by the lateral growth mechanism.

[0066] In an alternative embodiment, the upper surface 11a of the P-type semiconductor layer 11 can be made the Ga plane by: during the formation of the P-type semiconductor layer 11, the Ga plane of the P-type semiconductor layer 11 is oriented upward by epitaxial growth.

[0067] Next, step S2: Still referring to Figure 2 and Figure 1 as shown, a first N-type semiconductor layer 12 is formed on the P-type semiconductor layer 11. The first N-type semiconductor layer 12 includes a GaN-based material, and the upper surface 12a is the N plane.

[0068] The GaN-based material of the first N-type semiconductor layer 12 refers to the GaN-based material of the P-type semiconductor layer 11, and the two materials may be the same or different.

[0069] Taking the material of the first N-type semiconductor layer 12 as GaN for example, it can be grown by MOCVD technology. Exemplarily, NH 3 , TMGa are the N source and Ga source respectively, and H 2 is the carrier gas. The N-type doping ions can be at least one of silicon, germanium, and oxygen.

[0070] In an alternative embodiment, the upper surface 12a of the first N-type semiconductor layer 12 can be made the N plane by: directly bonding the Ga plane of the first N-type semiconductor layer 12 to the Ga plane of the P-type semiconductor layer 11.

[0071] In an alternative embodiment, the epitaxial layer of the first N-type semiconductor layer 12 for bonding can be prepared by the following method: a sacrificial layer is set during the preparation of the GaN-based material epitaxial layer with the upper surface being the Ga plane, and then a GaN-based material epitaxial layer with the upper surface being the Ga plane and a predetermined thickness is continuously prepared on the sacrificial layer. The sacrificial layer can be, for example, porous GaN, GaN after H implantation, etc. After preparation, through processes such as annealing, the GaN-based material epitaxial layer with the upper surface being the Ga plane above the sacrificial layer can be peeled off from the sacrificial layer, and the surface of the peeled GaN-based material epitaxial layer in contact with the sacrificial layer is the N plane.

[0072] In an alternative embodiment, the upper surface 12a of the first N-type semiconductor layer 12 can be made the N plane by: during the formation of the first N-type semiconductor layer 12, the N plane of the first N-type semiconductor layer 12 is oriented upward by polar inversion.

[0073] The polarity inversion method means that: First, a first N-type semiconductor layer 12 with a Ga surface on the upper surface 12a is epitaxially grown; then, a polarity inversion element is added during the epitaxial growth. The polarity inversion element is, for example, Mg, etc., to achieve an N surface facing upward.

[0074] In addition, it is also possible to: First, a polarity inversion layer is fabricated on the P-type semiconductor layer 11, and the material is, for example, Al 2 O 3 ; then, a GaN-based material is continuously grown on the polarity inversion layer to achieve an N surface facing upward.

[0075] Next, step S3: Still referring to Figure 2 and Figure 1 shown, a part of the first N-type semiconductor layer 12 in some regions is removed by wet etching to expose the P-type semiconductor layer 11.

[0076] The wet etching solution is, for example, a KOH solution, which is corrosive on the N surface but non-corrosive on the Ga surface. Since the upper surface of the P-type semiconductor layer 11 is a Ga surface, the etching process can automatically stop at the upper surface of the P-type semiconductor layer 11, and over-etching of the P-type semiconductor layer 11 will not occur.

[0077] In the prior art, dry etching is generally used to pattern the first N-type semiconductor layer 12. When the dry etching stops, over-etching of the P-type semiconductor layer 11 will occur. During the dry etching process, nitrogen atoms in the GaN-based material preferentially escape, resulting in an increase in the number of electron carriers in the P-type semiconductor layer 11, which will neutralize some hole carriers, causing a decrease in the hole carrier concentration and even surface inversion. Therefore, compared with dry etching, wet etching can avoid the above problems during the patterning process.

[0078] In subsequent processes, an electrical connection structure, such as a metal interconnection structure, can also be formed on the exposed area of the upper surface 11a of the P-type semiconductor layer 11 and the upper surface 12a of the first N-type semiconductor layer 12 to respectively lead out the electrical signals of the P-type semiconductor layer 11 and the first N-type semiconductor layer 12.

[0079] Figure 3 is a schematic structural diagram of the semiconductor structure of the second embodiment of the present invention. Referring to Figure 3 shown, the semiconductor structure 2 of the second embodiment is substantially the same as the semiconductor structure 1 of the first embodiment, and the difference is only that: the semiconductor substrate 10 is omitted.

[0080] It should be noted that, taking the Ga-N bond parallel to the C axis (

[0001] crystal direction) as a reference, if the Ga atom in each Ga-N bond is farther away from the lower surface, the upper surface is a Ga surface.

[0081] Figure 4 is Figure 3Flowchart of the method for fabricating the semiconductor structure in Figure 4 As shown in

[0082] Figure 5 is the flowchart of the method for fabricating the semiconductor structure of the third embodiment of the present invention. Refer to Figure 5 and Figure 2 As shown, the fabrication method of this Embodiment 3 is substantially the same as that of Embodiments 1 and 2, with the only difference being: adding step S11 to activate the P-type doping ions in the P-type semiconductor layer 11. Step S11 is carried out between step S1 and S2.

[0083] The P-type doping ions can be magnesium, and the activation can be achieved by high-temperature annealing. When growing P-type GaN-based materials by MOCVD technology, due to the presence of a large number of H atoms in the MOCVD growth environment, if the H atoms cannot be released, the acceptor dopant Mg in GaN is likely to form covalent bonds with H atoms and cannot generate holes, that is, it is passivated by H atoms. The upper surface 11a of the P-type semiconductor layer 11 in this step is unobstructed, so it is easy to release H atoms. A large number of P-type doping ions Mg can form covalent bonds with the atoms in the GaN-based material, that is, they are activated and avoid passivation.

[0084] In addition, a large number of Mg forming covalent bonds with the atoms in the GaN-based material can also prevent free Mg ions from entering the first N-type GaN-based material layer grown on it, improving the quality of the PN junction.

[0085] Figure 6 is the structural schematic diagram of the semiconductor structure of the fourth embodiment of the present invention. The semiconductor structure 3 of this Embodiment 4 is substantially the same as the semiconductor structures 1 and 2 of Embodiments 1, 2, and 3, with the only difference being: the exposed area of the upper surface 11a of the P-type semiconductor layer 11 has a positive electrode 131, and the upper surface 12a of the first N-type semiconductor layer 12 has a negative electrode 132.

[0086] There is an ohmic contact between the positive electrode 131 and the P-type semiconductor layer 11, and between the negative electrode 132 and the first N-type semiconductor layer 12.

[0087] The materials of the positive electrode 131 and the negative electrode 132 can both be metals or semiconductor materials with good conductivity after doping.

[0088] Correspondingly, for the manufacturing method, it includes: Step S4, forming a positive electrode 131 on the exposed area of the upper surface 11a of the P-type semiconductor layer 11, and forming a negative electrode 132 on the upper surface 12a of the first N-type semiconductor layer 12.

[0089] The forming methods of the positive electrode 131 and the negative electrode 132 can be electroplating or metal deposition methods.

[0090] Figure 7 It is a schematic structural diagram of the semiconductor structure according to the fifth embodiment of the present invention. Refer to Figure 7 As shown, the semiconductor structure 4 of this Embodiment 5 is substantially the same as the semiconductor structures 1 and 3 of Embodiments 1, 2, and 4, and the only difference is that: the semiconductor substrate 10 is the second N-type semiconductor layer 14; the first N-type semiconductor layer 12 is located in the emitter region 1c, and the second N-type semiconductor layer 14 in the collector region 1a and the P-type semiconductor layer 11 in the base region 1b are exposed.

[0091] In other embodiments, if the semiconductor substrate 10 is omitted, the semiconductor structure 4 includes:

[0092] The second N-type semiconductor layer 14, the P-type semiconductor layer 11, and the first N-type semiconductor layer 12 distributed from bottom to top.

[0093] It can be seen that the second N-type semiconductor layer 14, the P-type semiconductor layer 11, and the first N-type semiconductor layer 12 form an NPN bipolar transistor.

[0094] Figure 8 is Figure 7 The flowchart of the manufacturing method of the semiconductor structure in Figure 8 and Figure 2 As shown, the only difference is that: in Step S01, a second N-type semiconductor layer 14 is provided; in Step S1", a P-type semiconductor layer 11 is formed on the second N-type semiconductor layer 14, the P-type semiconductor layer 11 includes a GaN-based material, and the upper surface 11a is the Ga surface; in Step S21, the first N-type semiconductor layer 12 and the P-type semiconductor layer 11 in the collector region 1a are removed by dry etching to expose the second N-type semiconductor layer 14; in Step S3', the first N-type semiconductor layer 12 in the base region 1b is wet-etched to expose the P-type semiconductor layer 11.

[0095] In Step S01, the second N-type semiconductor layer 14 can be a GaN-based material, and the GaN-based material can be at least one of GaN, AlGaN, InGaN, and AlInGaN. The direction of the GaN covalent bond in the second N-type semiconductor layer 14 is not limited in this embodiment.

[0096] Step S21 is executed first, and then Step S3' is executed. In Step S21, the dry etching can be the ICP etching method, and the reaction gas can be Cl 2, the assist gas can be N 2 .

[0097] When the dry etching stops, the second N-type semiconductor layer 14 will be over-etched. However, during the dry etching process, the nitrogen atoms in the GaN-based material preferentially escape, resulting in an increase in the number of electron carriers. For the second N-type semiconductor layer 14, the surface resistivity will be reduced, which is beneficial to reducing the contact resistance of the electrical connection structure on the second N-type semiconductor layer 14.

[0098] Figure 9 is a schematic structural diagram of the semiconductor structure according to the sixth embodiment of the present invention. The semiconductor structure 5 of the sixth embodiment is substantially the same as the semiconductor structure 4 of the fifth embodiment, except that: the exposed second N-type semiconductor layer 14 has a collector C, the P-type semiconductor layer 11 has a base B, and the first N-type semiconductor layer 12 has an emitter E.

[0099] Between the collector C and the second N-type semiconductor layer 14, between the base B and the P-type semiconductor layer 11, and between the emitter E and the first N-type semiconductor layer 12 are all ohmic contacts.

[0100] The materials of the collector C, the base B, and the emitter E can all be metals or semiconductor materials with good conductivity after doping.

[0101] Figure 10 is a schematic structural diagram of the semiconductor structure according to the seventh embodiment of the present invention. Refer to Figure 10 As shown, the semiconductor structure 6 of the seventh embodiment is substantially the same as the semiconductor structure 5 of the sixth embodiment and the semiconductor structure 4 of the fifth embodiment, except that: it further includes a second N-type semiconductor layer 14, and the second N-type semiconductor layer 14 is located on the semiconductor substrate 10.

[0102] The method for forming the second N-type semiconductor layer 14 on the semiconductor substrate 10 can be the MOCVD method. The direction of the GaN covalent bond in the second N-type semiconductor layer 14 is not limited in this embodiment.

[0103] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, comprising: providing a P-type semiconductor layer (11), the P-type semiconductor layer (11) comprising a GaN-based material, and having an upper surface (11a) being a Ga surface; forming a first N-type semiconductor layer (12) on the P-type semiconductor layer (11), the first N-type semiconductor layer (12) comprising a GaN-based material, and having an upper surface (12a) being an N surface; wet etching to remove the first N-type semiconductor layer (12) in a partial region, exposing the P-type semiconductor layer (11); wherein, by using the directionality of wet etching, etching starts from the N surface of the first N-type semiconductor layer and automatically stops at the Ga surface of the P-type semiconductor layer; wherein, forming the first N-type semiconductor layer (12) having an upper surface (12a) being an N surface on the P-type semiconductor layer (11) by: directly bonding the Ga surface of the first N-type semiconductor layer (12) to the Ga surface of the P-type semiconductor layer (11).

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, before forming the first N-type semiconductor layer (12) on the P-type semiconductor layer (11), activating P-type doping ions in the P-type semiconductor layer (11).

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, the P-type semiconductor layer (11) is located on a second N-type semiconductor layer (14); the first N-type semiconductor layer (12) in the base region (1b) is wet etched; the manufacturing method further comprises: dry etching to remove the first N-type semiconductor layer (12) and the P-type semiconductor layer (11) in the collector region (1a), exposing the second N-type semiconductor layer (14).

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, providing the P-type semiconductor layer (11) comprises: providing a semiconductor substrate (10), forming a second N-type semiconductor layer (14) on the semiconductor substrate (10); forming the P-type semiconductor layer (11) on the second N-type semiconductor layer (14); or comprising: providing the second N-type semiconductor layer (14); forming the P-type semiconductor layer (11) on the second N-type semiconductor layer (14).

5. The method for manufacturing a semiconductor structure according to claim 3 or 4, characterized in that, forming a collector (C) on the second N-type semiconductor layer (14) in the collector region (1a), forming a base (B) on the P-type semiconductor layer (11) in the base region (1b), and forming an emitter (E) on the first N-type semiconductor layer (12) in the emitter region (1c).

6. A semiconductor structure, characterized in that, formed by the manufacturing method according to any one of claims 1-5, comprising: a P-type semiconductor layer (11) and a first N-type semiconductor layer (12) distributed from bottom to top; wherein: The P-type semiconductor layer (11) comprises a GaN-based material, and the upper surface (11a) is a Ga plane; the first N-type semiconductor layer (12) comprises a GaN-based material, and the upper surface (12a) is an N plane; a partial region of the Ga plane of the P-type semiconductor layer (11) is exposed.

7. The semiconductor structure according to claim 6, characterized in that, it further comprises a second N-type semiconductor layer (14), the P-type semiconductor layer (11) is located on the second N-type semiconductor layer (14); the second N-type semiconductor layer (14) in the collector region (1a) and the P-type semiconductor layer (11) in the base region (1b) are exposed.

8. The semiconductor structure according to claim 7, characterized in that, a collector (C) is provided on the exposed second N-type semiconductor layer (14), a base (B) is provided on the P-type semiconductor layer (11), and an emitter (E) is provided on the first N-type semiconductor layer (12).

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