Power semiconductor device, method for manufacturing the same, and power conversion device

Abstract

A power semiconductor device (100) that miniaturizes an insulating substrate and suppresses poor connection includes an insulating substrate (10), a semiconductor element (21), and a printed substrate (30). The semiconductor element (21) is bonded to one main surface of the insulating substrate (10). The printed substrate (30) is bonded so as to face the semiconductor element (21). A main electrode (21b) and a signal electrode (21c) are formed in the semiconductor element (21). The printed substrate (30) includes a core material (31), a first conductor layer (32), and a second conductor layer (33). The second conductor layer (33) has a bonding pad (33a). A missing portion (36C) is formed in the printed substrate (30). A metal column portion (51C) is arranged to be inserted into the missing portion (36C) and reach the insulating substrate (10). The signal electrode (21c) and the bonding pad (33a) are connected by a metal wire (90). The metal column portion (51C) and the insulating substrate (10) are bonded.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device for electric power and a method for manufacturing the same. Background Art

[0002] Semiconductor devices for electric power are used for controlling the main electric power of devices in a wide range of fields such as industrial equipment, electric railways, and home appliances. In particular, semiconductor devices for electric power loaded in industrial equipment are required to be miniaturized, have high heat dissipation, and high reliability. In a semiconductor device for electric power, power semiconductor elements such as an IGBT (Insulated Gate Bipolar Transistor) and an FWD (Free Wheeling Diode) are mounted on an insulating substrate with high heat dissipation. Wiring is connected to the surface electrodes of the power semiconductor elements mounted on the insulating substrate. Thereby, a circuit of the semiconductor device for electric power is formed.

[0003] In this way, in a semiconductor device for electric power, wiring is connected above the insulating substrate. Therefore, the area of the expensive insulating substrate becomes large. Thus, the cost of the semiconductor device for electric power increases. In addition, if the area of the insulating substrate becomes large, the outer shape of the semiconductor device for electric power becomes large. Therefore, for example, in Japanese Patent Laid-Open No. 2014-199955 (Patent Document 1), a semiconductor element bonded to the insulating substrate and a metal foil formed on a printed substrate arranged to face the semiconductor element are connected by a column electrode formed on the printed substrate. The printed substrate is arranged to overlap the insulating substrate, and thus it is considered that the area of the insulating substrate is suppressed to be small.

[0004] Prior Art Documents

[0005] Patent Documents

[0006] Patent Document 1: Japanese Patent Laid-Open No. 2014-199955 Summary of the Invention

[0007] Problems to be Solved by the Invention

[0008] In Japanese Patent Laid-Open No. 2014-199955, the column electrode is connected to the top of the emitter electrode of the semiconductor element. The area of the emitter electrode is very small in a plan view. Therefore, it is difficult to align the emitter electrode and the column electrode so that the column electrode overlaps directly above the emitter electrode. Therefore, a positional deviation may occur between the emitter electrode and the column electrode, and a connection failure may occur between the two.

[0009] The present disclosure has been made in view of the above problems. An object thereof is to provide a semiconductor device for electric power, a method for manufacturing the same, and a power conversion device including the power conversion device that can miniaturize an insulating substrate and suppress connection failures.

[0010] Means for Solving the Problem

[0011] The semiconductor device for power use according to the present disclosure includes an insulating substrate, a semiconductor element, and a printed circuit board. The semiconductor element is bonded to one main surface of the insulating substrate. The printed circuit board is bonded so as to face the semiconductor element. A main electrode and a signal electrode are formed in the semiconductor element. The printed circuit board includes a core material, a first conductor layer formed on a first main surface on the semiconductor element side of the core material, and a second conductor layer formed on a second main surface on the side opposite to the first main surface of the core material. The second conductor layer has a bonding pad. A missing portion in which the first conductor layer is partially missing is formed in the printed circuit board. A metal column portion that penetrates the missing portion and reaches the insulating substrate and is connected to the printed circuit board through a first conductive member is further provided. The signal electrode and the bonding pad are connected by a metal wire. The metal column portion and the insulating substrate are bonded through a second conductive member.

[0012] In the method for manufacturing a semiconductor device for power use according to the present disclosure, an insulating substrate on which a semiconductor element having a signal electrode formed thereon is bonded to one main surface is prepared. A printed circuit board is prepared, which includes a core material, a first conductor layer formed on a first main surface of the core material, and a second conductor layer formed on a second main surface on the side opposite to the first main surface of the core material, and a missing portion in which the first conductor layer is partially missing is formed. A metal column portion that penetrates the missing portion and extends outside the missing portion is bonded to the missing portion through a first conductive member. The printed circuit board is arranged so as to face the semiconductor element, and the metal column portion and the insulating substrate are bonded through a second conductive member. The signal electrode and the bonding pad included in the second conductor layer are connected by a metal wire.

[0013] Advantageous Effects of the Invention

[0014] According to the present disclosure, it is possible to provide a semiconductor device for power use that miniaturizes the insulating substrate and can suppress connection failures, a manufacturing method thereof, and a power conversion device including the power conversion device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic plan view showing the overall form of the semiconductor device for power use according to the first example of Embodiment 1 as viewed from above.

[0016] Figure 2 is a schematic cross-sectional view of a part along the line II-II of the semiconductor device for power use according to the first example of Embodiment 1. Figure 1 of the II-II line.

[0017] Figure 3 is Figure 1 A schematic plan view of a part where a semiconductor element is particularly arranged in the semiconductor device for power use.

[0018] Figure 4 is a schematic top view showing Figure 1 the form of the core material of a printed circuit board and the conductor layer on the lower side in the Z direction among semiconductor devices for electric power, in particular.

[0019] Figure 5 is a schematic top view showing Figure 1 the form of the core material of a printed circuit board and the conductor layer on the upper side in the Z direction among semiconductor devices for electric power, in particular.

[0020] Figure 6 is a schematic enlarged cross-sectional view of part VI surrounded by a dashed line in Figure 2 the first example of Embodiment 1.

[0021] Figure 7 is a schematic top view showing the overall form of a semiconductor device for electric power in the second example of Embodiment 1 when viewed from above.

[0022] Figure 8 is a schematic cross-sectional view of a part along line VIII-VIII in Figure 7 the semiconductor device for electric power in the second example of Embodiment 1.

[0023] Figure 9 is a schematic enlarged cross-sectional view of part IX surrounded by a dashed line in Figure 8 the third example of Embodiment 1.

[0024] Figure 10 is a schematic top view showing the overall form of a semiconductor device for electric power in the third example of Embodiment 1 when viewed from above.

[0025] Figure 11 is a schematic cross-sectional view of a part along line XI-XI in Figure 10 the semiconductor device for electric power in the third example of Embodiment 1.

[0026] Figure 12 is a schematic enlarged cross-sectional view of part XII surrounded by a dashed line in Figure 11 the third example of Embodiment 1.

[0027] Figure 13 is a schematic cross-sectional view of a part along line II-II in Figure 1 the first process of the manufacturing method of the semiconductor device for electric power in the first example of Embodiment 1.

[0028] Figure 14 is a schematic cross-sectional view of a part along line II-II in Figure 1 the first process of the manufacturing method of the semiconductor device for electric power in the third example of Embodiment 1.

[0029] Figure 15It is a schematic cross-sectional view of a part along the II-II line of the second process of the manufacturing method of the semiconductor device for power use showing the third example of Embodiment 1. Figure 1 along the II-II line.

[0030] Figure 16 It is a schematic cross-sectional view of a part along the II-II line of the second process of the manufacturing method of the semiconductor device for power use showing the first example of Embodiment 1. Figure 1 along the II-II line.

[0031] Figure 17 It is a schematic cross-sectional view of a part along the II-II line of the third process of the manufacturing method of the semiconductor device for power use showing the first example of Embodiment 1. Figure 1 along the II-II line.

[0032] Figure 18 It is a schematic cross-sectional view of a part along the II-II line of the fourth process of the manufacturing method of the semiconductor device for power use showing the first example of Embodiment 1. Figure 1 along the II-II line.

[0033] Figure 19 It is a schematic plan view showing the overall form of the semiconductor device for power use of Embodiment 2 when viewed from above.

[0034] Figure 20 It is a schematic cross-sectional view of a part along the XX-XX line among the semiconductor devices for power use of Embodiment 2. Figure 19 along the XX-XX line.

[0035] Figure 21 It is Figure 19 a schematic plan view of a part where semiconductor elements are particularly arranged among the semiconductor devices for power use.

[0036] Figure 22 It is showing Figure 19 a schematic plan view of the core material of the printed circuit board and the conductor layer on the lower side in the Z direction among the semiconductor devices for power use.

[0037] Figure 23 It is showing Figure 19 a schematic plan view of the core material of the printed circuit board and the conductor layer on the upper side in the Z direction among the semiconductor devices for power use.

[0038] Figure 24 It is a schematic plan view showing the overall form of the semiconductor device for power use of Embodiment 3 when viewed from above.

[0039] Figure 25 It is Figure 24 a schematic plan view of a part where semiconductor elements are particularly arranged among the semiconductor devices for power use.

[0040] Figure 26is a schematic top view showing Figure 24 in a power semiconductor device, particularly the core material of a printed circuit board and the form of the conductor layer on the lower side in the Z direction.

[0041] Figure 27 is a schematic top view showing Figure 24 in a power semiconductor device, particularly the core material of a printed circuit board and the form of the conductor layer on the upper side in the Z direction.

[0042] Figure 28 is a schematic top view showing the overall form of the power semiconductor device of Embodiment 4.

[0043] Figure 29 is a schematic cross-sectional view of a part along the Figure 28 XXIX - XXIX line in the power semiconductor device of Embodiment 4.

[0044] Figure 30 is a schematic enlarged cross-sectional view of the part XXX surrounded by a dashed line in Figure 29 in Embodiment 4.

[0045] Figure 31 is Figure 28 a schematic top view of a part where semiconductor elements are particularly arranged in a power semiconductor device.

[0046] Figure 32 is a schematic top view showing Figure 28 in a power semiconductor device, particularly the core material of a printed circuit board and the form of the conductor layer on the lower side in the Z direction.

[0047] Figure 33 is a schematic cross-sectional view of a part along the Figure 28 XXXIII - XXXIII line in the power semiconductor device of Embodiment 4.

[0048] Figure 34 is a block diagram showing the structure of a power conversion system to which the power conversion device of Embodiment 5 is applied.

[0049] (Explanation of Reference Numerals)

[0050] 10: Insulating substrate; 11: Insulating layer; 12: Fourth conductor layer; 13: Third conductor layer; 20: Semiconductor chip; 21: Semiconductor element; 21a, 22a: Chip body; 21b: Emitter electrode; 21c: Gate electrode; 22b: Electrode; 30: Printed circuit board; 31: Core material; 32: First conductor layer; 33: Second conductor layer; 33a: Bonding pad; 33b: Non-bonding pad; 34: Protrusion; 35: Conductor layer joint; 36A, 36D: Missing part; 36B, 36C: Through hole; 40: Conductive member; 41: Solder layer; 42: Third conductive member; 42b: Convex dot solder; 42d, 45d: Paste solder; 45A, 45B, 45C, 45D: Second conductive member; 46A, 46B, 46C, 46D: First conductive member; 46d: Solder; 51A, 51B, 51C, 51D: Metal column part; 51B1: Head; 51B2: Column part; 60: Housing; 61, 62: Inner side surface of housing; 70: Sealing resin; 80: External electrode terminal; 82: External main electrode terminal; 90: Metal wire; 100: Power semiconductor device; 200: Power conversion device; 201: Main conversion circuit; 202: Power semiconductor module; 203: Control circuit; 300: Load; 400: Power supply; C1: First center line; C2: Second center line. Detailed implementation mode

[0051] The following describes an implementation mode based on the accompanying drawings.

[0052] Implementation mode 1.

[0053] First, use Figures 1 - 6 to describe the structure of the power semiconductor device of the first example of this implementation mode. In addition, for convenience of description, the X direction, Y direction, and Z direction are introduced. Figure 1 is a schematic top view showing the overall form of the power semiconductor device of the first example of implementation mode 1. Figure 2 is a partial schematic cross-sectional view of the power semiconductor device of the first example of implementation mode 1 along Figure 1 the II-II line. Figure 3 is Figure 1 a schematic top view of the part where the semiconductor element is particularly arranged in the power semiconductor device. Figure 4 is a schematic top view showing Figure 1 the form of the core material of the printed circuit board and the conductor layer on the lower side in the Z direction in the power semiconductor device. Figure 5 is a schematic top view showing Figure 1 the form of the core material of the printed circuit board and the conductor layer on the upper side in the Z direction in the power semiconductor device. Figure 6 is in the first example of implementation mode 1 throughFigure 2 A schematic enlarged cross-sectional view of part VI surrounded by a dashed line in []. In addition, hereinafter, the lower side related to the Z direction, i.e., the negative side of the Z direction, will be simply referred to as the lower side, and the upper side related to the Z direction, i.e., the positive side of the Z direction, will be simply referred to as the upper side. In addition, hereinafter, the positive or negative side related to the X and Y directions extending in the horizontal direction of the figure will be simply referred to as the left side and the right side.

[0054] Refer to Figure 1 and Figure 2 Referring to [] and [], the power semiconductor device 100 of the first example of the present embodiment mainly includes an insulating substrate 10, a semiconductor chip 20, a printed substrate 30, a conductive member 40, a metal column portion 51C, a housing 60, a sealing resin 70, an external electrode terminal 80, and a metal wire 90. The insulating substrate 10 is a flat member having, for example, a rectangular shape in a plan view. The insulating substrate 10 has an insulating layer 11, a fourth conductor layer 12, and a third conductor layer 13.

[0055] The insulating layer 11 has a thickness of, for example, 0.125 mm. The insulating layer 11 is, for example, a resin insulating sheet. However, the insulating layer 11 is not limited thereto, and may be formed of any ceramic material selected from the group consisting of AlN (aluminum nitride), alumina, and SiN (silicon nitride), for example. The fourth conductor layer 12 is joined to the lower surface of the insulating layer 11. The fourth conductor layer 12 has a thickness of, for example, 2 mm. The third conductor layer 13 is disposed to be joined to the upper surface of the insulating layer 11, that is, on the surface of the insulating substrate 10 on the printed substrate 30 side as the upper side. The third conductor layer 13 has a thickness of, for example, 0.5 mm. The fourth conductor layer 12 and the third conductor layer 13 are formed of copper, for example.

[0056] Refer to Figure 3 [], the third conductor layer 13 has, for example, a rectangular shape in a plan view and is arranged such that a plurality of them are spaced apart from each other in the X direction. In addition, in [], two third conductor layers 13 are arranged spaced apart from each other in the X direction, but the number and arrangement form of the third conductor layers 13 are arbitrary. In addition, as shown in [], for example, the right third conductor layer 13 among the two can partially protrude to the left in the central portion of the insulating substrate 10 in the region on its left side compared to other regions. Correspondingly, the left third conductor layer 13 among the two can partially be recessed to the left in the central portion of the insulating substrate 10 in the region on its right side compared to other regions. In [], the protruding portion of the right third conductor layer 13 extends into the recessed portion of the left third conductor layer 13. Such a structure may be adopted. In addition, the fourth conductor layer 12 may or may not have the same planar shape as the third conductor layer 13. Figure 3 [], the third conductor layer 13 has, for example, a rectangular shape in a plan view and is arranged such that a plurality of them are spaced apart from each other in the X direction. In addition, in [], two third conductor layers 13 are arranged spaced apart from each other in the X direction, but the number and arrangement form of the third conductor layers 13 are arbitrary. In addition, as shown in [], for example, the right third conductor layer 13 among the two can partially protrude to the left in the central portion of the insulating substrate 10 in the region on its left side compared to other regions. Correspondingly, the left third conductor layer 13 among the two can partially be recessed to the left in the central portion of the insulating substrate 10 in the region on its right side compared to other regions. In [], the protruding portion of the right third conductor layer 13 extends into the recessed portion of the left third conductor layer 13. Such a structure may be adopted. In addition, the fourth conductor layer 12 may or may not have the same planar shape as the third conductor layer 13. Figure 3 [], for example, the right third conductor layer 13 among the two can partially protrude to the left in the central portion of the insulating substrate 10 in the region on its left side compared to other regions. Correspondingly, the left third conductor layer 13 among the two can partially be recessed to the left in the central portion of the insulating substrate 10 in the region on its right side compared to other regions. In [], the protruding portion of the right third conductor layer 13 extends into the recessed portion of the left third conductor layer 13. Such a structure may be adopted. In addition, the fourth conductor layer 12 may or may not have the same planar shape as the third conductor layer 13. Figure 3 [], the protruding portion of the right third conductor layer 13 extends into the recessed portion of the left third conductor layer 13. Such a structure may be adopted. In addition, the fourth conductor layer 12 may or may not have the same planar shape as the third conductor layer 13.

[0057] As the semiconductor chip 20, for example, it has an IGBT as the semiconductor element 21 and a diode 22 as other elements different from the semiconductor element 21. These semiconductor chips 20, namely the semiconductor element 21 and the diode 22, are joined to one main surface of the insulating substrate 10, that is, the upper main surface. More specifically, a plurality of semiconductor elements 21 and diodes 22 are joined to the upper surface of the third conductor layer 13 at intervals in the X direction and the Y direction. Additionally, as the diode, for example, an FWD is preferably used. Also, here, as an example of the semiconductor element 21, an IGBT is exemplified. However, as the semiconductor element 21, instead of the IGBT, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) can also be used.

[0058] In Figure 3 it, above each of the two third conductor layers 13 of the insulating substrate 10, three semiconductor elements 21 and three diodes 22 are joined in a row. That is to say, in Figure 3 it becomes a so-called 1in1 module structure in which the semiconductor element 21 and the diode 22 are arranged in pairs. However, the number and arrangement form of the semiconductor element 21 and the diode 22 are arbitrary. For example, it can also be configured as a 2in1 with two pairs of the semiconductor element 21 and the diode 22 or a 6in1 with six pairs. Further, it can also be a structure in which the above structure is loaded, a power semiconductor element serving as a converter and a power semiconductor element serving as a brake.

[0059] Additionally, in Figure 3 it is schematically illustrated that the semiconductor element 21 has one main electrode 21b and one signal electrode 21c on the chip body 21a. That is to say, the main electrode 21b and the signal electrode 21c are formed in the semiconductor element 21. Additionally, the main electrode 21b is, for example, an emitter electrode, and the signal electrode 21c is, for example, a gate electrode. Also, in Figure 3 it, schematically, one electrode 22b is illustrated above the chip body 22a of the diode 22.

[0060] Regarding the semiconductor element 21, the chip body 21a is, for example, 8 mm in length, 8 mm in width, and 0.08 mm in thickness in the longitudinal direction. Regarding the diode 22, the chip body 22a is, for example, 6 mm in length, 8 mm in width, and 0.08 mm in thickness in the longitudinal direction. On the upper surface of the semiconductor element 21 which is an IGBT, a gate electrode is formed as a signal electrode 21c that is 1 mm in length and 2 mm in width in the longitudinal direction. In addition, the number and arrangement form of the above-mentioned main electrode 21b, signal electrode 21c, and the electrode 22b of the diode 22 are arbitrary. These main electrode 21b, signal electrode 21c, and electrode 22b are all, for example, metal thin films formed of gold. In addition, when the semiconductor element 21 is a MOSFET, a source electrode is arranged as the main electrode 21b on its chip body, and a gate electrode is arranged as the signal electrode 21c.

[0061] Referring to Figure 4 and Figure 5 , the printed circuit board 30 is, for example, a flat member having a rectangular shape in a plan view. As Figure 2 shown, the printed circuit board 30 is joined to its upper side, for example, in a manner facing the semiconductor element 21 which is an IGBT and the diode 22. Specifically, a solder layer 41 is disposed on the lower surface of the semiconductor element 21 and the diode 22, and a third conductive member 42 serving as a solder layer is disposed on the upper surface. The semiconductor element 21 and the diode 22 are joined to the third conductor layer 13 of the insulating substrate 10 below them through the solder layer 41. In addition, the semiconductor element 21 and the diode 22 are joined to a first conductor layer 32 described later of the printed circuit board 30 above them through the third conductive member 42. In other words, the main electrode 21b and the printed circuit board 30 are connected via the third conductive member 42. Both the solder layer 41 and the third conductive member 42 are included in the conductive member 40 described above.

[0062] The thickness of the solder layer 41 is about 0.1 mm. The thickness of the third conductive member 42 is about 0.4 mm. The solder layer 41 and the third conductive member 42, for example, include a solder material of the Sn-Ag-Cu system. However, here, in at least one of the solder layer 41 and the third conductive member 42, not limited to the solder of the Sn-Ag-Cu system, other types of solder can also be used. Or, in the third conductive member 42, other conductive materials other than solder can also be used. Further, instead of the solder layer 41, other conductive materials other than solder can also be used. For example, as this conductive member, instead of the solder layer 41 and the third conductive member 42, a conductive adhesive in which silver filler is dispersed in epoxy resin, or silver nanopowder or copper nanopowder obtained by low-temperature sintering of nanoparticles can also be used. When these materials are used to form the conductive member, it also has the same joining effect as the case where the solder layer 41 and the third conductive member 42 are formed.

[0063] In this way, the insulating substrate 10 is joined to the lower side of the semiconductor chip 20. Accordingly, the insulating substrate 10 can be electrically connected to electrodes (not shown) on the surface of the lower side of the semiconductor chip 20. In addition, more detailed description of the conductive member 40 will be given later.

[0064] Referring to Figure 1 , the maximum area of the rectangle of the printed circuit board 30 in plan view can be smaller than the maximum area of the rectangle of the insulating substrate 10 in plan view. However, conversely, the maximum planar area can be larger for the printed circuit board 30 than for the insulating substrate 10, or the two can be substantially the same. It is preferable to arrange the printed circuit board 30 such that the center point of the rectangular planar shape thereof substantially coincides with the center point of the rectangular planar shape of the insulating substrate 10. However, the center point of the planar shape of the printed circuit board 30 and the center point of the planar shape of the insulating substrate 10 may not coincide. For example, the distance in the X direction between the two center points can be 5% or less of the maximum dimension of the printed circuit board 30 in the X direction, or can exceed 5%. The same applies to the Y direction. Here, the center point of the insulating substrate 10 means the intersection of the diagonals of the rectangular shape of the insulating substrate 10 in plan view. In the case where the insulating substrate 10 has a planar shape other than a rectangular shape, the center point of the insulating substrate 10 means the position of its center of gravity.

[0065] Referring to Figure 2 , the printed circuit board 30 has a core material 31, a first conductor layer 32, and a second conductor layer 33. The first conductor layer 32 is formed on the semiconductor element 21 side of the core material 31, that is, on the first main surface on the lower side of the core material 31 close to the semiconductor chip 20. In addition, the second conductor layer 33 is formed on the second main surface of the core material 31 on the side opposite to the above-mentioned first main surface, that is, on the upper side of the core material 31 far from the semiconductor chip 20. As described above, the first conductor layer 32 is joined to the semiconductor element 21 and the diode 22 via the third conductive member 42. Accordingly, the printed circuit board 30 is arranged along the main surface of the semiconductor chip 20 so as to face the upper side of the semiconductor element 21 etc. mounted on the insulating substrate 10.

[0066] The core material 31 has a thickness of, for example, 0.5 mm. The core material 31 is made of an insulating material called FR-4 (Flame Retardant Type 4, 4-type flame retardant), for example. Both the first conductor layer 32 and the second conductor layer 33 have a thickness of, for example, 0.4 mm and are made of copper, for example.

[0067] As Figure 4 shown, for example, regarding the first conductor layer 32, two first conductor layers 32 with relatively large planar areas are arranged at intervals from each other in the X direction. These two first conductor layers 32 are line-symmetrical with respect to a central line (not shown) extending in the center of the X direction in the vertical direction (i.e., the depth direction) of the figure. Regarding these two first conductor layers 32 amongFigure 4 The one on the left side, the outermost edge on the right side, i.e., the outer edge, is recessed near the center of the printed circuit board 30 towards Figure 4 the left side. Regarding these two first conductor layers 32 Figure 4 The one on the right side, the outermost edge on the left side, i.e., the outer edge, is recessed near the center of the printed circuit board 30 towards Figure 4 the right side. The recessed portions of these two first conductor layers 32 face each other in the X direction while surrounding the central portion of the printed circuit board 30 in a top view.

[0068] In addition, regarding these two first conductor layers 32, except for the above-mentioned recessed portions, each side is formed in a rectangular shape. As Figure 4 shown, the outer edges on the upper side and the lower side in Figure 4 can be formed to overlap with the outer edge of the printed circuit board 30. However, the outer edges on the upper side and the lower side in Figure 4 can also be formed inside the printed circuit board 30 so as not to overlap with the outer edge of the printed circuit board 30.

[0069] In the central portion of the printed circuit board 30 in a top view, a pattern of a first conductor layer 32 in a rectangular shape or a square shape is formed. The planar area of the first conductor layer 32 in this central portion is smaller than that of the above-mentioned two first conductor layers 32. The first conductor layer 32 in this central portion is formed of the same layer as each of the above-mentioned two first conductor layers 32.

[0070] Based on the above, the planar shapes and arrangements of the total three first conductor layers 32 shown in Figure 4 are line-symmetric with respect to the central line passing through the central portion in the X direction in the longitudinal direction. In addition, the planar shapes of the above-mentioned three first conductor layers 32 are line-symmetric with respect to the central line passing through the central portion in the Y direction in the lateral direction. In addition, the planar shapes and arrangements of the above-mentioned three first conductor layers 32 are point-symmetric with respect to Figure 4 the central point of Figure 4 . Figure 4

[0071] As Figure 5 shown, two second conductor layers 33 are formed at intervals from each other in the X direction, for example. However, these two are further divided into two at intervals from each other in the Y direction. That is, in Figure 5 the left half region, as the second conductor layer 33, a non-bonding pad 33b and a bonding pad 33a with a relatively large planar area are arranged. That is, the second conductor layer 33 has a bonding pad 33a as a part thereof. The bonding pad 33a is arranged in Figure 5The bonding pad 33a is located on the upper side of the non-bonding pad 33b in the left region, that is, on the inner side in the depth direction. The width of the bonding pad 33a in the Y direction is narrower than that of the non-bonding pad 33b. The bonding pad 33a is a rectangular shape extending elongated in the X direction.

[0072] In addition, Figure 5 In the right half of the region, a non-bonding pad 33b having a relatively large plane area and a bonding pad 33a are also arranged as the second conductor layer 33. That is, the second conductor layer 33 has the bonding pad 33a as a part thereof. The bonding pad 33a is arranged in Figure 5 The bonding pad 33a is located on the lower side of the non-bonding pad 33b in the right area of ​​the bonding pad 33a, that is, on the front side in the depth direction. The width of the bonding pad 33a in the Y direction is narrower than that of the non-bonding pad 33b. The bonding pad 33a is a rectangular shape extending elongated in the X direction.

[0073] like Figure 5 As shown in FIG. 1 , for example, the two non-bonding pads 33b and the bonding pad 33a constituting the second conductor layer 33 are line-symmetrical with each other about a center line (not shown) extending in the center of the X direction in the vertical direction of the figure, i.e., the depth direction. With respect to these two non-bonding pads 33b, the rightmost side, i.e., the outer edge, is located near the center of the printed circuit board 30. Figure 5 The left side of the two non-bonding pads 33b is concave. Figure 5 The leftmost side, i.e., the outer edge, is near the center of the printed substrate 30. Figure 5 The recessed portions of the two non-bonding pads 33b are each facing each other in the X direction, and surround the central portion of the printed circuit board 30 in a plan view.

[0074] In addition, regarding these two non-bonding pads 33b, except for the above-mentioned recessed portion, each side is formed in a rectangular shape. Figure 5 As shown, the second conductor layer 33 is Figure 5 The uppermost and lowermost outer edges of the second conductor layer 33 may be formed inside the printed substrate 30 so as not to overlap with the outer edges of the printed substrate 30. Figure 5 The upper and lower outer edges of the printed circuit board 30 may be formed to overlap with the outer edge of the printed circuit board 30 .

[0075] A second conductor layer 33 having a rectangular or square shape is patterned in the center portion of the printed circuit board 30 in a plan view. The second conductor layer 33 in the center portion is a non-bonding pad 33b having a smaller plane area than the non-bonding pads 33b of the two second conductor layers 33 described above. The non-bonding pad 33b in the center portion is formed in the same layer as the two large non-bonding pads 33b and the two bonding pads 33a described above.

[0076] According to the above, Figure 5The planar shapes and arrangements of the five second conductor layers 33 shown in the figure are, for example, line-symmetrical with respect to the center lines passing through the central portions in the X direction in the longitudinal direction Figure 5 and are line-symmetrical with respect to the center lines passing through the central portions in the Y direction in the lateral direction. In addition, the planar shapes and arrangements of the five second conductor layers 33 are, for example, point-symmetrical with respect to Figure 5 the central points. Figure 5

[0077] In addition, as Figure 2 shown, it is preferable to arrange at least a part of the emitter electrode or the like of the main electrode 21b to which the third conductive member 42 is attached of the semiconductor element 21 at a position overlapping the bonding pad 33a in a top view. Alternatively, the entire main electrode 21b to which the third conductive member 42 is attached of the semiconductor element 21 may be arranged at a position overlapping the bonding pad 33a in a top view.

[0078] In the present embodiment, the connection portion between the semiconductor chip 20 and the printed circuit board 30 has the following characteristics. As Figure 2 shown, signal electrodes 21c such as the gate electrode of the IGBT and the bonding pad 33a are electrically connected by a metal wire 90.

[0079] In addition, as Figure 2 shown, at least a part of the joint portion of the metal wire 90 joined to the bonding pad 33a, that is, the joined position, is arranged at a position facing the third conductive member 42 connecting the main electrode 21b of the semiconductor element 21 and the first conductor layer 32 in the Z direction. That is, at least a part of the position of the metal wire 90 joined to the bonding pad 33a is arranged at a position overlapping the third conductive member 42 of the semiconductor element 21 in a top view. Alternatively, the entire position of the metal wire 90 joined to the bonding pad 33a may be arranged at a position overlapping the third conductive member 42 of the semiconductor element 21 in a top view. In addition, as long as the position of the joint portion of the metal wire 90 is on the bonding pad 33a, it is not limited to the position facing the third conductive member 42 and is arbitrary.

[0080] Refer to Figure 2 and Figure 6, regarding the printed circuit board 30, the core material 31, the first conductor layer 32, and the second conductor layer 33 that constitute it are partially missing. The partially missing part is the through-hole portion 36C. The through-hole portion 36C penetrates the core material 31 from the first main surface to the second main surface in the Z direction, and further penetrates the first conductor layer 32 and the second conductor layer 33 that overlap the core material 31 in a plan view in the Z direction. That is, the through-hole portion 36C penetrates from the uppermost surface of the second conductor layer 33 to the lowermost surface of the first conductor layer 32 in a manner extending along the Z direction.

[0081] A conductor layer can be formed on the inner wall surface of the through-hole portion 36C. More specifically, on the inner wall surface of the through-hole portion 36C, a conductor layer joint portion 35 that conducts between the first conductor layer 32 and the second conductor layer 33 can be formed. That is, in Figure 2 , the first conductor layer 32 and the second conductor layer 33 are conducted through the conductor layer joint portion 35 on the inner wall surface of the through-hole portion 36C. The conductor layer joint portion 35 is formed of a conductor thin film such as copper that electrically and mechanically joins the first conductor layer 32 and the second conductor layer 33 on the inner wall surface of the through-hole portion 36C. More specifically, the conductor layer joint portion 35 is a coating film of, for example, copper formed independently of the first conductor layer 32 and the second conductor layer 33 on the inner wall surface of the through-hole portion 36C. However, instead of forming the conductor layer joint portion 35 in the through-hole portion 36C, the surface of the metal column portion 51C can directly contact the inner wall surface of the through-hole portion 36C.

[0082] The metal column portion 51C is inserted into the through-hole portion 36C in a manner extending along the Z direction. The metal column portion 51C is connected to the printed circuit board 30 through the first conductive member 46C. That is, in the through-hole portion 36C, both the first conductive member 46C as the conductive member 40 and the metal column portion 51C are arranged. In other words, the through-hole portion 36C is filled with the metal column portion 51C and the first conductive member 46C. The first conductive member 46C contains, for example, solder and fills the region from the side surface of the metal column portion 51C to the inner wall surface of the through-hole portion 36C. The metal column portion 51C and the through-hole portion 36C, in other words, the metal column portion 51C and the first conductor layer 32 and the second conductor layer 33 of the printed circuit board 30, are electrically connected through the first conductive member 46.

[0083] The metal column portion 51C extends from the uppermost surface of the third conductor layer 13, which is one of the main surfaces of the insulating substrate 10, through the through-hole portion 36C, beyond the uppermost surface of the through-hole portion 36C on the side opposite to the insulating substrate 10, and extends to the side of the printed circuit board 30 opposite to the insulating substrate 10. That is, the metal column portion 51C extends in the Z direction to the outside, i.e., the upper side, of the through-hole portion 36C. Here, the side of the printed circuit board 30 opposite to the insulating substrate 10 refers to the upper side of the second conductor layer 33. Thus, the metal column portion 51C penetrates the core material 31, the first conductor layer 32, and the second conductor layer 33 of the printed circuit board 30 in a manner extending in the Z direction.

[0084] Regarding the metal column portion 51C, in consideration of electrical conductivity, thermal conductivity, and solder jointability, it is preferably formed of copper. When the through-hole portion 36C has a cylindrical shape, the metal column portion 51C is also preferably cylindrical. In addition, the through-hole portion 36C and the metal column portion 51C may also be in the shape of a prism. However, from the viewpoint of reducing the thermal stress generated at the joint interface between the metal column portion 51C and the first conductive member 46, the metal column portion 51C is more preferably cylindrical.

[0085] In addition, the metal column portion 51C may also be such that a portion made of a metal material extends in a tubular shape and the central portion in a plan view is hollow. Or, the metal column portion 51C may also be in a form in which the whole is made of a metal material and the entire central portion in a plan view is filled with the metal material.

[0086] In addition, in Figure 2 and Figure 6 , a conductor layer joint portion 35 is formed on the inner wall surface of the through-hole portion 36C, and the conductor layer joint portion 35 is interposed between the first conductive member 46C and the through-hole portion 36C. However, here, such a case is also expressed as the metal column portion 51C being connected to the printed circuit board 30 within the through-hole portion 36C. In addition, such a case is sometimes expressed as the metal column portion 51C being joined or contacting the printed circuit board 30 within the through-hole portion 36C. The lower side of the metal column portion 51C reaches the uppermost surface of the insulating substrate 10. That is, the lowermost portion of the metal column portion 51C contacts the uppermost surface of the third conductor layer 13. The metal column portion 51C and the uppermost surface of the insulating substrate 10 are joined by the second conductive member 45C. The second conductive member 45C, which is a conductive member 40, also contains, for example, solder like the others. Thus, by joining the lowermost portion of the metal column portion 51C and the uppermost surface of the third conductor layer 13, the positional accuracy of the printed circuit board 30 in the Z direction is improved.

[0087] A plurality of through portions 36C and metal column portions 51C inside thereof are arranged. Preferably, the plurality of metal column portions 51C are arranged at positions that are point-symmetrical to each other with respect to the center of the insulating substrate 10 in a top view. Specifically, at the Y-direction end portions of each of the two large non-bonding pads 33b, on the side opposite to the side facing the bonding pads 33a adjacent thereto in the Y direction, three metal column portions 51C and through portions 36C are respectively formed at intervals in the X direction. In addition, one metal column portion 51C and through portion 36C are also formed at the small non-bonding pad 33b at the center in a top view so as to include, for example, the center point of the printed substrate 30 in a top view. That is, one of the plurality of metal column portions 51C is arranged at the center of the printed substrate 30 in a top view.

[0088] As Figure 2 and Figure 3 shown, in the Y direction, the through portions 36C, metal column portions 51C, diodes 22, and semiconductor elements 21 are arranged at intervals from each other in this order. On the left side of Figure 3 and on the Figure 2 side, from the negative side to the positive side in the Y direction, the through portions 36C, metal column portions 51C, diodes 22, and semiconductor elements 21 are arranged in this order. On the right side of Figure 3 , from the negative side to the positive side in the Y direction, the semiconductor elements 21, diodes 22, through portions 36C, and metal column portions 51C are arranged in this order.

[0089] Accordingly, in the example of Figures 1 - 6 , a total of seven metal column portions 51C and through portions 36C are arranged. However, this is just an example, and the number and positions are not limited thereto as described later. However, it is preferable to arrange each of the plurality of metal column portions 51C and through portions 36C at positions that are point-symmetrical to each other with respect to the center point of the insulating substrate 10 in a top view. In addition, it is preferable to arrange these at positions that are point-symmetrical to each other with respect to the center point of the printed substrate 30 in a top view. That is, it is preferable to arrange the plurality of metal column portions 51C other than one metal column portion 51C among the plurality of metal column portions 51C at positions that are point-symmetrical to each other with respect to the center of the printed substrate 30, for example, the center point.

[0090] Current flows through the metal column portion 51C. Figure 4Two large patterns of the first conductor layers 32 are respectively connected to three metal column portions 51C each. As long as the current capacity flowing through the patterns of the first conductor layers 32 can be satisfied, the number of metal column portions 51C connected to the patterns of the first conductor layers 32, that is, the number of through portions 36C, is arbitrary. This current capacity can be calculated by the product of the cross-sectional area intersecting the extending direction of the metal column portion 51C and the current density. For example, consider the case of a metal column portion 51C formed of copper with a circular cross-section having a diameter of 2.0 mm. In this case, the current capacity of each metal column portion 51C is about 200 A. For example, in the case of the power semiconductor device 100 in which a current of 600 A flows through the patterns of the first conductor layers 32, if the metal column portion 51C has a diameter of 2.0 mm, three or more can be arranged. Connected to Figure 4 Three metal column portions 51C of the first conductor layer 32 and the second conductor layer 33 having a large planar area respectively correspond to the U-phase, V-phase, and W-phase.

[0091] The main electrode 21b of the semiconductor element 21 and a surface electrode (not shown) of the diode 22 are connected by a conductive member 40. If it is assumed that the main electrode 21b such as the emitter electrode and the surface electrode (not shown) of the diode 22 are connected by the metal column portion 51C, a large current flows through the metal column portion 51C. Therefore, it is necessary to arrange a plurality of metal column portions 51C to disperse the current. In the case of arranging a plurality of metal column portions 51C, it is necessary to form a very large number of through portions 36C at a narrow pitch in the printed circuit board 30. However, processing such a large number of through portions 36C at a narrow pitch is difficult, and there is a case where the necessary number cannot be formed. Therefore, as described above, by connecting the main electrode 21b and the surface electrode of the diode 22 by the conductive member 40, the volume required for flowing a large current can be easily provided by the conductive member 40.

[0092] Due to such a form, in Figure 1 In the top view shown in, the main electrode 21b and the surface electrode of the diode 22 are arranged to overlap the printed circuit board 30 in the top view and are covered by the printed circuit board 30 from above. In addition, in Figure 1 In the top view shown in, the signal electrode 21c is arranged not to be covered by the printed circuit board 30. In addition, in the case of connecting the signal electrode 21c and the bonding pad 33a by a wire bonding process, in order to avoid interference between the bonding tool and the printed circuit board 30, the interval between the signal electrode 21c and the end portion, that is, the outer edge of the printed circuit board 30 needs to be set to 1 mm or more.

[0093] Based on the above, the metal column portion 51C functions as a conductor that electrically connects the third conductor layer 13 and the first conductor layer 32 and the second conductor layer 33 of the printed circuit board 30 facing it. That is to say, the third conductor layer 13 of the insulating substrate 10 and the first conductor layer 32 and the second conductor layer 33 of the printed circuit board 30 facing it are electrically connected via the second conductive member 45, the metal column portion 51C, and the first conductive member 46 (and the conductor layer joint portion 35).

[0094] The metal column portion 51C is controlled such that the gap (interval in the Z direction) between the third conductor layer 13 and the first conductor layer 32 becomes a fixed value. In addition, the dimensions of the plurality of metal column portions 51C in the Z direction are substantially equal.

[0095] In the case of the power semiconductor device 100 with a rated voltage of 1200V or less, the interval in the Z direction between the surface of the first conductor layer 32 of the printed circuit board 30 facing each other and the surface of the electrode (such as the signal electrode 21c) formed on the semiconductor element is preferably 0.3 mm or more. As Figure 6 shown, preferably, the length H2 extending upward in the Z direction of the metal column portion 51C is larger than the length H1 extending downward in the Z direction outside the printed circuit board 30. Specifically, the length H1 is 0.5 mm or shorter. In addition, H1 may be slightly increased compared to 0.5 mm. In contrast, preferably, the length H2 is set to at least 0.5 mm or more. However, the length H2 is, for example, about 1 mm or more and 3 mm or less, and more preferably 1.5 mm or more and 2 mm or less.

[0096] The housing 60 is configured to surround the outer edge portion of the insulating substrate 10 in a plan view, and houses the semiconductor element 21, the diode 22, the printed circuit board 30, etc. thereon. That is to say, it becomes the following form: a container-like member is formed by the insulating substrate 10 and the housing 60, and the semiconductor element 21, the diode 22, the printed circuit board 30, etc. are housed in the container-like member, and the container-like member is filled with the sealing resin 70. The sealing resin 70 includes, for example, epoxy resin. A part of the insulating substrate 10, specifically, for example, the region below the fourth conductor layer 12, may also be exposed to the outside from the container-like member.

[0097] The housing 60 is bonded to the insulating substrate 10 by a silicone adhesive (not shown), particularly to the end faces of the insulating layer 11 and the fourth conductor layer 12 and the region of the main surface adjacent to the end face of the fourth conductor layer 12. The housing 60 is, for example, a member mainly composed of PPS (polyphenylene sulfide). However, the housing 60 may also be formed of LCP (liquid crystal polymer) having higher heat resistance than PPS.

[0098] As Figure 2As shown, the housing 60 has a region with a relatively wide width in the X direction (and the Y direction not shown) on its lower side and a region with a relatively narrow width in the X direction (and the Y direction) on its upper side. A groove is formed in the housing 60. The groove extends horizontally in the wide-width region from the inner side surface 61 of the housing in the wide-width region, bends from there, and extends in the Z direction along the inner side surface 62 of the housing in the narrow-width region. The external electrode terminal 80 and the external main electrode terminal 82 are configured to be fitted in this groove. The external electrode terminal 80 is electrically connected to the bonding pad 33a of the printed circuit board 30 via the metal wire 90. Therefore, the external electrode terminal 80 is electrically connected to the signal electrode 21c. In addition, the external main electrode terminal 82 is electrically connected to the bonding pad 33a of the printed circuit board 30 via the metal wire 90. Therefore, the external main electrode terminal 82 is electrically connected to the signal electrode 21c. In addition, the external electrode terminal 80 is electrically connected to the main electrode 21b and the signal electrode 21c via the metal wire 90.

[0099] Next, use Figures 7 - 9 to illustrate the structure of the power semiconductor device according to the second example of the present embodiment. Figure 7 is a schematic plan view showing the overall form of the power semiconductor device according to the second example of Embodiment 1 as viewed from above. Figure 8 is a schematic cross-sectional view of a part along the Figure 7 VIII-VIII line of the power semiconductor device according to the second example of Embodiment 1. Figure 9 is in the third example of Embodiment 1 Figure 8 a schematic enlarged cross-sectional view of part IX surrounded by a dashed line in

[0100] Refer to Figure 7 , Figure 8 and Figure 9 , the power semiconductor device 100 according to the second example of the present embodiment has substantially the same structure as the power semiconductor device 100 according to the first example of the present embodiment. Therefore, the same reference numerals are given to the same structural elements, and the description of matters common to the first example is not repeated. In addition, even if the reference numerals are different, the content not repeatedly described below is basically the same as that of the first example.

[0101] In the power semiconductor device 100 of the second example, the core material 31, the first conductor layer 32, and the second conductor layer 33 constituting the printed circuit board 30 are partially missing in the through portion 36B. Although the symbols are different, the through portion 36B has the same shape, position, etc. as the through portion 36C. Instead of the metal pillar 51C, the metal pillar 51B is inserted into the through portion 36B. The metal pillar 51B is connected to the printed circuit board 30 through the first conductive member 46B in the through portion 36B. The lowermost part of the metal pillar 51B is connected to the third conductor layer 13 of the insulating substrate 10 through the second conductive member 45B. In addition, although the symbols are different, the materials, arrangement forms, etc. of the first conductive member 46B and the second conductive member 45B are the same as those of the first conductive member 46C and the second conductive member 45C.

[0102] The metal pillar 51B is inserted into the through portion 36B so as to extend in the Z direction, similarly to the metal pillar 51C of the first example. The metal pillar 51B extends from the through portion 36B beyond the uppermost surface of the second conductor layer 33 of the printed circuit board 30 to the outside of the through portion 36B on the upper side in the Z direction.

[0103] The shape, material, etc. of the metal column 51B are basically the same as those of the metal column 51C. Figure 9 As shown in FIG. 1 , the metal pillar portion 51B includes a head portion 51B1 and a columnar portion 51B2. The head portion 51B1 is a portion of the metal pillar portion 51B that is disposed outside the through portion 36B and extends in the XY direction along one main surface of the insulating substrate 10. In other words, the head portion 51B1 is a portion of the metal pillar portion 51B that extends in the XY direction. Figure 9 The head 51B1 is a region extending from the upper side of the second conductor layer 33 in the left-right direction of the figure, that is, the Y direction. In other words, the head 51B1 is a region in which the columnar portion 51B2 extending upward in the Z direction exceeds the third main surface of the printed circuit board 30 on the upper side in the Z direction and is arranged outside the through portion 36B. The columnar portion 51B2 is a region of the metal column 51B other than the head 51B1. The columnar portion 51B2 is a region extending from the head 51B1 (the lowermost surface) along the through portion 36B in a manner that includes the region inside the through portion 36B.

[0104] The columnar portion 51B2 has, for example, a cylindrical shape, but is not limited thereto. For example, the columnar portion 51B may also be in the shape of a polygonal column. In addition, the columnar portion 51B2 may also be a portion made of a metal material extending in a cylindrical shape and having a hollow central portion when viewed from above. Alternatively, the columnar portion 51B2 may be a portion made of a metal material as a whole and the entire portion including the central portion when viewed from above is filled with a metal material. Therefore, the head portion 51B1 is configured outside the through portion 36B to be connected to an end portion (the uppermost portion) in the direction in which the columnar portion 51B2 extends.

[0105] Thus, in the uppermost part in the Z direction, particularly in the cross-sectional shape of the region above the third conductor layer 13 of the insulating substrate 10, the metal column part 51B is different from the metal column part 51C.

[0106] Next, use Figures 10 - 12 to describe the structure of the power semiconductor device according to the third example of the present embodiment. Figure 10 is a schematic plan view showing the overall form of the power semiconductor device according to the third example of Embodiment 1. Figure 11 is a schematic cross-sectional view of a part along the Figure 10 XI-XI line among the power semiconductor devices according to the third example of Embodiment 1. Figure 12 is in the third example of Embodiment 1 Figure 11 a schematic enlarged cross-sectional view of the part XII surrounded by a dotted line.

[0107] Refer to Figure 10 , Figure 11 and Figure 12 , the power semiconductor device 100 according to the third example of the present embodiment has substantially the same structure as the power semiconductor device 100 according to the first example of the present embodiment. Therefore, the same reference numerals are given to the same structural elements, and the description of the matters common to the first example is not repeated. In addition, even if the reference numerals are different, the content not repeatedly described below is substantially the same as that of the first example.

[0108] In the power semiconductor device 100 according to the third example, the part where the first conductor layer 32 of the printed circuit board 30 is partially missing is the missing part 36A. The positions where the missing part 36A and the through parts 36B and 36C are formed are the same. However, the missing part 36A is formed by exposing the first main surface of the core material 31 directly below it by penetrating the first conductor layer 32 in the region where it is formed.

[0109] That is, the missing part 36A is not formed in such a way as to miss the core material 31 and the second conductor layer 33. In this way, the missing part 36A only penetrates a part in the Z direction connecting the first main surface and the second main surface of the printed circuit board 30. Therefore, the missing part 36A does not penetrate the printed circuit board 30. On the other hand, the through parts 36B and 36C as the missing parts penetrate all of the first conductor layer 32, the core material 31, and the second conductor layer 33 by penetrating the entire Z direction of the printed circuit board 30. In this regard, the third example is different from the first and second examples.

[0110] Instead of the metal column portion 51C, the metal column portion 51A is inserted into the missing portion 36A. The metal column portion 51A is connected to the printed circuit board 30 through the first conductive member 46A within the missing portion 36A. The lowermost portion of the metal column portion 51A is connected to the third conductor layer 13 of the insulating substrate 10 through the second conductive member 45A. In addition, the materials of the first conductive member 46A and the second conductive member 45A are the same as those of the first conductive member 46C and the second conductive member 45C.

[0111] The metal column portion 51A is inserted into the missing portion 36A in a manner extending along the Z direction. The metal column portion 51A extends downward along the Z direction from within the missing portion 36A to the uppermost surface of the third conductor layer 13 of the insulating substrate 10.

[0112] The material and the like of the metal column portion 51A are basically the same as those of the metal column portion 51C. In addition, the metal column portion 51A may be a portion made of a metal material extending in a cylindrical shape with a cavity in the central portion when viewed from above. Or, the metal column portion 51A may be in a form in which the whole is made of a metal material and the entire central portion when viewed from above is filled with the metal material.

[0113] In this way, the metal column portion 51A does not penetrate the printed circuit board 30. In this regard, the metal column portion 51A is different from the metal column portion 51B and the metal column portion 51C.

[0114] Next, use Figures 13 - 18 to illustrate the manufacturing method of the power semiconductor device 100 of Embodiment 1. In addition, hereinafter, among the manufacturing methods of the power semiconductor device 100, the processes of forming the insulating substrate 10 and the printed circuit board 30 and bonding the insulating substrate 10 and the printed circuit board 30 will be mainly described. Figures 13 - 18 All are Figure 2 similarly shown as a schematic cross-sectional view of a part along the Figure 1 II-II line. However, in Figures 13 - 15 , different from other figures, the Z direction, that is, up and down, is reversed. However, in the process as shown in Figures 13 - 15 , it is also possible to process without reversing the Z direction in the same manner as Figures 16 - 18 .

[0115] Figure 13 is a schematic cross-sectional view of a part along the Figure 1 II-II line showing the first process of the manufacturing method of the power semiconductor device according to the first example of Embodiment 1. Refer to Figure 13, in the manufacturing method of the power semiconductor device 100 of the first example, a printed circuit board 30 is prepared. The printed circuit board 30 includes a core material 31, a first conductor layer 32 formed on the first main surface of the core material 31, and a second conductor layer 33 formed on the second main surface of the core material 31 opposite to the first main surface. In the prepared printed circuit board 30, a missing portion where the first conductor layer 32 is partially missing is formed. However, in Figure 13 , the missing portion not only penetrates the first conductor layer 32 but also penetrates the entire printed circuit board 30 in the direction connecting the first main surface and the second main surface. Thus, a printed circuit board 30 is prepared in which a through hole 36C that penetrates all of the first conductor layer 32, the core material 31, and the second conductor layer 33 is formed.

[0116] Next, as Figure 13 shown, a metal column portion 51C is inserted into the through hole 36C. Although not shown, the printed circuit board 30 and the metal column portion 51C are fixed by a jig, thereby determining their positions relative to each other. That is, the positional relationship in the X and Y directions between the through hole 36C and the metal column portion 51C and the position of the metal column portion 51C in the Z direction are determined by the fixing of a jig (not shown).

[0117] Through this jig, the metal column portion 51C inserted into the through hole 36C and extending outside the through hole 36C is fixed to the printed circuit board 30. In this state, molten solder for forming the first conductive member 46C is provided into the space portion surrounded by the inner wall surface of the through hole 36C, that is, the inner wall surface of the through hole 36B (or the surface of the conductor layer joint portion 35 whose inner wall surface is copper-plated, for example) and the metal column portion 51C. The provided molten solder instantaneously solidifies by natural air cooling. Thus, the molten solder becomes the first conductive member 46C. Through the first conductive member 46C, the metal column portion 51C is joined into the through hole 36C. In addition, the molten solder for forming the first conductive member 46C is provided as a material obtained by heating a filamentous solder with a soldering iron or a soldering robot, etc.

[0118] The above is the process in the case where the metal column portion 51C of the first example is joined to the through hole 36C. In addition, the process in the case where the metal column portion 51B of the second example is joined to the through hole 36B is also substantially the same as that of the first example. This is because the metal column portion 51B penetrates through the through hole in the same manner as the metal column portion 51C.

[0119] Figure 14 is a schematic cross-sectional view of a part along the Figure 1 II-II line showing the first process of the manufacturing method of the power semiconductor device of the third example of Embodiment 1. Figure 15 is a schematic cross-sectional view of a part along the Figure 1Schematic cross-sectional view of a portion of the II-II line. Refer to Figure 14 and Figure 15 , in the method of manufacturing the power semiconductor device 100 of the third example, similar to Figure 13 , a printed circuit board 30 including a core material 31, a first conductor layer 32, and a second conductor layer 33 is prepared. In the prepared printed circuit board 30, a missing portion 36A where the first conductor layer 32 is partially missing is formed. However, in Figure 14 , the missing portion penetrates in such a way that only the first conductor layer 32 is partially missing.

[0120] As described above, in the present embodiment, in the process of preparing the printed circuit board 30, the through-holes 36B, 36C or the missing portion 36A can be formed after purchasing the printed circuit board 30. Alternatively, in the process of preparing the printed circuit board 30, a printed circuit board 30 in which the through-holes 36B, 36C or the missing portion 36A have already been formed can also be purchased.

[0121] In the missing portion 36A, molten solder 46d for forming the first conductive member 46A is provided. In this case, similar to the above, it is provided as a substance obtained by heating filamentous solder by a soldering iron or a soldering robot, etc. In this case, as described above, since the molten solder solidifies instantaneously, preferably, before providing the solder 46d, as Figure 15 shown, the metal column portion 51A is arranged to be inserted into the missing portion 36A and extend outside the missing portion 36A, and then the solder 46d is provided. In such a case, as Figure 15 shown, the inserted metal column portion 51A is joined to the missing portion 36A through the first conductive member 46A.

[0122] However, in the first example, instead of the molten solder, pasty solder can also be injected as the solder 46d. In this case, as Figure 14 shown, the pasty solder 46d is injected into the missing portion 36A. Then, the above-mentioned printed circuit board 30 is subjected to a reflow soldering process. As a result, as Figure 15 shown, the pasty solder 46d is solidified into the first conductive member 46A. Therefore, the metal column portion 51A is fixed and joined to the missing portion 36A through the first conductive member 46A so as to extend from inside the missing portion 36A to the outside thereof.

[0123] As Figure 13 and Figure 15As shown, on the bottom surface of the first conductor layer 32 that faces the main electrode 21b and the diode 22, bump-shaped solder 42b is formed. Regarding the bump-shaped solder 42b, paste solder can be provided on the bottom surface of the first conductor layer 32 by printing or dispenser. Alternatively, the bump-shaped solder 42b can be provided as a solid-shaped solder on the bottom surface of the first conductor layer 32. The provided solder can also be formed into a solid-shaped bump-shaped solder 42b through the reflow soldering process of the printed circuit board 30. In addition, the process of forming the bump-shaped solder 42b can also be carried out before the process of bonding the metal column part to the missing part or the through part.

[0124] Figure 16 is a schematic cross-sectional view of a part along the II-II line showing the second process of the manufacturing method of the power semiconductor device according to the first example of Embodiment 1. Refer to Figure 1 for the II-II line. Figure 16 , an insulating substrate 10 including an insulating layer 11, a fourth conductor layer 12 formed on the lower surface thereof, and a third conductor layer 13 formed on the upper surface thereof is prepared. For example, a semiconductor element 21 having a signal electrode 21c formed as a gate electrode is bonded onto one main surface of the insulating substrate 10, that is, onto the third conductor layer 13. In the process of preparing the insulating substrate 10, the semiconductor element 21 can be bonded after purchasing the insulating substrate 10. Alternatively, in the process of preparing the insulating substrate 10, an insulating substrate 10 already bonded with the semiconductor element 21 can also be purchased. In addition, the diode 22 is bonded onto the third conductor layer 13 at an interval from the semiconductor element 21. In this way, the semiconductor element 21 and the diode 22 as the semiconductor chip 20 are bonded onto the third conductor layer 13 of the insulating substrate 10 through a solder layer 41 as a conductive member 40. That is, in a state where the semiconductor element 21 and the diode 22 are loaded on the third conductor layer 13 with paste solder as the solder layer 41, a reflow soldering process is performed once, and the semiconductor chip 20 is fixed and bonded through the solidified solder layer 41.

[0125] Next, as Figure 16 shown, paste solder 42d for forming the third conductive member 42 (refer to Figure 2 ) is provided onto the main electrode 21b of the semiconductor element 21 by printing or dispenser. Paste solder 45d for forming the second conductive member 45C is provided onto the third conductor layer 13 of the insulating substrate 10.

[0126] Figure 16 The process can be carried out after the Figures 13 - 15 process or before the Figures 13 - 15 process.

[0127] Figure 17 is a schematic cross-sectional view of a portion along the II-II line of the third process of the manufacturing method of the power semiconductor device showing the first example of Embodiment 1. Refer to Figure 1 . With respect to Figure 17 the printed circuit board 30 that is turned upside down, it is arranged to face the upper side of the insulating substrate 10. However, as described above, in the case where the process is performed without inversion, in Figures 13 - 15 the printed circuit board 30 is processed as it is without inversion. Figures 13 - 15 In this state, it becomes a form in which the paste solder 45d adheres to the lowermost part of the metal column part 51C. At this time, simultaneously, the bump-shaped solder 42b and the paste solder 42d adhere. Further, simultaneously, the paste solder 42d on the semiconductor chip 20 adheres to the lowermost part of the first conductor layer 32. In this state, a reflow soldering process is performed. As a result, the bump-shaped solder 42b and the paste solder 42d are fixed as the third conductive member 42, and the semiconductor chip 20 and the first conductor layer 32 are joined. At the same time, the paste solder 45d is fixed as the second conductive member 45C, and the metal column part 51C and the third conductor layer 13 are joined via the second conductive member 45C. That is, the metal column part 51C and the insulating substrate 10 are joined by the second conductive member 45C. In Figure 17 the process, the metal column part 51C is arranged to penetrate through the through-hole part 36C from the third conductor layer 13 which is one main surface of the insulating substrate 10, and extend to the upper side of the through-hole part 36C on the side opposite to the insulating substrate 10.

[0128] In addition, the reason for forming both the bump-shaped solder 42b and the paste solder 42d to form the third conductive member 42 is as follows. By the deformable paste solder 42d, it is possible to absorb the deviation in the thickness in the Z direction of the already solidified bump-shaped solder 42b. As a result, the third conductive member 42 is formed to have a more uniform thickness, and the joining of the semiconductor chip 20 and the printed circuit board 30 can be performed with higher quality. For the above reasons, both the bump-shaped solder 42b and the paste solder 42d are formed. However, conversely to the above, for example, the bump-shaped solder 42b may be formed on the insulating substrate 10, and the paste solder 42d may be formed on the printed circuit board 30. Figure 17 In the process, the metal column part 51C is arranged to penetrate through the through-hole part 36C from the third conductor layer 13 which is one main surface of the insulating substrate 10, and extend to the upper side of the through-hole part 36C on the side opposite to the insulating substrate 10.

[0129] In addition, the reason for forming both the bump-shaped solder 42b and the paste solder 42d to form the third conductive member 42 is as follows. By the deformable paste solder 42d, it is possible to absorb the deviation in the thickness in the Z direction of the already solidified bump-shaped solder 42b. As a result, the third conductive member 42 is formed to have a more uniform thickness, and the joining of the semiconductor chip 20 and the printed circuit board 30 can be performed with higher quality. For the above reasons, both the bump-shaped solder 42b and the paste solder 42d are formed. However, conversely to the above, for example, the bump-shaped solder 42b may be formed on the insulating substrate 10, and the paste solder 42d may be formed on the printed circuit board 30.

[0130] Figure 18 is a schematic cross-sectional view of a portion along the II-II line of the fourth process of the manufacturing method of the power semiconductor device showing the first example of Embodiment 1. Refer to Figure 1 . Figure 18, the housing 60 is disposed on the insulating substrate 10. That is, it becomes the following form: The edge portions of the insulating layer 11 and the fourth conductor layer 12 of the insulating substrate 10, in particular, extend and come into contact with the grooves formed in the lower part of the housing 60. Next, the housing 60 and the insulating substrate 10 are fixed by a thermosetting adhesive (not shown). In addition, the signal electrode 21c and the bonding pad 33a are connected by a metal wire 90. This connection is performed by a generally known wire bonding process. The bonding pad 33a and the external electrode terminal 80 are wired by a metal wire 90.

[0131] Furthermore, although not shown, in the region where the semiconductor element 21, the metal column portion 51C, the printed substrate 30, etc. are accommodated in the container-like member formed by the housing 60 and the insulating substrate 10, a thermosetting sealing resin 70 is filled. The sealing resin 70 is heated and hardened. By this heating and hardening, the sealing resin 70 seals the inside of the above-mentioned container-like member. Thus, a power semiconductor device 100 in the form as Figure 2 shown is formed.

[0132] In addition, although not shown, in the manufacturing method of the power semiconductor device 100 of the first example, after the process of Figure 15 , the same processing as Figures 16 - 18 is also performed.

[0133] Next, the effects of the present embodiment will be described. The power semiconductor device 100 according to the present disclosure includes an insulating substrate 10, a semiconductor element 21, and a printed substrate 30. The semiconductor element 21 is bonded to one main surface of the insulating substrate 10. The printed substrate 30 is bonded so as to face the semiconductor element 21. The main electrode 21b and the signal electrode 21c are formed on the semiconductor element 21. The printed substrate 30 includes a core material 31, a first conductor layer 32 formed on the first main surface of the core material 31 on the semiconductor element 21 side, and a second conductor layer 33 formed on the second main surface of the core material 31 opposite to the first main surface. The second conductor layer 33 has a bonding pad 33a. Missing portions 36A, 36B, 36C where the first conductor layer 32 is partially missing are formed on the printed substrate 30. It also includes: metal column portions 51A, 51B, 51C that are inserted into the missing portions 36A, 36B, 36C and reach the insulating substrate 10 and are connected to the printed substrate 30 through first conductive members 46A, 46B, 46C. The signal electrode 21c and the bonding pad 33a are connected by a metal wire 90. The metal column portions 51A, 51B, 51C and the insulating substrate 10 are joined through second conductive members 45A, 45B, 45C.

[0134] In the method for manufacturing a semiconductor device for power use according to the present disclosure, an insulating substrate 10 having a semiconductor element 21 with a signal electrode 21c formed thereon is prepared and bonded to one main surface. A printed circuit board 30 is prepared, which includes a core material 31, a first conductor layer 32 formed on the first main surface of the core material 31, and a second conductor layer 33 formed on the second main surface of the core material 31 opposite to the first main surface, and missing portions 36A, 36B, and 36C in which the first conductor layer 32 is partially missing are formed. Metal column portions 51A, 51B, and 51C inserted through the missing portions 36A, 36B, and 36C and extending outside the missing portions 36A, 36B, and 36C are bonded to the missing portions 36A, 36B, and 36C by first conductive members 46A, 46B, and 46C. The printed circuit board 30 is arranged to face the semiconductor element 21, and the metal column portions 51A, 51B, and 51C and the insulating substrate 10 are bonded by second conductive members 45A, 45B, and 45C. The signal electrode 21c and a bonding pad 33a included in the second conductor layer 33 are connected by a metal wire 90.

[0135] The signal electrode 21c and the bonding pad 33a are wired by the metal wire 90. As a result, compared with directly electrically connecting the printed circuit board 30, for example, via a metal column portion or the like on a signal electrode 21c having a small area, the productivity is improved. The operation of aligning the metal column portion or the conductive member 40 on the signal electrode 21c having a very small planar area is difficult, and stable production may not be possible. According to the present disclosure, such difficult operations can be eliminated, and connection failures or the like between the two due to such difficult operations can be avoided. This is because, according to the wire bonding process, the metal wire 90 can be stably bonded to the signal electrode 21c having a small area.

[0136] In addition, in the present embodiment, the metal column portions 51A to 51C and the insulating substrate 10 are bonded by the second conductive members 45A to 45C. Compared with bonding to the signal electrode 21c, it is easier to bond the metal column portions to the insulating substrate 10 by the second conductive members 45A to 45C. This is because, relative to the signal electrode 21c having a planar size of 1 mm × 2 mm or less, on the insulating substrate 10, a position where the metal column portions can be bonded can be ensured to be at least 2 mm × 2 mm or more.

[0137] In the above-described semiconductor device 100 for power use, the missing portions are through-holes 36B and 36C that penetrate the entire first conductor layer 32, the core material 31, and the second conductor layer 33 by penetrating the entire printed circuit board 30 in the Z direction connecting the first main surface and the second main surface. The metal column portions 51B and 51C penetrate through the through-holes 36B and 36C from one main surface of the insulating substrate 10 and extend to the side opposite to the insulating substrate 10 of the through-holes 36B and 36C. Such a structure may be adopted.

[0138] In the manufacturing method of the above-described semiconductor device 100 for power use, the missing portions are through-holes 36B and 36C that penetrate the entirety of the first conductor layer 32, the core material 31, and the second conductor layer 33 in the Z direction that connects the first main surface and the second main surface of the printed circuit board 30. In the process of joining by the second conductive members 45A, 45B, and 45C, the metal column portions 51A to 51C are arranged to penetrate the missing portions 36A to 36C from one main surface of the insulating substrate 10 and extend to the side opposite to the insulating substrate 10 of the missing portions 36A to 36C. Such a method may be used.

[0139] The printed circuit board 30 is supported by the metal column portions 51B and 51C that penetrate the entirety of the printed circuit board 30, thereby being able to suppress the inclination of the printed circuit board 30. Therefore, the bonding strength of the metal wires 90 on the printed circuit board 30 is stable, and the reliability and productivity are improved.

[0140] In the above-described semiconductor device 100 for power use, the main electrode 21b and the printed circuit board 30 are connected by a third conductive member 42. Such a structure may be used. Thereby, the electrical connection between the main electrode 21b and the printed circuit board 30 is more reliably performed.

[0141] In the above-described semiconductor device 100 for power use, at least a part of the main electrode 21b of the semiconductor element 21 to which the third conductive member 42 is attached is arranged at a position that overlaps with the bonding pad 33a in a top view. Such a structure may be used.

[0142] The main electrode 21b of the semiconductor element 21 is arranged directly below the bonding pad 33a to which the metal wire 90 can be bonded, and the main electrode 21b is soldered by the third conductive member 42 directly above it. Through the third conductive member 42 directly below the bonding portion of the metal wire 90, the deformation of the printed circuit board 30 in the Z direction due to the load generated during the wire bonding process is suppressed, and the ultrasonic energy is stably transmitted to the bonding portion. Therefore, the bonding strength of the bonding portion of the metal wire 90 and the shape of the bonding portion are stable. Therefore, the bonding of the metal wire 90 through the wire bonding process can be stably performed.

[0143] In the above-described semiconductor device 100 for power use, at least a part of the position on the bonding pad 33a where the metal wire 90 is connected is arranged at a position that overlaps with the third conductive member 42 of the semiconductor element 21 in a top view. Such a structure may be used. Thus, the flexure of the printed circuit board 30 due to the load during the above-described wire bonding process is further suppressed. Therefore, the bondability of the metal wire 90 on the bonding pad 33a is further stabilized, and its reliability and productivity are further improved.

[0144] In the above-described semiconductor device 100 for power use, a plurality of metal column portions 51A to 51C are arranged. One of the plurality of metal column portions 51A to 51C is arranged at the center of the printed circuit board in a plan view. The other plurality of metal column portions 51A to 51C among the plurality of metal column portions 51A to 51C are arranged at positions that are point-symmetrical to each other with respect to the center of the printed circuit board 30. Such a structure may be adopted.

[0145] Accordingly, tilting of the printed circuit board 30 with respect to the insulating substrate 10 can be suppressed. Therefore, by stabilizing the bonding strength of the metal wire 90 to the bonding pad 33a, the reliability and productivity of the temperature cycle during heating can be improved.

[0146] In addition, the plurality of metal column portions 51A to 51C are fixed to the through-holes 36B, 36C and the insulating substrate 10 by the first conductive members 46A to 46C and the second conductive members 45A to 45C. The metal column portions 51A to 51C are arranged inside the through-holes 36B, 36C. Therefore, the inner wall surfaces of the through-holes 36B, 36C restrict the positions of the metal column portions 51A to 51C inside them. Thereby, the arrangement positions of the metal column portions 51A to 51C in the X direction and the Y direction can be determined with high precision.

[0147] In addition, in the present embodiment, preferably, for example, the length H2 shown in Figure 6 that is, for example, in the first example, the lengths by which the plurality of metal column portions 51C protrude from the through-hole 36C to the upper side of the second conductor layer 33 are all the same. However, the sameness here also includes cases with an error of about 0.05 mm. The positions of the plurality of metal column portions 51C in the Z direction are determined by a jig (not shown). However, it may also be that at least only the above-mentioned length H2 of the metal column portion 51C inside the through-hole 36C passing through the small non-bonding pad 33b at the center is different from that of the other plurality of metal column portions 51C, and the other plurality of metal column portions 51C are all of the same length H2.

[0148] The plurality of metal column portions 51C are arranged to have the same position coordinates in the Z direction. Thereby, it functions as a jig for supporting the printed circuit board 30. The parallelism of the printed circuit board 30 with respect to the insulating substrate 10 in the horizontal direction, that is, in the direction along the XY plane, can be improved.

[0149] Generally, in the wire bonding process, the bonding tool for transmitting the vibration of ultrasonic waves to the metal wire 90 while applying a bonding load and the bonding pad 33a as the object to be bonded are set to be substantially perpendicular to each other. Assuming that they are not set in this way, the relationship between the transmitted ultrasonic wave vibration and the applied load is unstable. Therefore, the bonding strength of the metal wire 90 becomes low. Assuming that the bonding strength is unstable due to the inclination of the printed circuit board 30, it may sometimes cause a reduction in the temperature cycle reliability during heating of the power semiconductor device 100, or become a defective product during manufacturing. Therefore, as described above, by making the lengths H2 between multiple ones substantially equal, the inclination of the printed circuit board 30 can be reduced. In addition, by making the lengths H2 substantially equal, the bonding strength from the metal wire 90 to the bonding pad 33a can be stabilized, improving the temperature cycle reliability and productivity during heating of the power semiconductor device 100. Additionally, the error in the Z-direction dimension of the plurality of metal column portions 51C themselves is preferably 1% or less of the dimension average, and more preferably 0.5% or less.

[0150] Embodiment 2.

[0151] First, use Figures 19 - 23 to illustrate the structure of the power semiconductor device of this embodiment. Figure 19 is a schematic plan view showing the overall form of the power semiconductor device of Embodiment 2 as viewed from above. Figure 20 is a schematic cross-sectional view of a part along the Figure 19 XX-XX line of the power semiconductor device of Embodiment 2. Figure 21 is Figure 19 a schematic plan view of a part of the power semiconductor device where semiconductor elements are particularly arranged. Figure 22 is to show Figure 19 a schematic plan view of the form of the core material of the printed circuit board and the conductor layer on the lower side in the Z direction of the power semiconductor device of Figure 23 is to show Figure 19 a schematic plan view of the form of the core material of the printed circuit board and the conductor layer on the upper side in the Z direction of the power semiconductor device of Figures 19 - 23 corresponds to Figures 1 - 5 the first example of Embodiment 1.

[0152] Referring to Figures 19 - 23 the power semiconductor device 100 of this embodiment has substantially the same structure as the power semiconductor device 100 of the first example of Embodiment 1. Therefore, the same reference numerals are given to the same structural elements, and the description of matters common to the first example of Embodiment 1 is not repeated. In addition, even if the reference numerals are different, the content not repeated below is basically the same as that of the first example of Embodiment 1.

[0153] In the present embodiment, among the plurality of metal column portions 51C, a part of the plurality of metal column portions 51C other than the one metal column portion 51C disposed at the center of the printed circuit board 30 in a plan view is arranged on the first center line C1 passing through the center of the printed circuit board 30 with respect to the X direction as the first direction. That is to say, for example, on the first center line C1, a total of three through holes 36C and the metal column portions 51C inside them are arranged at intervals in the Y direction with respect to the metal column portion 51C at the center of the printed circuit board 30. In other words, the three metal column portions 51C are arranged in a straight line at intervals in the Y direction.

[0154] These three metal column portions 51C in total (the central one can be excluded) are arranged at positions line-symmetric with respect to the second center line C2, and the second center line C2 is a line passing through the center of the printed circuit board 30 in the Y direction in a plan view, and the Y direction is the second direction orthogonal to the X direction. In other words, two of the three metal column portions 51C in total excluding the central one are arranged at positions line-symmetric with respect to the second center line C2. Therefore, the intervals in the Y direction are equal between the adjacent metal column portions 51C among the three metal column portions 51C arranged on the first center line C1.

[0155] These three metal column portions 51C in total are all arranged at positions overlapping the patterns of the non-bonding pads 33b with a small planar area and the first conductor layer 32, similarly to the metal column portion 51C in the central portion. Therefore, in Figure 22 and Figure 23 three first conductor layers 32 and non-bonding pads 33b with the same small planar area are respectively formed at intervals in the Y direction at the central portion in the X direction. Figure 4 and Figure 5

[0156] Next, in this power semiconductor device 100, similarly to Figure 3 three semiconductor elements 21 and three diodes 22 are bonded to each of the two third conductor layers 13 of the insulating substrate 10 in a row arrangement. However, the arrangement forms of the plurality of through holes 36C formed in each of the two large non-bonding pads 33b and the plurality of metal column portions 51C passing through the inside thereof are different from Figure 3 . Specifically, as Figure 20 and Figure 21 ​As shown, three metal column parts 51C and three through parts 36C are formed at intervals in the X direction in the central region in the Y direction when viewed from above each of the two large non-bonding pads 33b. That is, in the Y direction, the diode 22, the through part 36C, the metal column part 51C, and the semiconductor element 21 are arranged at intervals from each other. In other words, in the Y direction, the through part 36C and the metal column part 51C are arranged between the semiconductor element 21 and the diode 22. In Figure 21 the left side of Figure 20 and in Figure 21 , from the negative side to the positive side in the Y direction, they are arranged in the order of the diode 22, the through part 36C, the metal column part 51C, and the semiconductor element 21. In

[0157] the right side of

[0158] , from the negative side to the positive side in the Y direction, they are arranged in the order of the semiconductor element 21, the through part 36C, the metal column part 51C, and the diode 22.

[0159] Therefore, a total of six through parts 36C and metal column parts 51C are arranged in the parts of the two large non-bonding pads 33b. All these six metal column parts 51C are on the second center line C2 and are arranged at intervals from each other in the X direction. In other words, the six metal column parts 51C are arranged in a straight line at intervals from each other in the X direction.

[0160] Therefore, as long as the above-mentioned multiple other metal column portions 51C are point-symmetrical to each other about the center of the printed circuit board 30, i.e., for example, the center point, in the present embodiment, it is also possible to arrange them in the order of the through-hole portion 36C, the metal column portion 51C, the diode 22, and the semiconductor element 21 in the Y direction, for example, in the same manner as the first example of the first embodiment.

[0161] Examples of the through-hole portion 36C and the metal column portion 51C have been described above. However, in Figures 19 - 23 , instead of the through-hole portion 36C and the metal column portion 51C, it is also possible to use the through-hole portion 36B and the metal column portion 51B, or the missing portion 36A and the metal column portion 51A.

[0162] Next, the effects of the present embodiment will be described. In addition to the same effects as those of the first embodiment, the present embodiment also achieves the following effects.

[0163] Regarding the power semiconductor device 100 according to the present disclosure, one of the multiple metal column portions 51A to 51C is disposed at the center of the printed circuit board 30 in a top view. The other multiple metal column portions 51A to 51C among the multiple metal column portions 51A to 51C are disposed at positions that are point-symmetrical to each other about the center of the printed circuit board 30. It is preferably on the premise of the above. Further, regarding the power semiconductor device 100, a part of the multiple metal column portions 51A to 51C among the other multiple metal column portions 51A to 51C except the one at the center is arranged to be arranged on the first center line C1, and the first center line C1 is a line passing through the center of the printed circuit board 30 in the X direction as the first direction in a top view. The above-mentioned part of the multiple metal column portions 51A to 51C is disposed at positions that are line-symmetrical to each other about the second center line C2, and the second center line C2 is a line passing through the center in the Y direction, and the Y direction is the second direction orthogonal to the X direction in a top view of the printed circuit board 30. Such a structure is possible.

[0164] Based on the above, it is possible to suppress the inclination of the printed circuit board 30 with respect to the insulating substrate 10. Therefore, the bonding strength of the metal wire 90 to the bonding pad 33a is stabilized, and thereby the reliability and productivity of the thermal cycle can be improved.

[0165] On the first center line C1, a plurality of metal pillar portions 51A to 51C are arranged to be line-symmetric with each other about the second center line C2. Thereby, tilting during loading of the printed circuit board 30 onto the insulating substrate 10 and warping of the printed circuit board 30 or the insulating substrate 10 due to a temperature rise during soldering are suppressed. Thereby, the bonding strength of the metal wire 90 to the bonding pad 33a is stabilized, and the reliability and productivity against temperature cycling during heating can be improved. In addition, by suppressing deformation of the printed circuit board 30 due to temperature cycling during heating, skew of the third conductive member 42 on the semiconductor element 21 can be reduced, and the reliability of temperature cycling can be improved.

[0166] Embodiment 3.

[0167] First, use Figures 24 - 27 to describe the structure of the semiconductor device for power use of this embodiment. Figure 24 is a schematic plan view showing an overall form of the semiconductor device for power use of Embodiment 3. Figure 25 is Figure 24 a schematic plan view of a portion of the semiconductor device for power use in which semiconductor elements are particularly arranged. Figure 26 is a schematic plan view showing Figure 24 a form of a core material of a printed circuit board and a conductor layer on the lower side in the Z direction of the semiconductor device for power use. Figure 27 is a schematic plan view showing Figure 24 a form of a core material of a printed circuit board and a conductor layer on the upper side in the Z direction of the semiconductor device for power use. In addition, Figure 24 , Figure 25 , Figure 26 , Figure 27 corresponds to Figure 1 of the first example of Embodiment 1 Figure 3 , Figure 4 , Figure 5 .

[0168] Refer to Figures 24 - 27 , the semiconductor device for power use 100 of this embodiment has substantially the same structure as the semiconductor device for power use 100 of Embodiment 2. Therefore, the same reference numerals are given to the same structural elements, and descriptions of matters common to Embodiment 2 are not repeated. Moreover, even if the reference numerals are different, the content not repeatedly described below is substantially the same as that of Embodiment 2.

[0169] In this embodiment, the printed circuit board 30 includes a pair of protrusions 34. The protrusion 34 is a portion that includes the first center line C1 in the central portion of the printed circuit board 30 in the X direction and protrudes in the Y direction at the outer edge in a plan view with respect to a region other than the central portion. That is, as Figure 24 , Figure 26 ,Figure 27 As shown, in the protrusion 34, the outer edge on the negative Y side of the rectangular core material 31 protrudes downward, i.e., on the negative Y side. Figure 24 In addition, in the protrusion 34, the outer edge on the positive Y side of the rectangular core material 31 protrudes upward, i.e., on the positive Y side. Figure 24 of the upper side.

[0170] Subsequently, in the present embodiment, a part of the metal column portions 51C among the plurality, except for the central portion of the printed circuit board 30 in plan view, is disposed on each of the pair of protrusions 34. That is, for example, two metal column portions 51C and the through portion 36C on the first center line C1 in Embodiment 2, except for the center of the printed circuit board 30, are arranged to overlap with each of the pair of protrusions 34. Therefore, on the surface of the core material 31 in each of the pair of protrusions 34, a pattern of the first conductor layer 32 with a small planar area and a pattern of the non-bonding pad 33b are formed. The protrusion 34, each of the patterns with a small planar area overlapping therewith, and the metal column portion 51C are arranged to be substantially linearly aligned with the signal electrode 21c that is exposed without overlapping the printed circuit board 30 in the X direction.

[0171] In addition, the first conductor layer 32, the second conductor layer 33, and the metal column portion 51C formed in the protrusion 24 are formed to support the printed circuit board 30. Therefore, the first conductor layer 32, the second conductor layer 33, and the metal column portion 51C formed in the protrusion 24 are independent of the circuit (so-called power circuit) of the power conversion system described later.

[0172] As described above, an example having the through portion 36C and the metal column portion 51C has been described. However, in Figures 24 - 27 , instead of the through portion 36C and the metal column portion 51C, the through portion 36B and the metal column portion 51B can also be used, or the missing portion 36A and the metal column portion 51A can also be used. Regarding other modified examples, the examples conceivable in Embodiment 2 can basically be conceived in Embodiment 3 as well.

[0173] Next, the operation and effects of the present embodiment will be described. In addition to the same operation and effects as those of Embodiment 1 and Embodiment 2, the present embodiment also achieves the following operation and effects.

[0174] The semiconductor device 100 for power use according to the present disclosure is preferably premised on Embodiment 2. Further, regarding the semiconductor device 100 for power use, the printed circuit board 30 includes a pair of protrusions 34. The protrusions 34 include a first center line C1 in the central portion in the X direction as the first direction, and protrude in the Y direction as the second direction from the outer edge in a plan view of a region other than the central portion in the X direction. Among the plurality of metal column portions 51A to 51C other than one in the center, some of the plurality of metal column portions 51A to 51C are respectively disposed on each of the pair of protrusions 34. Such a structure may be adopted.

[0175] In this way, the regions where the first conductor layer 32 and the second conductor layer 33, which constitute the circuit (so-called power circuit) of the power conversion system described later, can be arranged can be expanded by a portion corresponding to the area of the protrusion 34. Therefore, the wiring density can be made higher.

[0176] Embodiment 4.

[0177] First, Figures 28 - 33 the structure of the semiconductor device for power use in this embodiment will be described. Figure 28 FIG. is a schematic plan view showing an overall form of the semiconductor device for power use in Embodiment 4 as viewed from above. Figure 29 FIG. is a schematic cross-sectional view of a portion along the Figure 28 XXIX-XXIX line of the semiconductor device for power use in Embodiment 4. Figure 30 FIG. is a schematic enlarged cross-sectional view of a portion XXX surrounded by a dashed line in Figure 29 Embodiment 4. Figure 31 FIG. is Figure 28 a schematic plan view of a portion where semiconductor elements are particularly arranged among the semiconductor devices for power use. Figure 32 FIG. is a schematic plan view showing Figure 28 the form of the core material of the printed circuit board and the conductor layer on the lower side in the Z direction among the semiconductor devices for power use. Figure 33 FIG. is a schematic cross-sectional view of a portion along the Figure 28 XXXIII-XXXIII line of the semiconductor device for power use in Embodiment 4. In addition, Figure 28 , Figure 29 , Figure 30 , Figure 31 , Figure 32 correspond to Figure 1 , Figure 2 , Figure 6 , Figure 3 , Figure 4 of the first example of Embodiment 1.

[0178] Refer to Figures 28 - 33, the semiconductor device 100 for power applications according to this embodiment has substantially the same structure as the semiconductor device 100 for power applications in the first example of Embodiment 1. Therefore, the same reference numerals are given to the same structural elements, and the description of matters common to the first example of Embodiment 1 will not be repeated. In addition, even if the reference numerals are different, the content not repeated below is basically the same as that of the first example of Embodiment 1.

[0179] In this embodiment, as the missing portions of the printed circuit board 30, in addition to the through-holes 36C, missing portions 36D are also formed. A plurality of missing portions 36D are formed at positions that overlap with the bonding pads 33a in a plan view. Similar to the missing portion 36A, the missing portion 36D does not penetrate the printed circuit board 30, but only penetrates a part of the Z direction connecting the first main surface and the second main surface of the printed circuit board 30. Specifically, the missing portion 36D is formed to penetrate the first conductor layer 32 in the region where it is formed, and expose the first main surface of the core material 31 directly below it.

[0180] Within the missing portion 36D, a metal column portion 51D is inserted in a manner extending along the Z direction in the same form as the metal column portion 51A. The metal column portion 51D does not penetrate the printed circuit board 30. The metal column portion 51D is connected to the printed circuit board 30 through a first conductive member 46D within the missing portion 36D. The lowermost portion of the metal column portion 51D is connected to the third conductor layer 13 of the insulating substrate 10 through a second conductive member 45D. In addition, the materials of the metal column portion 51D, the first conductive member 46D, and the second conductive member 45D are the same as those of the metal column portion 51C, the first conductive member 46C, and the second conductive member 45C.

[0181] In the first conductor layer 32 of the printed circuit board 30, a plurality of, for example, 8 missing portions 36D are formed. Therefore, the semiconductor device 100 for power applications has a plurality of, for example, 8 metal column portions 51D. The 8 missing portions 36D and the 8 metal column portions 51D inserted therethrough are arranged at intervals in the X direction and alternately with the emitter electrode 21b, which is the main electrode of the semiconductor element 21, on a straight line extending in the X direction. In other words, the 8 missing portions 36D and the 8 metal column portions 51D inserted therethrough are arranged with the semiconductor element 21 (emitter electrode 21b) interposed therebetween in the X direction. As Figure 31 shown, on the upper side and the lower side in the Y direction, a total of 8 missing portions 36D and metal column portions 51D, 4 in each, are arranged with each semiconductor element among the semiconductor elements 21 arranged in 3 in a column interposed therebetween in the X direction. The number of metal column portions 51D arranged in a straight line with the semiconductor element 21 interposed therebetween in the X direction is arbitrary. In addition, based on the above, as Figure 33 shown, the metal column portion 51D and the third conductive member 42 on the main electrode 21b of the semiconductor element 21 are arranged to be alternately arranged at intervals in the X direction.

[0182] In addition, as Figure 33 shown, in the present embodiment, at least a part of a plurality of positions (a plurality of bonding portions) of the connecting metal wires 90 on the bonding pads 33a is arranged at a position overlapping with the plurality of metal column portions 51D in a plan view. In other words, in the Z direction, from Figure 33 above to below, the bonding portions of the metal wires 90 and the metal column portions 51D are arranged in this order. Here, "a part" includes both the meaning of an area that is a part of the whole and the meaning of a part (at least one) among a plurality.

[0183] In addition, similarly to the first embodiment, the signal electrode 21c and the bonding pad 33a are connected by the metal wire 90. At least a part of the plurality of bonding portions where the metal wire 90 is bonded to the bonding pad 33a is arranged at a position overlapping with the third conductive member 42 in a plan view. In other words, in the Z direction, from Figure 33 above to below, the bonding portions of the metal wire 90, the third conductive member 42, and the semiconductor element 21 are arranged in this order. The definition of "a part" here is the same as above.

[0184] Based on the above, for each of the metal wires 90 of the plurality of metal wires, at least a part of it overlaps with either the third conductive member 42 or the metal column portion 51D in a plan view. The metal wires 90 of the plurality of metal wires are wired in a manner that does not interfere with each other.

[0185] Next, the effects of the present embodiment will be described. In addition to the same effects as the first embodiment, the present embodiment also achieves the following effects.

[0186] In the power semiconductor device 100 according to the present disclosure, a plurality of missing portions 36D are formed at positions overlapping with the bonding pads 33a in a plan view. The plurality of missing portions 36D at positions overlapping with the bonding pads 33a in a plan view and the metal column portions 51D within the plurality of missing portions 36D are arranged in a straight line in an alternating manner with the emitter electrode 21b that is the main electrode of the semiconductor element 21. Thus, for example, the bonding pads 33a are supported by the metal column portions 51D from below in the Z direction. Therefore, the flexure of the printed circuit board 30 caused by the load during the above-mentioned wire bonding process is further suppressed. Therefore, the bonding property of the metal wires 90 above the bonding pads 33a is further stabilized, and its reliability and productivity are further improved.

[0187] In the above-described semiconductor device 100 for power applications, at least a part of the position of the connecting metal wire 90 on the bonding pad 33a may also be arranged at a position that overlaps, in a plan view, with the metal column portion 51D at a position that overlaps the bonding pad 33a in a plan view. Thereby, the flexure of the printed circuit board 30 at the position (joint portion) of the connecting metal wire 90 on the bonding pad 33a is further suppressed. Accordingly, the joinability of the metal wire 90 above the bonding pad 33a is further stabilized, and its reliability and productivity are further improved.

[0188] Embodiment 5.

[0189] In this embodiment, the semiconductor devices of the above-described Embodiments 1 to 4 are applied to a power conversion device. The present disclosure is not limited to a specific power conversion device, but as Embodiment 5 below, the case where the present disclosure is applied to a three-phase inverter will be described.

[0190] Figure 34 FIG. is a block diagram showing the configuration of a power conversion system to which the power conversion device of Embodiment 5 is applied. In Figure 34 The power conversion system shown includes a power source 400, a power conversion device 200, and a load 300. The power source 400 is a DC power source that supplies DC power to the power conversion device 200. The power source 400 is not particularly limited, but can include, for example, a DC system, a solar cell, a storage battery, and may also include a rectifier circuit or an AC / DC converter connected to an AC system. The power source 400 may also include a DC / DC converter that converts the DC power output from the DC system into desired power.

[0191] The power conversion device 200 is a three-phase inverter connected between the power source 400 and the load 300, and converts the DC power supplied from the power source 400 into AC power and supplies the AC power to the load 300. The power conversion device 200 includes, as Figure 34 shown, a main conversion circuit 201 that converts the input DC power into AC power and outputs it, and a control circuit 203 that outputs a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201.

[0192] The load 300 is a three-phase motor driven by the AC power supplied from the power conversion device 200. In addition, the load 300 is not limited to a specific use and is a motor incorporated in various electrical devices. The load 300 is used, for example, as a motor for a hybrid vehicle, an electric vehicle, a railway vehicle, an elevator, or an air conditioning device.

[0193] The power conversion device 200 will be described in detail below. The main conversion circuit 201 includes switching elements and freewheeling diodes (not shown). The switching elements switch the voltage supplied from the power source 400. As a result, the main conversion circuit 201 converts the DC power supplied from the power source 400 into AC power and supplies it to the load 300. The specific circuit structure of the main conversion circuit 201 has various structures, but the main conversion circuit 201 of the present embodiment is a two-level three-phase full-bridge circuit, and may include six switching elements and six freewheeling diodes anti-parallelly connected to the respective switching elements. At least one of each switching element and each freewheeling diode of the main conversion circuit 201 is the semiconductor element 21 and the diode 22 included in any of the power semiconductor devices 100 of the above-described Embodiments 1 to 4. As the power semiconductor module 202 constituting the main conversion circuit 201, any of the power semiconductor devices 100 of the above-described Embodiments 1 to 4 can be applied. Two of the six switching elements are connected in series to form upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. Then, the three output terminals of the main conversion circuit 201, which are the output terminals of each upper and lower arm, are connected to the load 300.

[0194] In addition, the main conversion circuit 201 includes a drive circuit (not shown) for driving each switching element. The drive circuit may be built in the power semiconductor module 202, or may be a structure in which the drive circuit is separately provided from the power semiconductor module 202. The drive circuit generates a drive signal for driving the switching elements of the main conversion circuit 201 and supplies the drive signal to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, according to a control signal from a control circuit 203 described later, a drive signal that makes the switching element in an on state and a drive signal that makes the switching element in an off state are output to the control electrodes of the respective switching elements. When the switching element is maintained in the on state, the drive signal is a voltage signal (on signal) equal to or higher than the threshold voltage of the switching element, and when the switching element is maintained in the off state, the drive signal becomes a voltage signal (off signal) lower than the threshold voltage of the switching element.

[0195] The control circuit 203 controls the switching elements of the main conversion circuit 201 to supply desired power to the load 300. Specifically, based on the power to be supplied to the load 300, the time (on time) during which each switching element of the main conversion circuit 201 should be in the on state is calculated. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the on time of the switching elements according to the voltage to be output. Then, a control command (control signal) is output to the drive circuit included in the main conversion circuit 201 to output an on signal to the switching elements that should be in the on state at each time point and an off signal to the switching elements that should be in the off state. The drive circuit outputs an on signal or an off signal as a drive signal to the control electrodes of the respective switching elements according to this control signal.

[0196] As described above, in the power conversion device 200 of the present embodiment, as the power semiconductor module 202 constituting the main conversion circuit 201, the semiconductor device 100 for power use according to any of the first to fourth embodiments is applied. Therefore, similar to the above-described respective embodiments, the power conversion device 200 of the present embodiment can miniaturize the insulating substrate 10 and suppress connection failures.

[0197] In the present embodiment, an example in which the present disclosure is applied to a two-level three-phase inverter has been described. However, the present disclosure is not limited thereto, and can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is assumed, but it may also be a three-level power conversion device. Alternatively, it may be a multi-level power conversion device. When the power conversion device supplies power to a single-phase load, the present disclosure can also be applied to a single-phase inverter. When the power conversion device supplies power to a DC load or the like, the present disclosure can also be applied to a DC / DC converter or an AC / DC converter.

[0198] The power conversion device to which the present disclosure is applied is not limited to the case where the load is a motor. For example, it can be incorporated into a power supply device of an electric discharge machine or a laser processing machine, or a power supply device of an induction heating cooker or a non-contact power supply system. The power conversion device to which the present disclosure is applied can be used as a power conditioner for a solar power generation system or a power storage system.

[0199] The features described in the above-described respective embodiments (including each example) can also be applied in a manner of being appropriately combined within a technically non-contradictory range.

[0200] It should be considered that the embodiments disclosed this time are illustrative in all respects and not restrictive. The scope of the present disclosure is intended to be shown by the claims rather than the above description, and includes all changes within the meaning and scope equivalent to the claims.

Claims

1. A semiconductor device for electric power, comprising: An insulating substrate; A semiconductor element bonded to one main surface of the insulating substrate; and A printed circuit board bonded so as to face the semiconductor element, A main electrode and a signal electrode are formed on the semiconductor element, The printed circuit board includes a core material, a first conductor layer formed on a first main surface of the core material on the semiconductor element side, and a second conductor layer formed on a second main surface of the core material opposite to the first main surface, The second conductor layer has a bonding pad, A missing portion formed by partially missing the first conductor layer is formed on the printed circuit board, The semiconductor device for electric power further includes a metal column portion that penetrates into the missing portion and reaches the insulating substrate, and is connected to the printed circuit board through a first conductive member, The signal electrode and the bonding pad are connected by a metal wire, The metal column portion and the insulating substrate are joined through a second conductive member.

2. The semiconductor device for electric power according to claim 1, wherein, The missing portion is a through portion that passes through the entire thickness of the printed circuit board in a direction connecting the first main surface and the second main surface, passing through all of the first conductor layer, the core material, and the second conductor layer. The metal post portion penetrates through the through portion from one main surface of the insulating substrate and extends to the side opposite to the insulating substrate within the through portion.

3. The semiconductor device for electric power according to claim 1 or 2, wherein, The main electrode and the printed circuit board are connected by a third conductive member.

4. The semiconductor device for electric power according to claim 3, wherein, At least a part of the main electrode of the semiconductor element to which the third conductive member is attached is disposed at a position that overlaps with the bonding pad in a top view.

5. The semiconductor device for electric power according to claim 4, wherein, At least a part of the position on the bonding pad to which the metal wire is connected is disposed at a position that overlaps with the semiconductor element and the third conductive member in a top view.

6. The semiconductor device for electric power according to any one of claims 1 to 5, wherein, A plurality of the metal post portions are arranged. One of the plurality of metal post portions is disposed at the center of the printed circuit board in a top view. The other plurality of metal post portions among the plurality of metal post portions are disposed at positions that are point-symmetric with respect to the center of the printed circuit board.

7. The semiconductor device for electric power according to claim 6, wherein, A part of the other plurality of metal post portions is arranged on a first center line, which is a line passing through the center in a first direction of the printed circuit board in a top view. The part of the plurality of metal post portions is disposed at positions that are line-symmetric with respect to a second center line, which is a line passing through the center in a second direction orthogonal to the first direction of the printed circuit board in a top view.

8. The semiconductor device for electric power according to claim 7, wherein, The printed circuit board includes a pair of protrusions at a central portion in the first direction. The protrusions include the first center line, and the outer edge of the protrusions in a top view protrudes in the second direction with respect to the region other than the central portion. The part of the plurality of metal post portions are respectively disposed on each of the pair of protrusions.

9. The semiconductor device for electric power according to any one of claims 1 to 8, wherein, A plurality of the missing portions are formed at positions that overlap with the bonding pad in a top view. The plurality of missing portions at positions that overlap with the bonding pad in a top view and the metal post portions within the plurality of missing portions are arranged in a straight line in an alternating manner with the main electrode.

10. The semiconductor device for electric power according to claim 9, wherein, At least a part of the position on the bonding pad to which the metal wire is connected is disposed at a position that overlaps with the metal post portion at a position that overlaps with the bonding pad in a top view in a top view.

11. A power conversion device, comprising: A main conversion circuit having the semiconductor device for electric power according to any one of claims 1 to 10, the main conversion circuit converting the input electric power and outputting it; and A control circuit that outputs a control signal for controlling the main conversion circuit to the main conversion circuit.

12. A method for manufacturing a semiconductor device for electric power, comprising: A step of preparing an insulating substrate having a semiconductor element formed with a signal electrode bonded to one main surface; A process of preparing a printed circuit board, the printed circuit board including a core material, a first conductor layer formed on a first main surface of the core material, and a second conductor layer formed on a second main surface of the core material opposite to the first main surface, the printed circuit board having a missing portion formed by partial deletion of the first conductor layer; A process of joining a metal post portion inserted into the missing portion and extending outside the missing portion to the missing portion by a first conductive member; A process of disposing the printed circuit board facing the semiconductor element and joining the metal post portion and the insulating substrate by a second conductive member; And A process of connecting the signal electrode and the bonding pad included in the second conductor layer through a metal wire.

13. The method for manufacturing a semiconductor device for electric power according to claim 12, wherein, The missing part is a through-hole portion that penetrates the entire printed circuit board in a direction connecting the first main surface and the second main surface, and penetrates all of the first conductor layer, the core material, and the second conductor layer. In the process of bonding through the second conductive member, the metal column portion is configured to penetrate through the through-hole portion from the one main surface of the insulating substrate and extend to the opposite side of the through-hole portion from the insulating substrate.

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