A light-emitting diode and a light-emitting device thereof

Abstract

The present invention discloses a light-emitting diode, comprising: a semiconductor layer sequence having sidewalls and opposite first and second surfaces, including a semiconductor layer sequence arranged in sequence between the first and second surfaces, the second surface having a recess that at least penetrates an active layer, a second-type semiconductor layer, and a part of a first-type semiconductor layer, a first electrical connection layer being electrically connected to the first-type semiconductor layer through the recess, the first electrical connection layer including a reflective metal; the recess is located on the sidewall, and at least the sidewall above the recess has surface roughening, preventing abnormal yellow light process in the chip process due to the reflective metal and improving the product yield.

Description

Technical Field

[0001] The present invention relates to an optoelectronic component, and more particularly to a light-emitting diode structure and a light-emitting device thereof. Background Art

[0002] The current vertical product process only uses N-type conductive holes in the light-emitting region to achieve the functions of current spreading and current reduction. The disadvantage is that when the area of the N holes increases, the light-emitting region (roughened surface) also becomes smaller, resulting in a decrease in brightness. When fabricating N-type conductive holes with an increasingly smaller chip size, the process window is limited by the process platform, causing difficulties in the manufacturing process. Summary of the Invention

[0003] In order to solve the technical problems in the background art, a light-emitting diode is proposed, including:

[0004] A semiconductor layer sequence having sidewalls and opposite first and second surfaces, including a first-type semiconductor layer, an active layer designed to generate radiation, and a second-type semiconductor layer sequentially arranged between the first and second surfaces, a first electrical connection layer electrically connected to the first-type semiconductor layer, a second electrical connection layer electrically connected to the second-type semiconductor layer. The second surface of the semiconductor layer sequence has a recess that at least penetrates the active layer, the second-type semiconductor layer, and a part of the first-type semiconductor layer. An insulating layer extends from the recess to the second surface. The first electrical connection layer forms a protrusion in the recess. The first electrical connection layer is electrically connected to the first-type semiconductor layer through the recess. The first electrical connection layer and the second electrical connection layer are electrically isolated by the insulating layer. The first electrical connection layer includes a metal;

[0005] The recess is located at the edge of the sidewall and partially exposed from the sidewall. The recess is arranged at the edge of the light-emitting region, reducing the process difficulty, enlarging the chip manufacturing process window, and avoiding exposure abnormalities caused by metal scattering or reflection. The recess is arranged on the scribe line of the light-emitting diode chip.

[0006] According to the present invention, preferably, the first electrical connection layer includes a reflective metal, and at least the sidewall above the recess has a roughened surface, avoiding deviation of the photomask process from the design due to the reflective metal in the yellow light process, resulting in a decrease in the yield rate, blocking light from entering the semiconductor layer sequence, and being reflected by the reflective metal layer, causing photoresist (photoresist) abnormalities.

[0007] According to the present invention, preferably, the position of the first surface corresponding to the recess has a roughened surface or a patterned surface, and the area of the roughened surface or the patterned surface is at least 120% of the cross-sectional area of the recess.

[0008] According to the present invention, preferably, the reflective metal includes silver, aluminum, gold, titanium, or rhodium.

[0009] According to the present invention, preferably, the average particle size of the roughened sidewall surface above the recess is 0.5 μm to 2 μm. The sufficiently large roughened particles prevent light from entering the semiconductor layer sequence from being reflected by the reflective metal.

[0010] In some embodiments, preferably, the recesses are arranged continuously or discretely along the sidewalls.

[0011] In these embodiments, preferably, when the unilateral size of the light-emitting diode is less than 500 μm, the recesses are arranged continuously along the sidewalls; when the unilateral size of the light-emitting diode is not less than 500 μm, the recesses are discretely distributed along the sidewalls, increasing the current distribution uniformity.

[0012] In some embodiments, preferably, when the recesses are discretely arranged, the sidewalls between the recesses include a first-type semiconductor layer, an active layer, and a second-type semiconductor layer.

[0013] According to these embodiments, preferably, the sidewall includes a first sidewall and a second sidewall. The first sidewall includes a first-type semiconductor layer, the second sidewall includes a second-type semiconductor layer, and the average roughness of the first sidewall is not less than that of the second sidewall.

[0014] According to these embodiments, preferably, the height of the first sidewall is higher than that of the second sidewall.

[0015] According to these embodiments, preferably, the angle between the first sidewall and / or the second sidewall and the vertical plane is 20° to 60°.

[0016] In some embodiments of the present invention, the sidewall surface has steps, and the number of steps is not less than 3.

[0017] According to these embodiments, preferably, the width range of the steps is 1 nm to 5000 nm.

[0018] According to these embodiments, preferably, at least some of the steps are surface roughened, and from the second-type semiconductor layer to the first-type semiconductor layer, it is smooth to rough from bottom to top.

[0019] According to these embodiments, preferably, the particle size of the surface roughening is arranged in layers from small to large from the second-type semiconductor layer to the first-type semiconductor layer from bottom to top.

[0020] According to these embodiments, preferably, a conductive or insulating substrate is further provided on one side of the second surface.

[0021] According to the present invention, preferably, the first-type semiconductor layer, the active layer, and / or the second-type semiconductor layer are gallium nitride-based, and the surface roughening is performed by wet etching. The etching liquid includes KOH or NaOH with a relatively slow reaction rate. The reaction rate is slow and relatively gentle, which is beneficial to forming multiple steps at one time.

[0022] According to the present invention, preferably, the first surface is a light-emitting surface, and at least a part of the first surface is a roughened surface.

[0023] According to the present invention, preferably, the first-type semiconductor layer, the active layer, and / or the second-type semiconductor layer are gallium nitride-based.

[0024] According to the present invention, preferably, the side wall of the recess includes a first-type semiconductor layer. The first-type semiconductor layer is an N-type semiconductor layer and is doped with silicon. The second-type semiconductor layer is a P-type semiconductor layer and is doped with magnesium. The growth temperature of the first-type semiconductor layer is higher than that of the second-type semiconductor layer, and the growth rate of the first-type semiconductor layer is faster than that of the second-type semiconductor layer.

[0025] According to the present invention, preferably, the first electrical connection layer and / or the second electrical connection layer include a transparent conductive layer, and the transparent conductive layer is used to make an ohmic contact.

[0026] According to the present invention, preferably, the distance between the protrusion and the side wall is not greater than 8 μm.

[0027] The present invention also provides another light-emitting diode, comprising:

[0028] A semiconductor layer sequence having side walls and opposite first and second surfaces, including a first-type semiconductor layer, an active layer designed to generate radiation, a second-type semiconductor layer sequentially arranged between the first and second surfaces, a first electrical connection layer electrically connected to the first-type semiconductor layer, a second electrical connection layer electrically connected to the second-type semiconductor layer. The second surface has a recess that at least penetrates the active layer, the second-type semiconductor layer, and a part of the first-type semiconductor layer. An insulating layer extends from the recess to the second surface. The first electrical connection layer is electrically connected to the first-type semiconductor layer through the recess. The first electrical connection layer and the second electrical connection layer are electrically isolated by the insulating layer. The first electrical connection layer includes a reflective metal;

[0029] The distance between the recess and the side wall is 2 to 5 μm. In particular, the distance between the first electrical connection layer in the recess and the side wall is 2 to 5 μm. The recess is arranged in the light-emitting area. At least the side wall outside the recess has a surface roughening, avoiding deviation of the photomask process from the design due to the reflective metal in the yellow light process, resulting in a decrease in the yield, blocking light from entering the semiconductor layer sequence, and being reflected by the reflective metal layer, causing abnormalities in the photoresist.

[0030] According to the present invention, preferably, the position of the first surface corresponding to the recess has a roughened surface or a patterned surface, and the area of the roughened surface or the patterned surface is at least 120% of the cross-sectional area of the recess.

[0031] According to the present invention, preferably, the average particle size of the roughened sidewall surface above the recess is 0.5 μm to 2 μm. The sufficiently large roughened particles prevent light from entering the semiconductor layer sequence and being reflected by the reflective metal.

[0032] In some embodiments, preferably, the recesses are arranged continuously or discretely along the sidewalls.

[0033] According to the present invention, preferably, a conductive or insulating substrate is further provided on one side of the second surface.

[0034] According to the present invention, preferably, wet etching is used for surface roughening, and the etching liquid includes KOH or NaOH with a relatively slow reaction rate.

[0035] According to the present invention, preferably, the first-type semiconductor layer, the active layer, and / or the second-type semiconductor layer are gallium nitride-based.

[0036] The present invention also provides a light-emitting device, which has a packaging substrate and a glue layer. The above-mentioned light-emitting diode has its substrate partially or completely covered by the glue layer. In some embodiments, at least a part of the sidewalls of the light-emitting diode is covered by the glue layer.

[0037] Specifically, it includes a substrate, at least one light-emitting diode chip mounted on the substrate, and a glue material covering a part of the substrate and the sidewalls of a part of the light-emitting diode chip. The height of the glue material covering the highest point of the sidewall of the light-emitting diode chip does not exceed the height of the first surface of the semiconductor epitaxial stack of the light-emitting diode chip.

[0038] According to the present invention, preferably, the stepped corner design can effectively prevent the glue material from climbing. The more the number of steps, the more the corners, and the better the effect of preventing the glue material from climbing over to the chip surface.

[0039] As a further design, preferably, the angle range between the stepped slope of the stepped roughened structure and the horizontal plane is 30° to 50°, taking into account both the area of the light-emitting region and the impedance ability of the glue climbing during packaging.

[0040] The larger the angle between the stepped slope and the horizontal plane, the more the number of steps formed, the more the corners of the steps, and the better the effect of preventing the glue material from climbing over to the chip surface.

[0041] According to the present invention, preferably, the distance between the position where the glue material covers the highest point of the sidewall of the light-emitting diode chip and the first surface of the semiconductor epitaxial stack of the light-emitting diode chip ranges from greater than 0.1 μm.

[0042] According to the present invention, preferably, the stepped width ranges from 1 nm to 5000 nm, and the stepped width is at least greater than 1 nm to achieve the purpose of preventing the glue material from climbing.

[0043] According to the present invention, preferably, the step thickness ranges from 0.1 μm to 4 μm, or from 4 μm to 10 μm.

[0044] The smaller the step thickness, the more steps are formed, the more corners there are, and the better the effect of preventing the adhesive material from climbing over to the chip surface.

[0045] According to the present invention, preferably, the step thickness increases and decreases in a stepped manner from bottom to top, and the step thickness near the first surface of the semiconductor epitaxial stack is the smallest.

[0046] The corners of the steps can effectively prevent the adhesive material from climbing. The closer the corners are to the first surface of the semiconductor epitaxial stack, the better the effect of preventing the adhesive material from climbing over to the chip surface.

[0047] Compared with the prior art, the present application has at least the following beneficial effects:

[0048] 1. Solve the problems in the background art, overcome the difficulties in the manufacturing process caused by the limited process platform, and expand the process window by arranging the recess corresponding to the N holes (grooves) on the side wall and partially exposing it;

[0049] 2. By roughening the side wall surface, prevent the lithography process in the chip manufacturing process from being affected by the reflective metal material in the recess of the N holes (grooves), resulting in abnormal lithography, and avoid the light reflected from the side wall reaching the photoresist on the chip surface, causing the photoresist to absorb light non-presumably, resulting in problems in etching and unable to obtain the expected patterned structure;

[0050] 3. By roughening the side wall surface, prevent the adhesive layer from spreading upward to the first surface and affecting the light output effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0052] Figure 1 It is a schematic cross-sectional structure diagram of the first embodiment of the present invention;

[0053] Figure 2 and Figure 3 It is a schematic top view structure diagram of the first embodiment of the present invention. It should be noted that since the first type semiconductor layer above the recess has good light transmittance, the first electrical connection layer can be directly seen in the top view;

[0054] Figure 4 It is a schematic cross-sectional structure diagram of the second embodiment of the present invention;

[0055] Figure 5 and Figure 6 is a schematic cross-sectional structure diagram of the third embodiment of the present invention;

[0056] Figure 7 is a schematic cross-sectional structure diagram of the fourth embodiment of the present invention;

[0057] Figure 8 is a schematic cross-sectional structure diagram of the fifth embodiment of the present invention;

[0058] Figure 9 is a schematic cross-sectional structure diagram of the sixth embodiment of the present invention;

[0059] Figure 10 is a schematic cross-sectional structure diagram of the seventh embodiment of the present invention;

[0060] Figure 11 is a schematic cross-sectional structure diagram of the eighth embodiment of the present invention;

[0061] Identifications in the figure: 100, semiconductor layer sequence; 100`, sidewall; 100A`, first sidewall; 100B`, second sidewall; 101, first surface; 102, second surface; 103, groove; 104, step; 110, first-type semiconductor layer; 120, second-type semiconductor layer; 130, active layer; 210, first electrical connection layer; 211, bonding metal layer; 212, contact layer; 213, reflective layer; 220, second electrical connection layer; 221, transparent conductive layer; 222, reflective layer; 223, metal connection layer; 310, first insulating layer; 320, second insulating layer; 330, protective layer; 410, first electrode; 420, second electrode; 421, bonding wire; 500, light-blocking layer; 510, roughening cover layer; 600, white glue; 700, packaging base; 800, cavity. Detailed implementation manners

[0062] The following illustrates the implementation manners of the present application through specific specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or operated through other different specific implementation manners. Various details in the present application can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application.

[0063] Refer to Figures 1 to 3, in the first embodiment of the present invention, a light-emitting diode is disclosed, comprising: a semiconductor layer sequence 100 as an epitaxial structure, the semiconductor layer sequence 100 having sidewalls 100` and opposite first surface 101 and second surface 102, including a first-type semiconductor layer 110, a second-type semiconductor layer 120, and an active layer 130 located therebetween and designed to emit light, arranged in sequence between the first surface 101 and the second surface 102, a first electrical connection layer 210 electrically connected to the first-type semiconductor layer 110, a second electrical connection layer 220 electrically connected to the second-type semiconductor layer 120, the second surface 102 having a recess 103, the recess 103 penetrating at least the active layer 130, the second-type semiconductor layer 120, and a part of the first-type semiconductor layer 110, a first insulating layer 310 extending from the recess 103 to the second surface 102, the first electrical connection layer 210 forming a protrusion within the recess and being electrically connected to the first-type semiconductor layer 110 through the recess 103, electrically isolating the first electrical connection layer 210 and the second electrical connection layer 220 by using the first insulating layer 310 and the second insulating layer 320, and the first electrical connection layer 210 and / or the second electrical connection layer 220 including metal; in this embodiment, the recess 103 is located on the sidewall 100`, and a part of the recess 103 is exposed from the sidewall 100`.

[0064] The recesses 103 are arranged continuously or discretely along the sidewall 100`. In this embodiment, two corresponding size designs are proposed. When the unilateral size of the light-emitting diode is less than 600 μm, the recesses 103 are arranged continuously along the sidewall 100`. When the unilateral size of the light-emitting diode is not less than 600 μm, the recesses 103 are discretely distributed along the sidewall. When the recesses 103 are discretely arranged, the sidewall 100` between the recesses 103 includes the first-type semiconductor layer 110, the active layer 130, and the second-type semiconductor layer 120. When thinning the semiconductor layer sequence 100, using a patterning technique, a thickening design is added to the first surface 101 corresponding to the recess 103 to avoid abnormal current spreading caused by the first-type semiconductor layer 110 above the recess 103 being too thin.

[0065] In this embodiment, a conductive or insulating substrate is further provided on one side of the second surface 102. Taking the conductive substrate as an example in this embodiment, the conductive substrate is electrically connected to the contact layer 212 through a bonding metal layer 211. The material of the conductive substrate may include silicon, copper, molybdenum, or tungsten. In this embodiment, the conductive substrate serves as the first electrode 410 and is connected to the first electrical connection layer 210, and a second electrode 420 is provided on the upper surface of the second electrical connection layer 220. The first electrode 410 and the second electrode 420 are used to connect to an external circuit.

[0066] In this embodiment, the second electrical connection layer 220 includes a transparent conductive layer 221 for contacting the semiconductor layer sequence 100, a second reflective layer 2222, and a metal connection layer 223.

[0067] See Figure 4 Figure 4 , in the second embodiment of the present invention, the difference from the first embodiment is that the first electrical connection layer 210 includes a first reflective layer 213, and the reflective metal of the first reflective layer 213 includes silver, aluminum, gold, titanium or rhodium. The distance from the protruding portion of the first reflective layer 213, especially the protruding portion where the first electrical connection layer fills the recess, to the side wall is not greater than 8 μm. Correspondingly, at least the side wall 100` above the recess 103 is provided with surface roughening. The average particle size of the surface roughening of the side wall above the recess 103 is 0.1 μm to 2 μm, and light from the outside is avoided from hitting the first reflective layer 213 through surface particles. The angle between the side wall 100` and the vertical plane is 20° to 60°. In this embodiment, the method of surface roughening is wet etching, and the etching liquid includes KOH or NaOH. Using a relatively mild alkaline etching solution for etching, it is completed in one etching process. The first type semiconductor layer 110, the active layer 130 and / or the second type semiconductor layer 120 are gallium nitride-based. The side wall 100` of the recess 103 includes a first type semiconductor layer 110. The first type semiconductor layer 110 is an N-type semiconductor layer, the first type semiconductor layer 110 is doped with silicon, the second type semiconductor layer 120 is a P-type semiconductor layer, the second type semiconductor layer 120 is doped with magnesium, the growth temperature of the first type semiconductor layer 110 is higher than that of the second type semiconductor layer 120, the growth rate of the first type semiconductor layer 110 is faster than that of the second type semiconductor layer 120, and during the etching process, the etching rate of the first type semiconductor layer 110 is faster than that of the second type semiconductor layer 120. Therefore, by controlling the etching conditions, larger roughening particles can be produced. The structure of the surface roughening includes irregular roughening shapes, hemispherical shapes, conical shapes or cone-like shapes, etc.

[0068] See Figure 5 and Figure 6 Figure 6 , in the third embodiment of the present invention, the first surface 101 is a light-emitting surface, and light is excited by the active layer 130 and emitted from the first surface 101. At least a part of the first surface 101 is a roughened surface. In some embodiments of this embodiment, the position of the first surface 101 corresponding to the recess 103 has a roughened surface or a patterned surface. Looking from the top view direction, the area of the roughened surface or the patterned surface is at least 120% of the cross-sectional area of the recess 103 to ensure sufficient shielding of the light in the photolithography process from hitting the reflective material in the recess 103. The roughness range of the roughening structure on the first surface 101 is not less than 0.5 μm, for example, 0.5 μm to 2 μm.

[0069] See Figure 7, in the fourth embodiment of the present invention, at the position of the first surface 101 corresponding to the recess 103 and the position of the upper sidewall 100`, a light-blocking layer 500 is provided. The light-blocking layer 500 is, for example, a mirror or an opaque layer. The light-blocking layer 500 is used to prevent light from entering the semiconductor layer sequence 100 during lithography, such as a distributed Bragg reflector (DBR) or a selectively transmissive layer. In this embodiment, the light-blocking layer 500 is an insulating material. The light-blocking layer 500 extends from the light-emitting surface towards the substrate.

[0070] See Figure 8 , in the fifth embodiment of the present invention, at the position of the first surface 101 corresponding to the recess 103 and the position of the upper sidewall 100`, there is a roughened covering layer 510 that serves as a light blocker. For example, it can be a roughened insulating layer, and the material includes silicon dioxide, aluminum oxide, silicon nitride, or titanium oxide. The light-blocking roughened covering layer 510 is used to prevent light from entering the semiconductor layer sequence 100 during lithography. The roughened covering layer 510 with a roughened structure can prevent... In this embodiment, the roughened covering layer 510 extends from the first surface 101 towards the second surface 102.

[0071] See Figure 9 , in the sixth embodiment of the present invention, the sidewall 100` includes a first sidewall 100A` and a second sidewall 100B`. The first sidewall 100A` is formed by the first-type semiconductor layer 110 extending along an inclined plane, and the inclined plane has a fixed or non-fixed inclination angle. The second sidewall 100B` is formed by the second-type semiconductor layer 120 extending along an inclined plane, and the inclined plane has a fixed or non-fixed inclination angle. The roughness of the first sidewall 110A` is not less than that of the second sidewall 110B`. The beneficial effect is that it effectively improves the light-emitting effect at a small angle. Among them, the height of the first sidewall 110A` is higher than that of the second sidewall 110B`. Relative to the second sidewall 110B`, the first sidewall 110A` is closer to the first surface 101. The angle between the first sidewall 110A` and / or the second sidewall 110B` and the vertical plane is 20° to 60°.

[0072] See Figure 10In the seventh embodiment of the present invention, on the basis of the fifth embodiment, a step 104 is provided on the side wall surface, and the step 104 has a relatively dark and dark dividing line in appearance. The step includes the top surface of the first surface, and the number of steps 104 is not less than 3. The width of the step 104 ranges from 1nm to 2000nm. At least part of the step 104 is surface roughening, from the second type semiconductor layer 120 to the first type semiconductor layer 110, relatively speaking, the second type semiconductor layer has a smooth sidewall, and the first type semiconductor layer has a rough sidewall. The particle size of the surface roughening is arranged in layers from small to large from the second type semiconductor layer 120 to the first type semiconductor layer 110 from bottom to top. The roughness range of the stepped roughening structure is 0.1μm~2μm, and the roughness of the second sidewall 100B' is not greater than 0.1μm.

[0073] See also Figure 11 In the eighth embodiment of the present invention, a light-emitting device is provided. When a light-emitting chip is packaged, when a glue material, such as white glue 600, is filled into the cavity 800, the white glue 600 easily goes over the chip and covers the light-emitting surface (first surface 101) of the chip, thereby reducing the light-emitting area of the chip.

[0074] By roughening the table of the semiconductor layer sequence, the light extraction efficiency of the light emitting diode can be improved, and the brightness of the light emitting diode can be improved. Since the side of the conventional chip is a continuous and simple semiconductor epitaxial surface, the roughening effect is not ideal, and when the glue is filled in the packaging process, the glue is easy to climb over the chip and cover the light-emitting surface of the chip, affecting the chip's light-emitting efficiency. At the same time, the continuous and simple surface is prone to cause the glue to climb, causing light loss and other abnormalities. Therefore, setting a step 104 on the side wall surface can prevent the glue from climbing easily, thereby achieving the effect of improving the overall light output brightness of the light-emitting device.

[0075] The light emitting device provided in this embodiment is a packaging structure of a light emitting diode chip, which includes a packaging substrate 700, a light emitting diode chip, a white glue 600, and may also include a phosphor layer. The light emitting diode chip is mounted on the upper surface of the packaging substrate 700. The white glue 600 at least partially or completely covers the substrate (e.g., a conductive substrate). In some embodiments, the white glue 600 at least partially covers the side wall.

[0076] In this embodiment, the light emitting diode chip takes a vertical chip structure as an example, and the chip structure includes: a semiconductor layer sequence 100, a side wall 100', a first electrode 410, and a second electrode 420;

[0077] A semiconductor layer sequence 100 has a first surface 101 and a second surface 102 which are oppositely arranged. In the semiconductor layer sequence 100 of this embodiment, the first-type semiconductor layer 110 is an N-type semiconductor layer, the second-type semiconductor layer 120 is a P-type semiconductor layer, and the active layer 130 is a multi-quantum well for generating radiation.

[0078] The sidewall 100` includes a first sidewall 100A` and a second sidewall 100B`.

[0079] The first sidewall 100A` is formed on the side of the first-conductivity-type semiconductor layer 110 and the active layer 130.

[0080] The second sidewall 100B` is formed on the side of the second-conductivity-type semiconductor layer 120.

[0081] A roughening structure is provided on all or part of the wall surface of the first sidewall 100A`. The roughening structure is arranged in a stepped pattern, and the roughness of the first sidewall 100A` is greater than that of the second sidewall 100B`.

[0082] The number of steps 104 of the stepped roughening structure is 2 or more than 3. The corners of the steps 104 can effectively prevent the glue from climbing. The more the number of steps, the more the corners. When filling the glue in the packaging process, a hindering effect can be formed, and the better the effect of preventing the glue from turning over the chip.

[0083] The roughness range of the stepped roughening structure is 0.2μm to 2μm, the roughness of the second sidewall 602 is not greater than 1μm, the particle size of the stepped roughening structure is arranged in layers from small to large from bottom to top, and the roughening degree is arranged in layers from smooth to rough from bottom to top. The stepped roughening structure can effectively reduce the light loss caused by total reflection and improve the light emission efficiency at the same time.

[0084] As a better option, the angle range between the inclined surface of the step 104 of the stepped roughening structure and the horizontal plane is 30° to 50°, taking into account ensuring sufficient area of the first surface 101 and the active area 130, and at the same time being beneficial to the design of preventing glue climbing.

[0085] The larger the angle between the inclined surface of the step 104 and the horizontal plane, the more the number of steps formed, the more the corners, and the better the effect of preventing the glue from turning over to the chip surface.

[0086] The width range of the step 104 of the stepped roughening structure is 1nm to 5000nm, and the width of the step 104 is at least greater than 1nm to achieve the purpose of preventing the glue from climbing.

[0087] The thickness range of the step 104 is 0.1μm to 4μm, or 4μm to 10μm.

[0088] The smaller the thickness of the step 104, the larger the number of steps 104 formed, the more corners there are, and the better the effect of preventing the adhesive material from climbing over to the chip surface.

[0089] The thickness of the step 104 of the stepped roughened structure decreases step by step from bottom to top, and the thickness of the step 104 closest to the first surface 101 of the semiconductor layer sequence is the smallest.

[0090] The corner steps of the step 104 can effectively prevent the adhesive material from climbing. The closer the corner is to the first surface 101 of the semiconductor epitaxial stack, the better the effect of preventing the adhesive material from climbing over to the chip surface.

[0091] A roughened structure is provided on the first surface 101, and the roughness range of the roughened structure is 0.5 μm to 2 μm; in some embodiments, the first surface 101 is provided with a structure alternating between a plane and an inclined plane, which can thereby increase the light-emitting area, and at the same time increase the roughened area and roughened density, effectively improving the light-emitting efficiency.

[0092] A first electrical connection layer 210 is provided on the positive side of the first type semiconductor layer 110, and the first electrode 410 faces the positive side; the back side of the second type semiconductor layer 120 is connected to the positive side of the second electrical connection layer 220; the substrate 400 may include a conductive substrate and an insulating substrate, and the conductive substrate material may include silicon, copper or molybdenum, and the insulating substrate is, for example, sapphire or ceramic. The first type semiconductor layer includes a low-temperature gallium nitride-based semiconductor material. The second type semiconductor layer includes a high-temperature gallium nitride-based semiconductor material. The active layer includes a material of gallium nitride / indium gallium nitride.

[0093] The roughened structures of the first sidewall 100A`, the second sidewall 100B` and the first surface 101 include irregular roughened shapes, regular spherical and conical roughened shapes.

[0094] In this embodiment, white glue covers the sidewall 100` of the light-emitting diode chip. The multi-layer stepped roughened structure of the sidewall 100 of the semiconductor layer sequence of the light-emitting diode chip can effectively form a blocking effect, preventing the white glue from easily climbing over the chip, so that the height of the highest point of the white glue covering the sidewall 100` does not exceed the height of the first surface 101 of the first type semiconductor layer of the light-emitting diode chip, preventing the white glue from covering the light-emitting surface of the chip and avoiding reducing the light-emitting area of the chip. At the same time, the sidewall 100` is a multi-layer stepped roughened structure, and the particle sizes are arranged in layers from small to large from bottom to top, and the roughening degree is arranged in layers from smooth to rough from bottom to top. The smooth surface in the lower part can reduce abnormal light loss caused by the climbing of white glue.

[0095] The distance from the position where the white glue 600 covers the highest point of the side wall 100` of the light-emitting diode chip to the first surface 101 of the light-emitting diode chip ranges from not less than 0.1 μm. The material of the white glue includes resin, such as silicone resin. Commonly used silicone resin can be transparent or white. In this embodiment, white silicone resin is used. In the existing design, there is a phenomenon of glue creeping, such as capillary phenomenon.

[0096] The step surface corner of the step 104 can effectively prevent the white glue from climbing. The closer the step surface corner is to the first surface 101 of the first type semiconductor layer, the better the effect of preventing the white glue from climbing over to the chip surface. The vertical distance from the step surface closest to the first surface to the first surface is not greater than 2 μm.

[0097] It should be noted that in the drawings of this embodiment, the height of the second electrode 420 is lower than that of the semiconductor layer sequence 100. In fact, the height of the second electrode 420 can also be higher than that of the semiconductor layer sequence 100, and at the same time, it can be ensured that the glue material will not climb onto the second electrode 420.

[0098] In the ninth embodiment of the present invention, the difference from Embodiment 8 is that at least the side walls of the semiconductor epitaxial stack are covered with a protective layer 330. The protective layer 330 has the function of preventing glue climbing. The refractive index of the protective layer 330 is less than that of the semiconductor layer sequence 100, which is beneficial to the light extraction from the side of the light-emitting diode. The protective layer 330 can include one or more insulating materials such as silicon dioxide, silicon nitride, and aluminum oxide. In this embodiment, the material of the protective layer 330 is silicon dioxide. The thickness of the protective layer 330 is 100 - 20000 angstroms. A multi-layer stepped roughened structure is formed on the protective layer 330, replacing the structure of directly roughening on the semiconductor layer sequence 100 in Embodiment 9.

[0099] In the tenth embodiment of the present invention, the difference from Embodiment 8 is that the side wall 100` has several step surfaces. The vertical distance D1 from the step surface of the step 104 closest to the first surface to the first surface 101 is not greater than 2 μm. By using the buffering effect of the step surface, it is possible to prevent the glue material from climbing to the first surface 101 during glue injection. The distance from the position where the glue material covers the highest point of the side wall of the light-emitting diode chip to the first surface 101 of the semiconductor epitaxial stack of the light-emitting diode chip ranges from greater than 0.1 μm.

[0100] In the eleventh embodiment of the present invention, the difference from Embodiment 10 is that the chip structure of Embodiment 7 can be used as the light source of the light-emitting device.

[0101] The above are only the preferred embodiments of the present application. It should be noted that for those of ordinary skill in the art, without departing from the technical principle of the present application, several improvements and substitutions can still be made, and these improvements and substitutions should also be regarded as the protection scope of the present application.

Claims

1. A light-emitting diode, comprising: A semiconductor layer sequence having sidewalls and oppositely disposed first and second surfaces, including a first-type semiconductor layer, an active layer designed to generate radiation, and a second-type semiconductor layer sequentially arranged between the first and second surfaces, A first electrical connection layer electrically connected to the first-type semiconductor layer, A second electrical connection layer electrically connected to the second-type semiconductor layer, The second surface of the semiconductor layer sequence has a recess that penetrates at least the active layer, the second-type semiconductor layer, and a part of the first-type semiconductor layer, An insulating layer extends from the recess to the second surface, The first electrical connection layer forms a protrusion within the recess, and the first electrical connection layer is electrically connected to the first-type semiconductor layer through the recess, An insulating layer is provided between the first electrical connection layer and the second electrical connection layer to electrically isolate the first electrical connection layer and the second electrical connection layer. The first electrical connection layer includes a reflective metal; Characterized in that the recess is located at the edge of the sidewall, Part is exposed from the sidewall, and at least the sidewall above the recess has surface roughening.

2. The light-emitting diode according to claim 1, wherein The average particle size of the surface roughening of the sidewall above the recess is from 0.05 μm to 2 μm.

3. A light-emitting diode according to claim 1, characterized in that, The recesses are arranged continuously or discretely along the sidewall.

4. A light emitting diode according to claim 1, characterized in that, When the unilateral size of the light-emitting diode is less than 500 μm, the recesses are arranged continuously along the sidewall. When the unilateral size of the light-emitting diode is not less than 500 μm, the recesses are discretely distributed along the sidewall.

5. A light emitting diode according to claim 4, characterized in that, When the recesses are discretely arranged, the sidewall between the recesses includes the first-type semiconductor layer, the active layer, and the second-type semiconductor layer.

6. A light-emitting diode according to claim 4, characterized in that, The sidewall includes a first sidewall and a second sidewall. The first sidewall includes the first-type semiconductor layer, and the second sidewall includes the second-type semiconductor layer. The average roughness of the first sidewall is not less than that of the second sidewall.

7. A light-emitting diode according to claim 1, characterized in that, The height of the first sidewall is higher than that of the second sidewall.

8. A light emitting diode according to claim 1, characterized in that, The angle between the first sidewall and / or the second sidewall and the vertical plane is from 20° to 60°.

9. A light-emitting diode according to claim 1, characterized in that, The sidewall surface has steps, and the number of steps is not less than 3.

10. A light-emitting diode according to claim 9, characterized in that, The width range of the steps is from 1 nm to 5000 nm.

11. A light emitting diode according to claim 9, characterized in that, At least part of the steps is surface roughening. From the second-type semiconductor layer to the first-type semiconductor layer, from bottom to top, it is from smooth to rough, and the particle size of the surface roughening is arranged in layers from small to large from the second-type semiconductor layer to the first-type semiconductor layer.

12. A light emitting diode according to claim 1, characterized in that, A conductive or insulating substrate is also provided on one side of the second surface.

13. A light-emitting diode according to claim 1, characterized in that, The first-type semiconductor layer, the active layer, and / or the second-type semiconductor layer is gallium nitride-based, and the surface roughening is by wet etching. The etching liquid includes KOH or NaOH, and it is completed in one etching process.

14. A light-emitting diode according to claim 1, characterized in that, The first surface is the light-emitting surface, and at least part of the area of the first surface is a roughened surface.

15. A light emitting diode according to claim 14, characterized in that, The position of the first surface corresponding to the recess has a roughened surface or a patterned surface, and the area of the roughened surface or the patterned surface is at least 120% of the cross-sectional area of the recess.

16. A light-emitting diode according to claim 1, characterized in that, The reflective metal includes silver, aluminum, gold, titanium, or rhodium.

17. A light emitting diode according to claim 1, wherein, The sidewall of the recess includes the first-type semiconductor layer. The first-type semiconductor layer is an N-type semiconductor layer, the first-type semiconductor layer is doped with silicon, the second-type semiconductor layer is a P-type semiconductor layer, the growth temperature of the first-type semiconductor layer is higher than that of the second-type semiconductor layer, and the growth rate of the first-type semiconductor layer is faster than that of the second-type semiconductor layer.

18. A light-emitting diode according to claim 1, characterized in that, The first electrical connection layer and / or the second electrical connection layer includes a transparent conductive layer, and the transparent conductive layer is used to make an ohmic contact.

19. A light emitting diode according to claim 1, characterized in that, The distance between the protrusion and the side wall is not greater than 8 μm.

20. A light-emitting diode according to claim 1, characterized in that, The recess is located on the scribe line of the light-emitting diode.

21. A light-emitting diode according to claim 1, characterized in that, The insulating layer partially covers the recess, and an insulating through hole is provided in the recess. The insulating through hole exposes the first-type semiconductor layer, so that the protrusion of the first electrical connection layer is in electrical contact with the first-type semiconductor layer; The insulating layer is in partial contact with the second surface and exposes the second-type semiconductor layer, so that the second electrical connection layer is in electrical contact with the second-type semiconductor layer.

22. A light-emitting device having a packaging substrate and a glue layer, characterized in that, A light-emitting diode according to any one of claims 1 to 21, wherein at least a part of the side wall of the light-emitting diode is covered by an adhesive layer.

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