Forming thin film resistors (TFRs) in integrated circuit devices using a TFR cap layer as an etch stop and / or hard mask

Abstract

A method for forming a thin film resistor (TFR) in an integrated circuit (IC) device is provided. A TFR film is formed over an IC structure including IC elements and IC element contacts and the TFR film is annealed. At least one TFR cap layer is formed and a TFR etch defines a TFR element from the TFR film. A TFR contact etch forms TFR contact openings over the TFR element and a metal layer is formed over the IC structure and extends into the TFR contact openings to form metal contacts to the IC element contacts and the TFR element. The TFR cap layer, e.g., SiN cap and / or oxide cap, formed over the TFR film can (a) provide an etch stop during the TFR contact etch and / or (b) provide a hard mask during the TFR etch, which can eliminate the use of a photo mask and thereby eliminate the post-etch removal of photo mask polymer.

Description

[0001] Related Patent Applications

[0002] This application claims priority to commonly owned U.S. Provisional Patent Application No. 62 / 982,905, filed February 28, 2020, the entire contents of which are incorporated herein by reference for all purposes. TECHNICAL FIELD

[0003] The present disclosure relates to systems and methods of forming thin film resistors, such as for forming thin film resistors integrated in semiconductor integrated circuit (IC) devices. BACKGROUND

[0004] Many integrated circuit (“IC”) devices contain thin film resistors (TFRs) that provide various advantages over other types of resistors. For example, TFRs can be highly accurate and can be trimmed to provide very precise resistance values. As another example, TFRs typically have small parasitic components, which provides advantageous high frequency behavior. Further, TFRs typically have a low temperature coefficient of resistance (TCR) after a suitable anneal process that, for example, “adjusts” the TCR to near zero values, which can provide stable operation over a wide range of operating temperatures. TFR annealing can be performed at greater than 500 °C (e.g., in the range of 500 °C - 525 °C) to optimize TCR values.

[0005] TFRs can include any suitable resistive film formed on or in an insulating substrate. Some common IC integrated TFR resistive film materials include SiCr, SiCCr, TaN, and TiN, although any other suitable material can also be used. Manufacturing integrated TFRs typically requires adding multiple processing steps to the back-end IC integration flow, such as several expensive photomask processes. It would be advantageous to reduce the number of such steps (particularly the number of photomask processes) to reduce the cost of integrated TFR manufacturing.

[0006] Another issue, due to the relatively low melting point of aluminum, involves forming and annealing the TFR in an IC device that uses an aluminum interconnect layer (e.g., an interconnect layer formed of aluminum, aluminum copper, or aluminum silicon copper). A common aluminum interconnect layer is formed as a layer stack, e.g., a Ti layer, followed by a TiN layer, followed by an AlSiC layer (or AlCu or Al layer), followed by a second Ti layer, and finally a second TiN layer. Typical TFR annealing that can involve temperatures equal to or higher than 500°C can adversely affect such aluminum interconnects, which have an acceptable annealing temperature limit of about 450°C. For example, in the above-described aluminum interconnect layer stack, when the TFR is formed and annealed (e.g., at temperatures equal to or higher than 500°C) after the aluminum interconnect layer stack is formed, TiAl3 can form at the grain boundaries within the aluminum interconnect layer stack, which increases the sheet resistance of the aluminum interconnect (e.g., by a factor of 50 or more), which can result in electromigration problems in the IC structure.

[0007] Yet another issue with certain TFR integration processes involves forming heavy polymer residues, e.g., during formation of the TFR itself, through the polymer photo mask used for TFR etching. Such polymer residues are often difficult to prevent or completely remove, as chemical cleaning processes used to remove such polymer residues can damage sensitive structures in the area, such as IC element contacts (e.g., tungsten vias) exposed to the chemical cleaner. SUMMARY

[0008] Embodiments of the present invention address various issues with conventional TFR integration by forming a thin film resistor (TFR) after formation of IC elements (e.g., memory devices) and contacts (e.g., tungsten vias), but before formation of a first metal / interconnect layer (commonly referred to as a "metal 1" layer). By forming the TFR before formation of the metal 1 layer, TFR annealing can be performed at temperatures that would adversely affect the material of the metal 1 layer (e.g., in the case of aluminum (or other metal with a low melting temperature) being used for the metal 1 layer). Thus, forming the TFR before formation of the metal 1 layer (e.g., an aluminum metal 1 layer) enables TFR annealing at optimal temperatures (e.g., to optimize the TCR value of the TFR film), such as annealing at temperatures equal to or higher than 500°C (e.g., in the range of 500°C-525°C). Thus, embodiments of the present invention enable formation and optimal annealing of the TFR in an IC production flow that utilizes aluminum interconnects.

[0009] As used herein, "forming" any particular material layer (or other structure) can include depositing the respective material layer, growing the respective material layer (e.g., growing an oxide layer), or otherwise forming the respective material layer, and can include various process steps known in the art with respect to forming various types of layers in an IC structure.

[0010] Additionally, as used herein, an "etch process" can include a single etch or can include multiple etches of different etch chemistries or other etch parameters.

[0011] In some embodiments, the process of forming the TFR includes only two photomasks added to the background IC production flow (i.e., the IC production flow without forming the TFR).

[0012] In some embodiments, the TFR integration process includes forming a relatively thin nitride cap layer (e.g., SiN cap layer) over the TFR film layer, which acts as an etch stop during a TFR contact etch used to form a contact opening for coupling a metal interconnect layer (e.g., metal 1 layer) to the TFR. The nitride cap layer can provide protection for underlying structures (e.g., tungsten vias or other IC element contacts), which can allow the use of chemical cleaners (which are typically harmful to unprotected structures) to remove photoresist polymer residue formed during the TFR etch process.

[0013] In other embodiments, a nitride cap layer (e.g., SiN cap layer) formed over the TFR film layer acts both (a) as a hard mask during a TFR etch used to define TFR elements from the TFR film layer and (b) as an etch stop during a subsequent TFR contact etch used to form a contact opening for coupling a metal interconnect layer (e.g., metal 1 layer) to the TFR. By providing a nitride cap layer that acts as a hard mask during the TFR etch, existing photoresist material on the structure (if any) can be removed prior to performing the TFR etch, thereby eliminating or greatly reducing the formation of polymer material during the TFR etch process and, thus, the need for chemical cleaners of such polymer material. Additionally, the nitride cap layer can protect underlying structures (e.g., tungsten vias or other IC element contacts) during the TFR contact etch.

[0014] In yet other embodiments, an oxide cap layer is formed over the nitride cap layer, which collectively act as a hard mask during the TFR etch (used to define TFR elements from the TFR film layer) to reduce or eliminate the formation of polymer during the TFR etch. The oxide cap layer can be rounded during the TFR etch, which can help prevent electrical shorts ("stringers") from occurring along the TFR elements and between adjacent metal layer structures (e.g., metal 1 layer structures).

[0015] In one aspect of the application, a method for forming an integrated thin film resistor (TFR) in a semiconductor integrated circuit device is provided. An integrated circuit (IC) structure is provided that can include a plurality of IC elements and a plurality of conductive IC element contacts coupled to the plurality of IC elements. A TFR film layer is formed over the IC structure, and a TFR etch stop cap layer is formed over the TFR film layer. A first etch process is performed to remove selected portions of the TFR etch stop cap layer and portions of the TFR film layer underneath, defining an etch stop cap and an underlying TFR element. An oxide cap layer is formed over the structure. A second etch is performed to form at least one oxide cap opening in the oxide cap layer over the TFR element, the second etch process stopping at the etch stop cap, and a third etch process is performed through the at least one oxide cap opening to form at least one TFR contact opening in the etch stop cap, exposing a surface of the TFR element. A metal interconnect layer is formed over the IC structure, and the metal interconnect layer includes (a) at least one metal interconnect element coupled to at least one conductive IC element contact of the plurality of conductive IC element contacts and (b) at least one metal interconnect extending into the at least one TFR contact opening to contact the underlying TFR element.

[0016] In some embodiments, a TFR anneal can be performed at any time after the TFR film layer is formed but before the metal interconnect layer is deposited, e.g., to reduce and / or optimize the temperature coefficient of resistance (TCR) of the TFR film layer or TFR element. For example, a TFR anneal can be performed prior to the first etch to define the TFR element, or a TFR anneal can be performed after the first etch to define the TFR element and before or after the oxide cap layer is formed, or a TFR anneal can be performed at any other time after the TFR film layer is formed but before the metal interconnect layer is deposited. As used herein, “reducing” the TCR of a TFR film layer or TFR element means reducing the absolute value of the TCR value, i.e., making the TCR closer to zero.

[0017] In some embodiments, the TFR anneal includes an anneal at a temperature of at least 500 °C. In some embodiments, the TFR anneal includes an anneal at a temperature of 515 °C ± 10 °C for 15 minutes - 60 minutes.

[0018] In some embodiments, the method further includes forming a dielectric etch stop layer over the IC structure prior to forming the TFR film layer, wherein the first etch stops at the dielectric etch stop layer.

[0019] In some embodiments, the IC structure includes: a memory cell or a transistor structure, the memory cell or the transistor structure including at least one electrically conductive IC element contact connected to at least one of a source region, a drain region, and a gate region of the memory cell or the transistor structure.

[0020] In some embodiments, the TFR film layer includes silicon carbide chromium (SiCCr), silicon chromium (SiCr), chromium silicon nitride (CrSiN), tantalum nitride (TaN), tantalum silicide (Ta2Si), or titanium nitride (TiN).

[0021] In some embodiments, the etch stop cap includes silicon nitride (SiN).

[0022] In some embodiments, the metal interconnect layer includes aluminum.

[0023] In some embodiments, the second etching process includes wet etching.

[0024] In some embodiments, forming the metal interconnect layer includes forming a particular metal interconnect element that defines an electrically conductive connection between the TFR element and at least one of the plurality of electrically conductive IC element contacts.

[0025] In another aspect of the application, a method for forming an integrated thin film resistor (TFR) in a semiconductor integrated circuit device is provided. An integrated circuit (IC) structure is provided that can include a plurality of IC elements and a plurality of conductive IC element contacts connected to the plurality of IC elements. A first etch stop layer (e.g., a first SiN layer) is formed over the IC structure. A TFR film layer is formed over the first etch stop layer. A TFR hard mask cap layer (e.g., a second SiN layer) is formed over the TFR film layer. A first photo mask is formed and patterned over a portion of the TFR hard mask cap layer. A first etch process is performed to remove the exposed portion of the TFR hard mask cap layer and portions of the TFR film layer underneath, leaving a TFR hard mask cap and a TFR element underneath, wherein the first etch process stops at the first etch stop layer. The remaining portion of the first photo mask is removed. An oxide cap layer is then formed, and a second photo mask is formed and patterned over the oxide cap layer such that at least one second mask opening is aligned over the TFR element. A second etch process is performed to form at least one oxide cap opening in the oxide cap layer over the TFR element, and the remaining portion of the second photo mask is removed. A third etch process is performed through the at least one oxide cap opening to form at least one TFR contact opening in the TFR hard mask cap over the TFR element, thereby exposing a surface of the TFR element. A metal interconnect layer is formed to extend over the plurality of conductive IC element contacts and over the TFR hard mask cap and into the at least one TFR contact opening in the TFR hard mask cap. A third photo mask is formed and patterned, and a fourth etch process is performed to remove selected portions of the metal interconnect layer, thereby defining a plurality of metal interconnect elements.

[0026] In some embodiments, a TFR anneal can be performed at any time after the TFR film layer is formed but before the metal interconnect layer is deposited, e.g., to reduce and / or optimize the temperature coefficient of resistance (TCR) of the TFR film layer or TFR element. For example, a TFR anneal can be performed prior to the first etch for defining the TFR element, or a TFR anneal can be performed after the first etch for defining the TFR element and before or after the oxide cap layer is formed, or a TFR anneal can be performed at any other time after the TFR film layer is formed but before the metal interconnect layer is deposited.

[0027] In another aspect of the application, a method for forming an integrated thin film resistor (TFR) in a semiconductor integrated circuit device is provided. An integrated circuit (IC) structure is provided, which can include a plurality of IC elements and a plurality of conductive IC element contacts connected to the plurality of IC elements. A TFR film layer is formed over the IC structure, and a TFR hard mask cap layer is formed over the TFR film layer. A photo mask is formed and patterned over the TFR hard mask cap layer, a first etch process is performed to remove selected portions of the TFR hard mask cap layer, thereby defining a TFR hard mask cap, the first etch process stopping at the TFR film layer, and the photo mask is removed. After the photo mask is removed, a second etch process is performed, with the TFR hard mask cap acting as a hard mask, to remove selected portions of the TFR film layer, thereby defining a TFR element under the TFR hard mask cap. An oxide cap layer is formed over the structure. A third etch process is performed to form at least one oxide cap opening in the oxide cap layer over the TFR element, and a fourth etch process is performed through the at least one oxide cap opening to form at least one TFR contact opening in the TFR hard mask cap over the TFR element, thereby exposing a surface of the TFR element. A metal interconnect layer is formed over the IC structure, which includes (a) at least one metal interconnect element coupled to at least one conductive IC element contact of the plurality of conductive IC element contacts and (b) at least one metal interconnect member extending into the at least one TFR contact opening to contact the underlying TFR element.

[0028] In some embodiments, a TFR anneal can be performed at any time after the TFR film layer is formed but before the metal interconnect layer is deposited, e.g., to reduce and / or optimize the temperature coefficient of resistance (TCR) of the TFR film layer or TFR element. For example, a TFR anneal can be performed before the photo mask is formed over the TFR hard mask cap layer, or a TFR anneal can be performed after the second etch for defining the TFR element and before or after the oxide cap layer is formed, or a TFR anneal can be performed at any other time after the TFR film layer is formed but before the metal interconnect layer is deposited.

[0029] In some embodiments, the TFR anneal includes an anneal at a temperature of at least 500 °C. In some embodiments, the TFR anneal includes an anneal at a temperature of 515 °C ± 10 °C for 15 minutes - 60 minutes.

[0030] In some embodiments, the IC structure includes a memory cell or a transistor structure, the memory cell or the transistor structure including at least one conductive IC element contact connected to at least one of a source region, a drain region, and a gate region of the memory cell or the transistor structure.

[0031] In some embodiments, the second etching process rounds upper corners of the TFR hard mask cap.

[0032] In some embodiments, the method further comprises forming a dielectric etch stop layer over the IC structure prior to forming the TFR film layer, wherein the first etching stops at the dielectric etch stop layer

[0033] In some embodiments, the TFR film layer comprises silicon carbide chromium (SiCCr), silicon chromium (SiCr), chromium silicon nitride (CrSiN), tantalum nitride (TaN), tantalum silicide (Ta2Si), or titanium nitride (TiN).

[0034] In some embodiments, the TFR hard mask cap comprises silicon nitride (SiN).

[0035] In some embodiments, the metal interconnect layer comprises aluminum.

[0036] In some embodiments, the second etching process comprises a wet etch.

[0037] In some embodiments, forming the metal interconnect layer comprises forming a particular metal interconnect element that defines an electrically conductive connection between the TFR element and at least one of the plurality of electrically conductive IC element contacts.

[0038] In another aspect of the application, another method for forming an integrated thin film resistor (TFR) in a semiconductor integrated circuit device is provided. An integrated circuit (IC) structure is provided that can include a plurality of IC elements and a plurality of conductive IC element contacts connected to the plurality of IC elements. A first etch stop layer (e.g., a first SiN layer) is formed over the IC structure. A TFR film layer is formed over the first etch stop layer. A TFR hard mask cap layer (e.g., a second SiN layer) is formed over the TFR film layer. A first photo mask is formed and patterned over a portion of the TFR hard mask cap layer. A first etch process is performed to remove exposed portions of the TFR hard mask cap layer, leaving a TFR hard mask cap, wherein the first etch process stops at the TFR film layer. Remaining portions of the first photo mask are removed. A second etch process is performed, wherein the TFR hard mask cap acts as a hard mask, to remove exposed portions of the TFR film layer, defining a TFR element underneath the TFR hard mask cap. The second etch process can round upper corners of the TFR hard mask cap. An oxide cap layer is formed over the structure. A second photo mask is formed and patterned over the oxide cap layer, such that at least one second mask opening is aligned over the TFR element. A third etch process is performed to form at least one oxide cap opening in the oxide cap over the TFR element, and to remove remaining portions of the second photo mask. A fourth etch process is performed through the at least one oxide cap opening to form at least one TFR contact opening in the TFR hard mask cap over the TFR element, exposing a surface of the TFR element. A metal interconnect layer is formed extending over the plurality of conductive IC element contacts and over and into the at least one TFR contact opening in the TFR hard mask cap. A third photo mask is formed and patterned, and a fifth etch process is performed to remove selected portions of the metal interconnect layer, defining a plurality of metal interconnect elements.

[0039] In some embodiments, a TFR anneal can be performed at any time after the TFR film layer is formed but before the metal interconnect layer is deposited, e.g., to reduce and / or optimize the temperature coefficient of resistance (TCR) of the TFR film layer or TFR element.

[0040] In another aspect of the application, a method for forming an integrated thin film resistor (TFR) in a semiconductor integrated circuit device is provided. An integrated circuit (IC) structure is provided, which can include a plurality of IC elements and a plurality of conductive IC element contacts connected to the plurality of IC elements. A TFR film layer is formed over the IC structure, an etch stop cap layer is formed over the TFR film layer, and an oxide cap layer is formed over the etch stop cap layer. A photo mask is formed and patterned over the oxide cap layer, and a first etch process is performed to remove selected portions of the oxide cap layer, defining an oxide cap, and the photo mask is removed. After the photo mask is removed, a second etch process is performed, with the oxide cap acting as a hard mask, to remove selected portions of the etch stop cap layer and the underlying TFR film layer, defining an etch stop cap and an underlying TFR element below the oxide cap. A third etch process is performed to form at least one oxide cap opening in the oxide cap over the TFR element, and a fourth etch process is performed through the at least one oxide cap opening to form at least one TFR contact opening in the etch stop cap over the TFR element, exposing a surface of the TFR element. A metal interconnect layer is formed over the IC structure, including (a) at least one metal interconnect element coupled to at least one conductive IC element contact of the plurality of conductive IC element contacts and (b) at least one metal interconnect extending into the at least one TFR contact opening to contact the underlying TFR element.

[0041] In some embodiments, a TFR anneal can be performed at any time after the TFR film layer is formed but before the metal interconnect layer is deposited, e.g., to reduce and / or optimize the temperature coefficient of resistance (TCR) of the TFR film layer or TFR element.

[0042] In some embodiments, the IC structure includes a memory cell or a transistor structure, the memory cell or the transistor structure including at least one conductive IC element contact connected to at least one of a source region, a drain region, and a gate region of the memory cell or the transistor structure.

[0043] In some embodiments, the second etch process rounds upper corners of the oxide cap.

[0044] In some embodiments, the method further includes forming a dielectric etch stop layer over the IC structure prior to forming the TFR film layer, wherein the first etch stops at the dielectric etch stop layer.

[0045] In some embodiments, the TFR film layer includes silicon carbide chromium (SiCCr), silicon chromium SiCr), chromium silicon nitride (CrSiN), tantalum nitride (TaN), tantalum silicide (Ta2Si), or titanium nitride (TiN).

[0046] In some embodiments, the etch stop cap layer comprises silicon nitride (SiN).

[0047] In some embodiments, the metal interconnect layer comprises aluminum.

[0048] In some embodiments, the second etching process comprises a wet etch.

[0049] In some embodiments, forming the metal interconnect layer comprises forming a particular metal interconnect element that defines an electrically conductive connection between the TFR element and at least one of the plurality of electrically conductive IC element contacts.

[0050] In another aspect of the application, another method for forming an integrated thin film resistor (TFR) in a semiconductor integrated circuit device is provided. An integrated circuit (IC) structure is provided that can include a plurality of IC elements and a plurality of electrically conductive IC element contacts connected to the plurality of IC elements. A first etch stop layer (e.g., a first SiN layer) is formed over the IC structure. A TFR film layer is formed over the first etch stop layer. A TFR hard mask cap layer (e.g., a second SiN layer) is formed over the TFR film layer. An oxide cap layer is formed over the TFR hard mask cap layer. A first photo mask is formed and patterned over a portion of the oxide cap layer. A first etch is performed to remove an exposed portion of the oxide cap layer, leaving an oxide cap, wherein the first etching process stops at the etch stop cap layer and removes a remaining portion of the first photo mask. A second etching process is performed, wherein the oxide cap acts as a hard mask to remove an exposed portion of the etch stop cap layer and a portion of the TFR film layer underneath, defining an etch stop cap and a TFR element below the etch stop cap. The second etching process can round upper corners of the oxide cap. A second photo mask is formed and patterned such that at least one second mask opening is aligned over the TFR element. A third etching process is performed to form at least one oxide cap opening in the oxide cap over the TFR element and remove a remaining portion of the second photo mask. A fourth etching process is performed through the at least one oxide cap opening to form at least one TFR contact opening in the etch stop cap over the TFR element, exposing a surface of the TFR element. A metal interconnect layer is formed to extend over the plurality of electrically conductive IC element contacts and over the oxide cap and into the at least one TFR contact opening in the etch stop cap. A third photo mask is formed and patterned, and a fifth etching process is performed to remove selected portions of the metal interconnect layer, defining a plurality of metal interconnect elements.

[0051] In some embodiments, a TFR anneal can be performed any time after forming the TFR film but before depositing the metal interconnect layer, for example, to reduce and / or optimize the thermal coefficient of resistance (TCR) of the TFR film or TFR element.

[0052] In another aspect, semiconductor IC devices are provided that include thin film resistors (TFRs) produced according to any of the disclosed methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Example aspects of the present disclosure are described below with reference to the accompanying drawings, in which:

[0054] Figures 1A-1M The steps of a first exemplary method of integrating a thin film resistor (TFR) in a semiconductor integrated circuit (IC) device according to a first exemplary embodiment of the present invention are shown;

[0055] Figures 2A-2M shows steps of a second exemplary method of integrating a thin film resistor (TFR) in a semiconductor integrated circuit (IC) device according to a second exemplary embodiment of the present invention;

[0056] Figures 3A-3K shows steps of a third exemplary method of integrating a thin film resistor (TFR) in a semiconductor integrated circuit (IC) device according to a third exemplary embodiment of the present invention; and

[0057] Figures 4A-4C and Figures 5A-5C It shows how the rounded lateral edges of the TFR oxide cap can prevent or reduce the occurrence of electrical shorts (commonly referred to as "stringers") in an integrated TFR. More specifically, Figures 4A-4C shows the removal of selected portions of a metal layer deposited over a TFR oxide cap with rounded lateral edges, while Figures 5A-5C Shown is the removal of selected portions of a metal layer deposited over a TFR oxide cap having vertical ("squared") lateral edges.

[0058] It should be understood that any reference numerals of any illustrated element appearing in multiple different figures have the same meaning in the multiple figures, and that reference or discussion herein of any illustrated element in the context of any particular figure also applies to every other figure (if any) in which the same illustrated element is shown. DETAILED DESCRIPTION

[0059] Embodiments of the invention provide improved techniques for integrating thin film resistors (TFRs) in semiconductor integrated circuit (IC) devices, e.g., by allowing TFR integration with aluminum interconnects, which can reduce costs compared to conventional techniques. In some embodiments, the TFR is formed after the IC elements and IC element contacts (e.g., tungsten vias) are formed, but before the first metal / interconnect layer (“metal 1” layer) is formed. This can allow, e.g., TFR annealing (e.g., to optimize the TFR film’s TCR value) to be performed at temperatures of 500°C or higher (e.g., in the range of 500°C-525°C). Thus, the annealed TFR can be integrated into an IC device that uses aluminum interconnects, since the aluminum interconnects (which are typically not resistant to the high temperatures experienced during typical TFR annealing) are not formed until after the TFR annealing. The TFR annealing can be performed at any time in the process prior to deposition of the first metal / interconnect layer.

[0060] Additionally, in some embodiments, the process of forming the integrated TFR adds only two additional photomasks to the baseline IC production flow. In some embodiments, the TFR formation process includes forming a TFR etch stop layer (e.g., a SiN layer) over the IC structure (and under the TFR elements), which protects the underlying IC elements (e.g., memory elements and tungsten contacts), allowing chemical cleaning to be performed to remove polymer residue formed during at least one etch process. Additionally, a second TFR etch stop layer (e.g., a SiN layer) can be formed over the TFR elements, which can act as an etch stop during TFR contact etching to form contact openings for coupling metal interconnect layers (e.g., metal 1 layers) to the TFR.

[0061] In other embodiments, a nitride cap (e.g., a SiN cap) and / or an oxide cap formed over the TFR film layer collectively act as a hard mask during TFR etching to define TFR elements from the TFR film layer. Providing such a hard mask can remove the need to use a photomask for TFR etching, thereby eliminating or greatly reducing the formation of polymer material during the TFR etch process, thereby eliminating or reducing the need for chemical cleaners to remove such polymer material. Additionally, the oxide cap layer can become rounded during TFR etching, which can help prevent electrical shorts (“stringers”) from occurring along the TFR elements and between adjacent metal layer structures (e.g., metal 1 layer structures).

[0062] Figures 1A-1M A first exemplary method of integrating a thin film resistor (TFR) in a semiconductor integrated circuit (IC) device is shown, according to a first exemplary embodiment.

[0063] Figure 1AAn exemplary integrated circuit (IC) structure 100 is shown, for example, during the fabrication of an IC device. In this example, the IC structure 100 includes a transistor structure 112 formed over a substrate 113, with a plurality of conductive contacts 114 (e.g., tungsten vias) extending through an integral insulating region 120 formed over the transistor structure 112. However, the IC structure 100 may include any other IC device or structure (e.g., one or more complete or partial memory cells or memory cell structures) and the conductive contacts associated with such structures. In this exemplary embodiment, the integral insulating region 120 includes (a) a high-density plasma (HDP) pre-metal dielectric (PMD) oxide layer 120A, (b) a PMD oxide film 120B (e.g., a PMD P TEOS (phosphorus-doped tetraethyl orthosilicate film)), and (c) a PMD cap layer 120C.

[0064] Figure 1A The state may be represented during the IC manufacturing process after forming the conductive contact (eg, tungsten via) 114 and the wet chemical mechanical polishing (W CMP) process at the top of the structure 100 .

[0065] Next, if Figure 1B As shown, a TFR layer stack 130 is formed over the bulk insulating region 120 and the conductive contacts 114. First, a dielectric etch stop layer 132 (e.g., a SiN layer) may be formed to, for example, protect the conductive contacts (e.g., tungsten vias) 114 from being etched later in FIG. Figure 1D A thin resistive film layer (TFR film layer) 134 may then be formed on the dielectric etch stop layer 132. The TFR film layer 134 may include SiCCr, SiCr, TaN, TiN, or any other suitable TFR material.

[0066] In some embodiments (e.g., Figures 1A-1M In the exemplary embodiment shown in FIG. 1 , a TFR anneal may be performed at this time, for example, to adjust or optimize the temperature coefficient of resistance (TCR) of the TFR film layer 134. For example, the anneal may be performed at a temperature of ≥500°C. In some embodiments, the TFR anneal may include annealing at 515°C ± 10°C for 15 minutes to 60 minutes (e.g., 30 minutes). In other embodiments, the TFR anneal may be performed during the process described below with reference to FIG. Figure 1K The TFR anneal may be performed at any other point prior to depositing the first metal layer / interconnect layer 160 (e.g., "Metal 1" layer) discussed below. For example, in some embodiments, a TFR anneal may be performed after forming the TFR etch stop capping layer 136 as discussed below. In other embodiments, a TFR anneal may be performed after etching to define the following with respect to the Figure 1D In other embodiments, the TFR element 134A may be as follows with respect toFigure 1J The TFR anneal is described as being performed after the TFR contact etch is complete.

[0067] In Figure 1B After the TFR anneal as shown, a TFR etch stop cap layer 136 can be formed over the TFR film layer 134. In this embodiment, the TFR etch stop cap layer 136 includes a SiN layer.

[0068] As Figure 1C A first photo mask 140 can be formed and patterned (e.g., using known photolithography techniques) over the TFR etch stop cap layer 136 (in this example, at a location laterally offset from the underlying transistor structure 112) for forming the TFR, as shown.

[0069] As Figure 1D A dry etch can then be performed to remove the exposed portions of the TFR etch stop cap layer 136 and the underlying TFR film layer 134 to define an etch stop cap 136A and an underlying TFR element 134A, as shown. The etch can be configured to stop at the dielectric etch stop layer 132, which can protect the underlying structure, including the conductive contacts (e.g., tungsten contacts) 114, as shown.

[0070] As Figure 1E The remaining portions of the photoresist 140 can be lifted off to reveal the etch stop cap 136A, as shown. In some embodiments, a chemical cleaner can be used to lift off the remaining portions of the photoresist 140, as the underlying conductive contacts (e.g., tungsten contacts) 114 are protected by the dielectric etch stop layer 132.

[0071] As Figure 1F An oxide cap layer 144 is formed over the structure, as shown. In some embodiments, the oxide cap layer 144 can include the same material as the PMD cap layer 120C below the dielectric etch stop layer 132, but can have a reduced thickness compared to the PMD cap layer 120C.

[0072] As Figure 1G A second photo mask 150 is formed over the oxide cap layer 144 and patterned over selected regions of the TFR etch stop cap 136A and the TFR element 134A to define a mask opening 152 aligned over the TFR element 134A, as shown.

[0073] As Figure 1HAs shown, a first TFR contact etch is performed to (a) remove selected portions of oxide cap layer 144 to define oxide cap 144A having oxide cap opening 156. The first TFR contact etch may stop on dielectric etch stop layer 132 at an area outside the outer perimeter of photomask 150, and may stop on etch stop cap 136A at a bottom of oxide cap opening 156 within the outer perimeter of photomask 150.

[0074] The first TFR contact etch can be a wet etch or a dry etch. Wet etching can improve the performance of subsequent metal deposition (e.g., Figure 1K 1 layer deposition) and can reduce the occurrence of electrical shorts (commonly referred to as “stringers”) along TFR element 134A and between adjacent metal structures (eg, Metal 1 layer structures).

[0075] like Figure 1I As shown, the remaining portion of photomask 150 can be removed, for example, by a resist stripper. In some embodiments, a chemical cleaner can be used to remove the remaining portion of photomask 150 because the underlying IC structures (e.g., tungsten vias 114) are protected by dielectric etch stop layer 132.

[0076] like Figure 1J As shown, a second TFR contact etch can be performed to (a) remove the portion of the TFR etch stop cap 136A exposed through the oxide cap opening 156 in the oxide cap 144A to define a TFR contact opening 158 that exposes the top surface of the TFR element 134A, and (b) remove the portion of the dielectric etch stop layer 132 exposed outside the perimeter of the oxide cap 144A, which can expose the top surface of the PMD cap layer 120C and the underlying conductive contact (e.g., tungsten contact) 114. In embodiments where the dielectric etch stop layer 132 comprises a SiN layer, the second TFR contact etch can include a mild SiN transparent acid etch with high selectivity to oxide to protect the underlying conductive contact (e.g., tungsten contact) 114.

[0077] like Figure 1K As shown, IC device processing can continue by forming a first metal layer / interconnect layer, referred to as "Metal 1" layer 160. In the illustrated embodiment, Metal 1 layer 160 comprises aluminum. In other embodiments, Metal 1 layer 160 may comprise copper or other metals. As shown, Metal 1 layer 160 extends into oxide cap opening 156 and TFR contact opening 158, thereby contacting TFR element 134A at different contact locations (e.g., at contact locations at or near opposite lateral sides or ends of TFR element 134A). Metal 1 layer 160 also extends over tungsten contacts 114 and contacts these conductive contacts (e.g., tungsten contacts) 114.

[0078] Next, if Figure 1L As shown, a third photomask 170 may be formed and patterned over the Metal 1 layer.

[0079] Finally, if Figure 1M As shown, the aluminum metal 1 layer 160 may be etched using a third photomask 170 to define a plurality of aluminum metal 1 elements (eg, metal interconnect elements) 180A-180D, and the aluminum metal 1 layer 160 may then be removed. Figure 1L The remaining photoresist material of the third photomask 170 is removed. For example, as shown, the Metal 1 layer can be etched to define aluminum interconnect elements 180A and 180B that contact the conductive contacts (e.g., tungsten vias) 114, and aluminum interconnect elements 180C and 180D that contact different contact locations of the TFR element 134A. In this exemplary illustration, the first aluminum interconnect element 180C conductively connects the first contact location of the TFR element 134A to the conductive contact (e.g., tungsten via) 114A coupled to the source or drain region of the transistor structure 112, and the second interconnect element 180D conductively contacts the second contact location of the TFR element 134A to other IC component structures (not shown). The TFR element 134A, together with the first interconnect element 180C and the second interconnect element 180D, defines an integrated TFR (indicated at 190).

[0080] Figures 2A-2M An exemplary method of integrating a thin film resistor (TFR) in a semiconductor integrated circuit (IC) device according to an exemplary embodiment is shown.

[0081] Figure 2A An exemplary integrated circuit (IC) structure 200 is shown, for example, during the fabrication of an IC device. In this example, the integrated circuit (IC) structure 200 includes a transistor structure 212 formed over a substrate 213, with a plurality of conductive contacts 214 (e.g., tungsten vias) extending through an integral insulating region 220 formed over the transistor structure 212. However, the integrated circuit (IC) structure 200 may include any other IC device or structure (e.g., one or more complete or partial memory cells or memory cell structures) and the conductive contacts associated with such structures. In this exemplary embodiment, the integral insulating region 220 includes (a) a HDP PMD oxide layer 220A, (b) a PMD oxide film 220B (e.g., PMD P TEOS), and (c) a PMD capping layer 220C.

[0082] Figure 2A It may represent a state during an integrated circuit (IC) manufacturing process after forming a conductive contact (eg, tungsten via) 214 and a wet chemical mechanical polishing (W CMP) process at the top of the structure 200 .

[0083] Next, as shown in Figure 2B , a TFR layer stack 230 is formed over the bulk insulating region 220 and the conductive contacts 214. First, a dielectric etch stop layer 232 (e.g., a SiN layer) can be formed, for example, to protect the conductive contacts (e.g., tungsten vias) 214 from subsequent TFR etching shown below at Figure 2E . A thin resistive film layer (TFR film layer) 234 can then be formed over the dielectric etch stop layer 232. The TFR film layer 234 can include SiCCr, SiCr, TaN, TiN, or any other suitable TFR material.

[0084] In some embodiments (e.g., the example embodiment shown in Figures 2A-2M ), a TFR anneal can be performed at this time, for example, to adjust or optimize the temperature coefficient of resistance (TCR) of the TFR film layer 234. For example, the anneal can be performed at a temperature of > 500 °C. In some embodiments, the TFR anneal can include an anneal at 515 °C ± 10 °C for 15-60 minutes (e.g., 30 minutes). In other embodiments, the TFR anneal can be performed at any other point in the process prior to deposition of the first metal layer / interconnect layer 260 (e.g., the “metal 1” layer) discussed below with reference to Figure 2K . For example, in some embodiments, the TFR anneal can be performed after formation of the TFR hard mask cap layer 236 as discussed below. In other embodiments, the TFR anneal can be performed after etching to define the TFR element 234A discussed below with respect to Figure 2E . In other embodiments, the TFR anneal can be performed after completion of the TFR contact etching and removal of the photoresist as described below with respect to Figures 2H-2I .

[0085] After the TFR anneal shown in Figure 2B , a TFR hard mask cap layer 236 can be formed over the TFR film layer 234. In this embodiment, the TFR hard mask cap layer 236 includes a SiN layer.

[0086] As shown in Figure 2C , a first photomask 240 can be formed and patterned (e.g., using known photolithography techniques) over the TFR hard mask cap layer 236 of Figure 2B (at locations laterally offset from the underlying transistor structure 212 in this example). Etching (e.g., dry etching) can then be performed to remove exposed portions of the TFR hard mask cap layer 236 of Figure 2B , and stop on the TFR film layer 234, thereby defining a TFR hard mask cap 236A.

[0087] As shown in Figure 2D , the TFR hard mask cap 236A can be lifted off. Figure 2Cthe remaining portion of the photoresist 240. In some embodiments, a chemical cleaner can be used since the underlying conductive contacts (e.g., tungsten contacts) 214 are protected by the TFR film layer 234 and the underlying dielectric etch stop layer 232.

[0088] As shown, a TFR hardmask cap 236A can be used as a hardmask to perform a TFR etch (e.g., dry etch) to remove the exposed portion of the TFR film layer 234 to define a TFR element 234A. As shown, the TFR film etch can round the exposed upper corner 237 of the TFR hardmask cap 236A and can stop on the dielectric etch stop layer 232 to protect the underlying structures (e.g., tungsten contacts 214). Using the TFR hardmask cap 236A as a hardmask for the TFR etch avoids the need to use a photo mask for this etch, which can avoid the formation of polymer residue through the photo mask and thus eliminate the typical issues associated with removing such polymer residue. Figure 2E As shown, an oxide cap layer 244 is then formed over the structures. In some embodiments, the oxide cap layer 244 can comprise the same material as the PMD cap layer 220C below the dielectric etch stop layer 232. The oxide cap layer 244 can have a reduced thickness compared to the PMD cap layer 220C, but is thick enough to stop a subsequent metal etch (e.g., Metal 1 layer etch) as shown.

[0089] Figure 2F As shown, a second photo mask 250 is formed on the oxide cap layer 244 and patterned over selected areas of the TFR element 234A to define mask openings 252 aligned over the TFR element 234A. Figure 2M As shown, a first TFR contact etch is performed to (a) remove selected portions of the oxide cap layer 244 to define an oxide cap 244A having oxide cap openings 256. The first TFR contact etch can stop on the dielectric etch stop layer 232 at areas outside the outer periphery of the photo mask 250 and can stop on the TFR hardmask cap 236A at the bottom of the oxide cap openings 256 within the outer periphery of the photo mask 250.

[0090] Figure 2G The first TFR contact etch can be a wet etch or a dry etch. A wet etch can improve metal flow during a subsequent metal deposition (e.g., Metal 1 layer deposition) as shown and can reduce the occurrence of electrical shorts (commonly referred to as “stringers”) along the TFR element 234A and between adjacent metal structures (e.g., Metal 1 layer structures).

[0091] As shown, a second TFR contact etch is performed to (b) remove the TFR element 234A to define a TFR element 234B having TFR element openings 258. The second TFR contact etch can stop on the dielectric etch stop layer 232 at areas outside the outer periphery of the photo mask 250 and can stop on the TFR hardmask cap 236A at the bottom of the TFR element openings 258 within the outer periphery of the photo mask 250. Figure 2H The second TFR contact etch can be a wet etch or a dry etch. A wet etch can improve metal flow during a subsequent metal deposition (e.g., Metal 1 layer deposition) as shown and can reduce the occurrence of electrical shorts (commonly referred to as “stringers”) along the TFR element 234A and between adjacent metal structures (e.g., Metal 1 layer structures).

[0092] Figure 2K As shown, a Metal 1 layer is deposited over the structures. In some embodiments, the Metal 1 layer can be deposited by a physical vapor deposition (PVD) process. In some embodiments, the Metal 1 layer can be deposited by an atomic layer deposition (ALD) process. In some embodiments, the Metal 1 layer can be deposited by a chemical vapor deposition (CVD) process. In some embodiments, the Metal 1 layer can be deposited by an electrochemical deposition (ECD) process. In some embodiments, the Metal 1 layer can be deposited by a plating process. In some embodiments, the Metal 1 layer can be deposited by a combination of two or more of the above processes. ​​​

[0093] like Figure 2I As shown, it can be removed, for example, by a resist stripping solution Figure 2H In some embodiments, a chemical cleaner may be used to remove the remaining portion of the second photomask 250. Figure 2H The remaining portion of the second photomask 250 is removed because the underlying IC structures (eg, tungsten vias 214 ) are protected by the dielectric etch stop layer 232 .

[0094] like Figure 2J As shown, a second TFR contact etch can be performed to (a) remove the portion of the TFR hard mask cap 236A exposed by the oxide cap opening 256 in the oxide cap 244A to define a TFR contact opening 258 that exposes the top surface of the TFR element 234A, and (b) remove the portion of the dielectric etch stop layer 232 exposed outside the perimeter of the oxide cap 244A, which can expose the top surface of the PMD cap layer 220C and the underlying conductive contact (e.g., tungsten contact) 214. In embodiments where the dielectric etch stop layer 232 comprises a SiN layer, the second TFR contact etch can include a mild SiN transparent acid etch with high selectivity to oxide to protect the underlying conductive contact (e.g., tungsten contact) 214.

[0095] like Figure 2K As shown, IC device processing can continue by forming a first metal layer / interconnect layer, referred to as "Metal 1" layer 260. In the illustrated embodiment, Metal 1 layer 260 comprises aluminum. In other embodiments, Metal 1 layer 260 can comprise copper or other metals. As shown, Metal 1 layer 260 extends into oxide cap opening 256 and TFR contact opening 258, thereby contacting TFR element 234A at various contact locations of TFR element 234A. Metal 1 layer 260 also extends over and contacts tungsten contacts 214.

[0096] Next, if Figure 2L As shown, a third photomask 270 may be formed and patterned over the Metal 1 layer.

[0097] Finally, if Figure 2MAs shown, the aluminum metal 1 layer 260 can be etched using the third photo mask 270 to define a plurality of aluminum metal 1 elements (e.g., metal interconnect elements) 280A-280D, and then the remaining photoresist material of the third photo mask 270 can be removed. For example, as shown, the metal 1 layer can be etched to define aluminum interconnect elements 280A and 280B in contact with conductive contacts (e.g., tungsten vias) 214 and aluminum interconnect elements 280C and 280D in contact with different contact locations of the TFR element 234A. In this example illustration, a first aluminum interconnect element 280C electrically connects a first contact location of the TFR element 234A with a conductive contact (e.g., tungsten via) 214A coupled to a source or drain region of the transistor structure 212, and a second interconnect element 280D electrically contacts a second contact location of the TFR element 234A with other IC element structures (not shown). The TFR element 234A collectively defines an integrated TFR (indicated at 290) with the first interconnect element 280C and the second interconnect element 280D.

[0098] As discussed below, for example, with respect to Figures 4A-4C and Figures 5A-5C The rounded upper corners 237 of the TFR hard mask cap 236A can facilitate removal of selected portions of the metal 1 layer 260 adjacent to selected lateral edges of the TFR element 234A, for example, to further prevent electrical shorts (“gallows”) in the fabricated device.

[0099] Figures 3A-3K An example method of integrating a thin film resistor (TFR) in a semiconductor integrated circuit (IC) device is shown, according to one example embodiment.

[0100] Figure 3A An example integrated circuit (IC) structure 300, for example, during fabrication of an IC device, is shown. In this example, the integrated circuit (IC) structure 300 includes a transistor structure 312 formed over a substrate 313, with a plurality of conductive contacts 314 (e.g., tungsten vias) extending through a bulk insulating region 320 formed over the transistor structure 312. However, the integrated circuit (IC) structure 300 can include any other IC device or structure (e.g., one or more complete or partial memory cells or memory cell structures) and conductive contacts associated with such structures. In this example embodiment, the bulk insulating region 320 includes (a) an HDP PMD oxide layer 320A, (b) a PMD oxide film 320B (e.g., PMD PTEOS), and (c) a PMD cap layer 320C.

[0101] Figure 3AIt may represent a state during an integrated circuit (IC) manufacturing process after forming a conductive contact (eg, tungsten via) 314 and a wet chemical mechanical polishing (W CMP) process at the top of the structure 300 .

[0102] Next, if Figure 3B As shown, a TFR layer stack 330 is formed over the bulk insulating region 320 and the conductive contacts 314. First, a dielectric etch stop layer 332 (e.g., a SiN layer) may be formed to, for example, protect the conductive contacts (e.g., tungsten vias) 314 from being etched later in FIG. Figure 3E A thin resistive film layer (TFR film layer) 334 may then be formed on the dielectric etch stop layer 332. The TFR film layer 334 may include SiCCr, SiCr, TaN, TiN, or any other suitable TFR material.

[0103] In some embodiments (e.g., Figures 3A-3K In the exemplary embodiment shown in FIG. 3 , a TFR anneal may be performed at this time, for example, to adjust or optimize the temperature coefficient of resistance (TCR) of the TFR film layer 334. For example, the anneal may be performed at a temperature of ≥500° C. In some embodiments, the TFR anneal may include annealing at 515° C. ±10° C. for 15 minutes to 60 minutes (e.g., 30 minutes). In other embodiments, the TFR anneal may be performed during the process described below with reference to FIG. Figure 3I The TFR anneal may be performed at any other point prior to depositing the first metal layer / interconnect layer 360 (e.g., "Metal 1" layer) discussed below. For example, in some embodiments, the TFR anneal may be performed after forming the etch stop layer 336 as discussed below. In other embodiments, the TFR anneal may be performed after etching to define the following with respect to the Figure 3E In other embodiments, the TFR element 334A may be as follows with respect to Figure 3H The TFR anneal is described as being performed after the TFR contact etch is completed.

[0104] exist Figure 3C After the TFR anneal shown, an etch stop layer 336 may be formed on the TFR film layer 334. In this embodiment, the etch stop layer 336 comprises a SiN layer. An oxide cap layer 338 may then be formed on the etch stop layer 336.

[0105] like Figure 3C As shown, it is possible (for example, using known photolithographic techniques) to Figure 3BA first photomask 340 is formed and patterned over the oxide capping layer 338 (in this example, at a location laterally offset from the underlying transistor structure 312). An etch (e.g., a dry etch) may then be performed to remove the exposed portion of the oxide capping layer 338 and stop at the etch stop layer 336, thereby defining an oxide cap 338A.

[0106] like Figure 3D As shown, it can be stripped (for example, using a chemical cleaning process) Figure 3C The remaining portion of the photoresist 340 is removed.

[0107] like Figure 3E As shown, a TFR etch (e.g., a dry etch) can be performed using the oxide cap 338A as a hard mask to remove the exposed portions of the etch stop layer 336 and the underlying TFR film layer 334, thereby defining the etch stop cap 336A and the TFR element 334A below the etch stop cap 336A. As shown, the TFR etch can round the exposed upper corners 337 of the oxide cap 338A and can stop on the dielectric etch stop layer 332 to protect the underlying structures (e.g., tungsten contacts) 314. Using the oxide cap 338A as a hard mask for the TFR etch avoids the need to use a photomask for this etch, which can prevent the formation of polymer residues through the photomask and thus eliminate the typical problems associated with removing such polymer residues.

[0108] like Figure 3F As shown, a second photomask 350 is formed over the structure and patterned to define a mask opening 352 aligned over the TFR element 334A. A first TFR contact etch is performed to define an oxide cap opening 356 in the oxide cap 338A, stopping at the etch stop cap 336A. The first TFR contact etch can be a wet etch or a dry etch. A wet etch can improve the performance of subsequent metal deposition (e.g., Figure 3I 1 layer deposition) and can reduce the occurrence of electrical shorts (commonly referred to as “stringers”) along TFR element 334A and between adjacent metal structures (eg, Metal 1 layer structures).

[0109] like Figure 3G As shown, it can be removed, for example, by a resist stripping solution Figure 3F In some embodiments, a chemical cleaner can be used to remove the remaining portion of the second photomask 350 because the underlying IC structure (eg, tungsten via) 314 is protected by the dielectric etch stop layer 332.

[0110] like Figure 3H As shown, a second TFR contact etch may be performed to (a) remove Figure 3G(b) removing the portion of the dielectric etch stop layer 332 exposed through the oxide cap opening 356 in the oxide cap 338A to define a TFR contact opening 358 that exposes the top surface of the TFR element 334A, and (c) removing the portion of the dielectric etch stop layer 332 exposed through the oxide cap opening 356 in the oxide cap 338A to define a TFR contact opening 358 that exposes the top surface of the TFR element 334 Figure 3G The portion of the dielectric etch stop layer 332 exposed outside the perimeter of the oxide cap 340 may expose the top surface of the PMD cap layer 320C and the underlying conductive contact (e.g., tungsten contact) 314. In embodiments where the dielectric etch stop layer 332 comprises a SiN layer, the second TFR contact etch may comprise a mild SiN transparent acid etch with high selectivity to oxide to protect the underlying conductive contact (e.g., tungsten contact) 314.

[0111] like Figure 3I As shown, IC device processing can continue by forming a first metal layer / interconnect layer, referred to as "Metal 1" layer 360. In the illustrated embodiment, Metal 1 layer 360 comprises aluminum. In other embodiments, Metal 1 layer 360 can comprise copper or other metals. As shown, Metal 1 layer 360 extends into oxide cap opening 356 and TFR contact opening 358, thereby contacting TFR element 334A at various contact locations of TFR element 334A. Metal 1 layer 360 also extends over and contacts tungsten contacts 314.

[0112] Next, if Figure 3J As shown, a third photomask 370 may be formed and patterned over the Metal 1 layer.

[0113] Finally, if Figure 3K As shown, the aluminum metal 1 layer 360 may be etched using a third photomask 370 to define a plurality of aluminum metal 1 elements (eg, metal interconnect elements) 380A-380D, and the aluminum metal 1 layer 360 may then be removed. Figure 3J The remaining photoresist material of the third photomask 370 is removed. For example, as shown, the metal 1 layer can be etched to define aluminum interconnect elements 380A and 380B that contact conductive contacts (e.g., tungsten vias) 314, and aluminum interconnect elements 380C and 380D that contact different contact locations of the TFR element 334A. In this exemplary illustration, a first aluminum interconnect element 380C conductively connects a first contact location of the TFR element 334A to a conductive contact (e.g., tungsten via) 314A coupled to a source or drain region of the transistor structure 312, and a second interconnect element 380D conductively contacts a second contact location of the TFR element 334A to other IC component structures. The TFR element 334A, together with the first interconnect element 380C and the second interconnect element 380D, defines an integrated TFR (indicated at 390).

[0114] As discussed below, for example, relative to Figures 4A-4C andFigures 5A-5C The rounded upper corners 337 of the oxide cap 338A can facilitate removal of selected portions of the metal 1 layer 360 adjacent to selected lateral edges of the TFR element 234A, for example, to further prevent electrical shorts ("stringers") in the fabricated device.

[0115] Figures 4A-4C and Figures 5A-5C The following example illustrations show how the rounded upper corners 237 of the TFR hardmask cap 236A (in the embodiment of FIG. 2A) or the rounded upper corners 337 of the oxide cap 338A (in the embodiment of FIG. 3A) can facilitate removal of selected portions of the relevant metal layer (metal 1 layer 260 or 360) to physically separate interconnect elements (e.g., elements 280C and 280D or elements 380C and 380D) from one another, as compared to similar structures with TFR oxide caps having vertical ("squarized") lateral edges. Figures 2A-2M Figures 3A-3K The following example illustrations show how the rounded upper corners 237 of the TFR hardmask cap 236A (in the embodiment of FIG. 2A) or the rounded upper corners 337 of the oxide cap 338A (in the embodiment of FIG. 3A) can facilitate removal of selected portions of the relevant metal layer (metal 1 layer 260 or 360) to physically separate interconnect elements (e.g., elements 280C and 280D or elements 380C and 380D) from one another, as compared to similar structures with TFR oxide caps having vertical ("squarized") lateral edges. Figures 4A-4C is a cross-sectional view of a selected portion of an example IC structure 10 taken through the TFR element 34 in a direction perpendicular to the cross-section shown in FIG. 2A. As shown, the TFR cap 36A having rounded upper corners 44 is formed over the TFR element. In contrast, Figures 2A-2M and Figures 3A-3K is a cross-sectional view of a selected portion of an example IC structure 10 taken through the TFR element 34 in a direction perpendicular to the cross-section shown in FIG. 2A. As shown, the TFR cap 36A having rounded upper corners 44 is formed over the TFR element. In contrast, Figures 5A-5C is a cross-sectional view of a selected portion of an IC structure 10' that is similar to the IC structure 10 but has a TFR cap with vertical ("squarized") lateral edges, unlike the rounded upper corners 44 of the TFR cap 36A shown in FIG. 2A. Figures 4A-4C

[0116] Figure 4A and Figure 5A shows (a) a selected portion of the IC structure 10 after deposition of a metal layer 60 over the TFR cap 36A having rounded upper corners 44 (hereinafter referred to as rounded oxide cap edges ( Figure 4A )) and a selected portion of the IC structure 10' after deposition of a metal layer 60' over the TFR cap 36A' having vertical lateral edges 44'. The same metal thickness (indicated as T 金属 ) was deposited for the metal layer 60 and the metal layer 60'.

[0117] Figure 4A is similar to the IC structure in FIG. 2A, except that a photo mask is formed and patterned over the metal layer 60 and a metal etch is performed to define metal elements (e.g., Figure 2M the elements 280A-280D shown in FIG. 2A or Figure 3K ​​In this example, the metal layer 60 in the illustrated cross section should be completely removed by metal etching in order to remove the metal contacts (e.g., Figure 2M The interconnecting elements 280C and 280D shown or Figure 3K Any conductive connection provided between interconnecting elements 380C and 380D) as shown prevents electrical shorting ("stringers") across TFR element 34A. Figure 4A and Figure 5A As shown, the thickest portions of metal layers 60 and 60' are located adjacent to lateral edges 48 and 48' of TFR elements 34A and 34A' (indicated as approximately at locations 64 and 64'), and therefore the metal etch should be sufficient to remove the full metal thickness in these locations. As explained below, the rounded upper corners 44 of TFR cover 36A reduce the metal thickness in these locations, thereby reducing the required metal etching parameters (e.g., etching time or etching intensity).

[0118] Figure 4A and Figure 5A The metal layers 60 and 60' shown may each include an aluminum layer applied as a sputtered film, such as Al, AlCu, and AlSiCu. As is known in the art, physical sputtered films such as Al, AlCu, and AlSiCu are generally not completely conformal. "Bread-loafing" occurs over the upper corners of the physical structure (e.g., Figure 4A As shown, at 66, and as Figure 5A As shown, at 66'). As shown, Figure 5A Compared to the vertical TFR cover edge 44' shown, Figure 4A The rounded upper corners (e.g., rounded TFR cover corners) 44 shown reduce the degree of "bread slicing" at the upper corners. This reduced "bread slicing" effect and the rounded profile of the metal layer 60 above the rounded upper corners (e.g., rounded TFR cover corners) 44 result in a lower surface area adjacent to the lateral edges 48 of the TFR element 34A (i.e., at the Figure 4A The vertical metal thickness T at position 64 shown) 金属_圆化_盖 , the vertical metal thickness is less than that adjacent to the lateral edge 48' of the TFR element 34A' of the IC structure 10' (ie, at Figure 5A The vertical metal thickness T at the position 64' shown) 金属_方化_盖 Therefore, compared with the smaller T 金属_方化_盖 Come check out T 金属_圆化_盖As can be seen, the maximum vertical thickness of metal to be removed during metal etching (to prevent electrical shorts across TFR elements 34A or 34A’) is reduced due to the rounded upper corner (e.g., rounded TFR cap corner) 44 as compared to the vertical TFR cap edge 44’.

[0119] Figure 4B and Figure 5B selected portions of IC structure 10 and IC structure 10’ are shown during metal etching to remove each metal layer 60 and 60’. In particular, Figure 4B and Figure 5B selected portions of IC structure 10 and IC structure 10’ are shown during etching, where each metal layer 60 and 60’ has a thickness T 金属 of horizontal area has been removed, while the area of metal layer 60 and 60’ at the lateral edge 48, 48’ of each TFR element 34A, 34A’ remains. As shown, the maximum remaining metal thickness T Figure 4B ) in a structure with a rounded TFR cap corner (e.g., rounded TFR cap corner) 44 金属_圆化_盖 is less than the maximum remaining metal thickness T Figure 5B ) in a structure with a squared TFR cap edge 44’ 金属_方化_盖 and thus requires a shorter etch time (or less etch strength) to completely remove.

[0120] Figure 4C and Figure 5C selected portions of IC structure 10 and IC structure 10’ are shown after additional etch time (over-etching), particularly when the thickest area of metal layer 60 (at T 金属_圆化_盖 ) has been completely removed. As shown, in a structure with a squared TFR cap edge 44’ Figure 5C ), the thickness of metal layer 60’ (indicated by T 金属_方化_盖 ) remains when the metal layer 60 Figure 4C ) in IC structure 10 has been completely removed. Thus, the rounded upper corner (e.g., rounded TFR cap corner) 44 formed in IC structure 10 can reduce the etch time (or reduce the etch strength required) to completely remove metal layer 60 to prevent electrical shorts across TFR elements 34A. The reduced etch time (or reduced etch strength) enables thinner photoresist, for example, as compared to an IC structure using a squared TFR cap edge 44’ Figures 5A-5C ), which enables tighter metal line spacing in IC structure 10. This reduction in metal line spacing can enable overall reduction in size of IC structure 10, which can enable more IC devices per wafer, which can reduce the cost per device.

[0121] While the disclosed embodiments are described in detail in the disclosure, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the spirit and scope of the embodiments.

Claims

1. A method of forming an integrated thin film resistor (TFR) in a semiconductor integrated circuit device, the method comprising: forming an integrated circuit (IC) structure comprising a plurality of IC components and a plurality of electrically conductive IC component contacts connected to the plurality of IC components, wherein the plurality of electrically conductive IC component contacts do not include a metal having a low melting temperature; forming a TFR film layer on the integrated circuit (IC) structure; forming a TFR cap layer on the TFR film layer; performing a first etching process to remove selected portions of the TFR cap layer, thereby defining the cap and underlying TFR elements; forming an oxide capping layer; performing a second etching process to form at least one oxide cap opening in the oxide cap layer above the TFR element; performing a third etching process through the at least one oxide cap opening to form at least one TFR contact opening in the cap, thereby exposing a surface of the TFR element; forming a metal interconnect layer over the integrated circuit (IC) structure, the metal interconnect layer comprising (a) at least one metal interconnect element coupled to at least one of the plurality of conductive IC element contacts and (b) at least one metal interconnect extending into the at least one TFR contact opening to contact the TFR element; and At some time after forming the TFR film layer and before forming the metal interconnection layer, a TFR annealing is performed to anneal the TFR film layer or the TFR element.

2. The method according to claim 1, further comprising: forming a dielectric etch stop layer over the integrated circuit (IC) structure before forming the TFR film layer; The first etch stops at the dielectric etch stop layer.

3. The method of any one of claims 1-2, wherein the integrated circuit (IC) structure comprises: A memory cell or transistor structure includes at least one electrically conductive IC component contact connected to at least one of a source region, a drain region, and a gate region of the memory cell or transistor structure.

4. The method according to any one of claims 1 to 2, wherein the TFR film layer comprises silicon chromium carbide (SiCCr), silicon chromium (SiCr), chromium silicon nitride (CrSiN), tantalum nitride (TaN), tantalum silicide (Ta2Si), or titanium nitride (TiN).

5. The method of any one of claims 1-2, wherein the TFR cap layer comprises silicon nitride (SiN).

6. The method of any one of claims 1-2, wherein the metal interconnect layer comprises aluminum.

7. The method of any one of claims 1-2, wherein the TFR annealing comprises annealing at a temperature of at least 500°C.

8. The method according to any one of claims 1-2, wherein the TFR annealing comprises annealing at a temperature of 515°C ± 10°C for 15 minutes to 60 minutes.

9. The method according to any one of claims 1-2, wherein the second etching process comprises wet etching.

10. The method according to any one of claims 1-2, wherein the at least one metal interconnection element comprises: A first metal interconnect element defines a conductive connection between the TFR element and at least one conductive IC component contact of the plurality of conductive IC component contacts.

11. The method according to any one of claims 1 to 2, wherein: The first etching process further removes portions of the underlying TFR film layer and defines a TFR etch stop cap and an underlying TFR element; The TFR cap layer is an etch stop cap layer; The cap defined is the TFR etch stop cap; The second etching process stops at the etching stop cap; and Contact with the TFR element is made at the exposed surface of the TFR element.

12. The method according to any one of claims 1 to 2, wherein: The TFR capping layer is a TFR hard mask capping layer; The method further includes: forming and patterning a photomask over the TFR hard mask capping layer; The first etching process stops at the TFR film layer; The method further includes: removing the photomask; The method further includes: after removing the photomask, performing a fourth etching process using the TFR hard mask cap as a hard mask to remove selected portions of the TFR film layer, thereby defining a TFR element below the TFR hard mask cap; Forming the oxide capping layer is performed after the fourth etching process; and Performing the third etch process further forms the TFR contact opening in the TFR hard mask cap above the TFR element.

13. The method according to claim 12, further comprising: forming a dielectric etch stop layer over the integrated circuit (IC) structure before forming the TFR film layer; The second etch stops at the dielectric etch stop layer.

14. The method according to any one of claims 1 to 2, wherein: The TFR cap layer is an etch stop cap layer; The oxide capping layer is formed on the etch stop capping layer; and The method further comprises: forming and patterning a photomask over the oxide cap layer; performing a fourth etching process to remove selected portions of the oxide cap layer, thereby defining the oxide cap; removing the photomask; and After removing the photomask, the first etching process is performed, in which the oxide cap acts as a hard mask to remove the selected portion of the TFR film layer. 15 . The method of claim 12 , wherein the first etching process or the fourth etching process rounds upper corners of the oxide cap or the TFR hard mask cap.

16. The method of claim 15 , wherein the fourth etching process removes selected portions of the oxide capping layer, thereby defining the oxide capping that stops at an etch stop capping layer; and the first etching removes exposed portions of the etch stop capping layer outside the oxide capping, thereby defining an etch stop capping below the oxide capping and above the TFR element.

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