Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure, comprising: providing a substrate, on which a dielectric layer is formed; forming a transition layer and a sacrificial layer on the dielectric layer; performing several ion implantations on the sacrificial layer to form several mutually discrete modified layers in the sacrificial layer; removing the remaining sacrificial layer to form a first graphic structure on the transition layer; forming a second graphic structure on the transition layer, the second graphic structure being mutually discrete from the first graphic structure; using the first graphic structure and the second graphic structure as masks, etching the transition layer until the surface of the dielectric layer is exposed, and forming mutually discrete cut-off graphics on the dielectric layer. The method for forming a semiconductor structure provided by an embodiment of the present invention simplifies the process flow and is conducive to improving the performance of the formed semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] The metal interconnection structure is an indispensable structure in semiconductor devices, which is used to realize the interconnection between active areas, between transistors, or between metal lines of different layers, and complete the transmission and control of signals. Therefore, in the semiconductor manufacturing process, the formation of the metal interconnection structure has a great influence on the performance of semiconductor devices and the semiconductor manufacturing cost. In order to increase the density of devices, the size of semiconductor devices in integrated circuits has been continuously reduced. In order to realize the electrical connection of each semiconductor device, a multi-layer interconnection structure is usually required.

[0003] The interconnect structure includes a zero-layer metal layer (M0) electrically connected to the source and drain regions of the lower layer, a zero-layer gate metal layer (M0G) electrically connected to the gate structure, and an upper metal layer connected to the zero-layer metal layer (M0) and the zero-layer gate metal layer (M0G). According to different requirements, an isolation structure needs to be formed between adjacent local interconnect structures, such as a partition structure (M0C) between the zero-layer metal layer (M0). As the size of semiconductor devices decreases, the spacing between M0Cs is gradually reduced.

[0004] However, the process of forming the zero-layer metal layer isolation structure (M0C) is currently complicated, and the performance of the formed semiconductor structure needs to be further improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, simplify the process steps, and improve the performance of the formed semiconductor structure.

[0006] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, on which a dielectric layer is formed; forming a transition layer and a sacrificial layer located on the transition layer on the dielectric layer; performing several ion implantations on the sacrificial layer to form several mutually discrete modified layers in the sacrificial layer respectively; removing the remaining sacrificial layer to form a first graphic structure on the transition layer; forming a second graphic structure on the transition layer, the second graphic structure being mutually discrete from the first graphic structure; etching the transition layer using the first graphic structure and the second graphic structure as masks until the surface of the dielectric layer is exposed, thereby forming mutually discrete cut-off graphics on the dielectric layer.

[0007] Optionally, the method of performing ion implantation on the sacrificial layer includes: forming a patterned layer on the sacrificial layer, wherein the patterned layer has an opening, and the opening exposes a portion of the surface of the sacrificial layer; and performing ion implantation on the sacrificial layer exposed by the opening.

[0008] Optionally, the process parameters of the ion implantation include: the implanted ions include boron ions, phosphorus ions or arsenic ions; the implantation energy is 1KeV~5KeV, and the implantation dose is 1E14~5E15atoms / cm 2 .

[0009] Optionally, the method for forming the second graphic structure includes: forming a second graphic material layer on the transition layer; and patterning the second graphic material layer to form a second graphic structure on the transition layer.

[0010] Optionally, the second graphic material layer includes a photoresist layer, a bottom anti-reflection layer, a spin-on glass layer or a spin-on carbon layer.

[0011] Optionally, after forming the first graphic structure, the second graphic structure is formed.

[0012] Optionally, the material of the transition layer includes metal or metal compound.

[0013] Optionally, the material of the transition layer includes one or more of titanium nitride, titanium oxide, titanium or titanium aluminum compounds.

[0014] Optionally, the method of etching the transition layer using the first graphic structure and the second graphic structure as masks includes a plasma dry etching process; the process parameters of the plasma dry etching process include: the etching gas includes a fluorine-containing gas or a chlorine-containing gas.

[0015] Optionally, the material of the sacrificial layer includes amorphous silicon, amorphous carbon or amorphous germanium.

[0016] Optionally, the method for removing the remaining sacrificial layer includes a wet etching process; the process parameters of the wet etching process include: the etching solution includes a TMAH solution or an ammonia solution.

[0017] Optionally, a gate structure is formed on the surface of the substrate, source-drain doped layers are formed in the substrate on both sides of the gate structure, and the dielectric layer covers the surfaces of the gate structure and the source-drain doped layers.

[0018] Optionally, after forming the cut-off pattern, it also includes: forming a first mask layer on the substrate, the first mask layer exposing a portion of the cut-off pattern and the surface of the dielectric layer above the source-drain doped layer; etching the dielectric layer using the first mask layer as a mask until the surface of the source-drain doped layer is exposed, forming a groove in the dielectric layer between adjacent cut-off patterns; and forming an interconnect structure in the groove.

[0019] Optionally, the method of etching the dielectric layer using the first mask layer as a mask includes a dry etching process; process parameters of the dry etching process include: the etching gas includes a mixed gas of HF and CF4.

[0020] Optionally, the dry etching process has an etching selectivity ratio of greater than 10:1 for the dielectric layer and the cut-off pattern.

[0021] Optionally, before forming the interconnection structure in the groove, the method further includes: removing the cut-off pattern.

[0022] Optionally, the method for removing the cut-off pattern includes a wet etching process; the etching solution of the wet etching process includes a mixed solution of H2O2 and NH4OH.

[0023] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0024] First, a modified layer is formed in the sacrificial layer by ion implantation, the remaining sacrificial layer that has not been implanted with ions is removed, a first graphic structure is formed on the transition layer, and then a second graphic structure separate from the first graphic structure is directly formed on the transition layer. The formation process of the second graphic structure reduces steps such as ion implantation, simplifies the process flow, reduces the number of graphic transfers, and improves the graphic transfer accuracy of the second graphic structure. When the transition layer is etched using the first graphic structure and the second graphic structure as masks, it is beneficial to improve the quality of the formed cutting graphic, thereby improving the quality of the partition structure of the subsequently formed interconnection structure, and is beneficial to improving the performance of the semiconductor structure finally formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figures 1 to 7 is a schematic structural diagram of a semiconductor structure forming process in one embodiment;

[0026] Figures 8 to 20 It is a schematic structural diagram corresponding to each step of a formation process of a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0027] As can be seen from the background technology, the performance of the semiconductor structure formed by the current method of forming the zero-layer metal layer partition structure (M0C) needs to be improved. The reason is now explained in conjunction with a specific embodiment.

[0028] refer to Figure 1 , providing a substrate 100 , on which a dielectric layer 101 is formed; forming a transition layer 102 on the dielectric layer 101 and a sacrificial layer 103 on the transition layer 102 .

[0029] After the sacrificial layer 103 is formed, multiple ion implantations are performed on the sacrificial layer 103 to form a plurality of mutually independent modified layers in the sacrificial layer 103 .

[0030] refer to Figure 2 In this embodiment, taking the formation of four modified layers as an example, the steps of forming a single modified layer include: forming a first patterned layer 104 on the sacrificial layer 103, wherein the first patterned layer 104 has a first opening 105, and the first opening 105 exposes a portion of the surface of the sacrificial layer 103; performing ion implantation on the sacrificial layer 103 exposed by the first opening 105, and forming a first modified layer 106 in the sacrificial layer 103.

[0031] refer to Figures 3 to 5 A second modified layer 108 is formed by using a second patterned layer 107; a third modified layer 110 is formed by using a third patterned layer 109; and a fourth modified layer 112 is formed by using a fourth patterned layer 111. The formation methods of the second modified layer 108, the third modified layer 110 and the fourth modified layer 112 are the same as the formation method of the first modified layer 106, and will not be described in detail herein.

[0032] refer to Figure 6 After forming a plurality of modified layers, the remaining sacrificial layer 103 is removed.

[0033] refer to Figure 7 The transition layer 102 is etched using the first modified layer 106 , the second modified layer 108 , the third modified layer 110 and the fourth modified layer 112 as masks until the surface of the dielectric layer 101 is exposed, and a plurality of mutually discrete cut-off patterns 113 are formed on the dielectric layer 101 .

[0034] In this embodiment, a gate structure (not shown) is formed on the surface of the substrate 100 , source-drain doping layers (not shown) are provided in the substrate 100 on both sides of the gate structure, and the dielectric layer 101 covers the surfaces of the gate structure and the source-drain doping layers.

[0035] In the subsequent process of forming a zero-layer metal layer located on the source-drain doped layer, the cut-off pattern 113 is used to form a partition structure (M0C) between zero-layer metal layers. Since the material of the cut-off pattern 113 and the material of the dielectric layer 101 have an etching selectivity ratio, when the dielectric layer 101 is etched using the zero-layer metal mask layer as a mask, the dielectric layer 101 covered by the cut-off pattern 113 is prevented from being etched, thereby forming a groove in the dielectric layer 101 between the cut-off patterns 113, and a zero-layer metal layer is formed in the groove, and the dielectric layer is used as an isolation between adjacent zero-layer metal layers.

[0036] In the process of forming the cutting pattern 113 by the above method, the formation of each cutting pattern 113 requires first forming a modified layer with a corresponding patterned layer, and transferring the pattern to the transition layer 102 through the modified layer to form the corresponding cutting pattern 113. On the one hand, the modified layer formed by ion implantation is prone to diffusion during the subsequent high-temperature process, resulting in unclear boundaries of the modified layer. When the cutting pattern 113 is formed using the modified layer as a mask, the pattern accuracy of the formed cutting pattern 113 is poor; and the formation process of the cutting pattern 113 requires multiple pattern transfer processes, and the process flow is relatively complicated. On the other hand, due to the further reduction in the size of semiconductor devices, when using each patterned layer to form a corresponding modified layer, due to insufficient overlay alignment accuracy, it may affect other adjacent modified layers, thereby affecting the performance of the formed semiconductor structure.

[0037] In order to solve the above problems, the embodiment of the present invention uses several ion implantations to form several modified layers, then removes the sacrificial layer that has not been ion implanted, forms several mutually independent first graphic structures on the transition layer, and then directly forms a second graphic structure that is independent of the first graphic structure on the transition layer. Since the second graphic structure is not formed by ion implantation, the problem of unclear graphics caused by ion diffusion is avoided, and the graphic layers required for ion implantation are reduced, the process flow is simplified, and the number of graphic transfers can be reduced. When the first graphic structure and the second graphic structure are used as masks to etch the transition layer to form a cutting graphic, it is beneficial to improve the accuracy of the graphic transfer. When the interconnection structure is subsequently formed, the cutting graphic is used to form a partition structure between the interconnection structures, which can improve the accuracy of the partition structure graphic, thereby improving the performance of the formed semiconductor structure.

[0038] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] Figures 8 to 20 It is a schematic structural diagram corresponding to each step of a formation process of a semiconductor structure in one embodiment of the present invention.

[0040] refer to Figure 8 and Fig. 9 , Figure 8 It is a top view of the semiconductor structure omitting the dielectric layer. Fig. 9 yes Figure 8 A schematic cross-sectional structure diagram along the AA direction is provided, wherein a substrate 200 is provided, and a dielectric layer 210 is formed on the substrate 200 .

[0041] The substrate 200 provides a process platform for subsequently forming a semiconductor structure.

[0042] The material of the dielectric layer 210 includes low-k dielectric material (low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9), ultra-low-k dielectric material (ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6) or dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0043] In this embodiment, the material of the dielectric layer 210 is a low-k dielectric material, including one or more of SiOH, SiOCH, SiOC and SiOCN.

[0044] In this embodiment, the substrate 200 is used to form a fin field effect transistor, and the substrate 200 includes a substrate 201 and a plurality of fins 202 discretely arranged on the substrate 201 ; in other embodiments, the substrate may also be used to form a planar field effect transistor.

[0045] The material of the substrate 200 is silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate 200 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. In this embodiment, the substrate 200 is a silicon substrate.

[0046] The material of the fin 202 is the same as that of the substrate 201 . In this embodiment, the material of the fin 202 is silicon.

[0047] In this embodiment, the method further includes: forming an isolation layer 203 on the substrate 201 , wherein the isolation structure 203 covers a portion of the sidewall surface of the fin 202 .

[0048] In this embodiment, a gate structure 204 is further formed on the substrate 200 , and source-drain doped layers 205 are further formed in the substrate 200 on both sides of the gate structure 204 . The dielectric layer 210 covers the surfaces of the gate structure 204 and the source-drain doped layers 205 .

[0049] In this embodiment, the gate structure 204 spans across the fin 202 , and the source-drain doped layers 205 are located in the fin 202 on both sides of the gate structure 204 .

[0050] In this embodiment, the steps of forming the gate structure 204 and the source-drain doped layer 205 include: forming a dummy gate structure (not shown) across the fin 202 on the substrate 201; etching the fins 202 on both sides of the dummy gate structure to form source-drain grooves (not shown) in the fins 202; forming a source-drain doped layer 205 in the source-drain grooves; forming a first dielectric layer (not shown) on the substrate 201, the first dielectric layer covering the surface of the source-drain doped layer, the sidewall surface of the dummy gate structure, and exposing the top surface of the dummy gate structure; removing the dummy gate structure to form a gate opening in the first dielectric layer; and forming a gate structure 204 in the gate opening.

[0051] In this embodiment, after the gate structure 204 is formed, the method further includes: forming a second dielectric layer (not shown) on the gate structure 204 , and the dielectric layer 210 includes a first dielectric layer and a second dielectric layer.

[0052] refer to Fig.10 , Fig.10 and Fig. 9 A transition layer 220 and a sacrificial layer 230 located on the transition layer 220 are formed on the dielectric layer 210 in the same viewing direction.

[0053] The material of the transition layer 220 includes metal or metal compound, including one or more of titanium nitride, titanium oxide, titanium or titanium aluminum compound. In this embodiment, the material of the transition layer 220 is titanium nitride.

[0054] In this embodiment, the process of forming the transition layer 220 is a physical vapor deposition process; in other embodiments, the transition layer 220 may also be formed by a chemical vapor deposition process.

[0055] The material of the sacrificial layer 230 includes amorphous silicon, amorphous carbon or amorphous germanium. In this embodiment, the material of the sacrificial layer 230 is amorphous silicon.

[0056] In this embodiment, the sacrificial layer 230 is formed by a chemical vapor deposition process; in other embodiments, the sacrificial layer 230 may also be formed by an atomic layer deposition process.

[0057] After the sacrificial layer 230 is formed, several ion implantations are performed on the sacrificial layer 230 to form several discrete modified layers in the sacrificial layer 230 .

[0058] In this embodiment, the step of single ion implantation includes: forming a patterned layer (not shown) on the sacrificial layer 230 , wherein the patterned layer has an opening, and the opening exposes a portion of the surface of the sacrificial layer 230 ; and implanting ions into the sacrificial layer 230 exposed by the opening.

[0059] In this embodiment, there is an etching selectivity ratio between the modified layer formed after ion injection and the sacrificial layer 230 without ion injection, so that when the sacrificial layer 230 without ion injection is subsequently removed, damage to the modified layer is avoided, which is beneficial to ensure the accuracy of the transferred pattern.

[0060] It should be noted that the number of modified layers formed can be adjusted according to actual process requirements, and the present invention does not impose any limitation on this.

[0061] In this embodiment, for the convenience of explanation, the modified layer includes a first modified layer, a second modified layer and a third modified layer. Accordingly, the first modified layer, the second modified layer and the third modified layer are formed by a first patterned layer, a second patterned layer and a third patterned layer, respectively.

[0062] refer to Fig.11 , Fig.11 and Fig.10 In accordance with the viewing direction, a first patterned layer 231 is formed on the sacrificial layer 230, and the first patterned layer 231 has a first opening 232, and the first opening 232 exposes a portion of the sacrificial layer 230; ion implantation is performed on the sacrificial layer 230 exposed by the first opening 232 to form a first modified layer 233 in the sacrificial layer 230.

[0063] In this embodiment, the first patterned layer 231 is a patterned photoresist layer.

[0064] In this embodiment, the step of forming the first patterned layer 231 includes: forming a first photoresist layer (not shown) on the sacrificial layer 230 ; and exposing and developing the first photoresist layer using a first mask to form the first patterned layer 231 .

[0065] In this embodiment, the pattern of the first mask corresponds to the pattern of the first modified layer 233 .

[0066] The process parameters of the ion implantation include: the implanted ions include boron ions, phosphorus ions or arsenic ions; the implantation energy is 1KeV~5KeV, and the implantation dose is 1E14~5E15atoms / cm 2 .

[0067] refer to Fig.12 , Fig.12 and Fig.11The viewing direction is consistent with that of the first modified layer 233, and the first patterned layer 231 is removed after the first modified layer 233 is formed; a second patterned layer 234 is formed on the sacrificial layer 230, and the second patterned layer 234 has a second opening 235, and the second opening 235 exposes a portion of the sacrificial layer 230; ion implantation is performed on the sacrificial layer 230 exposed by the second opening 235, and a second modified layer 236 is formed in the sacrificial layer 230.

[0068] In this embodiment, an ashing process is used to remove the first patterned layer 231 .

[0069] In this embodiment, the material and forming method of the second patterned layer 234 are consistent with those of the first patterned layer 231 , and are not described again. It should be noted that the pattern of the second mask used to form the second patterned layer 234 corresponds to the pattern of the second modified layer 236 .

[0070] In this embodiment, the ion implantation process for forming the second modified layer 236 is the same as the ion implantation process for forming the first modified layer 231 , and will not be described in detail herein.

[0071] refer to Fig.13 , Fig.13 and Fig.12 The viewing direction is consistent with that of the first embodiment. After forming the second modified layer 236, the second patterned layer 234 is removed. A third patterned layer 237 is formed on the sacrificial layer 230. The third patterned layer 237 has a third opening 238. The third opening 238 exposes a portion of the sacrificial layer 230. Ions are implanted into the sacrificial layer 230 exposed by the third opening 238 to form a third modified layer 239 in the sacrificial layer 230.

[0072] In this embodiment, an ashing process is used to remove the second patterned layer 234 .

[0073] In this embodiment, the material and forming method of the third patterned layer 237 are consistent with those of the first patterned layer 231 , and are not described again. It should be noted that the pattern of the third mask used to form the third patterned layer 237 corresponds to the pattern of the third modified layer 239 .

[0074] In this embodiment, the ion implantation process for forming the third modified layer 239 is the same as the ion implantation process for forming the first modified layer 231 , and will not be described in detail herein.

[0075] refer to Fig.14 , Fig.14 and Fig.13The viewing direction is consistent with that of the embodiment. After forming the third modified layer 239 , the third patterned layer 237 is removed; the remaining sacrificial layer 230 is removed, and a first pattern structure 240 is formed on the transition layer 220 .

[0076] In this embodiment, an ashing process is used to remove the third patterned layer 234 .

[0077] In this embodiment, the process for removing the remaining sacrificial layer 230 is a wet etching process; the process parameters of the wet etching process include: the etching solution includes a TMAH solution or an ammonia solution.

[0078] In this embodiment, the wet etching process has a high etching selectivity ratio for the sacrificial layer 230 that has not been ion-implanted to the modified layer, so when the remaining sacrificial layer 230 is removed, the modified layer can be prevented from being etched and damaged.

[0079] In this embodiment, the first graphic structure 240 includes a first modified layer 233 , a second modified layer 236 and a third modified layer 239 which are separate from each other.

[0080] After the first graphic structure 240 is formed, a second graphic structure is formed on the transition layer 230 .

[0081] In this embodiment, the step of forming the second graphic structure includes:

[0082] refer to Fig.15 , Fig.15 and Fig.14 A second graphic material layer (not shown) is formed on the transition layer 220 in accordance with the viewing direction, and the top surface of the second graphic material layer is flush with the top surface of the first graphic structure 240; the second graphic material layer is exposed and developed using a mask corresponding to the position of the second graphic structure to form a second graphic structure 250.

[0083] In this embodiment, the second pattern material layer is a photoresist layer.

[0084] In this embodiment, the second graphic material layer is directly patterned to form the second graphic structure 250, which reduces the steps such as the ion implantation process and simplifies the process flow. The mask corresponding to the position of the second graphic structure is used to directly transfer the pattern to the second graphic material layer, which reduces the number of pattern transfers and improves the accuracy of the pattern transfer. In addition, since the second graphic structure 250 is formed without using the ion implantation process, the problem of unclear pattern of the second graphic structure 250 caused by ion diffusion is avoided.

[0085] refer to Fig.16 and Fig.17 , Fig.16It is a top view of the semiconductor structure omitting the dielectric layer. Fig.17 yes Fig.16 The schematic cross-sectional structure diagram along the BB direction shows that the first graphic structure 240 and the second graphic structure 250 are used as masks to etch the transition layer 220 until the surface of the dielectric layer 210 is exposed, and separate cut-off graphics 260 are formed on the dielectric layer 210 .

[0086] In this embodiment, the cutting pattern 260 corresponds to the position and size of the partition structure between the interconnected structures formed subsequently.

[0087] In this embodiment, the process of etching the transition layer is a plasma dry etching process; the process parameters of the plasma dry etching process include: the etching gas includes a fluorine-containing gas or a chlorine-containing gas.

[0088] Among them, fluorine-containing gases include SF6 gas or C x H y F z Gas, x is a natural number greater than or equal to 1, y is a natural number greater than or equal to 0, and z is a natural number greater than or equal to 1; chlorine-containing gas includes Cl2.

[0089] It should be noted that in this embodiment, in the cutting direction along BB, the cutting pattern 260 includes a first graphic structure 240 and a second graphic structure 250. In other cutting directions, there may also be other cutting patterns, and the position and size of the cutting pattern may be determined according to actual process requirements.

[0090] refer to Fig.18 , Fig.18 It is a top view of the semiconductor structure. A first mask layer 270 is formed on the substrate 200 . The first mask layer 270 exposes a portion of the cut-off pattern 260 and the surface of the dielectric layer 210 above the source-drain doping layer 205 .

[0091] In this embodiment, the first mask layer 270 is used to form a groove located above the source-drain doping layer 205. The first mask layer 270 has a groove opening 271. The groove opening 271 is continuous in a direction perpendicular to the extension direction of the fin 202, exposing the surface of the dielectric layer 210 on both sides of the gate structure 204 and a portion of the surface of the cut-off pattern 260.

[0092] refer to Fig.19 and Fig. 20 , Fig.19 is a top view of the semiconductor structure. Fig. 20 and Fig.17In accordance with the viewing direction, the first mask layer 270 is used as a mask to etch the dielectric layer 210 exposed by the groove opening 271, and a groove 280 is formed in the dielectric layer 210 between adjacent cut-off patterns 260, and the bottom of the groove 280 exposes the top surface of the source-drain doping layer 205.

[0093] In this embodiment, the process of etching the dielectric layer 210 is a dry etching process; the process parameters of the dry etching process include: the etching gas includes a mixed gas of HF and CF4.

[0094] The dry etching process has an etching selectivity ratio of greater than 10:1 for the dielectric layer 210 and the cut-off pattern 260. Since the dielectric layer 210 and the cut-off pattern 260 have an etching selectivity ratio, the cut-off pattern 260 can be prevented from being etched and damaged during the etching of the dielectric layer 210, thereby protecting the dielectric layer 210 covered by the cut-off pattern 260, and having a dielectric layer as a partition structure between adjacent grooves.

[0095] After the groove 280 is formed, the cut-off pattern 260 is removed.

[0096] In this embodiment, the method for removing the cut-off pattern 260 includes a wet etching process; the etching solution of the wet etching process includes a mixed solution of H2O2 and NH4OH.

[0097] In this embodiment, the method further includes: forming an interconnect structure (not shown) in the trench 280 , wherein the interconnect structure is electrically connected to the source-drain doped layer 205 .

[0098] The interconnect structure is made of metal, including conductive materials such as copper, aluminum, and cobalt.

[0099] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, on which a dielectric layer is formed; forming a transition layer and a sacrificial layer on the transition layer on the dielectric layer; Performing ion implantation on the sacrificial layer several times to form a plurality of mutually discrete modified layers in the sacrificial layer respectively; removing the remaining sacrificial layer and forming a first graphic structure on the transition layer; forming a second graphic structure on the transition layer, wherein the second graphic structure is not formed by ion implantation, and the second graphic structure is separate from the first graphic structure; The transition layer is etched using the first graphic structure and the second graphic structure as masks until the surface of the dielectric layer is exposed, thereby forming mutually separate cut-off graphics on the dielectric layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The method for performing ion implantation on the sacrificial layer comprises: forming a patterned layer on the sacrificial layer, wherein the patterned layer has an opening, and the opening exposes a portion of the surface of the sacrificial layer; and performing ion implantation on the sacrificial layer exposed by the opening.

3. The method for forming a semiconductor structure according to claim 2, wherein: The process parameters of the ion implantation include: the implanted ions include boron ions, phosphorus ions or arsenic ions; the implantation energy is 1KeV~5KeV, and the implantation dose is 1E14~5E15atoms / cm 2 .

4. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the second graphic structure includes: forming a second graphic material layer on the transition layer; and patterning the second graphic material layer to form a second graphic structure on the transition layer.

5. The method for forming a semiconductor structure according to claim 4, wherein: The second pattern material layer includes a photoresist layer, a bottom anti-reflection layer, a spin-on glass layer or a spin-on carbon layer.

6. The method for forming a semiconductor structure according to claim 1, wherein: After forming the first graphic structure, the second graphic structure is formed.

7. The method for forming a semiconductor structure according to claim 1, wherein: The material of the transition layer includes metal or metal compound.

8. The method for forming a semiconductor structure according to claim 7, wherein: The material of the transition layer includes one or more of titanium nitride, titanium oxide, titanium or titanium aluminum compound.

9. The method for forming a semiconductor structure according to claim 8, wherein: Using the first graphic structure and the second graphic structure as masks, a method for etching the transition layer includes a plasma dry etching process; The process parameters of the plasma dry etching process include: the etching gas includes a fluorine-containing gas or a chlorine-containing gas.

10. The method for forming a semiconductor structure according to claim 1, wherein: The material of the sacrificial layer includes amorphous silicon, amorphous carbon or amorphous germanium.

11. The method for forming a semiconductor structure according to claim 10, wherein: The method for removing the remaining sacrificial layer includes a wet etching process; the process parameters of the wet etching process include: the etching solution includes a TMAH solution or an ammonia solution.

12. The method for forming a semiconductor structure according to claim 1, wherein: A gate structure is formed on the surface of the substrate, source-drain doping layers are formed in the substrate on both sides of the gate structure, and the dielectric layer covers the surfaces of the gate structure and the source-drain doping layers.

13. The method for forming a semiconductor structure according to claim 12, wherein: After forming the cutting pattern, the method further includes: forming a first mask layer on the substrate, wherein the first mask layer exposes a portion of the cutting pattern and the surface of the dielectric layer above the source-drain doped layer; etching the dielectric layer using the first mask layer as a mask until the surface of the source-drain doped layer is exposed, and forming a groove in the dielectric layer between adjacent cutting patterns; and forming an interconnect structure in the groove.

14. The method for forming a semiconductor structure according to claim 13, wherein: The method of etching the dielectric layer using the first mask layer as a mask includes a dry etching process; the process parameters of the dry etching process include: the etching gas includes a mixed gas of HF and CF4.

15. The method for forming a semiconductor structure according to claim 14, wherein: The etching selectivity ratio of the dry etching process to the dielectric layer and the cut-off pattern is greater than 10:

1.

16. The method for forming a semiconductor structure according to claim 13, wherein: Before forming the interconnection structure in the groove, the method further includes: removing the cut-off pattern.

17. The method for forming a semiconductor structure according to claim 16, wherein: The method for removing the cut-off pattern includes a wet etching process; the etching solution of the wet etching process includes a mixed solution of H2O2 and NH4OH.

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