A fin-type floating gate memory device

Abstract

The application provides a fin floating gate memory device, comprising: a substrate; an isolation layer located on one side of the substrate; a fin located on the side of the isolation layer away from the substrate; a tunneling dielectric layer covering the periphery of the fin; a floating gate covering the periphery of the tunneling dielectric layer; a gate oxide layer covering the periphery of the floating gate; and a control gate covering the periphery of the gate oxide layer; wherein the ratio of the thickness of the top of the tunneling dielectric layer to the thickness of the sidewall is (2-3):1. The fin floating gate memory device of the application is aimed at the problem of uneven carrier concentration of the fin structure in the working process, and the ratio of the thickness of the top of the tunneling dielectric layer to the thickness of the sidewall is set to (2-3):1, that is, the side tunneling layer is thinner than the top tunneling layer, and through the structure, the electrons and holes in the fin are more easily injected and tunnel through the dielectric layer to reach the floating gate.

Description

Technical Field

[0001] This invention relates to the field of storage device technology, and more particularly to a fin-type floating gate storage device. Background Technology

[0002] The development of humankind has been accompanied by the development of storage devices. When information needs to be stored, storage devices are required. From the earliest stone carvings, bamboo slips, and cloth used for storing information to the current dominant use of paper, this process has taken thousands of years and can be considered quite slow. After entering the 20th century, with the development of electronic technology, the world entered the electronic age, and storage devices have developed tremendously, with new types of storage devices constantly emerging and their functions continuously enhanced.

[0003] The technology prototype of flash memory was first proposed by Schmin of Bell Labs in 1967 and has dominated the non-volatile memory market for the past 30 years. After decades of in-depth research and exploration, memory technology has matured, and floating-gate flash memory is increasingly widely used in the commercial field. However, it also faces significant limitations. The IC industry has historically followed Moore's Law, where integration density doubles every 18 months. Therefore, the first major problem restricting the development of floating-gate flash memory is the continuous shrinkability of its size. As the size of memory cells continues to shrink, the voltage required for programming and erasing operations cannot be reduced proportionally. Shorter gate lengths require thinner tunneling oxide layers to control the device, which may compromise device reliability and flash memory functionality, and the short-channel effect is significant. To overcome these problems, various new structures have emerged. US Patent 6,413,802 by Chenming Hu et al. discloses a FinFET formed on SOI (Semiconductor On Insulator), including a channel region formed in the middle of the fins of the semiconductor material and source / drain regions formed at both ends of the fins. Gate electrodes surround the channel region on both sides (i.e., a dual-gate structure), thereby forming an inversion layer on each side of the channel. FinFETs are considered one of the most promising new structural devices to replace planar silicon CMOS devices due to their good cutoff performance, scalability, and compatibility with conventional manufacturing processes. However, SOI FinFETs increase the overall device cost due to the increased cost of the substrate. To reduce R&D costs and improve the yield of integrated circuits, companies increasingly need professional simulation tools to accurately evaluate the performance of semiconductor device structures and arrays, and to optimize and balance the device structure based on the performance evaluation. Currently, semiconductor process and device simulation (TCAD) tools are playing an increasingly important role in the semiconductor circuit manufacturing industry.

[0004] As CMOS device sizes continue to shrink, flash memory, driven by both technology and market forces, is evolving towards faster write / erase, higher density, higher reliability, lower voltage, and lower power consumption. However, flash memory and floating-gate devices also face many limitations and challenges in their development. When the physical size of devices shrinks to below 50nm, traditional floating-gate devices face even more severe challenges, with decreased reliability, mainly in the following aspects:

[0005] (1) The reduction in device size leads to a decrease in the control effect of the control gate on the floating gate, i.e., a decrease in the GCR (Gate coupling ratio). Existing solutions involve surrounding the floating gate with the control gate, such as dual-gate or ring-gate devices. However, this becomes difficult to implement when the size shrinks to below 30nm. The decrease in GCR requires a higher operating voltage for cell operations, which exacerbates oxide degradation and reduces reliability.

[0006] (2) The thickness of the tunneling oxide layer in floating gate memory cannot be further reduced. When the oxide layer is less than 6 nm, the direct tunneling effect and stress-induced leakage current (SILC) in the ultrathin oxide layer will greatly affect the performance of the device. Therefore, the thickness of the tunneling oxide layer cannot be reduced to below 8 nm. Faced with the limitations of leakage current and process, the thickness of the ONO (Oxide-Nitride-Oxide) dielectric layer can be reduced to a minimum of about 14 nm. Therefore, the problem of reducing the vertical dimension of the device is very difficult.

[0007] (2) As device size continues to shrink, the coupling coefficient between the control gate and the floating gate memory layer also decreases. Furthermore, as the spacing between adjacent devices decreases, crosstalk between adjacent cells and floating gate interference become increasingly severe, significantly impacting device reliability. For memory devices using polysilicon as the floating gate, the thickness of polysilicon is difficult to reduce, while the width and length of the device channel continue to shrink. This results in a more "slender" overall device shape, increasing the difficulty and reliability of manufacturing processes. At the same time, the parasitic capacitance between adjacent "slender" memory cells increases due to their close proximity, leading to enhanced interference between adjacent cells and potentially causing data errors.

[0008] (3) Due to the reduction in size, the number of electrons that can be stored in a single floating gate is greatly reduced and very limited. Therefore, even the loss of a few electrons will cause a serious drift in the threshold voltage of the entire device, which will reduce the data accuracy of the storage cell.

[0009] Given the existing technical problems with floating gate devices, it is necessary to improve them. Summary of the Invention

[0010] In view of this, the present invention proposes a fin-type floating gate memory device, which solves or at least partially solves the technical defects existing in the prior art.

[0011] In a first aspect, the present invention provides a fin-type floating gate storage device, comprising:

[0012] Substrate;

[0013] An isolation layer is located on one side of the substrate;

[0014] Fins are located on the side of the isolation layer away from the substrate;

[0015] A tunneling medium layer that covers the outer periphery of the fins;

[0016] A floating gate, which covers the outer periphery of the tunneling medium layer;

[0017] A gate oxide layer that covers the outer periphery of the floating gate;

[0018] A control gate, which covers the outer periphery of the gate oxide layer;

[0019] The ratio of the top thickness to the sidewall thickness of the tunneling medium layer is (2-3):1.

[0020] Preferably, in the fin-type floating gate storage device, the ratio of the top thickness of the tunneling dielectric layer to the thickness of the sidewall is 2:1.

[0021] Preferably, in the fin-type floating gate memory device, both the control gate and the floating gate are made of polycrystalline silicon material.

[0022] Preferably, in the fin-type floating gate memory device, the gate oxide layer is made of silicon dioxide.

[0023] Preferably, in the fin-type floating gate storage device, the material used for the tunneling dielectric layer includes any one of silicon dioxide, silicon nitride, and hafnium oxide.

[0024] Preferably, in the fin-type floating gate storage device, the material of the isolation layer is silicon dioxide.

[0025] Preferably, in the fin-type floating gate memory device, the thickness of the floating gate is 7-9 nm, the thickness of the control gate is 4-6 nm, and the thickness of the gate oxide layer is 4-5 nm.

[0026] The fin-type floating gate memory device of the present invention has the following advantages over the prior art:

[0027] The fin-type floating gate memory device of the present invention addresses the problem of uneven carrier concentration during operation of the fin structure by setting the ratio of the top thickness of the tunneling dielectric layer to the thickness of the sidewall to (2-3):1. That is, the present invention uses a side tunneling layer that is thinner than the top tunneling layer. This structure makes it easier for electrons and holes in the fins to be injected and tunnel through the dielectric layer to reach the floating gate. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of the structure of the fin-type floating gate memory device of the present invention;

[0030] Figure 2 The charge distribution in the device constructed using simulation software for the fin-type floating gate memory device in Comparative Example 1 is shown in the simulation (write operation).

[0031] Figure 3 The performance simulation curves (charge-time) of the fin-type floating gate memory device in Comparative Example 1 are shown.

[0032] Figure 4 The graph shows the transfer characteristic curves read from the performance simulation of the fin-type floating gate memory device in Comparative Example 1.

[0033] Figure 5 The charge distribution in the fin-type floating gate memory device during simulation (write operation) in Example 1;

[0034] Figure 6 The performance simulation curve (charge-time) of the fin-type floating gate memory device in Example 1 is shown.

[0035] Figure 7 The transfer characteristic curve is read from the performance simulation of the fin-type floating gate memory device in Example 1 (the programming and erasure thresholds can be extracted);

[0036] Figure 8 This is a performance simulation curve (charge-time) of the fin-type floating gate memory device in Example 2;

[0037] Figure 9 This is a transfer characteristic curve read from the performance simulation of the fin-type floating gate memory device in Example 2. Detailed Implementation

[0038] The technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0039] This invention provides a fin-type floating gate memory device, such as... Figure 1 As shown, it includes:

[0040] Substrate 1;

[0041] An isolation layer 2 is located on one side of the substrate 1;

[0042] Fin 3 is located on the side of the isolation layer 2 away from the substrate 1;

[0043] The tunneling medium layer 4 covers the outer periphery of the fin 3;

[0044] Floating gate 5, which covers the outer periphery of tunneling medium layer 4;

[0045] Gate oxide layer 6, which covers the outer periphery of floating gate 5;

[0046] The control gate 7 is covered around the outer periphery of the gate oxide layer 6;

[0047] The ratio of the top thickness to the sidewall thickness of the tunneling medium layer 4 is (2-3):1.

[0048] The fin-type floating gate memory device of the present invention has the following structure: Figure 1 As shown, this invention does not improve the main structure of the fin-type floating gate memory device; it only changes the top thickness and sidewall thickness of the tunneling dielectric layer 4 from a uniform thickness to a ratio of (2-3):1. The fin-type floating gate memory device of this invention also includes source and drain electrodes and... ditch Specifically, the tunneling dielectric layer 4 covers the outer periphery of the fin 3, but the tunneling dielectric layer 4 does not completely cover the fin 3. The two sides of the fin 3 are not covered by the tunneling dielectric layer 4. A source electrode 8 and a drain electrode 9 are respectively disposed on both sides of the fin 3 located on the tunneling dielectric layer 4, and the area between the source electrode 8 and the drain electrode 9 is... ditch Furthermore, the channel extends through the fin 3. Specifically, the height of the conductive channel is the same as the height of the fin 3, the width of the conductive channel is the same as the width of the fin 3, and the length of the channel is the distance between the source electrode 8 and the drain electrode 9.

[0049] To address the issue of uneven carrier concentration in fin structures during operation, this invention sets the ratio of the top thickness of the tunneling dielectric layer to the thickness of the sidewall to (2-3):1. In other words, this invention employs a side tunneling layer that is thinner than the top tunneling layer. This structure allows electrons and holes in the fins to more easily penetrate the dielectric layer through injection and tunneling to reach the floating gate.

[0050] In some embodiments, the ratio of the top thickness of the tunneling medium layer 4 to the thickness of the sidewall is 2:1.

[0051] In some embodiments, both the control gate 7 and the floating gate 5 are made of polycrystalline silicon.

[0052] In some embodiments, the gate oxide layer 6 is made of silicon dioxide.

[0053] In some embodiments, the material used for the tunneling dielectric layer 4 includes any one of silicon dioxide, silicon nitride, and hafnium oxide.

[0054] In some embodiments, the material of the isolation layer 2 is silicon dioxide.

[0055] In some embodiments, the thickness of the floating gate 5 is 7–9 nm, the thickness of the control gate 7 is 4–6 nm, and the thickness of the gate oxide layer 6 is 4–5 nm.

[0056] In some embodiments, the conductive channel has a width of 30–40 nm, a length of 35–45 nm, and a height of 45–50 nm.

[0057] Based on the same inventive concept, this application also provides a method for fabricating a fin-type floating gate memory device, comprising the following steps:

[0058] A silicon substrate is provided;

[0059] A silicon oxide isolation layer is formed by oxidizing the silicon substrate.

[0060] A silicon layer is deposited on a silicon oxide isolation layer, and then coated to form the first layer of photoresist. After masking, exposure, and etching, the silicon layer on the silicon oxide isolation layer is formed into a fin structure. After substrate doping, a channel is formed.

[0061] A second layer of photoresist is coated on the fin structure. After masking, exposure, and etching, the pattern to be doped is formed, and the doped regions of the source and drain are formed inside the fin.

[0062] A first silicon dioxide dielectric layer is grown on the fin structure, and the first silicon dioxide dielectric layer is etched to form a tunneling dielectric layer, with the ratio of the top thickness of the tunneling dielectric layer to the thickness of the sidewall being (2~3):1.

[0063] A first polysilicon thin layer is deposited on the fin structure and the tunneling dielectric layer. The floating gate of the device is formed by masking, exposure and etching of the first polysilicon thin layer.

[0064] A second silicon dioxide dielectric layer is grown on the fin structure and the floating gate, and the second silicon dioxide dielectric layer is etched to form a gate oxide layer.

[0065] A second polysilicon thin layer is deposited on the fin structure and the gate oxide layer. The control gate of the device is formed by masking, exposure, and etching of the second polysilicon thin layer.

[0066] The structure of the fin-type floating gate memory device of this application will be further described below with specific embodiments.

[0067] Example 1

[0068] This application provides a fin-type floating gate storage device, including...

[0069] Substrate 1 is a silicon substrate;

[0070] An isolation layer 2 is located on one side of the substrate 1, and the material of the isolation layer 2 is silicon dioxide;

[0071] Fin 3 is located on the side of the isolation layer 2 away from the substrate 1, and the material of fin 3 is silicon.

[0072] The tunneling dielectric layer 4 covers the outer periphery of the fin 3, and the material of the tunneling dielectric layer 4 is silicon dioxide;

[0073] The floating gate 5 is wrapped around the outer periphery of the tunneling dielectric layer 4, and the material of the floating gate 5 is polycrystalline silicon.

[0074] Gate oxide layer 6, which covers the outer periphery of floating gate 5, is made of silicon dioxide.

[0075] The control gate 7 is covered around the gate oxide layer 6, and the material of the control gate 7 is polycrystalline silicon.

[0076] In this case, the two sides of the fin 3 are not covered by the tunneling dielectric layer 4. The source electrode 8 and the drain electrode 9 are respectively set on both sides of the tunneling dielectric layer 4, and the channel between the source electrode 8 and the drain electrode 9 is the fin 3.

[0077] The floating gate 5 has a thickness of 8 nm, the control gate 7 has a thickness of 5 nm, and the gate oxide layer 6 has a thickness of 4 nm. ditch The width is 35nm, the length is 40nm, and the height is 50nm. The top thickness of the tunneling dielectric layer 4 is 6nm and the sidewall thickness is 3nm.

[0078] Example 2

[0079] This application provides a fin-type floating gate memory device with the same structure as in embodiment 1, except that the top thickness of the tunneling dielectric layer 4 is 6-12 nm and the sidewall thickness is 2-4 nm.

[0080] Comparative Example 1

[0081] This comparative example provides a fin-type floating gate memory device with the same structure as in Example 1, except that the top thickness and sidewall thickness of the tunneling dielectric layer 4 are both 6 nm.

[0082] Performance testing

[0083] The charge distribution of the fin-type floating gate memory device in Comparative Example 1 during a simulated (write operation) was analyzed using simulation software. The results are as follows: Figure 2 As shown in the figure. The performance simulation curves (charge-time) of the fin-type floating gate memory device in Comparative Example 1 were obtained using simulation software, and the results are as follows. Figure 3 As shown. The threshold voltage characteristic curve read from the performance simulation of the fin-type floating gate memory device in Comparative Example 1 is shown in the figure. Figure 4 As shown.

[0084] from Figure 2 It can be seen that electrons have difficulty tunneling into the side floating gates, and instead accumulate in the top floating gate and corners, which is illogical. According to... Figure 3 and Figure 4 The performance and threshold extraction curves show that, under this structure, the device completely loses the performance of a floating gate device. Based on this, the device structure is improved, and the structure of this invention is proposed.

[0085] The fin-type floating gate memory device in Embodiment 1 of this invention differs from traditional planar floating gate structures and ordinary fin-type floating gate structures. Due to the significant reduction in device size, the size of the polysilicon floating gate in the floating gate device also becomes increasingly smaller. During device operation, electrons are injected into the polysilicon floating gate during the write operation. As the device size shrinks, the number of electrons that can be stored in the floating gate is greatly reduced and very limited. Even the loss of a few electrons can cause a severe drift in the threshold voltage of the entire device, reducing the data accuracy of the memory cell. During device simulation, using a traditional structure, when a suitable programming voltage is applied to the gate, electrons in the fin are injected into the floating gate during device operation. However, during the source / drain doping of the fin, a deviation inevitably occurs between the impurity concentration at the top and the impurity concentration at the sidewalls, with the impurity concentration at the sidewalls being much lower than that at the top. This change causes different levels of difficulty for charge carriers to pass through the tunneling layer. Under the same gate voltage, it is more difficult for charge carriers to pass through the sidewalls. During the write operation, electrons accumulate at the top and corners of the polysilicon floating gate, while only a very small number of electrons are injected into the sidewalls. This is clearly detrimental to device performance. To improve this situation, the present invention employs tunneling layers of varying thicknesses at different locations. Simulations using this structure yielded satisfactory performance. Figure 5 The charge distribution of the fin-type floating gate memory device in Example 1 during a write operation during simulation is shown below. Figure 2 By comparison, it is clear that a large number of electron charges are concentrated in the floating gate, unlike... Figure 2 The electron charge distribution in the floating gate is relatively uniform, and the electron tunneling performance is good. This invention only describes the write operation; the hole tunneling capability in the erase operation is similar and will not be described in detail here.

[0086] Furthermore, performance simulations were performed on the fin-type floating gate memory device in Example 1, such as... Figure 6 As shown, Figure 6 The simulation demonstrated the device's excellent programming and erasing performance. The programming voltage used in the simulation was 9V, and the pulse width was 10. -6 s, pulse delay is 5×10 -3 s; Erase voltage is -8V, pulse width is 10 ms. -6 s, pulse delay is 7.5×10 -3 s 。 This structure can achieve lower programming and erasing voltages, and its read / write speeds are comparable to those of planar floating-gate memory devices.

[0087] Then, the threshold voltage during the erase process in the performance simulation was read. For example... Figure 7As shown, by adding a read voltage of -1 to 3V, the threshold voltages during the device's erase and write processes are extracted, resulting in the curve shown in the figure. The device has a programming threshold voltage of 1.34V, an erase threshold voltage of 0.20V, and a memory window of 1.14V, which is acceptable for a floating gate memory device.

[0088] In Example 2, the fin-type floating gate memory device has a top thickness of 6–12 nm and a sidewall thickness of 2–4 nm, with a top-to-sidewall thickness ratio of approximately 3:1. The charge change curve was obtained by simulation of the fin-type floating gate memory device in Example 2, as shown below. Figure 8 As shown. The device can still perform operations such as carrier tunneling. However, after the sidewalls are thinned to a certain thickness, electron injection intensifies, and an excessive amount of electron charge is stored within the floating gate. This is detrimental to other device performance characteristics, such as retention and durability. The threshold voltage of the device during operation is read, such as... Figure 9 As shown, the two threshold values ​​of the device coincide under this structure (the thickness of the top of the tunneling layer to the sidewall is 3:1), indicating that the device has lost its floating gate storage performance. The single threshold value makes the device transform into a general MOS device.

[0089] By comparing the device structures in Examples 1-2 and Comparative Example 1, the device performance is compared. The device used in Example 1 (with a 2:1 ratio of tunneling layer top to sidewall thickness), considering the ratio of the tunneling layer top to sidewall dimensions and the simulation performance of the three devices, shows that a 2:1 ratio is the easiest to achieve in practice and provides the best performance. In simulations, thinning or increasing the tunneling layer thickness while maintaining the original ratio can negatively impact device performance. As seen in this invention, at a 3:1 ratio, the device loses the performance expected of a floating gate device. Replacing the silicon dioxide dielectric layer with a high-k dielectric can adjust device performance and expand the storage window. Similarly, device performance can be fine-tuned by changing the channel aspect ratio and the fin height until a desired device structure is obtained. The key point of this invention is the inconsistency between the top and sidewall thicknesses of the tunneling dielectric layer. This structure allows for more uniform and reasonable carrier tunneling and injection into the floating gate in the fin-type floating gate device, resulting in more satisfactory performance.

[0090] For actual devices, performance tests can be performed using various testing equipment under the same voltage conditions.

[0091] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A fin-type floating gate storage device, characterized in that, include: Substrate; An isolation layer is located on one side of the substrate; Fins are located on the side of the isolation layer away from the substrate; A tunneling medium layer that covers the outer periphery of the fins; A floating gate, which covers the outer periphery of the tunneling medium layer; A gate oxide layer that covers the outer periphery of the floating gate; A control gate, which covers the outer periphery of the gate oxide layer; The ratio of the top thickness to the sidewall thickness of the tunneling medium layer is 2:

1.

2. The fin-type floating gate storage device as described in claim 1, characterized in that, Both the control gate and the floating gate are made of polycrystalline silicon.

3. The fin-type floating gate storage device as described in claim 1, characterized in that, The gate oxide layer is made of silicon dioxide.

4. The fin-type floating gate storage device as claimed in claim 1, characterized in that, The material used in the tunneling medium layer includes any one of silicon dioxide, silicon nitride, and hafnium oxide.

5. The fin-type floating gate storage device as claimed in claim 1, characterized in that, The material of the isolation layer is silicon dioxide.

6. The fin-type floating gate storage device as claimed in claim 1, characterized in that, The thickness of the floating gate is 7-9 nm, the thickness of the control gate is 4-6 nm, and the thickness of the gate oxide layer is 4-5 nm.

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