A top-gate bottom-contact device based on deuterium annealing process and its manufacturing method and organic field-effect transistor

Abstract

The present invention discloses a top-gate bottom-contact device structure comprising, from top to bottom, a gate layer, an insulating layer, a semiconductor layer, a source / drain electrode layer, and a base layer. The semiconductor layer is made of an organic polymer, wherein the degree of unsaturation of carbon-carbon double bonds in the monomers of the organic polymer is ≥8. The insulating layer and the semiconductor layer are integrally formed. The surface layer of the semiconductor is treated with deuterium gas annealing to obtain the insulating layer. The technical solution of the present invention eliminates the need to select new materials and prepare a separate insulating layer. Instead, deuterium gas annealing is used to convert the surface semiconductor layer into an insulating material, utilizing deuterium gas to perform an addition reaction on the surface of the semiconductor layer. This allows the insulating layer to be formed directly on the surface of the semiconductor layer, reducing the number of processing steps for the insulating layer and fundamentally resolving the difficult problem of selecting insulating and semiconductor materials.

Description

Technical Field

[0001] The present invention relates to the technical field of organic field effect transistors in semiconductor materials, and in particular to a top-gate bottom-contact device structure and a manufacturing method thereof based on a deuterium gas annealing process, and an organic field effect transistor. Background Art

[0002] Organic field effect transistors (FETs) are active devices that use electric fields to control the conductive properties of solid materials. Due to their advantages such as small size, light weight, low power consumption, good thermal stability, no secondary breakdown phenomenon, and wide safe operating area, they have become one of the important components in the microelectronics industry.

[0003] Organic field-effect transistors (OFETs), the most fundamental building blocks of flexible electronics, have garnered widespread attention. Organic field-effect transistor structures include top-contact and bottom-contact structures. The latter is also known as a top-gate bottom-contact device structure. In this device structure, the source and drain electrodes are fabricated first, and the gate acts as an encapsulation. The top layer is then covered with an insulating layer, which effectively protects the organic semiconductor by blocking corrosion from water and oxygen in the air. This gives the top-gate bottom-contact device structure excellent device stability and, therefore, great market application prospects.

[0004] However, the production process of this structure requires the preparation of a dielectric layer and gate electrode on the organic semiconductor layer, significantly limiting the choice of materials for the organic semiconductor and insulating layers. This is because top-gate, bottom-contact device structures typically require the spin-coating of an organic material as an insulating layer onto the fabricated device. The solvent used in the preparation of the top insulating layer requires cross-solubility with the semiconductor layer. The selection of mutually immiscible solvents severely restricts the types of materials used for the insulating and semiconductor layers. Furthermore, the inevitable solvent compatibility issues mentioned above can lead to defects at the interface between the two during processing, creating numerous "traps." These traps must be filled by the charge induced by the gate voltage before they can accumulate in the channel, resulting in an increase in the threshold voltage. Existing insulating layer materials primarily include PPMA, CYTOP, PI, PVP, PS, BCB, and PVA. These insulating layer materials inevitably dissolve with the semiconductor material, impacting the performance of the organic field-effect transistor, significantly limiting the choice of materials for both the semiconductor and insulating layers.

[0005] On the other hand, in the prior art, deuterium annealing processes are often used to eliminate the defect density and charge density at the interface of the oxide layer of the gate layer. For example, Chinese invention patent CN109300782A discloses a method for manufacturing a semiconductor device, in which a deuterium annealing process is performed on the gate oxide layer to fill the "dangling" bonds in the interface layer using the deuterium annealing process, thereby improving the "dangling" bonds in the interface layer between the substrate and the gate oxide layer. Specifically, the invention uses a laser rapid annealing process + a deuterium annealing process to eliminate the interface effect between the gate oxide layer and the substrate, and the deuterium gas used for annealing is a mixture of nitrogen and deuterium. The principle adopted is to remove the intrinsic oxide layer through laser treatment, prevent the adsorption of organic matter and adverse effects on the subsequent deuterium annealing process, and promote the diffusion of deuterium atoms to the interface layer, thereby ensuring that the subsequent deuterium annealing process has a high and stable deuterium atom diffusion amount; the deuterium annealing process is used to fill the "dangling" bonds in the interface layer. However, the prior art does not disclose the application of the deuterium annealing process in the selection and conversion of insulating layer and semiconductor layer materials.

[0006] For flexible devices, the existing technology usually uses spin coating or printing of polymer materials and then annealing at an appropriate temperature as a dielectric insulating layer. The present invention improves the process based on the existing technology. There is no need to change other operations. Only the annealing process needs to be improved. There is no need to add any steps, which saves costs. Summary of the Invention

[0007] The purpose of the present invention is to provide a top-gate bottom-contact device structure and manufacturing method and an organic field-effect transistor, which utilizes the annealing of the semiconductor layer under high-temperature conditions of deuterium gas to achieve the transformation of the surface of the semiconductor layer into an insulating layer, thereby fundamentally solving the solvent selection problem of the insulating layer and reducing interface traps between the semiconductor layer and the insulating layer, thereby lowering the threshold voltage.

[0008] In order to achieve the above-mentioned object of the invention, the technical solution of the present invention is:

[0009] A top-gate bottom-contact device structure based on a deuterium gas annealing process comprises, from top to bottom, a gate layer, an insulating layer, a semiconductor layer, a source-drain electrode layer, and a base layer, wherein the semiconductor layer is made of an organic polymer, and the degree of unsaturation of the carbon-carbon double bond in the monomer of the organic polymer is ≥8; the insulating layer and the semiconductor layer are an integral structure; the surface layer of the semiconductor is treated by a deuterium gas annealing process, and the organic polymer is converted by addition with deuterium gas to obtain the insulating layer.

[0010] Furthermore, the organic polymer is spin-coated on the surface of the source and drain electrode layer through a spin-coating process to form the semiconductor layer.

[0011] Furthermore, the temperature in the annealing process is 200-600° C. and maintained for 10-30 minutes.

[0012] Furthermore, the monomers of the organic polymer contain groups with carbon-carbon double bonds, including one or more of vinyl groups, styryl groups, and aromatic groups, and the carbon-carbon double bonds form a conjugated chain structure.

[0013] Furthermore, the monomer of the organic polymer is structural formula 1: Among them, R1, R2, R3, and R4 are hydrogen or C1-C20 alkyl groups; R5 is at least one of vinyl, thienyl, dithienyl, dithienyl, terthienyl, phenyl, styryl, and diphenyl.

[0014] Preferably, taking structural formula 2 as an example: structural formula 2 is subjected to an addition reaction by a deuterium gas annealing process to obtain structural formula 3. Wherein, structural formula 2 is Structural formula 3 is That is, the unsaturated carbon of C=C in the structural formula 1 undergoes an addition reaction through the deuterium gas annealing process, and the deuterium atom is added to the carbon atom to form a saturated carbon.

[0015] Preferably, an organic polymer having a carbon-carbon double bond unsaturation degree ≥8 in other monomers is used, and a deuterium gas annealing process is performed to carry out an addition reaction to transform the spin-coated organic layer into an insulating layer.

[0016] Preferably, the organic polymer includes but is not limited to the following structures:

[0017] Structural formula 4: Structural formula: 5:

[0018] Structural formula 6: Structural formula 7:

[0019] Structural formula 8: Structural formula 9:

[0020]

[0021] Structural formula 10: Structural formula 11:

[0022]

[0023] Structural Formula 12:

[0024] Structural formula 13:

[0025] Structural formula 14:

[0026] In the above structural formulas 1-14, n and y are both greater than or equal to 10.

[0027] Obviously, the carbon-carbon double bonds of the above-mentioned monomer structure form a conjugated chain, which improves electron mobility and provides a basis for the two-stage transport of electrons in the drain electrode and source electrode of the organic semiconductor.

[0028] Furthermore, the deuterium annealing process is performed by adding an organic polymer capable of contacting deuterium gas to the surface of the semiconductor layer to obtain the insulating layer. Preferably, the deuterium annealing process conditions include an annealing temperature of 200-600°C for 10-30 minutes. The thickness of the organic polymer applied by the spin coating process is 50-500 nm. The top-gate bottom-contact device structure includes vacuum-evaporating aluminum on the insulating layer to form a gate layer with a thickness of 30-120 nm.

[0029] The above-mentioned top-gate bottom-contact device structure includes, from top to bottom, a gate layer-insulating layer-semiconductor layer-source-drain electrode layer-glass substrate layer. The insulating layer is coated with an organic polymer on the semiconductor layer by a spin coating process, and then subjected to a deuterium gas annealing process to undergo a deuterium gas addition reaction to form an insulating layer. The semiconductor layer and the insulating layer are an integral structure. After the annealing process, the carbon-carbon double bonds of the organic polymer on the surface of the semiconductor layer that is exposed and accessible to deuterium gas are directly subjected to an addition reaction to form an insulating layer. There is no need to spin-coat the insulating layer again, which reduces the process and avoids the problem of solvent selection between the insulating layer and the semiconductor layer. Preferably, the addition reaction of deuterium gas with the carbon-carbon double bond can proceed more rapidly in the presence of a catalyst. The catalyst is preferably a transition metal catalyst, including but not limited to Ni, Pd, Pt, etc.

[0030] On the other hand, in order to achieve the above-mentioned purpose, the present invention also provides another technical solution:

[0031] That is, the manufacturing method of the above-mentioned top-gate bottom-contact device structure includes the following process steps: processing the base layer - forming a source-drain electrode layer on the base layer - spin-coating an organic polymer to form the semiconductor layer - processing the surface of the semiconductor layer through a deuterium gas annealing process to form the insulating layer - forming the gate layer on the insulating layer.

[0032] Furthermore, the process includes the following steps: cleaning the glass substrate - vacuum evaporation of metal chromium - vacuum evaporation of gold - spin coating - deuterium gas annealing process - vacuum evaporation of aluminum;

[0033] The method comprises a spin coating process, wherein the organic polymer is spin-coated on the surface of the exposed glass substrate and the source-drain electrode layer to prepare the semiconductor layer.

[0034] The deuterium gas annealing process is to add an organic polymer capable of contacting deuterium gas to the surface of the semiconductor layer through the deuterium gas annealing process to obtain the insulating layer.

[0035] The vacuum-evaporated metal chromium and the vacuum-evaporated gold form the source-drain electrode layer;

[0036] The gate layer is formed by the vacuum aluminum evaporation process.

[0037] The glass substrate cleaning process includes, in sequence, ammonia cleaning - piranha cleaning solution cleaning - electronic grade acetone cleaning - ultrapure water cleaning - oxygen plasma cleaning.

[0038] Furthermore, a photoresist coating-etching process is also included between the vacuum gold evaporation process and the spin coating process.

[0039] Furthermore, the following process steps are included:

[0040] (1) Cleaning of the glass substrate: cleaning with ammonia at 60°C for 1 hour, piranha solution at 100°C for 1 hour, electronic grade acetone for 1 hour, ultrapure water, drying, and oxygen plasma cleaning.

[0041] (2) Vacuum evaporation of metallic chromium with a thickness of 20 to 100 nm and a pressure of 10 -8 Pa;

[0042] (3) Vacuum evaporation of gold, thickness of 20 to 100 nm, pressure of 10 -8 Pa;

[0043] (4) Apply photoresist at 6000 r / min, then perform exposure and development processes, and wet-etch with etching solution;

[0044] (5) Spin coating, the thickness of the organic polymer spin coating is 50 to 550 nm; the spin-coated organic polymer is coated on the surface after photolithography and etching, and the organic polymer is further defined as having an unsaturation degree of carbon-carbon double bonds in its monomers ≥8.

[0045] (6) Deuterium annealing, 200-600°C, hold for 10-30 minutes; the organic polymer and deuterium gas are added to form an insulating layer with a thickness of 20-500 nm; the organic polymer not added is a semiconductor layer with a thickness of 10-50 nm; further, the process gas is pure deuterium gas with a flow rate of 800 sccm-1000 sccm;

[0046] (7) Vacuum-deposited aluminum with a thickness of 30 to 120 nm.

[0047] The inventive principle of the present invention:

[0048] The semiconducting properties of the organic semiconductor layer are regulated by the material's energy level, which in turn is regulated by the material's structure. The double bond composition and number in the polymer structure greatly affect the material's energy level, further affecting the material's insulating properties. The semiconducting and insulating properties of the material can be mutually converted under certain conditions. On the other hand, the charge in the organic semiconductor is transmitted in a hopping manner, so the presence of traps at the interface between the organic semiconductor and the insulating layer will limit the effective transmission of carriers. However, in the present invention, since the insulating layer and the organic semiconductor are integrated into a single structure, the possibility of traps at the interface between the two is eliminated, which is conducive to the efficient transmission of electrons.

[0049] According to the formula Δn trap =CΔV / q, where Δn trap is the maximum trap density, C is the unit surface capacitance of the insulating layer, q is the elementary charge, and ΔV is the change in threshold voltage. This formula shows that an increase in traps increases the threshold voltage. Clearly, when the insulating layer is formed after surface treatment of the semiconductor layer, resulting in an integrated structure of the insulating and semiconductor layers, the interface traps between the two are greatly reduced, thereby correspondingly lowering the threshold voltage.

[0050] At the same time, the selection of semiconductor materials with conjugated chain structures further enables the carriers in the organic semiconductor to flow smoothly at the semiconductor layer / insulating layer interface without being captured by interface traps.

[0051] Furthermore, the present invention utilizes deuterium gas to perform a deuterium addition reaction on the surface of the semiconductor layer, converting the surface semiconductor layer into an insulating material, thereby fundamentally resolving the problem of selecting the material for the top insulating layer. Specifically, deuterium gas is a stable isotope of hydrogen with a neutron number of 2. Compared to hydrogen, deuterium gas has a shorter depth and greater molecular kinetic energy. Therefore, the use of deuterium gas can effectively control the thickness of the insulating layer to meet the requirements of organic semiconductor devices. At the same time, because the semiconductor layer and the insulating layer are made of the same material, the interface between the insulating layer and the semiconductor layer is relatively smooth, forming an excellent carrier transmission channel.

[0052] Obviously, the organic field-effect transistor prepared by adopting the above technical solution avoids defects at the interface between the semiconductor and the insulating layer, thereby reducing the threshold voltage and improving the performance of the transistor.

[0053] In summary, the present invention adopts the above technical solutions to achieve the following technical effects:

[0054] (1) By adopting the technical solution of the present invention, there is no need to reselect materials and prepare the insulating layer separately. Instead, deuterium gas annealing is performed and deuterium gas is used to perform an addition reaction on the surface of the semiconductor layer to convert the surface semiconductor layer into an insulating material. The insulating layer is directly formed on the surface of the semiconductor layer, which reduces the processing steps of the insulating layer and fundamentally solves the problem of selecting insulating materials and semiconductor materials.

[0055] (2) The technical solution of the present invention is adopted to directly perform surface treatment on the semiconductor layer, thereby overcoming the problem of solvent selection in the preparation process of the insulating layer and the semiconductor layer.

[0056] (3) The technical solution of the present invention is adopted, and the insulating layer is an integrated structure formed by directly processing the surface structure of the semiconductor layer material, which avoids defects between the interface between the semiconductor layer and the insulating layer and greatly reduces the traps between the interfaces of the two, thereby reducing the threshold voltage and improving the performance of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 Schematic diagram of the top-gate bottom-contact device structure in the prior art of the present invention.

[0058] Figure 2 Deuterium addition reaction equation in the embodiment of the present invention.

[0059] Figure 3 Flowchart for preparing a top-gate bottom-contact device structure in an embodiment of the present invention.

[0060] Figure 4 Flow chart of the deuterium annealing process in an embodiment of the present invention.

[0061] Figure 5 Output characteristic curve of the organic field-effect transistor prepared in an embodiment of the present invention.

[0062] Figure 6 Transfer characteristic curve of the organic field effect transistor prepared according to the embodiment of the present invention. DETAILED DESCRIPTION

[0063] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the specific content of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0064] See Figure 1 The top-gate bottom-contact device structure prepared in this embodiment includes, from top to bottom, a gate layer; an insulating layer; a semiconductor layer; a source-drain electrode layer; and a base layer, wherein the insulating layer and the semiconductor layer are an integrated structure.

[0065] Specifically, see Figure 2 The fabrication process for a top-gate bottom-contact device structure includes: treating a semiconductor glass substrate; forming a source / drain electrode layer on the glass substrate; spin-coating an organic semiconductor material onto the source / drain electrode layer and the glass substrate to form an organic semiconductor layer; treating the surface of the organic semiconductor layer through a deuterium annealing process to form an insulating layer; and forming a gate layer on the insulating layer. The organic semiconductor material is an organic polymer. The monomers of the organic polymer have a carbon-carbon double bond with an unsaturation degree of ≥8, and the carbon-carbon double bond is a conjugated chain structure, which can improve electron mobility.

[0066] Preferably, the monomer of the organic polymer is of structural formula 1: Among them, R1, R2, R3, and R4 are hydrogen or C1-C20 alkyl groups; R5 is at least one of vinyl, thienyl, dithienyl, dithienyl, terthienyl, phenyl, styryl, and diphenyl.

[0067] That is, the unsaturated carbon of C=C in the structural formula 1 undergoes an addition reaction through the deuterium gas annealing process, and the deuterium atom is added to the carbon atom to form a saturated carbon.

[0068] After a spin coating process, an organic polymer is coated on the exposed glass substrate and the surface of the source and drain electrode layer to form a semiconductor layer. This layer is then subjected to high-temperature annealing in a deuterium atmosphere, i.e., a deuterium annealing process. Specifically, the semiconductor layer exposed to the deuterium atmosphere is kept at a temperature of 200-600°C for 10-30 minutes. During this process, a high-temperature deuterium addition reaction occurs on the surface of the semiconductor layer that the deuterium gas can contact, and shallow surface penetration occurs, forming an insulating layer with a thickness of 20-500 nm. For the reaction equation, see [ 1 ]. Figure 3 .

[0069] This embodiment takes structural formula 2 as an example.

[0070] After the deuterium annealing process, the structural formula 2 undergoes an addition reaction to obtain the structural formula 3. Structural formula 3 is The carbon-carbon double bond in structural formula 3 reacts with deuterium gas under high temperature conditions to generate a deuterated saturated carbon-carbon structure, while other unsaturated bonds are not affected.

[0071] Preferably, the addition reaction can be carried out in the presence of a catalyst. The catalyst is a transition metal catalyst, preferably, Ni, Pd, Pt, etc. However, for the present invention, in the deuterium annealing process, no additional catalyst is needed. The reason is that the polymerization reaction of the organic polymer coated in the spin coating process has already adopted the above-mentioned transition metal as a catalyst for the polymerization reaction, and, after the polymerization reaction, the transition metal catalyst is contained in the polymer, and the catalyst content therein is sufficient to catalyze the completion of the addition reaction of the carbon-carbon double bond with deuterium gas. Therefore, the present invention can directly carry out the spin coating-deuterium annealing process without the need for additional catalyst addition, thereby reducing the number of operating steps.

[0072] Or see Bis-Diketopyrrolopyrrole Moiety as a Promising Building Block to Enable Balanced Ambipolar Polymers for Flexible Transistors, Jie Yanget.al, Adv.Mater., DOI: 10.1002 / adma.201606162.

[0073] Preferably, the organic polymer includes but is not limited to the following structures:

[0074] Structural formula 4: Structural formula: 5:

[0075] Structural formula 6: Structural formula 7:

[0076] Structural formula 8: Structural formula 9:

[0077]

[0078] Structural formula 10: Structural formula 11:

[0079]

[0080] Structural Formula 12: Structural formula 13: Structural formula 14: In the above structural formulas 1-14, n and y are both greater than or equal to 10.

[0081] This embodiment provides a process for preparing a top-gate bottom-contact device structure. Figure 3 , specifically including the following steps:

[0082] (1) Cleaning the glass substrate to form a glass substrate layer;

[0083] The cleaning steps include:

[0084] a. Wash with 10% ammonia water at 60℃ for 1 hour, then rinse with ultrapure water;

[0085] b. Wash with piranha solution at 100°C for 1 hour, then rinse with ultrapure water;

[0086] c. Wash with electronic grade acetone for 1 hour and then rinse with ultrapure water;

[0087] d. 120℃, 1h drying;

[0088] e. Oxygen plasma cleaning for 30 minutes.

[0089] (2) Source and drain electrode layer: Vacuum evaporation of metallic chromium with a thickness of 20 to 100 nm and a pressure of 10 -8 Pa; vacuum evaporation gold, thickness 20 ~ 100nmnm, pressure 10 -8 Pa, forming the source electrode and drain electrode layers.

[0090] (3) Etching process: Apply photoresist, 6000r / min, then undergo exposure and development process, exposure time is 10s, wet etching with etching solution, partially exposing the metal gold.

[0091] (4) Spin coating process: Spin coating an organic polymer on the surface treated in step (3) to form a spin coating layer, wherein the thickness of the organic polymer in the spin coating layer is 50 to 550 nm; wherein the structure of the organic polymer is represented by structural formula 2.

[0092] (5) Deuterium annealing process: The spin-coated layer of structure 2 is exposed to a deuterium atmosphere at 200-600°C for 10-30 minutes to undergo a deuterium addition reaction. The organic matter after the addition is structure 3, forming an insulating layer. The thickness of the insulating layer is 20-500 nm. The thickness of the unadded organic polymer structure 2 is retained, forming a semiconductor layer. The thickness of the semiconductor layer is 10-50 nm.

[0093] (6) Vacuum-deposit aluminum to a thickness of 30 to 120 nm to form a gate layer.

[0094] At this point, the top-gate bottom-contact device structure is completed. Through the above preparation process, a bottom-contact device having a gate-insulating layer-semiconductor layer-source-drain electrode layer-glass substrate structure from top to bottom is obtained.

[0095] The transfer characteristics and output characteristics of the device prepared by the above steps were measured. Figure 5 and Figure 6 . Migration rate: 0.6cm 2 / (V·s)

[0096] Test Equipment: An Agilent B1500A tester was used to measure the device's operating output and transfer characteristics. The test was conducted in air, without an inert gas atmosphere, demonstrating the device's higher and more stable performance after packaging.

[0097] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A top-gate bottom-contact device structure based on a deuterium annealing process, characterized in that: From top to bottom, it includes a gate layer, an insulating layer, a semiconductor layer, a source-drain electrode layer, and a base layer, wherein the insulating layer and the semiconductor layer are an integrated structure; The semiconductor layer is made of an organic polymer, and the degree of unsaturation of carbon-carbon double bonds in monomers of the organic polymer is ≥8; the surface layer of the semiconductor is treated by a deuterium gas annealing process, and the organic polymer is converted into the insulating layer by addition of deuterium gas; The temperature in the annealing process is 200-600°C and maintained for 10-30 minutes; The monomers of the organic polymer contain groups with carbon-carbon double bonds, including one or more of vinyl groups, styryl groups, and aromatic groups, and the carbon-carbon double bonds form a conjugated chain structure; The monomer of the organic polymer is structural formula 1: Among them, R1, R2, R3, and R4 are hydrogen or C1-C20 alkyl groups; R5 is at least one of vinyl, thienyl, dithienyl, dithienyl, terthienyl, phenyl, styryl, and diphenyl.

2. The method for manufacturing a top-gate bottom-contact device structure according to claim 1, wherein: The process comprises the following steps: treating a base layer - forming a source-drain electrode layer on the base layer - spin coating the organic polymer to form the semiconductor layer - treating the surface of the semiconductor layer by a deuterium gas annealing process to form the insulating layer - forming the gate layer on the insulating layer.

3. The method for manufacturing a top-gate bottom-contact device structure according to claim 2, wherein: The process includes the following steps: cleaning the glass substrate - vacuum evaporation of metal chromium - vacuum evaporation of gold - photolithography - etching - spin coating - deuterium annealing - vacuum evaporation of aluminum; The method comprises a spin coating process, wherein the spin coating process is to spin-coat an organic polymer on the surface of the source-drain electrode layer to prepare the semiconductor layer; The deuterium annealing process is to add an organic polymer capable of contacting deuterium gas to the surface of the semiconductor layer through the deuterium annealing process to obtain the insulating layer; The vacuum-evaporated metal chromium and the vacuum-evaporated gold form the source-drain electrode layer; The gate layer is formed by the vacuum aluminum evaporation process.

4. The method for manufacturing a top-gate bottom-contact device structure according to claim 3, wherein: The glass substrate cleaning process includes, in sequence, ammonia cleaning - piranha cleaning solution cleaning - electronic grade acetone cleaning - ultrapure water cleaning - oxygen plasma cleaning.

5. The method for manufacturing a top-gate bottom-contact device structure according to any one of claims 2 to 4, wherein: The process steps include: (1) Cleaning of the glass substrate: cleaning with ammonia at 60°C for 1 hour, piranha solution at 100°C for 1 hour, electronic grade acetone for 1 hour, ultrapure water, drying, and oxygen plasma cleaning. (2) Vacuum evaporation of metallic chromium with a thickness of 20 to 100 nm and a pressure of 10 -8 Pa; (3) Vacuum evaporation of gold, thickness of 20 to 100 nm, pressure of 10 -8 Pa; (4) Apply photoresist at 6000 r / min, then perform exposure and development processes, and wet-etch with etching solution; (5) Spin coating process, the thickness of the organic polymer spin coating is 50 to 550 nm; (6) Deuterium annealing, 200-600°C, hold for 10-30 min, the organic polymer and deuterium gas add to form an insulating layer with a thickness of 20-500 nm; the organic polymer not added is a semiconductor layer with a thickness of 10-50 nm; (7) Vacuum-deposited aluminum with a thickness of 30 to 120 nm. 6 . An organic field effect transistor, comprising the top-gate bottom-contact device structure according to claim 1 or the top-gate bottom-contact device structure manufactured by the method for manufacturing the top-gate bottom-contact device structure according to any one of claims 2 to 5 .

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