Doherty amplifier and communication device

Abstract

The Doherty amplifier (10) is configured such that a ratio Z3 / Z2 of a characteristic impedance Z3 of a second transmission line (13) to a characteristic impedance Z2 of a first transmission line (12) is a power distribution ratio P2 / P3 of a signal to be amplified by the carrier amplifier (18) and the peak amplifier (19) when both the carrier amplifier (18) and the peak amplifier (19) are saturated, and a resistance value R of the resistor (14) is iso is the following value, which is the input impedance Z of the carrier amplifier (18) when the carrier amplifier (18) is saturated. cin0 The input impedance Z of the peak amplifier (19) when the peak amplifier (19) is saturated pin0 The value obtained by multiplying the sum by a proportionality coefficient w that is less than 1 and greater than 0.

Description

Technical Field

[0001] The present disclosure relates to a Doherty amplifier and a communication device. Background Art

[0002] In the following patent document 1, a Doherty amplifier is disclosed, which includes: an isolation resistance variable distributor, which distributes an input signal into two and outputs the two distributed signals respectively; a carrier amplifier circuit, which amplifies one of the two signals output from the isolation resistance variable distributor; and a peak amplifier circuit, which amplifies the other of the two signals. In addition, the Doherty amplifier includes: a detection circuit, which converts the power of the input signal into a voltage and outputs the voltage as an input power level; and a control circuit, which controls the resistance value of the variable resistor of the isolation resistance variable distributor according to the input power level output from the detection circuit, thereby changing the distribution ratio of the input signal in the isolation resistance variable distributor. Since the Doherty amplifier includes a detection circuit and a control circuit, it is possible to prevent the gain of the amplified signal associated with the distribution loss in the isolation resistance variable distributor from decreasing. That is, the Doherty amplifier can prevent the gain of the composite signal of the signal output from the carrier amplifier circuit and the signal output from the peak amplifier circuit from decreasing during the period from the fallback to the saturation operation.

[0003] Furthermore, the Doherty amplifier includes a delay circuit that delays the input signal by a time required from when the input signal is input to the detection circuit until when the control circuit completes the change of the distribution ratio.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2008-125044 Summary of the invention

[0007] Problem that the invention aims to solve

[0008] The Doherty amplifier disclosed in Patent Document 1 includes a delay circuit for delaying an input signal. Therefore, the Doherty amplifier has a problem that an amplified signal cannot be outputted during the period from when the input signal is input to the delay circuit until the delay time of the delay circuit elapses.

[0009] The present disclosure is completed to solve the above-mentioned problems, and its purpose is to obtain a Doherty amplifier that does not have a delay circuit that delays the signal of the amplification object, and can prevent the gain of the composite signal of the signal output from the carrier amplifier and the signal output from the peak amplifier from decreasing during the period from back-off to saturation operation.

[0010] Means used to solve problems

[0011] The Doherty amplifier disclosed in the present invention comprises: a first transmission line, one end of which is connected to an input terminal for inputting a signal to be amplified; a second transmission line, one end of which is connected to the input terminal; a resistor, which is connected between the other end of the first transmission line and the other end of the second transmission line; a carrier amplifier, which amplifies the signal output from the other end of the first transmission line and outputs the amplified signal to an output synthesis point; and a peak amplifier, which amplifies the signal output from the other end of the second transmission line and outputs the amplified signal to the output synthesis point, wherein the ratio of the characteristic impedance of the second transmission line to the characteristic impedance of the first transmission line is a power distribution ratio of the signal to be amplified to the carrier amplifier and the peak amplifier when both the carrier amplifier and the peak amplifier are saturated, and the resistance value of the resistor is a value obtained by multiplying the sum of the input impedance of the carrier amplifier when the carrier amplifier is saturated and the input impedance of the peak amplifier when the peak amplifier is saturated by a proportionality coefficient less than 1 and greater than 0.

[0012] Effects of the Invention

[0013] According to the present disclosure, the Doherty amplifier is configured such that the ratio of the characteristic impedance of the second transmission line to the characteristic impedance of the first transmission line is the power distribution ratio of the signal to be amplified to the carrier amplifier and the peak amplifier when both the carrier amplifier and the peak amplifier are saturated, and the resistance value of the resistor is the value obtained by multiplying the sum of the input impedance of the carrier amplifier when the carrier amplifier is saturated and the input impedance of the peak amplifier when the peak amplifier is saturated by a proportionality coefficient less than 1 and greater than 0. Therefore, the Doherty amplifier of the present disclosure does not need to include a delay circuit for delaying the signal to be amplified, and can prevent the gain of the composite signal of the signal output from the carrier amplifier and the signal output from the peak amplifier from the fallback to the saturation operation from decreasing. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 1 is a diagram showing the structure of the Doherty amplifier 10 according to the first embodiment.

[0015] Figure 2 2 is a diagram showing the internal structure of the carrier amplifier 18 .

[0016] Figure 3 2 is a diagram showing the internal structure of the peak amplifier 19 .

[0017] Figure 4 It is shown Figure 1 The Smith chart of the input reflection of the peak amplifier 19 during the period from the linear operation to the saturation operation of the Doherty amplifier is shown.

[0018] Figure 5 It is shown Figure 1 The Smith chart of the input reflection of the peak amplifier 19 during the period from the linear operation to the saturation operation of the Doherty amplifier is shown.

[0019] Figure 6 1 is a structural diagram showing the details of the Wilkinson distributor 11 .

[0020] Figure 7 is a graph showing the reflection coefficient Γ when the peak amplifier 19 is viewed from the output terminal 11b of the Wilkinson divider 11. pin An illustration of the normalized power allocation ratio when the proportional coefficient w is changed from 0.2 to 1.8 in steps of 0.2 when the phase is 180 degrees.

[0021] Figure 8 It shows that when the proportional coefficient w is 0.4, the reflection coefficient Γ of the second signal pin An illustration of the normalized power split ratio when the phase changes from 0 degrees to 180 degrees in steps of 22.5 degrees.

[0022] Fig. 9 is the reflection coefficient Γ for achieving ideal operation. pin An explanatory diagram of the gain of the output power of the Doherty amplifier 10 when the phase condition is , and the proportionality coefficient w is less than 1 and greater than 0.

[0023] Fig.10 1 is a diagram showing the configuration of the Wilkinson divider 11 of the Doherty amplifier 10 according to the second embodiment.

[0024] Fig.11 It shows that Figure 1 The structure of the communication device of the Doherty amplifier 10 is shown. DETAILED DESCRIPTION

[0025] Hereinafter, in order to explain the present disclosure in more detail, the mode for implementing the present disclosure will be described with reference to the drawings.

[0026] Implementation method 1.

[0027] Figure 1 1 is a diagram showing the structure of the Doherty amplifier 10 according to the first embodiment.

[0028] exist Figure 1 In FIG. 1 , the input terminal 1 is a terminal for inputting a signal to be amplified from outside the Doherty amplifier 10 .

[0029] The load 2 is an external load of the Doherty amplifier 10. One end of the load 2 is connected to the other end of an output matching circuit 22 of the Doherty amplifier 10, which will be described later, and the other end of the load 2 is grounded.

[0030] The Doherty amplifier 10 amplifies a signal input from an input terminal 1, and outputs the amplified signal to a load 2. The power of the signal input from the input terminal 1 is P1.

[0031] The Wilkinson divider 11 includes a first transmission line 12 , a second transmission line 13 , and a resistor 14 .

[0032] The Wilkinson divider 11 divides the power P1 of the signal input from the input terminal 1 into two. The Wilkinson divider 11 outputs the first signal as one signal after the division from the output terminal 11a to the phase adjustment circuit 15 described later, and outputs the second signal as the other signal after the division from the output terminal 11b to the coefficient adjustment circuit 16 described later.

[0033] One end of the first transmission line 12 is connected to the input terminal 11 , and the other end of the first transmission line 12 is connected to one end of the resistor 14 and the output terminal 11 a , respectively.

[0034] The first transmission line 12 has an electrical length of one-quarter wavelength (hereinafter referred to as "λ / 4") at the frequency of the signal input from the input terminal 1. The electrical length of λ / 4 is an electrical length of 90 degrees. The characteristic impedance of the first transmission line 12 is Z2.

[0035] One end of the second transmission line 13 is connected to the input terminal 11 , and the other end of the second transmission line 13 is connected to the other end of the resistor 14 and the output terminal 11 b , respectively.

[0036] The second transmission line 13 has an electrical length of λ / 4 at the frequency of the signal input from the input terminal 1. The characteristic impedance of the second transmission line 13 is Z3.

[0037] The ratio Z3 / Z2 of the characteristic impedance Z3 of the second transmission line 13 to the characteristic impedance Z2 of the first transmission line 12 is the power allocation ratio P2 / P3 of the signal to be amplified with respect to the carrier amplifier 18 and the peak amplifier 19 when both the carrier amplifier 18 and the peak amplifier 19 are saturated. P2 is the power of the signal output from the output terminal 11a when the carrier amplifier 18 is saturated. P3 is the power of the signal output from the output terminal 11b when the peak amplifier 19 is saturated.

[0038] The resistor 14 is connected between the other end of the first transmission line 12 and the other end of the second transmission line 13 .

[0039] The resistance value of resistor 14 is R iso is the input impedance Z of the carrier amplifier 18 when the carrier amplifier 18 is saturated. cin0 The input impedance Z of the peak amplifier 19 when the peak amplifier 19 is saturated pin0 The value obtained by multiplying the sum by a proportionality coefficient w that is less than 1 and greater than 0.

[0040] The following is the input impedance Z of the carrier amplifier 18 when the carrier amplifier 18 is saturated. cin0 Sometimes it is referred to as the input impedance of the carrier amplifier 18 when it is saturated. In addition, the input impedance Z of the peak amplifier 19 when the peak amplifier 19 is saturated is pin0 This is sometimes referred to as the input impedance of the peak amplifier 19 when operating in saturation.

[0041] The saturation operation of the carrier amplifier 18 is a time point when the amplification operation of the carrier amplifier 18 for the first signal is saturated, and the saturation operation of the peak amplifier 19 is a time point when the amplification operation of the peak amplifier 19 for the second signal is saturated.

[0042] One end of the phase adjustment line 15 is connected to the other end of the first transmission line 12 and one end of the resistor 14 via the output terminal 11a, respectively, and the other end of the phase adjustment line 15 is connected to the input side of the carrier amplifier 18. The phase adjustment line 15 has the same electrical length as the coefficient adjustment line 16. The same electrical length here is not limited to the case where the electrical lengths are identical in a strict sense, and also includes the case where the electrical lengths are different within the range where there is no problem in practical use.

[0043] The characteristic impedance of the phase adjustment circuit 15 and the input impedance Z of the carrier amplifier 18 cin0 The same here is not limited to the characteristic impedance of the phase adjustment circuit 15 and the input impedance Z of the carrier amplifier 18. cin0 Although the two are identical in a strict sense, they also include different ones within the range that there is no practical problem.

[0044] One end of the coefficient adjustment line 16 is connected to the other end of the second transmission line 13 and the other end of the resistor 14 via the output terminal 11b, and the other end of the coefficient adjustment line 16 is connected to one end of the phase adjustment line 17 described later. The coefficient adjustment line 16 is used to adjust the reflection coefficient Γ of the second signal in the peak amplifier 19 when the peak amplifier 19 is viewed from the other end of the second transmission line 13. pin line.

[0045] One end of the phase adjustment line 17 is connected to the other end of the coefficient adjustment line 16, and the other end of the phase adjustment line 17 is connected to the input side of the peak amplifier 19. The phase adjustment line 17 has an electrical length of λ / 4 at the frequency of the signal input from the input terminal 1.

[0046] The characteristic impedance of the coefficient adjustment circuit 16 and the characteristic impedance of the phase adjustment circuit 17 are respectively equal to the input impedance Z of the peak amplifier 19 when in saturation operation. pin0 The same as mentioned above is not limited to the case where the impedances are identical in a strict sense, but also includes the case where the impedances are different within the range where there is no practical problem.

[0047] By inserting the phase adjustment circuit 17 between the coefficient adjustment circuit 16 and the peak amplifier 19 , the phase difference between the path from the carrier amplifier 18 to the output synthesis point 21 described later and the path from the peak amplifier 19 to the output synthesis point 21 is compensated.

[0048] The input side of the carrier amplifier 18 is connected to the other end of the phase adjustment line 15, and the output side of the carrier amplifier 18 is connected to one end of a quarter wavelength line 20 described later. The carrier amplifier 18 amplifies the first signal output from the other end of the first transmission line 12 and then passing through the phase adjustment line 15, and outputs the amplified first signal to the output combining point 21 via the quarter wavelength line 20.

[0049] The carrier amplifier 18 is biased to class AB, so the input impedance Z of the carrier amplifier 18 is cin0 There is no change during the period from the linear operation to the saturation operation. The linear operation is the time point when the carrier amplifier 18 starts amplifying the first signal. During the linear operation, the peak amplifier 19 has not started amplifying the second signal.

[0050] exist Figure 1 In the Doherty amplifier 10 shown, the saturation operation of the carrier amplifier 18 occurs simultaneously with the saturation operation of the peak amplifier 19. The simultaneous operation here is not limited to the case where the saturation operation occurs at the same time in a strict sense, but also includes the case where the saturation operation is different within the range that there is no practical problem.

[0051] There is a back-off period between the linear operation period and the saturation operation period. The back-off period is a time point when the peak amplifier 19 amplifies the second signal abruptly.

[0052] Figure 2 2 is a diagram showing the internal structure of the carrier amplifier 18 .

[0053] like Figure 2As shown, the carrier amplifier 18 includes, in addition to the transistor 18 a for amplifying the first signal, an input matching circuit 18 b connected to the input side of the transistor 18 a and an output matching circuit 18 c connected to the output side of the transistor 18 a .

[0054] In addition, if Figure 2 As shown, the carrier amplifier 18 further includes a stabilization circuit 18d that blocks the passage of frequency components other than the desired frequency component included in the first signal and allows the desired frequency component to pass.

[0055] The stabilization circuit 18d is connected between the phase adjustment circuit 15 and the input matching circuit 18b, and is implemented by, for example, a low-pass filter, a band-pass filter, or a high-pass filter.

[0056] In addition, Figure 2 In the embodiment, the stabilizing circuit 18d is connected between the phase adjustment line 15 and the input matching circuit 18b. However, this is just an example, and the stabilizing circuit 18d may be connected between the input matching circuit 18b and the transistor 18a, between the transistor 18a and the output matching circuit 18c, or between the output matching circuit 18c and the quarter wavelength line 20.

[0057] The input side of the peak amplifier 19 is connected to the other end of the phase adjustment line 17, and the output side of the peak amplifier 19 is connected to the output synthesis point 21. The peak amplifier 19 amplifies the second signal output from the other end of the second transmission line 13 and then passing through the coefficient adjustment line 16 and the phase adjustment line 17, and outputs the amplified second signal to the output synthesis point 21.

[0058] The peak amplifier 19 is biased to class C, so the input impedance of the peak amplifier 19 is Z pin0 It changes greatly during the period from linear operation to saturation operation.

[0059] Figure 3 2 is a diagram showing the internal structure of the peak amplifier 19 .

[0060] like Figure 3 As shown, the peak amplifier 19 includes, in addition to the transistor 19 a for amplifying the second signal, an input matching circuit 19 b connected to the input side of the transistor 19 a and an output matching circuit 19 c connected to the output side of the transistor 19 a .

[0061] In addition, if Figure 3 As shown, the peak amplifier 19 includes a stabilization circuit 19d that blocks the passage of frequency components other than the desired frequency component included in the second signal and allows the desired frequency component to pass.

[0062] The stabilization circuit 19d is connected between the phase adjustment circuit 17 and the input matching circuit 19b, and is implemented by, for example, a low-pass filter, a band-pass filter, or a high-pass filter.

[0063] In addition, Figure 2 In the embodiment, the stabilizing circuit 19d is connected between the phase adjustment line 17 and the input matching circuit 19b. However, this is just an example, and the stabilizing circuit 19d may be connected between the input matching circuit 19b and the transistor 19a, between the transistor 19a and the output matching circuit 19c, or between the output matching circuit 19c and the output combining point 21.

[0064] One end of the 1 / 4 wavelength line 20 is connected to the output side of the carrier amplifier 18, and the other end of the 1 / 4 wavelength line 20 is connected to the output combining point 21. The 1 / 4 wavelength line 20 has an electrical length of λ / 4 at the frequency of the signal input from the input terminal 1. The 1 / 4 wavelength line 20 is connected between the carrier amplifier 18 and the output combining point 21 in order to modulate the impedance during back-off.

[0065] The output side of the peak amplifier 19 and the other end of the quarter wavelength line 20 are connected to the output combining point 21. The amplified first signal output from the carrier amplifier 18 and then passing through the quarter wavelength line 20 and the amplified second signal output from the peak amplifier 19 are combined at the output combining point 21 with the same phase.

[0066] One end of the output matching circuit 22 is connected to the output combining point 21 , and the other end of the output matching circuit 22 is connected to the load 2 . The output matching circuit 22 is provided to match the impedance of the output side of the Doherty amplifier 10 with the impedance of the load 2 .

[0067] The carrier amplifier 18 is biased to class AB, so the input impedance Z of the carrier amplifier 18 is cin0 The characteristic impedance of the phase adjustment circuit 15 does not change during the period from linear operation to saturation operation. The characteristic impedance of the phase adjustment circuit 15 is equal to the input impedance Z of the carrier amplifier 18 during the period from linear operation to saturation operation. cin0 same.

[0068] Therefore, the absolute value of the input reflection when the carrier amplifier 18 is viewed from the output terminal 11 a of the Wilkinson divider 11 is 0 during the period from the linear operation to the saturation operation of the carrier amplifier 18 .

[0069] The characteristic impedance of the coefficient adjustment circuit 16 and the characteristic impedance of the phase adjustment circuit 17 are respectively equal to the input impedance Z of the peak amplifier 19 when in saturation operation. pin0 same.

[0070] The peak amplifier 19 is different from the carrier amplifier 18 and is biased to class C. Therefore, the input impedance Z of the peak amplifier 19 is pin0 It changes greatly during the period from linear operation to saturation operation.

[0071] Therefore, except when the peak amplifier 19 is in saturation operation, the characteristic impedance of the coefficient adjustment circuit 16 and the characteristic impedance of the phase adjustment circuit 17 are respectively equal to the input impedance Z of the peak amplifier 19. pin0 different.

[0072] Figure 4 It is shown Figure 1 The Smith chart of the input reflection of the peak amplifier 19 during the period from the linear operation to the saturation operation of the Doherty amplifier 10 is shown. Figure 4 The input reflection of the peak amplifier 19 shown is the input reflection when the peak amplifier 19 is viewed from the input side of the coefficient adjustment line 16 .

[0073] Figure 4 The impedance at the center of the Smith chart is the input impedance Z when the peak amplifier 19 operates in saturation. pin0 . Figure 4 The impedance at the center of the Smith chart shown is the input impedance Z when the peak amplifier 19 is in saturation operation. pin0 It is standardized and therefore recorded as 1.0.

[0074] When the peak amplifier 19 operates in saturation mode, Figure 4 As shown, the absolute value of the input reflection of the peak amplifier 19 is zero.

[0075] When the peak amplifier 19 operates in a linear manner, as shown in FIG. Figure 4 As shown, the absolute value of the input reflection of the peak amplifier 19 is not 0, but a value close to 1.

[0076] Figure 5 It is shown Figure 1 The Smith chart of the input reflection of the peak amplifier 19 during the period from the linear operation to the saturation operation of the Doherty amplifier 10 is shown.

[0077] exist Figure 5 , the input reflection of the peak amplifier 19 when the electrical length of the coefficient adjustment line 16 is 0 degrees, 30 degrees, 60 degrees, 90 degrees, 120 degrees, and 150 degrees are shown. The input reflection of the peak amplifier 19 when the electrical length of the coefficient adjustment line 16 is 0 degrees and Figure 4 The input reflections of the peaking amplifier 19 are shown to be the same.

[0078] Even if the electrical length of the coefficient adjustment line 16 changes, the characteristic impedance of the coefficient adjustment line 16 and the characteristic impedance of the phase adjustment line 17 are respectively equal to the input impedance Z of the peak amplifier 19 in saturation operation. pin0 Therefore, when the electrical length of the coefficient adjustment line 16 changes, the phase of the input reflection during the linear operation of the peak amplifier 19 changes.

[0079] Therefore, the input reflection of the peak amplifier 19 when the peak amplifier 19 is observed from the input side of the coefficient adjustment circuit 16 is as follows: Figure 5 As shown, the electrical length of line 16 is adjusted according to the factor to rotate on the Smith chart.

[0080] In addition, the phase of the input reflection of the peak amplifier 19 changes depending on the type of the transistor 19 a included in the peak amplifier 19 or the type of each of the input matching circuit 19 b and the output matching circuit 19 c .

[0081] Exists to achieve Figure 1 The range of input reflection phases for ideal operation of the Doherty amplifier 10 is shown.

[0082] An ideal job is one that meets the following two conditions.

[0083] Condition (1)

[0084] After the carrier amplifier 18 starts the signal amplification operation earlier than the peak amplifier 19 , the peak amplifier 19 suddenly starts the signal amplification operation from the fallback operation time between the linear operation time and the saturation operation time.

[0085] Condition (2)

[0086] The saturation operation of the carrier amplifier 18 and the saturation operation of the peak amplifier 19 occur simultaneously.

[0087] Figure 5 The input reflection phase range 30 shown is to achieve Figure 1 The range of the input reflection phase when viewing the peak amplifier 19 from the output terminal 11b of the Wilkinson divider 11 required for the ideal operation of the Doherty amplifier 10 shown is within Figure 1 The Doherty amplifier 10 shown is designed with known values.

[0088] exist Figure 5 In the example, from Figure 1 The range 30 of the input reflection phase of the output terminal 11 b when viewing the peak amplifier 19 is shown to be in the range of 135 degrees to 220 degrees.

[0089] exist Figure 5In the example, when the phase of the input reflection of the peak amplifier 19 is 120 degrees, the phase of the input reflection of the peak amplifier 19 is included in the range 30 of the input reflection phase of the Doherty amplifier 10.

[0090] exist Figure 1 In the Doherty amplifier 10 shown, in order to satisfy condition (1), the electrical length of the coefficient adjustment line 16 is set when designing the Doherty amplifier 10 so that the phase of the input reflection of the peak amplifier 19 is included in the range 30 of the input reflection phase.

[0091] In addition, Figure 1 In the Doherty amplifier 10 shown in the figure, in order to satisfy both conditions (1) and (2), the resistance value R of the resistor 14 is iso The value is the input impedance Z when the carrier amplifier 18 is in saturation operation. cin0 When the peak amplifier 19 works in saturation, the input impedance Z pin0 The value obtained by multiplying the sum by a proportionality coefficient w that is less than 1 and greater than 0.

[0092] Next, Figure 1 The operation of the Doherty amplifier 10 is illustrated.

[0093] When a signal to be amplified is input from the input terminal 1 , the Wilkinson divider 11 divides the power P1 of the input signal into two.

[0094] The Wilkinson divider 11 outputs the first signal as one of the divided signals from the output terminal 11 a to the carrier amplifier 18 via the phase adjustment line 15 .

[0095] Furthermore, the Wilkinson divider 11 outputs the second signal as the other signal after the distribution from the output terminal 11 b to the peak amplifier 19 via the coefficient adjustment line 16 and the phase adjustment line 17 .

[0096] The detailed operation of the Wilkinson divider 11 will be described later.

[0097] The carrier amplifier 18 amplifies the first signal output from the output terminal 11 a of the Wilkinson divider 11 and then passed through the phase adjustment line 15 .

[0098] The carrier amplifier 18 outputs the amplified first signal to an output combining point 21 via a quarter wavelength line 20 .

[0099] The peak amplifier 19 amplifies the second signal output from the output terminal 11 b of the Wilkinson divider 11 and then passing through the coefficient adjustment circuit 16 and the phase adjustment circuit 17 .

[0100] The peak amplifier 19 amplifies the second signal and outputs the amplified second signal to the output combining point 21 .

[0101] At the output combining point 21 , the amplified first signal output from the carrier amplifier 18 and then passing through the quarter wavelength line 20 and the amplified second signal output from the peak amplifier 19 are combined in the same phase.

[0102] The synthesized signal at the output synthesis point 21 (hereinafter referred to as “synthesized signal”) is output to the load 2 via the output matching circuit 22 .

[0103] Next, the operation of the Wilkinson divider 11 will be described in detail.

[0104] Figure 6 2 is a structural diagram showing the details of the Wilkinson divider 11 .

[0105] exist Figure 6 In FIG. 1 , I1 is the current of the signal input from the input terminal 1 , and V1 is the voltage of the signal input from the input terminal 1 .

[0106] Z in yes Figure 1 The input impedance of the Doherty amplifier 10 is shown as Γ in It is a reflection coefficient of an input signal in the Doherty amplifier 10 when the inside of the Doherty amplifier 10 is viewed from the input terminal 1 .

[0107] I2 (−λ / 4) is the current of the signal input to the first transmission line 12 , and V2 (−λ / 4) is the voltage of the signal input to the first transmission line 12 .

[0108] I2 ( 0 ) is the current of the signal output from the first transmission line 12 , and V2 ( 0 ) is the voltage of the signal output from the first transmission line 12 .

[0109] I3 (−λ / 4) is the current of the signal input to the second transmission line 13 , and V3 (−λ / 4) is the voltage of the signal input to the second transmission line 13 .

[0110] I3 ( 0 ) is the current of the signal output from the second transmission line 13 , and V3 ( 0 ) is the voltage of the signal output from the second transmission line 13 .

[0111] I iso is the current flowing in resistor 14, I2(0)-I iso is the current of the signal output from the output terminal 11a to the phase adjustment line 15, I3(0)+I iso This is the current of the signal output from the output terminal 11b to the coefficient adjustment line 16.

[0112] Z cin is the impedance of the carrier amplifier 18 viewed from the output terminal 11a, Γ cin It is a reflection coefficient of the first signal in the carrier amplifier 18 when the carrier amplifier 18 is viewed from the output terminal 11 a .

[0113] Z pin is the impedance when the peak amplifier 19 is viewed from the output terminal 11b, Γ pin It is the reflection coefficient of the second signal in the peak amplifier 19 when the peak amplifier 19 is viewed from the output terminal 11 b .

[0114] The impedance Z when the carrier amplifier 18 is viewed from the output terminal 11a cin , the input impedance Z of the carrier amplifier 18 when it is saturated cin0 and the reflection coefficient Γ of the first signal cin The relationship between is expressed as the following formula (1).

[0115]

[0116] The impedance Z when the peak amplifier 19 is viewed from the output terminal 11b pin , the input impedance Z of the peak amplifier 19 when it is saturated pin0 and the reflection coefficient Γ of the second signal pin The relationship between is expressed as the following formula (2).

[0117]

[0118] The input impedance Z of the carrier amplifier 18 is cin0 The input reflection coefficient of the carrier amplifier 18 does not change during the period from linear operation to saturation operation, so the input reflection coefficient of the carrier amplifier 18 is always Γ cin =0.

[0119] The input impedance Z of the peak amplifier 19 pin0 The operation changes from the linear operation to the saturation operation, so the reflection coefficient Γ of the second signal in the peak amplifier 19 is pin like Figure 5 As shown, the electrical length of the line 16 changes according to the coefficient adjustment.

[0120] The following describes the operation of the Wilkinson divider 11 when both the carrier amplifier 18 and the peak amplifier 19 are saturated, and the operation of the Wilkinson divider 11 during a period from a linear operation to a saturated operation.

[0121] [Operation of Wilkinson Divider 11 When Both Carrier Amplifier 18 and Peak Amplifier 19 Are Saturated]

[0122] When both the carrier amplifier 18 and the peak amplifier 19 are saturated, the power distribution ratio P2 / P3 of the signal in the Wilkinson divider 11 is equal to the desired power distribution ratio 1 / K. 2 The power distribution ratio P2 / P3 is a power distribution ratio P2 / P3 between the power P2 of the first signal output from the output terminal 11a toward the carrier amplifier 18 and the power P3 of the second signal output from the output terminal 11b toward the peak amplifier 19.

[0123] When both the carrier amplifier 18 and the peak amplifier 19 are saturated, the ratio Z3 / Z2 of the characteristic impedance Z3 of the second transmission line 13 to the characteristic impedance Z2 of the first transmission line 12 and the input impedance Z pin0 The input impedance Z of the carrier amplifier 18 cin0 Ratio Z pin0 / Z cin0 , and the power allocation ratio P2 / P3 is expressed as the following formula (3).

[0124]

[0125] exist Figure 1 When the Doherty amplifier 10 is designed as shown, the input impedance Z of the Doherty amplifier 10 is in The input impedance Z of the carrier amplifier 18 when operating in saturation cin0 is a known value.

[0126] Therefore, the characteristic impedance Z2 of the first transmission line 12 can be obtained by in and input impedance Z cin0 Substitute it into the following formula (4) and find it.

[0127]

[0128] The characteristic impedance Z3 of the second transmission line 13 can be obtained by substituting the characteristic impedance Z2 of the first transmission line 12 into the following equation (5).

[0129]

[0130] If the resistance value of resistor 14 is R iso As shown in the following formula (6), with the input impedance Z cin0 and input impedance Z pin0 If the sum of the currents and the currents are consistent, no current flows through the resistor 14, and therefore the output terminal 11a and the output terminal 11b are isolated from each other.

[0131]

[0132] If the resistance value of resistor 14 is R iso As shown in the following formula (7), the resistance value R shown in formula (6) is iso A current flows through the resistor 14 by multiplying the value obtained by the proportionality coefficient w which is less than 1 and greater than 0. When the current flows through the resistor 14, Figure 1 When the operation of the Doherty amplifier 10 shown is other than the saturation operation, the power distribution ratio P2 / P3 changes. However, when both the carrier amplifier 18 and the peak amplifier 19 are saturated, even if the current flows through the resistor 14, the power distribution ratio P2 / P3 does not change, but is the same as the desired power distribution ratio 1 / K. 2 Consistent.

[0133]

[0134] [Operation of Wilkinson Divider 11 from Linear Operation to Saturation Operation]

[0135] The power distribution ratio P2 / P3 during the period from the linear operation to the saturation operation of the Doherty amplifier 10 is expressed as in the following equation (8).

[0136]

[0137]

[0138] The power distribution ratio P2 / P3 during the period from the linear operation to the saturation operation of the Doherty amplifier 10 changes according to the proportionality coefficient w as shown in equation (8).

[0139] Figure 7 is a graph showing the reflection coefficient Γ when the peak amplifier 19 is viewed from the output terminal 11b of the Wilkinson divider 11. pin An illustration of the normalized power allocation ratio when the proportional coefficient w is changed from 0.2 to 1.8 in steps of 0.2 when the phase is 180 degrees.

[0140] exist Figure 7 In FIG. 1 , the horizontal axis is the absolute value of the input reflection of the peak amplifier 19. When the absolute value of the input reflection is 0, the peak amplifier 19 is saturated. When the peak amplifier 19 operates linearly, the absolute value of the input reflection is a value close to 1.

[0141] The vertical axis is the normalized power split ratio when the Doherty amplifier 10 operates from linear operation to saturation operation. The normalized power split ratio is calculated by 1 / K 2 The power distribution ratio P2 / P3 is normalized. Therefore, when the normalized power distribution ratio is 1, the power distribution ratio P2 / P3 is 1 / K 2 .

[0142] Even if the proportionality factor w varies within the range of 0.2 to 1.8, when the peak amplifier 19 is saturated, Figure 7 As shown, the standardized power distribution ratio is 1, and the power distribution ratio P2 / P3 is 1 / K 2 .

[0143] When the absolute value of the input reflection of the peak amplifier 19 is greater than 0 and the peak amplifier 19 is not operating in saturation, the normalized power distribution is as follows: Figure 7 As shown, it changes according to the proportionality factor w.

[0144] When the proportionality factor w is greater than 1, Figure 7 As shown, regardless of the absolute value of the input reflection of the peak amplifier 19, the normalized power allocation ratio is always greater than 1, and more power is allocated to the carrier amplifier 18 than to the peak amplifier 19 during the period from linear operation to saturation operation of the Doherty amplifier 10.

[0145] Therefore, when the proportionality factor w is greater than 1, it is difficult to suddenly start the operation of the peak amplifier 19 during backoff. Therefore, the carrier amplifier 18 may saturate before the peak amplifier 19, making it difficult to achieve an ideal operation in which the carrier amplifier 18 and the peak amplifier 19 are saturated simultaneously.

[0146] When the proportionality factor w is less than 1, such as Figure 7 As shown, there is an absolute value of the input reflection of the peak amplifier 19 where the normalized power division ratio is less than 1.

[0147] For example, when the proportionality factor w is 0.4, Figure 7 As shown, in the range where the absolute value of the input reflection of the peak amplifier 19 is greater than 0 and less than about 0.72, the normalized power division ratio is less than 1.

[0148] When the proportionality coefficient w is 0.4, when the absolute value of the input reflection of the peak amplifier 19 is less than 1 and greater than about 0.72, more power is allocated to the carrier amplifier 18 than to the peak amplifier 19. That is, during the period from the linear operation to the fallback of the Doherty amplifier 10, more power is allocated to the carrier amplifier 18 than to the peak amplifier 19.

[0149] Furthermore, when the absolute value of the input reflection of the peak amplifier 19 is in the range of less than about 0.72 and greater than 0, more power is allocated to the peak amplifier 19 than to the carrier amplifier 18. That is, more power is allocated to the peak amplifier 19 than to the carrier amplifier 18 during the period from the back-off time to the saturation time of the operation of the Doherty amplifier 10.

[0150] Therefore, the carrier amplifier 18 can start the signal amplification operation earlier than the peak amplifier 19, and then the peak amplifier 19 can start the signal amplification operation rapidly. In addition, when the absolute value of the input reflection of the peak amplifier 19 is 0 and the peak amplifier 19 is saturated, the power distribution ratio P2 / P3 becomes the desired power distribution ratio 1 / K. 2 That is, when the absolute value of the input reflection of the peak amplifier 19 is 0, both the carrier amplifier 18 and the peak amplifier 19 are saturated.

[0151] Figure 8 It shows that when the proportional coefficient w is 0.4, the reflection coefficient Γ of the second signal pin An illustration of the normalized power split ratio when the phase changes from 0 degrees to 180 degrees in steps of 22.5 degrees.

[0152] exist Figure 8 In FIG. 1 , the horizontal axis is the absolute value of the input reflection of the peak amplifier 19, and the vertical axis is the normalized power distribution ratio of the Doherty amplifier 10 in the range from linear operation to saturation operation. The normalized power distribution ratio is calculated by 1 / K 2 Obtained by normalizing the power distribution ratio P2 / P3.

[0153] exist Figure 8 In the example, when the reflection coefficient of the second signal is Γ pin When the phase is in the range of 135 degrees to 180 degrees, there is an absolute value of the input reflection of the peak amplifier 19 where the normalized power division ratio is less than 1.

[0154] However, in Figure 8 In the example, when the reflection coefficient of the second signal is Γ pin When the phase is in the range of 0 degrees to 90 degrees, there is no absolute value of the input reflection of the peak amplifier 19 whose normalized power division ratio is less than 1.

[0155] In addition, the equation (8) representing the power distribution ratio P2 / P3 from the linear operation to the fallback is the reflection coefficient Γ of the second signal pin The phase of is an even function, so even at the reflection coefficient Γ pin When the phase is in the range of 180 degrees to 225 degrees, there is also an absolute value of the input reflection of the peak amplifier 19 where the normalized power division ratio is less than 1.

[0156] However, when the reflection coefficient of the second signal Γ pin When the phase is in the range of 270 degrees to 360 degrees, there is no absolute value of the input reflection of the peak amplifier 19 whose normalized power division ratio is less than 1.

[0157] According to the above, there is a reflection coefficient Γ that can achieve the ideal operation of the Doherty amplifier 10 pin phase condition.

[0158] Fig. 9 is the reflection coefficient Γ for achieving ideal operation. pin An explanatory diagram of the gain of the output power in the Doherty amplifier 10 under the phase condition of and with the proportionality coefficient w being less than 1 and greater than 0.

[0159] In the Doherty amplifier described in Patent Document 1, the peak amplifier cannot rapidly start amplifying the signal during back-off, so the gain rapidly decreases during the period from back-off to saturation operation, and the gain characteristic becomes nonlinear.

[0160] exist Figure 1 In the Doherty amplifier 10 shown in FIG. 1 , the peak amplifier 19 can abruptly start the amplification operation of the signal during the back-off period, thereby ensuring the flatness of the gain during the period from the back-off period to the saturation operation period. Figure 1 In the Doherty amplifier 10 shown, the carrier amplifier 18 and the peak amplifier 19 can be saturated simultaneously, so that the saturated output power is increased compared with the Doherty amplifier described in Patent Document 1.

[0161] The Doherty amplifier described in Patent Document 1 includes a delay circuit to prevent a problem in which two divided signals are output from the isolation resistance variable divider before the control circuit completes the change of the division ratio, thereby reducing the gain of the combined signal.

[0162] Figure 1 The Doherty amplifier 10 shown prevents the gain of the synthesized signal from decreasing without the control circuit described in Patent Document 1, and does not need to include the delay circuit described in Patent Document 1. Figure 1 The Doherty amplifier 10 shown does not cause a problem in which an amplified signal cannot be output during the period from when an input signal is input to the delay circuit until the delay time of the delay circuit elapses.

[0163] in addition, Figure 1 The Doherty amplifier 10 shown does not include the detection circuit, control circuit, and delay circuit described in Patent Document 1, and can therefore be downsized and simplified compared to the Doherty amplifier described in Patent Document 1, and can also reduce power consumption.

[0164] In the above-mentioned first embodiment, the Doherty amplifier 10 is configured such that the ratio Z3 / Z2 of the characteristic impedance Z3 of the second transmission line 13 to the characteristic impedance Z2 of the first transmission line 12 is the power distribution ratio P2 / P3 of the signal of the amplification object to the carrier amplifier 18 and the peak amplifier 19 when both the carrier amplifier 18 and the peak amplifier 19 are saturated, and the resistance value R of the resistor 14 is iso is the input impedance Z of the carrier amplifier 18 when the carrier amplifier 18 is saturated. cin0 The input impedance Z of the peak amplifier 19 when the peak amplifier 19 is saturated pin0 The value obtained by multiplying the sum of the signals by a proportionality coefficient w that is less than 1 and greater than 0. Therefore, the Doherty amplifier 10 can prevent a decrease in the gain of a composite signal of a signal output from the carrier amplifier 18 and a signal output from the peak amplifier 19 during the period from the back-off time to the saturation operation without having to include a delay circuit that delays the signal to be amplified.

[0165] Implementation method 2.

[0166] In the second embodiment, a Doherty amplifier 10 in which a Wilkinson divider 11 includes capacitors 41 and 42 connected in series with a resistor 40 will be described.

[0167] Fig.10 1 is a diagram showing the structure of the Wilkinson divider 11 of the Doherty amplifier 10 of the second embodiment. Fig.10 In, with Figure 1 The same reference numerals denote the same or corresponding parts, and thus their descriptions are omitted.

[0168] The resistor 40 has a resistance value of R iso In addition to the resistance 40a, it also has a parasitic inductance 40b.

[0169] One end of the capacitor 41 is connected to the other end of the first transmission line 12 and the output terminal 11 a , respectively, and the other end of the capacitor 41 is connected to one end of the resistor 40 .

[0170] One end of the capacitor 42 is connected to the other end of the second transmission line 13 and the output terminal 11 b , respectively, and the other end of the capacitor 42 is connected to the other end of the resistor 40 .

[0171] The capacitor 41 and the capacitor 42 are provided to compensate for phase rotations in the first signal and the second signal caused by the parasitic inductance 40 b of the resistor 40 .

[0172] Since the Wilkinson divider 11 has capacitors 41 and 42 connected in series with the resistor 40, even if the resistor 40 has a parasitic inductance 40b, it can be connected with the resistor 40. Figure 1The Doherty amplifier 10 shown likewise prevents the gain of the composite signal from decreasing.

[0173] When the signal to be amplified is a communication signal, a device having Figure 1 The communication device of the Doherty amplifier shown serves as an amplifier for amplifying a communication signal.

[0174] Fig.11 It shows that Figure 1 The structure of the communication device of the Doherty amplifier 10 is shown.

[0175] Figure 1 The Doherty amplifier shown does not include the delay circuit described in Patent Document 1. Therefore, Fig.11 The communication device shown can amplify the communication signal without causing a delay in the communication signal corresponding to the delay time of the delay circuit.

[0176] Although Fig.11 The communication device shown has Figure 1 The Doherty amplifier 10 shown may also include Fig.10 A Doherty amplifier 10 with a Wilkinson divider 11 is shown.

[0177] In addition, the present disclosure allows free combination of the various embodiments, modification of arbitrary components of the various embodiments, or omission of arbitrary components in the various embodiments.

[0178] Industrial Applicability

[0179] The present disclosure is applicable to Doherty amplifiers and communication devices.

[0180] Description of Reference Numerals

[0181] 1 input terminal, 2 load, 10 Doherty amplifier, 11 Wilkinson divider, 11a, 11b output terminals, 12 first transmission line, 13 second transmission line, 14 resistor, 15 phase adjustment line, 16 coefficient adjustment line, 17 phase adjustment line, 18 carrier amplifier, 18a transistor, 18b input matching circuit, 18c output matching circuit, 18d stabilization circuit, 19 peak amplifier, 19a transistor, 19b input matching circuit, 19c output matching circuit, 19d stabilization circuit, 20 quarter wavelength line, 21 output synthesis point, 22 output matching circuit, 30 input reflection phase range, 40 resistor, 40a resistor, 40b parasitic inductance, 41, 42 capacitors.

Claims

1. A Doherty amplifier, characterized in that: The Doherty amplifier has: A first transmission line, one end of which is connected to an input terminal for inputting a signal to be amplified; a second transmission line, one end of which is connected to the input terminal; a resistor connected between the other end of the first transmission line and the other end of the second transmission line; a carrier amplifier that amplifies the signal output from the other end of the first transmission line and outputs the amplified signal to an output synthesis point; as well as a peak amplifier that amplifies the signal output from the other end of the second transmission line and outputs the amplified signal to the output combining point, The ratio of the characteristic impedance of the second transmission line to the characteristic impedance of the first transmission line is a power allocation ratio of the amplification target signal to the carrier amplifier and the peak amplifier when both the carrier amplifier and the peak amplifier are saturated. The resistance value of the resistor is a value obtained by multiplying the sum of the input impedance of the carrier amplifier when the carrier amplifier is saturated and the input impedance of the peak amplifier when the peak amplifier is saturated by a proportionality coefficient that is less than 1 and greater than or equal to 0.

2. The Doherty amplifier according to claim 1, characterized in that The Doherty amplifier has: a coefficient adjustment circuit connected between the other end of the second transmission line and the peak amplifier, and adjusting a reflection coefficient of a signal in the peak amplifier when the peak amplifier is viewed from the other end of the second transmission line; as well as The phase adjustment line is connected between the other end of the first transmission line and the carrier amplifier and has the same electrical length as that of the coefficient adjustment line.

3. The Doherty amplifier according to claim 1, characterized in that The Doherty amplifier includes a capacitor connected in series with the resistor.

4. A communication device, characterized in that: The communication device comprises the Doherty amplifier according to any one of claims 1 to 3, The amplification target signal is a communication signal, and the Doherty amplifier is used as an amplifier for amplifying the communication signal.

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