Chip, preparation method and electronic device

Abstract

The application discloses a chip, a preparation method and an electronic device, relates to the technical field of chips, and can reduce the surface area occupied by a thin film resistor on a chip, and further reduce the volume of the whole chip. The chip comprises a silicon substrate, the silicon substrate comprises at least one through silicon via, the through silicon via penetrates through the silicon substrate, and a conductive thin film covers the inner wall of the through silicon via, one end of the conductive thin film is used for connecting a voltage source, and the other end is used for grounding.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip technical field, and particularly to a chip, a preparation method and an electronic device. BACKGROUND

[0002] With the rapid increase of chip integration, the research on chip thermal effect is more and more important. In order to avoid the damage to the chip caused by the local temperature being too high, it is usually necessary to integrate a temperature sensor in the chip to detect the change of temperature in real time, and the commonly used temperature sensor is a thermal resistance.

[0003] However, in order to realize high temperature sensitivity, the existing thin film resistance temperature sensor needs to increase the resistance value of the sensor itself, and in order to achieve this goal, a certain length of thin film resistance is needed, which will result in a larger surface area occupied by the temperature sensor, and further result in a larger volume of the overall chip. SUMMARY

[0004] The embodiments of the present application provide a chip, a preparation method and an electronic device, which can reduce the surface area occupied by the thin film resistance on the chip, and further reduce the volume of the overall chip.

[0005] In a first aspect, the embodiments of the present application provide a chip, comprising:

[0006] a silicon substrate, the silicon substrate comprising at least one through-silica via, the through-silica via penetrating through the silicon substrate;

[0007] a conductive thin film, the conductive thin film covering the inner wall of the through-silica via, one end of the conductive thin film being used for connecting a voltage source, and the other end of the conductive thin film being used for grounding.

[0008] In some embodiments, the silicon substrate comprises at least two through-silica vias, and the conductive thin films covering the inner walls of the at least two through-silica vias are connected in series, one end of the conductive thin film after being connected in series being used for connecting the voltage source, and the other end of the conductive thin film after being connected in series being used for grounding.

[0009] In some embodiments, the surfaces of both sides of the silicon substrate are provided with redistribution layers, and the redistribution layers are used for electrically connecting the conductive thin films covering the inner walls of different through-silica vias, so that the conductive thin films of the inner walls of different through-silica vias are connected in series.

[0010] In some embodiments, the redistribution layers comprise a first redistribution layer and a second redistribution layer, and the first redistribution layer and the second redistribution layer are respectively located on different sides of the silicon substrate.

[0011] One end of the conductive thin film of the inner wall of the same through-silica via is electrically connected to the first redistribution layer, and the other end of the conductive thin film is electrically connected to the second redistribution layer.

[0012] In some embodiments, the chip further comprises:

[0013] an insulating film, the insulating film being arranged between the conductive film and the silicon substrate, the insulating film being configured to insulate the conductive film from the silicon substrate.

[0014] In some embodiments, the conductive film comprises a metal material; and / or,

[0015] the insulating film comprises silicon oxide.

[0016] A second aspect of the embodiments of the present application provides a method for manufacturing a chip, comprising:

[0017] arranging at least one through-silicon via in a silicon substrate, so that the through-silicon via penetrates the silicon substrate;

[0018] arranging a conductive film, so that the conductive film covers an inner wall of the through-silicon via;

[0019] connecting one end of the conductive film to a voltage source and the other end to a ground.

[0020] In some embodiments, the number of the through-silicon vias is at least two.

[0021] The arranging of the conductive film, so that the conductive film covers the inner wall of the through-silicon via, comprises:

[0022] arranging a conductive film layer, so that the conductive film layer covers at least surfaces of two sides of the silicon substrate and the inner wall of the through-silicon via;

[0023] etching the conductive film layer, so that the conductive film layer between any two different through-silicon vias is disconnected, to obtain the conductive film, wherein the conductive film covers the inner wall of the through-silicon via;

[0024] After the arranging of the conductive film is completed, the method further comprises:

[0025] arranging a redistribution layer, so that the redistribution layer is electrically connected to the conductive film covered by the inner wall of each through-silicon via, to realize series connection of the conductive film of the inner wall of each through-silicon via.

[0026] In some embodiments, before the arranging of the conductive film, the method further comprises:

[0027] arranging an insulating film, so that the insulating film insulates the conductive film from the silicon substrate.

[0028] A third aspect of the embodiments of the present application provides an electronic device, comprising:

[0029] the chip as described in the first aspect.

[0030] The chip, fabrication method, and electronic device provided in this application embodiment utilize a conductive thin film as a thin-film resistor for temperature sensing. The conductive thin film covers the inner wall of a through-silicon via (TSV), with one end connected to a voltage source and the other end grounded, forming a conductive loop. This loop senses temperature changes in the chip by utilizing the change in resistance with temperature. Since the conductive thin film passes through the TSV and covers its inner wall, the length extension direction of the conductive film is changed from the surface of the silicon substrate to the longitudinal thickness direction of the silicon substrate. In other words, the depth of the TSV is used as the length of the conductive film, reducing the surface area occupied by the conductive film on the silicon substrate. The depth of the TSV can be used to increase the length of the conductive film, thereby increasing its resistance value and avoiding an increase in chip size. Attached Figure Description

[0031] Figure 1 A schematic cross-sectional structure diagram of a chip provided for an embodiment of this application;

[0032] Figure 2 A schematic top view of a chip provided for an embodiment of this application;

[0033] Figure 3 A schematic cross-sectional structure diagram of another chip provided in an embodiment of this application;

[0034] Figure 4 A schematic top view of another chip provided in an embodiment of this application;

[0035] Figure 5 A schematic cross-sectional structure diagram of another chip provided in an embodiment of this application;

[0036] Figure 6 A schematic cross-sectional structure diagram of another chip provided in an embodiment of this application;

[0037] Figure 7 A schematic flowchart illustrating a chip fabrication method provided in an embodiment of this application;

[0038] Figure 8 This is a schematic structural block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0039] To better understand the technical solutions provided in the embodiments of this specification, the technical solutions of the embodiments of this specification will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of this specification and the specific features in the embodiments are detailed descriptions of the technical solutions of the embodiments of this specification, rather than limitations on the technical solutions of this specification. In the absence of conflict, the embodiments of this specification and the technical features in the embodiments can be combined with each other.

[0040] In this document, relational terms such as first and second and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element. The terms "two or more" and "two or more than two" include both two and more than two entities.

[0041] With the rapid increase of chip integration, the research on chip thermal effect is more and more important. In order to avoid the damage to the chip caused by the local temperature being too high, it is usually necessary to integrate a temperature sensor in the chip to detect the change of temperature in real time, and the commonly used temperature sensor is a thermal resistance.

[0042] However, in order to realize high temperature sensitivity, the existing thin film resistance temperature sensor needs to increase the resistance value of the sensor itself, and in order to achieve this goal, a certain length of thin film resistance is needed, which will cause the temperature sensor to occupy a large surface area, and further cause the overall chip volume to be large.

[0043] Therefore, the embodiments of the present application provide a chip, a preparation method and an electronic device, which can reduce the surface area occupied by the thin film resistance on the chip, and further reduce the volume of the overall chip.

[0044] In a first aspect, the embodiments of the present application provide a chip, Figure 1 A schematic cross-sectional structure diagram of a chip provided by the embodiments of the present application; Figure 2 A schematic top view of a chip provided by the embodiments of the present application. In combination with Figure 1 And Figure 2The chip provided by the embodiment of the present application comprises: a silicon substrate 100, the silicon substrate 100 comprises at least one through silicon via 110, the through silicon via 110 penetrates the silicon substrate 100; and a conductive film 200, the conductive film 200 covers the inner wall of the through silicon via 110, one end of the conductive film 200 is used for connecting a voltage source, and the other end is used for grounding, and the voltage source can provide a power supply voltage VDD. The conductive film 200 can form a conductive loop by connecting the power supply voltage VDD at one end and grounding at the other end. The conductive film 200 forming the conductive loop can be used as a thin film resistance, and is used for forming a thin film resistance temperature sensor. During the working process of the chip, the temperature of the chip will change due to the operation of other devices, and the temperature will generally rise. The rise of the temperature of the chip will cause the resistance of the conductive film 200 to change. The change of the resistance of the conductive film 200 can be reflected by testing the change of the current flowing through the conductive film 200, or the change of the voltage difference between the two ends of the conductive film 200. The resistance change of the conductive film 200 can reflect the temperature change of the chip, thereby realizing the effect of temperature sensing. That is, the conductive film 200 covering the inner wall of the through silicon via 110 is used as a thermal resistance material, the resistance value of the thermal resistance material changes with the temperature, the resistance value is calculated to calculate the temperature of the measured object, thereby forming an on-chip resistance temperature sensor.

[0045] Reference Figure 1 And Figure 2 It is easy to understand that, since the conductive film 200 covers the inner wall of the through silicon via 110, the length L of the conductive film 200 covering the inner wall of the through silicon via 110 is the hole depth of the through silicon via 110, the width d of the conductive film 200 is the corresponding circumference of the hole diameter of the through silicon via 110, and the thickness h of the conductive film 200 is the film thickness. Then the resistance value R0 of the conductive film 200 as a thin film resistance temperature sensor under the condition of 0℃ is ρ×L / (d×h), wherein ρ is the resistivity of the conductive film 200.

[0046] Generally, the thin film resistance of the existing thin film resistance temperature sensor in the chip is arranged on the surface of the silicon substrate, and the length of the thin film resistance extends on the surface of the silicon substrate. In order to improve the temperature sensing sensitivity of the thin film resistance, it is necessary to increase the resistance value of the thin film resistance under the condition of 0℃, and then it is necessary to increase the length of the thin film resistance or reduce the thickness or width of the thin film resistance, which will further increase the area of the silicon substrate required by the chip, and further cause the increase of the volume of the chip.

[0047] To address the aforementioned issues, the chip provided in this application embodiment utilizes a conductive thin film 200 as a thin-film resistor for temperature sensing. The conductive thin film 200 covers the inner wall of the through-silicon via 110. One end of the conductive thin film 200 is connected to a voltage source, and the other end is grounded, forming a conductive loop. This loop uses the change in resistance with temperature to sense temperature changes in the chip. Since the conductive thin film 200 passes through the through-silicon via 110 and covers its inner wall, the length extension direction of the conductive thin film 200 is changed from the surface of the silicon substrate 100 to the longitudinal thickness direction of the silicon substrate 100. That is, the length of the conductive thin film 200 is used as the depth of the through-silicon via 110. This reduces the surface area occupied by the conductive thin film 200 on the silicon substrate 100, and the length of the conductive thin film 200 can be increased by utilizing the depth of the through-silicon via 110, thereby increasing the resistance value of the conductive thin film 200 and avoiding an increase in chip size.

[0048] In some embodiments, the silicon substrate includes at least two through-silicon vias (TSVs), and conductive thin films covering the inner walls of the at least two TSVs are connected in series. One end of the series-connected conductive films is used to connect to a voltage source, and the other end is used to ground. There can be two or more TSVs on the silicon substrate; this application does not specifically limit the number of TSVs.

[0049] For example, Figure 3 This is a schematic cross-sectional structural diagram of another chip provided in an embodiment of this application. For example... Figure 3 As shown, the silicon substrate 100 can be divided into a temperature sensor region 101 and a device region 102. The temperature sensor region 101 can be used to set up silicon vias 110 and conductive thin films 200, while the device region 102 can be used to set up electronic devices. Multiple electronic devices can be connected to form an integrated circuit, and the chip can then serve as an integrated circuit chip. The device region 102 can also be used to set up other sensors, and the chip can then serve as a sensor chip. No specific limitations are made in the embodiments of this application. Figure 3 The number of through-silicon vias 110 shown is merely illustrative and not intended to limit the scope of this application. The conductive films 200 covering the inner walls of different through-silicon vias 110 can be connected in series. One end of each series-connected conductive film 200 can be connected to a power supply voltage VDD, and the other end can be grounded. The resistance of each series-connected conductive film 200 is the sum of its individual resistances. The more conductive films 200 covering the inner walls of the through-silicon vias 110 are connected in series, the higher the resistance of the thin-film resistance temperature sensor can be, thus improving its temperature sensitivity. Multiple through-silicon vias 110 can be arranged in an array; this embodiment does not impose specific limitations on this arrangement.

[0050] In some embodiments, the conductive film 200 may include a metallic material, such as platinum or copper, which has superior conductivity.

[0051] For example, using the conductive film 200 within a TSV (Through Silicon Via) as a thin-film resistor, to obtain a resistance of 100 ohms (ohms, a unit of resistance value), the conductive film 200 can be a platinum film. The diameter of a single TSV 110 is 10 μm, the film thickness is 1 μm, the calculated length of the conductive film is approximately 3 cm, and the depth of the TSV is 100 μm. Approximately 300 TSVs are needed in series to obtain a resistance of 100 ohms. The 300 TSVs are arranged in a 17×18 array, i.e., a 17-row, 18-column TSV array is required, with a spacing of 10 μm between the TSVs. The entire TSV array is 0.34 mm × 0.36 mm in size, occupying approximately 1 / 10 of the area on the silicon substrate surface of a conventional thin-film resistance temperature sensor. In the chip provided in this embodiment, the area occupied by the thin-film resistance temperature sensor formed by the series-connected conductive films 200 on the silicon substrate 100 is significantly reduced.

[0052] The chip provided in this application embodiment utilizes a through-silicon via (TSV) array to deposit a conductive thin film 200 on the inner wall of the TSV 110. The conductive thin film 200 serves as a thermal resistance material. The conductive thin films 200 in the TSV array are connected in series to form a series circuit. A voltage and ground are applied to the two ends of the TSV array, respectively. The resistance of the conductive thin film 200 in the TSV array is measured by an external circuit. Based on the relationship between the resistance of the conductive thin film 200 and the temperature, the temperature is measured.

[0053] In some implementations... Figure 4 A schematic top view of another chip provided in an embodiment of this application. (See attached image.) Figure 4 As shown, a redistribution layer 300 is provided on both sides of the silicon substrate 100. The redistribution layer 300 is used to electrically connect the conductive films 200 covering the inner walls of different through-silicon vias 110, so that the conductive films 200 on the inner walls of different through-silicon vias 110 are connected in series.

[0054] In order to reduce the area of ​​traditional thin-film resistance temperature sensors and thus reduce the overall size of the chip, the chip provided in this application embodiment proposes to set a through-silicon via (TSV) temperature sensor on the chip. The depth of the TSV is used as the length of the thin-film resistor. The upper and lower surfaces of the TSV are connected to form an RDL (Re-distributed layer) to form a TSV array series circuit. The chip temperature is reflected according to the resistance change of the circuit, thus forming a temperature sensor.

[0055] In some implementations... Figure 5 This is a schematic cross-sectional structural diagram of another chip provided in an embodiment of this application. For example... Figure 5As shown, the rewiring layer 300 includes a first rewiring layer 310 and a second rewiring layer 320, the first rewiring layer 310 and the second rewiring layer 320 are respectively located at different sides of the silicon substrate 100; one end of the conductive film 200 on the inner wall of the same through silicon via 110 is electrically connected to the first rewiring layer 310, and the other end is electrically connected to the second rewiring layer 320. For example, in the preparation process of the chip, the conductive film layer can be first formed on the surfaces of the two sides of the silicon substrate 100 and the inner wall of the through silicon via 110 by using a film forming process, and then the conductive film layer on the surfaces of the two sides of the silicon substrate 100 is etched by using an etching process, and the conductive film layer on the inner wall of the through silicon via 110 is retained to obtain the conductive film 200; the rewiring layer 300 is formed on the surfaces of the two sides of the silicon substrate 100 by using a film forming process, the first rewiring layer 310 electrically connects one end of the conductive film 200 on the inner wall of the through silicon via 110 to the series connected conductive film 200, and the second rewiring layer 320 electrically connects the other end of the conductive film 200 on the inner wall of the same through silicon via 110 to the series connected conductive film 200, so that the conductive film 200 in the hole depth direction of the through silicon via 110 is connected to the series circuit, and the length of the conductive film 200 in the hole depth direction of the through silicon via 110 serves as the length of the film resistor. It should be noted that one end of the conductive film 200 covered by the inner wall of the same through silicon via 110 is close to the upper surface of the silicon substrate 100, and the other end is close to the lower surface of the silicon substrate 100. One end of the series connected conductive film 200 can be electrically connected to a voltage source through the rewiring layer 300, and the other end can also be grounded through the rewiring layer 300. The material of the rewiring layer 300 can be a metal material, and the material of the rewiring layer 300 can be the same as or different from the material of the conductive film 200, which is not limited in the embodiments of the present application.

[0056] In some embodiments, Figure 6 Another schematic cross-sectional structure diagram of a chip is provided in the embodiments of the present application. As shown, Figure 6 The chip provided by the embodiments of the present application further includes an insulating film 400, the insulating film 400 is arranged between the conductive film 200 and the silicon substrate 100, and the insulating film 400 is used to isolate the conductive film 200 and the silicon substrate 100. Since the silicon substrate 100 is usually single crystal silicon, the silicon substrate 100 has a certain conductivity, so that in order to avoid the influence of other factors on the conductive circuit of the conductive film 200, it is necessary to isolate the conductive film 200 and the silicon substrate 100. For example, the insulating film 400 can include silicon oxide, silicon nitride or other insulating materials. The preparation of silicon oxide can directly oxidize the silicon substrate 100, and the silicon oxide can be formed on the surface of the silicon substrate 100 and the inner wall surface of the through silicon via 110, which is simple in process and does not need to use other materials.

[0057] In a second aspect, the embodiments of the present application provide a chip preparation method, Figure 7A schematic flow chart of a chip preparation method is provided in the embodiments of the present application. As shown in Figure 7 The chip preparation method provided in the embodiments of the present application comprises the following steps.

[0058] S500: At least one through-silicon via is arranged on the silicon substrate, so that the through-silicon via penetrates the silicon substrate. The through-silicon via can be prepared by etching process.

[0059] S600: A conductive film is arranged, so that the conductive film covers the inner wall of the through-silicon via. The conductive film can be prepared by magnetron sputtering or atomic layer deposition. Referring to Figure 1 and Figure 2 , it can be easily understood that, since the conductive film 200 covers the inner wall of the through-silicon via 110, the length L of the conductive film 200 covered by the inner wall of the through-silicon via 110 is the hole depth of the through-silicon via 110, the width d of the conductive film 200 is the circumference corresponding to the hole diameter of the through-silicon via 110, and the thickness h of the conductive film 200 is the film thickness. Then, the resistance value R0 of the conductive film 200 as a film resistance temperature sensor at 0℃ is ρ×L / (d×h), wherein ρ is the resistivity of the conductive film.

[0060] S700: One end of the conductive film is connected to a voltage source, and the other end is grounded. The conductive film 200 is connected to the power supply voltage VDD at one end and grounded at the other end, so as to form a conductive loop. The conductive film 200 forming the conductive loop can be used as a film resistance for forming a film resistance temperature sensor. During the operation of the chip, the temperature of the chip will change due to the operation of other devices, and the temperature will usually rise. The rise of the temperature of the chip will cause the resistance of the conductive film 200 to change. The change of the resistance of the conductive film 200 can be reflected by testing the change of the current flowing through the conductive film 200 or by testing the change of the voltage difference between the two ends of the conductive film 200. The resistance change of the conductive film 200 can reflect the temperature change of the chip, so as to realize the effect of temperature sensing. That is, the conductive film 200 covered by the inner wall of the through-silicon via 110 is used as a thermal resistance material, the resistance value of the thermal resistance material changes with the temperature in a single value, the resistance value is calculated to calculate the temperature of the measured object, so as to form a chip resistance temperature sensor.

[0061] The chip preparation method provided by the embodiment of the application sets the conductive film 200 as a thin film resistor for temperature sensing. The conductive film 200 covers the inner wall of the through silicon via 110, one end of the conductive film 200 is used for connecting a voltage source, and the other end is used for grounding. The conductive film 200 is connected to the power supply voltage VDD at one end and grounded at the other end, so as to form a conductive loop. The conductive loop uses the change of resistance with temperature to sense the temperature change of the chip. The conductive film 200 passes through the through silicon via 110 and covers the inner wall of the through silicon via 110. The length extension direction of the conductive film 200 is converted from the surface of the silicon substrate 100 to the longitudinal thickness direction of the silicon substrate, that is, the hole depth of the through silicon via 110 is used as the length of the conductive film 200. The surface area of the silicon substrate 100 occupied by the conductive film 200 is reduced, the depth of the through silicon via 110 is used to increase the length of the conductive film 200, the resistance value of the conductive film 200 is increased, and the volume of the chip is avoided to be increased.

[0062] In some embodiments, the number of through silicon vias is at least two; and the step S600 can include:

[0063] The conductive film layer is set to cover at least the surfaces of two sides of the silicon substrate and the inner wall of the through silicon via;

[0064] The conductive film layer is etched to disconnect the conductive film layer between any different through silicon vias, to obtain a conductive film, wherein the conductive film covers the inner wall of the through silicon via. For example, in the preparation process of the chip, the conductive film layer can be first set on the surfaces of two sides of the silicon substrate 100 and the inner wall of the through silicon via 110 by using a film forming process, and then the conductive film layer on the surfaces of two sides of the silicon substrate 100 is etched by using an etching process, and the conductive film layer on the inner wall of the through silicon via 110 is retained to obtain the conductive film 200.

[0065] After the conductive film is set, the method further includes:

[0066] The redistribution layer is set to electrically connect the conductive films covered by the inner walls of different through silicon vias, to realize the series connection of the conductive films of the inner walls of different through silicon vias. For example, Figure 5The re-wiring layer 300 includes a first re-wiring layer 310 and a second re-wiring layer 320, and the first re-wiring layer 310 and the second re-wiring layer 320 are located at different sides of the silicon substrate 100, respectively. One end of the conductive film 200 on the inner wall of the same through silicon via 110 is electrically connected to the first re-wiring layer 310, and the other end of the conductive film 200 is electrically connected to the second re-wiring layer 320. The re-wiring layer 300 is arranged on the two side surfaces of the silicon substrate 100 by a film forming process. The first re-wiring layer 310 electrically connects one end of the conductive film 200 on the inner wall of the through silicon via 110 to the series-connected conductive film 200, and the second re-wiring layer 320 electrically connects the other end of the conductive film 200 on the inner wall of the same through silicon via 110 to the series-connected conductive film 200. Thus, the conductive film 200 in the hole depth direction of the through silicon via 110 is connected to the series-connected loop, and the length of the conductive film 200 in the hole depth direction of the through silicon via 110 serves as the length of the film resistor. One end of the series-connected conductive film 200 can be electrically connected to a voltage source through the re-wiring layer 300, and the other end can be grounded through the re-wiring layer 300. The material of the re-wiring layer 300 can be a metal material, and the material of the re-wiring layer 300 can be the same as or different from the material of the conductive film 200, which is not limited in the embodiments of the present application.

[0067] In some embodiments, before the conductive film is arranged, the method further includes:

[0068] The insulating film is arranged to isolate the conductive film from the silicon substrate.

[0069] As shown in Figure 6 , the insulating film 400 is arranged between the conductive film 200 and the silicon substrate 100, and the insulating film 400 is arranged before the conductive film 200, and the insulating film 400 is used to isolate the conductive film 200 from the silicon substrate 100. Since the silicon substrate 100 is usually single crystal silicon, the silicon substrate 100 has a certain conductivity, and therefore it is necessary to isolate the conductive film 200 from the silicon substrate 100 in order to avoid the influence of other factors on the conductive loop of the conductive film 200. For example, the insulating film 400 can include silicon oxide, silicon nitride or other insulating materials. The arrangement of the insulating film 400 can directly oxidize the silicon substrate 100, and can form silicon oxide on the surface of the silicon substrate 100 and the inner wall surface of the through silicon via 110, which is simple in process and does not require the use of other materials.

[0070] In a third aspect, the embodiments of the present application provide an electronic device, Figure 8 The electronic device provided by the embodiments of the present application is shown in Figure 8 The electronic device provided by the embodiments of the present application includes the chip 1000 as described in the first aspect.

[0071] It should be noted that the chip provided in the present application can be a wafer, a die or a wafer. For example, the electronic device provided in the embodiments of the present application can be a memory, a controller, a control mainboard, a computer integrated device, etc., and the embodiments of the present application are not limited specifically.

[0072] It should be noted that in the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0073] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system or a computer program product. Therefore, the present application can adopt a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware aspects.

[0074] The above, the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

[0075] Although the preferred embodiments of the present application have been described, those skilled in the art can make further changes and modifications to the embodiments once they know the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0076] Obviously, those skilled in the art can make various modifications and changes to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and changes of the present application fall within the scope of the claims of the present application and their equivalents, the present application also intends to include these modifications and changes.

Claims

1. A chip, characterized in that, include: A silicon substrate, the silicon substrate including at least one through-silicon via (TSV) penetrating the silicon substrate; A conductive film covers the inner wall of the through-silicon via, one end of which is used to connect to a voltage source and the other end is used to ground. The conductive thin film serves as a thin-film resistor for temperature sensing.

2. The chip according to claim 1, characterized in that, The silicon substrate includes at least two through-silicon vias, and the conductive films covering the inner walls of the at least two through-silicon vias are connected in series. One end of the series-connected conductive films is used to connect to the voltage source, and the other end of the series-connected conductive films is used to ground.

3. The chip according to claim 2, characterized in that, A redistribution layer is provided on both sides of the silicon substrate. The redistribution layer is used to electrically connect the conductive films covering the inner walls of different through-silicon vias, so that the conductive films on the inner walls of different through-silicon vias are connected in series.

4. The chip according to claim 3, characterized in that, The redistribution layer includes a first redistribution layer and a second redistribution layer, wherein the first redistribution layer and the second redistribution layer are located on different sides of the silicon substrate. One end of the conductive film on the inner wall of the same through-silicon via is electrically connected to the first rewiring layer, and the other end is electrically connected to the second rewiring layer.

5. The chip according to claim 1, characterized in that, Also includes: An insulating film is disposed between the conductive film and the silicon substrate, and the insulating film is used to isolate the conductive film from the silicon substrate.

6. The chip according to claim 5, characterized in that, The conductive thin film comprises a metallic material; and / or, The insulating film comprises silicon oxide.

7. A method for fabricating a chip, characterized in that, include: At least one through-silicon via is formed on a silicon substrate such that the through-silicon via penetrates the silicon substrate; A conductive film is provided so that the conductive film covers the inner wall of the through silicon via; One end of the conductive film is connected to a voltage source, and the other end is grounded; The conductive thin film serves as a thin-film resistor for temperature sensing.

8. The method for fabricating a chip according to claim 7, characterized in that, The number of through-silicon vias is at least two; The step of setting a conductive film to cover the inner wall of the through-silicon via includes: A conductive thin film layer is provided such that the conductive thin film layer at least covers the surfaces on both sides of the silicon substrate and the inner wall of the through-silicon via; The conductive thin film layer is etched to break the conductive thin film layer between any different through-silicon vias, thereby obtaining the conductive thin film, wherein the conductive thin film covers the inner wall of the through-silicon via; After the conductive film is set, the following steps are also included: A redistribution layer is provided to electrically connect the conductive films covering the inner walls of different through-silicon vias, thereby achieving series connection of the conductive films on the inner walls of different through-silicon vias.

9. The method for fabricating a chip according to claim 7, characterized in that, Before setting the conductive film, the method further includes: An insulating film is provided to isolate the conductive film from the silicon substrate.

10. An electronic device, characterized in that, include: The chip as described in any one of claims 1-6.

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