Semiconductor structure and method of fabricating the same

Abstract

This invention provides a semiconductor structure and its fabrication method. The semiconductor structure includes at least one transistor, which includes: a channel region located in a semiconductor layer; a gate region located at least on one side of the channel region; a source region located at a first end of the channel region; and a drain region located at a second end of the channel region. The first end and the second end are opposite ends of the channel region in a first direction, which is the direction of the semiconductor layer thickness. At least one of the source and drain regions includes a first layer region and a second layer region, and both the source and drain regions contain a third layer region. The first layer region is located on the side closer to the channel region; the third layer region is located on the side farther from the channel region; and a second layer region is located between the first and third layer regions. The doping type of the second layer region is different from the doping types of the first and third layer regions, or the second layer region is an intrinsically undoped region. This invention can reduce the parasitic capacitance of the transistor and improve its response speed.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor structure and its fabrication method. Background Technology

[0002] Transistors in semiconductor structures are widely used as switching devices or driving devices in electronic devices. For example, transistors can be used in Dynamic Random Access Memory (DRAM) to control each memory cell. Understandably, the basic memory cell structure of DRAM consists of a transistor and a storage capacitor, and its main operating principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0003] However, existing transistors still have many problems that need to be improved. Summary of the Invention

[0004] To address one or more of the related technical problems, embodiments of the present invention provide a semiconductor structure and a method for fabricating the same.

[0005] This invention provides a semiconductor structure, including: at least one transistor, the transistor including: a channel region located in a semiconductor layer;

[0006] The gate is located at least on one side of the channel region;

[0007] The source region is located at the first end of the channel region;

[0008] A drain region is located at the second end of the channel region; wherein the first end and the second end are opposite ends of the channel region in a first direction, the first direction being the direction of the semiconductor layer thickness;

[0009] At least one of the source region and the drain region includes a first layer region and a second layer region, and both the source region and the drain region contain a third layer region; the first layer region is located on the side closer to the channel region; the third layer region is located on the side farther from the channel region; the second layer region is located between the first layer region and the third layer region;

[0010] The doping type of the second layer region is different from that of the first layer region and the third layer region, or the second layer region is an intrinsically undoped region.

[0011] In the above scheme, the doping type of both the first layer region and the third layer region is N-type doping;

[0012] The second layer region is doped with P-type doping.

[0013] In the above scheme, the maximum doping concentration of the third layer region is greater than the maximum doping concentration of the first layer region; the maximum doping concentration of the first layer region is greater than or equal to the maximum doping concentration of the second layer region.

[0014] In the above scheme, the projection of the gate along the second direction does not completely overlap with the projection of the second layer region along the second direction; the second direction is perpendicular to the first direction and points from the gate to the channel region.

[0015] In the above scheme, the projection of the gate along the second direction does not overlap with the projection of the second layer region along the second direction.

[0016] In the above scheme, the material of the second layer region and the material of the semiconductor layer both include monocrystalline silicon or polycrystalline silicon.

[0017] In the above scheme, the material of the second layer region includes silicon germanide, polycrystalline silicon, or a composite material of silicon germanide and polycrystalline silicon; the material of the semiconductor layer includes monocrystalline silicon.

[0018] In the above scheme, the at least one transistor includes a first transistor and a second transistor arranged in parallel and separated by an insulating layer;

[0019] The gate of the first transistor is located on the side of the first transistor that is furthest from the insulating layer; the gate of the second transistor is located on the side of the second transistor that is furthest from the insulating layer.

[0020] In the above scheme, the transistor type includes one of the following:

[0021] Columnar gate transistor;

[0022] Semi-surround gate transistor;

[0023] All-around gate transistor.

[0024] This invention also provides a semiconductor structure, comprising:

[0025] A memory cell array; each memory cell in the memory cell array includes a transistor extending in a first direction and a memory cell coupled to the transistor, wherein the transistor includes a semiconductor body extending in the first direction and a gate contacting at least one side of the semiconductor body;

[0026] Multiple bit lines; the multiple bit lines are coupled to the memory cell and extend in a second direction perpendicular to the first direction, and a corresponding bit line and a corresponding memory cell are coupled to the opposite end of each memory cell in the memory cell in the first direction;

[0027] The semiconductor body includes:

[0028] The channel region is located within the semiconductor layer;

[0029] The source region is located at the first end of the channel region;

[0030] A drain region is located at the second end of the channel region; wherein the first end and the second end are opposite ends of the channel region in a first direction, the first direction being the direction of the semiconductor layer thickness;

[0031] At least one of the source region and the drain region includes a first layer region and a second layer region, and both the source region and the drain region contain a third layer region; the first layer region is located on the side closer to the channel region; the third layer region is located on the side farther from the channel region; the second layer region is located between the first layer region and the third layer region;

[0032] The doping type of the second layer region is different from that of the first layer region and the third layer region, or the second layer region is an intrinsically undoped region.

[0033] In the above scheme, the doping type of both the third layer region and the first layer region is N-type doping;

[0034] The second layer region is doped with P-type doping.

[0035] In the above scheme, the maximum doping concentration of the third layer region is greater than the maximum doping concentration of the first layer region; the maximum doping concentration of the first layer region is greater than or equal to the maximum doping concentration of the second layer region.

[0036] In the above scheme, one of the source region and the drain region of the transistor is coupled to the memory cell in the corresponding memory cell.

[0037] In the above scheme, another of the source region and the drain region of the transistor is coupled to the corresponding bit line.

[0038] In the above scheme, the semiconductor structure includes: dynamic random access memory, ferroelectric memory, phase change memory, magnetic change memory, or resistive change memory.

[0039] In the above scheme, the semiconductor structure includes a dynamic random access memory, and the memory cell includes a storage capacitor;

[0040] One end of the storage capacitor is coupled to the third layer region of the source region of the transistor;

[0041] The bit line is coupled to the third layer region of the drain region of the transistor.

[0042] This invention also provides a method for fabricating a semiconductor structure.

[0043] A memory cell array is formed; each memory cell in the memory cell array includes a transistor extending in a first direction and a memory cell coupled to the transistor;

[0044] Multiple bit lines are formed; the multiple bit lines are coupled to the memory cell and extend in a second direction perpendicular to the first direction, and a corresponding bit line and a corresponding memory cell are coupled to the opposite end of each memory cell in the memory cell in the first direction;

[0045] The method for manufacturing the transistor includes:

[0046] A semiconductor layer is provided, wherein the semiconductor layer has at least one active pillar;

[0047] A source region is formed at the first end of the active pillar;

[0048] A gate is formed on at least one side of the active pillar;

[0049] A drain region is formed at the second end of the active pillar; wherein the first end and the second end are opposite ends of the active pillar in a first direction, the first direction being the thickness direction of the semiconductor layer; the active pillar between the source region and the drain region constitutes the channel region of the transistor;

[0050] At least one of the source region and the drain region includes a first layer region and a second layer region, and both the source region and the drain region contain a third layer region; the first layer region is located on the side closer to the channel region; the third layer region is located on the side farther from the channel region; the second layer region is located between the first layer region and the third layer region;

[0051] The doping type of the second layer region is different from that of the first layer region and the third layer region, or the second layer region is an intrinsically undoped region.

[0052] In the above scheme, the formation of the second layer area includes:

[0053] The second layer region is formed through diffusion or in-situ doping processes.

[0054] In the above scheme, the material of the second layer region is the same as the material of the semiconductor layer;

[0055] The process includes forming a source region at the first end of the active pillar and forming a drain region at the second end of the active pillar; comprising:

[0056] Different concentrations of ions are implanted sequentially at the first end of the active pillar near the first surface of the semiconductor layer to form the first layer region, the second layer region, and the third layer region of the source region, respectively.

[0057] The semiconductor layer is thinned from its second surface and in a direction perpendicular to the semiconductor layer to expose the second end of the active pillar away from the first surface of the semiconductor layer; wherein the second surface is the opposite of the first surface.

[0058] Different concentrations of ions are implanted sequentially at the second end of the active column to form the first, second, and third layers of the drain region, respectively.

[0059] In the above scheme, the material of the second layer is different from the material of the semiconductor layer;

[0060] The process includes forming a source region at the first end of the active pillar and forming a drain region at the second end of the active pillar; comprising:

[0061] Ion implantation is performed on the first end of the active pillar near the first surface of the semiconductor layer to form the first layer region of the source region;

[0062] A first material layer is formed on the first layer of the source region, and ion implantation is performed on the first material layer to form the second layer of the source region;

[0063] A second material layer is formed on the second layer of the source region, and ion implantation is performed on the second material layer to form the third layer of the source region;

[0064] The semiconductor layer is thinned from its second surface and in a direction perpendicular to the semiconductor layer to expose the second end of the active pillar away from the first surface of the semiconductor layer; wherein the second surface is the opposite of the first surface.

[0065] Ion implantation is performed on the second end of the active post to form the first layer of the drain region.

[0066] A third material layer is formed on the first layer of the drain region, and ion implantation is performed on the third material layer to form the second layer of the drain region;

[0067] A fourth material layer is formed on the second layer of the drain region, and ion implantation is performed on the fourth material layer to form the third layer of the drain region.

[0068] This invention provides a semiconductor structure and its fabrication method. The semiconductor structure includes at least one transistor, comprising: a channel region located in a semiconductor layer; a gate region located at least on one side of the channel region; a source region located at a first end of the channel region; and a drain region located at a second end of the channel region. The first end and the second end are opposite ends of the channel region in a first direction, which is the direction of the semiconductor layer thickness. At least one of the source region and the drain region includes a first layer region and a second layer region, and both the source region and the drain region contain a third layer region. The first layer region is located on the side closer to the channel region; the third layer region is located on the side farther from the channel region; and the second layer region is located between the first layer region and the third layer region. The doping type of the second layer region is different from the doping types of the first layer region and the third layer region, or the second layer region is an intrinsically undoped region. In various embodiments of the present invention, by providing a first layer region and a second layer region in the source region and / or drain region, and providing a third layer region in both the source region and drain region, and making the doping type of the second layer region different from that of the first layer region and the third layer region, a capacitor can be formed between the third layer region and the first and second layer regions. This capacitor is connected in series with the parasitic capacitance of the bit line, thereby reducing the parasitic capacitance of the transistor. This increases the sensing margin of the transistor and improves the reliability of the readout security factor. At the same time, it can also reduce the formation rate of minority carriers in the inversion layer between the gate and the channel region, thereby reducing the parasitic capacitance of the gate, increasing the sensing margin, and improving reliability. In addition, it can also reduce the junction depth at the bit line connecting the drain region or the source region, thereby improving the response speed of the transistor. Attached Figure Description

[0069] Figure 1a This is a circuit connection diagram of a DRAM transistor provided in an embodiment of the present invention;

[0070] Figure 1b This is a schematic diagram of a transistor structure provided in an embodiment of the present invention;

[0071] Figure 2a This is a schematic diagram of a semiconductor structure provided in an embodiment of the present invention;

[0072] Figure 2b This is a schematic diagram of a semiconductor structure provided in an embodiment of the present invention;

[0073] Figure 2c This is a schematic diagram of a semiconductor structure provided in an embodiment of the present invention;

[0074] Figure 3a This is a schematic diagram of another semiconductor structure provided in an embodiment of the present invention;

[0075] Figure 3b This is a schematic diagram of yet another semiconductor structure provided in an embodiment of the present invention;

[0076] Figure 4 A schematic flowchart of a transistor fabrication method provided in an embodiment of the present invention;

[0077] Figures 5a to 5c This is a schematic diagram illustrating the implementation process of a semiconductor structure fabrication method provided in an embodiment of the present invention;

[0078] Figures 6a to 6j This is a schematic diagram illustrating the implementation process of another semiconductor structure fabrication method provided in this embodiment of the invention;

[0079] Figure 7 This is a schematic diagram of another semiconductor structure provided in an embodiment of the present invention;

[0080] Figure 8 This is a schematic diagram of the test results of a simulation process provided in an embodiment of the present invention;

[0081] Figure 9 This is a schematic diagram of the structure of a memory provided in an embodiment of the present invention.

[0082] Explanation of reference numerals in the attached figures

[0083] 20 - Transistor; 201 - Channel region; 202 - Source region; 203 - Drain region; 204 - Gate; 205 - First layer region; 206 - Second layer region; 207 - Third layer region; 208 - Gate oxide layer; 209a - First material layer; 209b - Second material layer; 209c - Third material layer; 209d - Fourth material layer; 210 - Bit line; 211 - Storage capacitor contact; 30 - First transistor; 301 - Channel region of the first transistor; 304 - Gate of the first transistor; 305 - First storage capacitor; 40 - Second transistor; 401 - Channel region of the second transistor; 404 - Gate of the second transistor; 405 - Second storage capacitor; 50 - Insulating layer; 60 - Semiconductor structure; N1 - Doping concentration of the third layer region; N2 - Doping concentration of the first layer region; N3 - Doping concentration of the second layer region; T1 - Transistor without a second layer region; T2 - Transistor with a second layer region;

[0084] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The figures illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed Implementation

[0085] To make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0086] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the invention.

[0087] It is understood that the meanings of “on”, “above” and “over” in this invention should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0088] Furthermore, for ease of description, spatial relative terms such as “on,” “above,” “above,” “upper,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0089] In embodiments of the invention, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include various semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0090] In embodiments of the invention, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (where interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.

[0091] In this embodiment of the invention, the terms "first," "second," etc., are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0092] The semiconductor structure involved in the embodiments of this application is at least a portion that will be used in subsequent processes to form the final device structure. Here, the final device may include a memory, including but not limited to dynamic random access memory (DRAM). The following description uses dynamic random access memory as an example only.

[0093] However, it should be noted that the following embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention.

[0094] With the development of dynamic random access memory technology, the size of memory cells is getting smaller and smaller, and their array architecture has increased from 8F. 2 Go to 6F 2 Then go to 4F 2 Furthermore, based on the requirements for ions and leakage current in dynamic random access memory, the memory architecture has evolved from planar array transistors to recessed gate array transistors, then from recessed gate array transistors to buried channel array transistors, and finally from buried channel array transistors to vertical channel array transistors.

[0095] In some embodiments of the present invention, regardless of whether it is a planar transistor or a buried transistor, the dynamic random access memory is composed of multiple memory cell structures. Each memory cell structure mainly consists of a transistor and a memory cell (storage capacitor) controlled by the transistor. That is, the dynamic random access memory includes an architecture of 1 transistor (T) and 1 capacitor (C) (1T1C). Its main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0096] Figure 1a This is a schematic diagram of a control circuit using a 1T1C architecture provided in an embodiment of the present invention, as shown below. Figure 1a As shown, the drain of transistor T is electrically connected to the bit line (BL), the source region of transistor T is electrically connected to one of the electrode plates of capacitor C, and the other electrode plate of capacitor C can be connected to a reference voltage, which can be ground voltage or other voltages. The gate of transistor T is connected to the word line (WL). The transistor T is turned on or off by applying a voltage through the word line WL. The bit line BL is used to perform read or write operations on transistor T when it is turned on.

[0097] It is understandable that, such as Figure 1b As shown, the source (S) and drain (D) of transistor T are located on opposite sides of the gate (G), with the channel region between the source and drain. The projection of the gate along the X-axis must cover the projection of the channel region along the X-axis. However, in some embodiments of this invention, due to process differences, there may be partial overlap between the projection of the gate along the X-axis and the source and / or drain. (Refer to...) Figure 1b The dashed circle in the image is shown.

[0098] This results in adjacent transistors in the dynamic random access memory being placed closer together, which in turn increases the parasitic capacitance from the gate to the bit line. In addition, when the operating voltage is applied to the drain and the voltage applied to the gate is less than 0, gate-inducible drain leakage (GIDL) will occur in the area where the drain and gate overlap. If the gate-inducible drain leakage problem is too large, it may cause the transistor to have a floating body effect, resulting in charge loss of the memory cell or storage node.

[0099] To address one or more of the above-mentioned problems, embodiments of the present invention provide a semiconductor structure; Figures 2a-2c A three-dimensional structural diagram of the semiconductor structure provided in the embodiments of the present invention, such as... Figure 2a , Figure 2b , Figure 2c As shown, the semiconductor structure includes at least one transistor 20, the transistor 20 comprising:

[0100] Channel region 201 is located in the semiconductor layer;

[0101] Source region 202 is located at the first end of the channel region;

[0102] Drain region 203 is located at the second end of the channel region; wherein the first end and the second end are respectively the two opposite ends of the channel region 201 in a first direction, the first direction being the direction of the semiconductor layer thickness;

[0103] Gate 204 is located at least on one side of the channel region 201;

[0104] At least one of the source region 202 and the drain region 203 includes a first layer region 205 and a second layer region 206, and both the source region 202 and the drain region 203 contain a third layer region 207; the first layer region 205 is located on the side closer to the channel region; the third layer region 207 is located on the side farther from the channel region; the second layer region 206 is located between the first layer region 205 and the third layer region 207;

[0105] The doping type of the second layer region 206 is different from that of the first layer region 205 and the third layer region 207, or the second layer region 206 is an intrinsically undoped region.

[0106] It should be noted that, here and below, the first direction is the direction of the semiconductor layer thickness; the second direction is perpendicular to the first direction and perpendicular to the semiconductor layer surface; the third direction is perpendicular to both the first and second directions; for ease of description of the first, second, and third directions in the embodiments of the present invention, in the following embodiments, the first direction is represented by the Z direction in the figures; the second direction is represented by the X direction in the figures; and the third direction is represented by the Y direction in the figures; however, it should be noted that the above description of directions is only for illustrating the present invention and is not intended to limit the scope of the present invention.

[0107] For example, when the first direction is the Z-axis direction, the parallel arrangement direction of the source region 202, the channel region 201, and the drain region 203 can be parallel to the Z-axis direction.

[0108] Here, the semiconductor layer may include a single-element semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a germanium-silicon (SiGe) substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. Preferably, the substrate is a silicon substrate.

[0109] In some embodiments of the present invention, the transistor 20 has a vertical channel (i.e., channel region 201), and the source region 202 and drain region 203 of the transistor 20 are respectively located at opposite ends of the vertical channel (i.e., the first end and the second end). Here, the source region 202 is located at the first end of the channel region 201; the drain region 203 is located at the second end of the channel region 201; wherein the positions of the source region 202 and the drain region 203 are interchangeable. That is, the source region 202 and the drain region 203 are respectively the two ends of the channel region 201 arranged opposite each other in the Z-axis direction and whose positions can be interchanged.

[0110] In some embodiments of the present invention, the gate 204 may be located on one side of the channel region 201; it may be located on opposite sides of the channel region 201; or it may be located around the channel region 201. The specific location can be set according to the actual needs of the transistor; here, the example of the gate 204 being located on one side of the channel region 201 is used for illustration.

[0111] Here, the material of the gate 204 may include metal or polysilicon.

[0112] It should be noted that in some embodiments of the present invention, a gate oxide layer 208 is further provided between the gate 204 and the channel region 201 for electrically isolating the channel region 201 and the gate 204.

[0113] Understandably, the gate oxide layer in a transistor can be used to sense different electric fields and apply them to the surface of the channel region, so that minority carriers of the substrate (semiconductor layer) are adsorbed onto the surface of the channel region and accumulate and invert, making the gate oxide layer the same as the doping type of the source and drain regions, thereby realizing the conduction between the source and drain regions.

[0114] In some embodiments, after a gate voltage is applied to the gate, i.e., a strong electric field is generated, electrons drift and accelerate continuously along the direction of the electric field, thus gaining a large kinetic energy. When the electrons move from the source region to the drain region, the presence of the voltage difference causes the electrons to collide with the gate oxide layer and be injected into the gate oxide layer, thereby generating a hot carrier effect. This hot carrier effect has a significant impact on the reliability of the transistor.

[0115] Here, the material of the gate oxide layer 208 may include, but is not limited to, silicon oxide.

[0116] In this embodiment of the invention, a first layer region 205 and a second layer region 206 are provided in the source region 202 and / or the drain region 203; a third layer region 207 is provided in both the source region 202 and the drain region 203.

[0117] In some embodiments, the first layer region 205 can be understood as a lightly doped drain region; the second layer region 206 can be understood as a doped region; or an intrinsically undoped region; the third layer region 207 in the source region 202 can be understood as a source; and the third layer region 207 in the drain region 203 can be understood as a drain.

[0118] Understandably, the lightly doped drain region is a structure adopted by the device to reduce the drain electric field and improve the hot carrier effect. That is, a drain region with a low doping concentration is set near the drain region or source region in the channel region, so that the lightly doped drain region also bears part of the voltage. This structure can prevent the hot carrier effect.

[0119] In other words, in some embodiments of the present invention, the first layer region 205 can be used to prevent hot carrier effects.

[0120] Here, the second layer region 206 is a doped region, which can be understood as ion doping of the second layer region 206 to give it doped properties.

[0121] The second layer region 206 being an intrinsically undoped region can be understood as a pure semiconductor material layer that is not doped, such as a silicon layer.

[0122] Here, the doping type of the second layer region 206 is different from that of the first layer region 205.

[0123] It should be noted that in some embodiments of the present invention, the first layer region 205 may only be provided with the source region 202; it may only be provided with the drain region 203; or it may be provided with both the source region 202 and the drain region 203. When the second layer region 206 is provided, it must appear in both the source region 202 and / or the drain region 203 at the same time as the first layer region 205.

[0124] For example, the first layer region 205 and the second layer region 206 are only disposed in the source region 202, as shown in the reference. Figure 2a .

[0125] For example, the first layer region 205 and the second layer region 206 are only disposed in the drain region 203, as shown in the reference. Figure 2b .

[0126] For example, the first layer region 205 and the second layer region 206 are simultaneously disposed in the source region 202 and the drain region 203, as shown in the reference. Figure 2c .

[0127] For example, the first layer region 205 and the second layer region 206 are disposed in the source region 202, and only the first layer region 205 is disposed in the drain region 203.

[0128] For example, the first layer region 205 and the second layer region 206 are disposed in the drain region 203, and only the first layer region 205 is disposed in the source region 202.

[0129] Here, the doping type of the second layer region 206 is different from that of the first layer region 205 and the third layer region 207.

[0130] Understandably, during the read operation of the memory cell, the doping type of the second layer region 206 is different from that of the first layer region 205 and the third layer region 207, which can form a capacitor between the second layer region 206, the first layer region 205 and the third layer region 207. This capacitor is connected in series with the parasitic capacitance from the gate 204 to the bit line, which reduces the parasitic capacitance of the transistor, thereby increasing the sensing margin of the transistor and improving the reliability of the read security factor.

[0131] In addition, the second layer region 206 is located between the third layer region 207 and the first layer region 205, which can reduce the junction depth at the connection between the bit line and the third layer region 207 and improve the response speed of the transistor.

[0132] For example, when the third layer region 207 of the drain region 203 is connected to the bit line, the junction depth at the connection between the third layer region 207 of the drain region 203 and the bit line can be reduced, thereby improving the response speed of the transistor 20.

[0133] In some embodiments of the present invention, transistor 20 can be an N-type transistor or a P-type transistor.

[0134] For example, in an N-type transistor, the first layer region 205 and the third layer region 207 are both N-type doped, while the second layer region 206 is P-type doped.

[0135] In a P-type transistor, the first layer region 205 and the third layer region 207 are both P-type doped; while the second layer region 206 is N-type doped.

[0136] It is understandable that the doping type of the second layer region 206 is different from that of the third layer region 207, which can reduce the formation rate of minority carriers in the inversion layer between the gate 204 and the channel region 201, thereby reducing the parasitic capacitance from the gate 204 to the bit line.

[0137] In addition, when the doping type of the third layer region 207 is different from that of the second layer region 206, the second layer region 206 and the first layer region 205 deplete each other to reduce the voltage difference between the drain region 203 and the gate 204, and / or between the source region 202 and the gate 204, thereby reducing the gate-induced drain leakage problem.

[0138] In some embodiments of the present invention, the concentration of the second layer region 206 can be adjusted according to actual needs.

[0139] In some embodiments, the maximum doping concentration of the third layer region 207 is greater than the maximum doping concentration of the first layer region 205; the maximum doping concentration of the first layer region 205 is greater than or equal to the maximum doping concentration of the second layer region 206.

[0140] In some embodiments of the present invention, the doping concentrations of the third layer region 207 of the source region 202 and the third layer region 207 of the drain region 203 are similar, both being N1; the doping concentrations of the first layer region 205 of the source region 202 and the first layer region 205 of the drain region 203 are both N2; the doping concentrations of the second layer region 206 of the source region 202 and the second layer region 206 of the drain region 203 are both N3. Here, the doping concentration N1 of the third layer region 207 is greater than the doping concentration N2 of the first layer region 205, i.e., N1 > N2; the doping concentration N2 of the first layer region 205 is greater than or equal to the doping concentration N3 of the second layer region 206, i.e., N2 ≥ N3.

[0141] For example, the doping concentration range of the third layer region 207 of the source region 202 and the third layer region 207 of the drain region 203 can be: 1e19atom / cm 3 Up to 1e21atom / cm 3 The doping concentration range of the first layer region 205 of the source region 202 and the first layer region 205 of the drain region 203 can be: 1e16atom / cm 3 Up to 1e19atom / cm 3 The doping concentration range of the second layer region 206 of the source region 202 and the second layer region 206 of the drain region 203 can be: 1e0atom / cm 3 Up to 1e16atom / cm 3 Here, the atom / cm 3 This indicates the number of atoms contained in each cubic centimeter.

[0142] It should be noted that in some specific examples, after forming the first layer region 205 of the source region 202 and the first layer region 205 of the drain region 203, the second layer region 206 of the source region 202 and the second layer region 206 of the drain region 203, and the third layer region 207 of the source region 202 and the third layer region 207 of the drain region 203, the doping concentration in the overlapping regions between the first layer region 205, the second layer region 206, and the third layer region 207 in the source region 202 or the drain region 203 is relatively complex and may show a situation different from the above doping concentration pattern.

[0143] Therefore, for the sake of rigor, it is hereby defined that the maximum doping concentration of the third layer region 207 of the source region 202 or the drain region 203 is greater than the maximum doping concentration of the first layer region 205 of the source region 202 or the drain region 203; and the maximum doping concentration of the first layer region 205 of the source region 202 or the drain region 203 is greater than or equal to the maximum doping concentration of the second layer region 206 of the source region 202 or the drain region 203.

[0144] It should be noted that the maximum concentration here can be understood as the desired doping concentration to be achieved in manufacturing. Cases where the doping concentration differs from the above-mentioned doping concentration rule due to manufacturing differences or special locations of the structure (such as the boundary between different doping concentrations) are included within the scope of protection of this application.

[0145] In some embodiments of the present invention, the material of the second layer region 206 may be the same as or different from the material of the channel region 201.

[0146] In some embodiments, the material of the second layer region 206 of the source region 202 or the drain region 203 is the same as the material of the semiconductor layer.

[0147] For example, the material of the second layer region 206 of the source region 202 or the drain region 203 and the material of the semiconductor layer both include monocrystalline silicon (Si) or polycrystalline silicon (Poly).

[0148] In some embodiments, the material of the second layer region 206 of the source region 202 or the drain region 203 is different from the material of the semiconductor layer.

[0149] For example, the material of the second layer region 206 of the source region 202 or the drain region 203 includes silicon germanide (SiGe), polycrystalline silicon, or a composite material of silicon germanide and polycrystalline silicon; the material of the semiconductor layer includes monocrystalline silicon.

[0150] In some embodiments of the present invention, the thickness of the second layer region 206 of the source region 202 or the drain region 203 needs to be matched with the total thickness of the transistor. The thickness of the second layer region 206 of the source region 202 or the drain region 203 can be set according to the actual thickness of the transistor or the actual needs of those skilled in the art.

[0151] In some embodiments, the thickness of the second layer region 206 of the source region 202 or the second layer region 206 of the drain region 203 is 10nm-20nm.

[0152] It should be noted that in some embodiments of the present invention, the two ends of the gate 204 and the gate oxide layer 208 may extend to be flush with the third layer region 207 of the source region 202 or extend to the two ends of the third layer region 207 of the drain region 203. However, it is understood that the normal operation of the transistor 20 is guaranteed as long as the projection of the gate 204 and the gate oxide layer 208 along the second direction covers the channel region 201. When the projection of the gate 204 and the gate oxide layer 208 along the second direction extends beyond the channel region 201 to both ends, the more it extends, the larger the overlap area of ​​the projection of the gate 204 and the third layer region 207 in the source region 202 or the third layer region 207 in the drain region 203 along the second direction, and the larger the parasitic capacitance in the transistor 20.

[0153] Based on this, in some embodiments of the present invention, the projection of the gate 204 along the second direction does not completely overlap with the projection of the second layer region 206 along the second direction; the second direction is perpendicular to the first direction and points from the gate 204 to the channel region 201.

[0154] Here, the projection of the gate 204 along the second direction may partially overlap with the projection of the second layer region 206 along the second direction, or it may not overlap with the projection of the second layer region 206 along the second direction at all.

[0155] In order to fulfill the basic functions of a transistor, the projection of the gate 204 along the second direction must completely cover the channel region. The less the projection of the gate along the second direction overlaps with the source or drain region, the smaller the parasitic capacitance of the transistor. In addition, it can also reduce the probability of gate-induced drain leakage problems.

[0156] In practical applications, the projection length of the gate along the second direction can also be set according to process requirements. It should be noted that in this embodiment of the invention, the semiconductor structure may include one or more transistors.

[0157] In some embodiments, such as Figure 3a As shown, the semiconductor structure includes a first transistor 30 and a second transistor 40 arranged side by side and separated by an insulating layer;

[0158] The gate 304 of the first transistor 30 is located on the side of the first transistor 30 away from the insulating layer 50; the gate 404 of the second transistor 40 is located on the side of the second transistor 40 away from the insulating layer 50.

[0159] In some embodiments of the present invention, reference is made to Figure 3a , Figure 3b An insulating layer 50 is provided between the first transistor 30 and the second transistor 40.

[0160] Here, the material of the insulating layer 50 can be silicon dioxide or other insulating materials.

[0161] In the first transistor 30, the channel region 301 includes a first side and a second side; the first side of the channel region 301 can be understood as the side of the first transistor 30 that is away from the insulating layer 50, and the second side of the channel region 301 can be understood as the side of the first transistor 30 that is close to the insulating layer 50. Here, the gate 304 is located on the first side of the channel region 301.

[0162] In the second transistor 40, the channel region 401 includes a first side and a second side; wherein, the first side of the channel region 401 can be understood as the side of the second transistor 40 that is closer to the insulating layer 50; the second side of the channel region 401 can be understood as the side of the second transistor 40 that is farther away from the insulating layer 50; here, the gate 404 is located on the second side of the channel region 401.

[0163] It should be noted that the aforementioned provision of a second layer region 206 for the source region 202 between the third layer region 207 and the first layer region 205 of the source region 202, and / or provision of a second layer region 206 for the drain region 203 between the third layer region 207 and the first layer region 205 of the drain region 203, can both be applied to the first transistor 30 and the second transistor 40. In practical applications, transistors can include different types of transistors. Specifically,

[0164] Depending on the number of gates, transistors can include single-gate transistors and dual-gate transistors.

[0165] Depending on the positional relationship between the gate and the channel region, transistors can also include: pillar gate transistors, semi-all-around gate transistors, and fully all-around gate transistors.

[0166] Based on the cross-sectional shape of the source region, drain region, and channel region in the XZ plane, transistors can include: I-type gate transistors, L-type gate transistors, T-type gate transistors, U-type gate transistors, etc.

[0167] Based on the cross-sectional shape of the source and drain regions in the XZ plane, transistors can include: square transistors, elliptical transistors, semi-circular transistors, etc.

[0168] It should be noted that the cross-sectional shape of the second layer region 206 in the transistor is the same as the (horizontal) cross-sectional shape of the third layer region of the source region and the third layer region of the drain region.

[0169] In some embodiments of the present invention, the transistor includes one of the following types:

[0170] Columnar gate transistor;

[0171] Semi-surround gate transistor;

[0172] All-around gate transistor.

[0173] Among them, in a pillar-type gate transistor, the gate surrounds the channel region in a pillar-like form; in a semi-around-type gate transistor, the gate partially surrounds the channel region; and in a fully around-type gate transistor, the gate fully surrounds the channel region.

[0174] It should be noted that the transistor types in the embodiments of the present invention may include the above-mentioned types, but are not limited thereto.

[0175] here, Figure 3b This is a schematic diagram of yet another semiconductor structure provided in an embodiment of the present invention. For example... Figure 3b As shown, the semiconductor structure also includes a bit line 210 connected to the third layer region 207 of the drain region 203, a first storage capacitor 305 and a second storage capacitor 405 connected to the third layer region 207 of the source region 202. The first electrodes of the first storage capacitor 305 and the second storage capacitor 405 are connected to the third layer region 207 of the source region 202 through a storage capacitor contact 211. The second electrode of the first storage capacitor 305 is connected to a common terminal (not shown in the figure). Here, the first storage capacitor 305 and the second storage capacitor 405 are used to store data.

[0176] Based on the above semiconductor structure, this embodiment of the invention also provides a method for fabricating a semiconductor structure; wherein, the step of forming the semiconductor structure includes:

[0177] Step 1: Forming a memory cell array; each memory cell in the memory cell array includes a transistor extending in a first direction and a memory cell coupled to the transistor;

[0178] Step 2: Form multiple bit lines; the multiple bit lines are coupled to the memory cell and extend in a second direction perpendicular to the first direction, and a corresponding bit line and a corresponding memory cell are coupled to the opposite end of each memory cell in the memory cell in the first direction.

[0179] It should be noted that the technology for forming memory cell arrays and corresponding multiple bit lines is relatively mature, and will not be elaborated here.

[0180] Here, an embodiment of the present invention provides a method for forming a transistor. Figure 4 This is a schematic flowchart illustrating a transistor fabrication method according to an embodiment of the present invention. Figure 4 As shown, the method for forming the transistor includes the following steps:

[0181] Step 401: Provide a semiconductor layer having at least one active pillar;

[0182] Step 402: Form a source / drain region at the first end of the active pillar;

[0183] Step 403: Form a gate on at least one side of the active pillar;

[0184] Step 404: Form a drain region / source region at the second end of the active pillar; wherein the first end and the second end are opposite ends of the active pillar in a first direction, the first direction being the thickness direction of the semiconductor layer; the active pillar between the source region and the drain region constitutes the channel region of the transistor;

[0185] At least one of the source region and the drain region includes a first layer region and a second layer region, and both the source region and the drain region contain a third layer region; the first layer region is located on the side closer to the channel region; the third layer region is located on the side farther from the channel region; the second layer region is located between the first layer region and the third layer region;

[0186] The doping type of the second layer region is different from that of the first layer region and the third layer region, or the second layer region is an intrinsically undoped region.

[0187] It should be understood that Figure 4 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 4 The steps shown can be adjusted in order according to actual needs. Figures 5a to 5c A cross-sectional schematic diagram of the fabrication process of a semiconductor structure provided in an embodiment of the present invention. Figures 6a to 6jThis is a cross-sectional schematic diagram illustrating the fabrication process of another semiconductor structure provided in an embodiment of the present invention. The following is in conjunction with… Figure 4 , Figures 5a to 5c , Figures 6a to 6j The method for fabricating the semiconductor structure provided in the embodiments of the present invention will be described in detail.

[0188] It should be noted that in this embodiment of the invention, the source region and the drain region need to be respectively located on both sides of the channel region; in other words, if the source region is formed in step 402, the drain region needs to be formed in step 404; or, if the drain region is formed in step 402, the source region needs to be formed in step 404. Here, the example of forming the source region in step 402 and the drain region in step 404 is used for illustration; the formation order of steps 402, 403, and 404 can be set according to implementation requirements. In other words, the execution order of each step in the following embodiments is only used to illustrate the present invention and is not intended to limit the scope of the present invention.

[0189] In step 401, as Figure 5a As shown, a semiconductor layer is provided.

[0190] The semiconductor layer has at least one active pillar; the active pillar extends along a first direction; the first direction is the thickness direction of the semiconductor layer.

[0191] For example, the first direction is the Z-axis direction, and the active column extends along the Z-axis direction.

[0192] It should be noted that the extension direction of the active column can be selected according to actual needs; here, we will take the extension of the active column along the Z-axis as an example.

[0193] The semiconductor layer may be made of silicon (Si), germanium (Ge), silicon germanide (SiGe) substrate, etc.; in some specific embodiments, the semiconductor layer may also be silicon-on-insulator (SOI) or germanium-on-insulator (GOI).

[0194] In some embodiments of the present invention, the semiconductor layer may be formed by processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD).

[0195] In step 402, as Figure 5b As shown, a source region 202 is formed at the first end of the active pillar.

[0196] Here, the first layer region 205 can be understood as a lightly doped drain region; the second layer region 206 can be understood as a doped region; or an intrinsically undoped region; in some embodiments, the first layer region 205 and the second layer region 206 can be disposed only in the source region 202; or only in the drain region 203; or simultaneously in the source region 202 and the drain region 203.

[0197] Preferably, the first layer region 205 and the second layer region 206 are only disposed in the drain region 203.

[0198] It should be noted that the first layer region 205 and the second layer region 206 must appear simultaneously in the source region 202 and / or the drain region 203, as previously mentioned, and will not be repeated here.

[0199] Here, both the source region 202 and the drain region 203 contain a third layer region 207; in other words, the third layer region 207 of the source region 202 can be understood as the source; the third layer region 207 of the drain region 203 can be understood as the drain.

[0200] Here, to facilitate understanding of the formation process of the first layer region 205, the second layer region 206, and the third layer region 207, the following embodiments will be described using the example that both the source region 202 and the drain region 203 contain the first layer region 205, the second layer region 206, and the third layer region 207. However, it should be understood that the following description of the placement of the first layer region 205 and the second layer region 206 is only for illustrating the present invention and is not intended to limit the scope of the present invention.

[0201] Based on this, the source region 202 has a first layer region 205, a second layer region 206, and a third layer region 207 arranged in parallel; the first layer region 205 of the source region 202 is located on the side closer to the channel region; the third layer region 207 of the source region 202 is located on the side away from the channel region; the second layer region 206 of the source region 202 is located between the first layer region 205 and the third layer region 207 of the source region 202.

[0202] Here, the first end and the second end of the active pillar are respectively the two opposite ends of the active pillar in a first direction, where the first direction is the thickness direction of the semiconductor layer.

[0203] It should be noted that the material of the second layer region 206 can be the same as or different from the material of the active pillar; when the material of the second layer region 206 is the same as or different from the material of the active pillar, the methods for forming the source region and the drain region are different.

[0204] In this embodiment of the invention, when the material of the second layer region 206 is the same as the material of the active pillar, the source region and the drain region are formed using method one.

[0205] For example, the material of the second layer region 206 and the material of the semiconductor layer both include monocrystalline silicon or polycrystalline silicon.

[0206] When the material of the second layer region 206 is different from the material of the active pillar, the source region and drain region are formed by method two.

[0207] For example, the material of the second layer region 206 includes silicon germanide, polycrystalline silicon, or a composite structure of silicon germanide and polycrystalline silicon; the material of the semiconductor layer includes monocrystalline silicon.

[0208] The following is in conjunction with the appendix Figures 5a-5c Method 1 introduces the formation of source region 202 and drain region 203. Here, refer to... Figure 5a , Figure 5b A first layer region 205, a second layer region 206, and a third layer region 207 of the source region 202 are formed sequentially and parallelly at the first end of the active pillar; specifically,

[0209] Ions of different concentrations are implanted sequentially at the first end of the active pillar near the first surface of the semiconductor layer to form the first layer region 205, the second layer region 206, and the third layer region 207 of the source region 202, respectively.

[0210] In some embodiments, the first layer region 205, the second layer region 206, and the third layer region 207 forming the source region 202 include:

[0211] The first layer region 205, the second layer region 206, and the third layer region 207 of the source region 202 are formed by diffusion or in-situ doping processes.

[0212] For example, firstly, a first layer region 205 of the source region 202 is formed on the side of the first end of the active pillar near the channel region 201 by a diffusion process or an in-situ doping process.

[0213] Secondly, through diffusion or in-situ doping processes, a second layer region 206 of the source region 202 is formed on the side of the first layer region 205 of the source region 202 away from the channel region 201.

[0214] Finally, a third layer region 207 of the source region 202 is formed on the side of the second layer region 206 of the source region 202 away from the first layer region 205 of the source region 202 by diffusion process or in-situ doping process.

[0215] In practical applications, after each diffusion or in-situ doping process, the first layer 205, the second layer 206, and the third layer 207 of the source region 202 typically require annealing. Alternatively, annealing can be performed on each of these layers after each diffusion or in-situ doping operation; or, after three diffusion or in-situ doping operations, all three layers can be annealed simultaneously. The annealing method can be selected based on actual requirements.

[0216] In practical applications, the annealing process is relatively mature, so it will not be elaborated on here.

[0217] Here, the material of the second layer region 206 of the source region 202 and the material of the semiconductor layer both include monocrystalline silicon or polycrystalline silicon.

[0218] In some embodiments, the doped ions of the first layer region 205 and the third layer region 207 of the source region 202 can be N-type ions or P-type ions; the doped ions of the second layer region 206 of the source region 202 can be P-type ions or N-type ions; however, in this embodiment of the invention, the doping type of the second layer region 206 of the source region 202 is different from that of the first layer region 205 and the third layer region 207 of the source region 202; therefore, when the doped ions of the first layer region 205 and the third layer region 207 of the source region 202 are N-type ions, the doped ions of the second layer region 206 of the source region 202 are P-type ions; when the doped ions of the first layer region 205 and the third layer region 207 of the source region 202 are P-type ions, the doped ions of the second layer region 206 of the source region 202 are N-type ions.

[0219] It should be noted that in some other embodiments, when the second layer region 206 of the source region 202 is an intrinsically undoped region, no ion doping operation is performed on the second layer region 206 of the source region 202 during the formation of the second layer region 206 of the source region 202.

[0220] In step 403, refer to Figure 5b This forms the gate and gate oxide layer.

[0221] It should be noted that when the semiconductor structure includes multiple transistors, that is, during the process of forming multiple gates and gate oxide layers, multiple gate isolation structures need to be formed on the semiconductor layer first; wherein, the multiple gate isolation structures are spaced apart from the multiple gates, and the gate isolation structures are used to isolate the multiple gates.

[0222] For example, in some embodiments of the present invention, the method of forming a gate isolation structure may include: forming an isolation oxide layer, depositing a nitride, a mask layer and a shallow trench isolation structure and etching the shallow trench isolation structure, then filling the shallow trench isolation region with oxide, and finally removing the nitride and performing chemical mechanical polishing (CMP) on the filled oxide.

[0223] It should be noted that, in the embodiments of the present invention, the gate isolation structure can be deposited by any suitable deposition process, and the material of the gate isolation structure includes any insulating material, such as silicon nitride, silicon oxynitride, silicon carbide or silicon dioxide.

[0224] Here, to clearly describe the transistor formation process, a semiconductor structure including a transistor is used as an example for illustration. However, it should be noted that this description is only for illustrating the present invention and is not intended to limit the scope of the present invention.

[0225] In some embodiments of the present invention, reference is made to Figure 5b Before forming the gate 204, a gate oxide layer 208 needs to be formed on one side of the active pillar; the gate oxide layer 208 can be used to suppress short-channel effects. Furthermore, setting the thickness of the gate oxide layer 208 to different thicknesses can solve the matching problem of the semiconductor structure under different voltage requirements. Here, the thickness of the gate oxide layer 208 can be set according to the actual needs of the transistor.

[0226] Next, a gate 204 is formed on the side of the gate oxide layer 208 away from the active pillar.

[0227] Here, the material of the gate 204 may include, but is not limited to, polysilicon.

[0228] Gate formation methods include, but are not limited to, PVD, CVD, ALD, etc.

[0229] It should be noted that the thickness of the gate oxide layer 208 is less than the thickness of the gate electrode 204. In practical applications, such as... Figure 5b As shown, the active pillar includes a first end and a second end; here, the material forming the active pillar includes, but is not limited to, single-crystal silicon.

[0230] In step 404, refer to Figure 5cA drain region 203 is formed at the second end of the active post. Here, the drain region 203 has a first layer region 205, a second layer region 206, and a third layer region 207 arranged in parallel. The first layer region 205 is located on the side closer to the channel region. The third layer region 207 is located on the side away from the channel region. The second layer region 206 is located between the first layer region 205 and the third layer region 207.

[0231] The semiconductor layer is thinned from its second surface and in a direction perpendicular to the semiconductor layer to expose the second end of the active pillar away from the first surface of the semiconductor layer; wherein the second surface is the opposite of the first surface.

[0232] Ions of different concentrations are implanted sequentially at the second end of the active pillar near the first surface of the semiconductor layer to form the first layer region 205, the second layer region 206, and the third layer region 207 of the drain region 203, respectively.

[0233] In some embodiments, the first layer region 205, the second layer region 206, and the third layer region 207 forming the drain region 203 include:

[0234] The second layer region 206, the first layer region 205, and the third layer region 207 of the drain region 203 are formed by diffusion or in-situ doping processes.

[0235] For example, firstly, a first layer region 205 of the drain region 203 is formed on the side of the first end of the active pillar near the channel region 201 by a diffusion process or an in-situ doping process.

[0236] Secondly, a second layer region 206 of the drain region 203 is formed on the side of the first layer region 205 away from the channel region 201 through a diffusion process or an in-situ doping process.

[0237] Finally, a third layer region 207 of the drain region 203 is formed on the side of the second layer region 206 away from the first layer region 205 by diffusion process or in-situ doping process.

[0238] In practical applications, after each diffusion or in-situ doping process, the first, second, and third layers of the drain region 203 typically require annealing. Alternatively, after each diffusion or in-situ doping operation, the first layer 205, second layer 206, or third layer 207 of the drain region 203 can be annealed individually. Or, after three diffusion or in-situ doping operations, all three layers can be annealed simultaneously. The annealing method can be selected based on actual requirements.

[0239] In practical applications, the annealing process is relatively mature, so it will not be elaborated on here.

[0240] Here, the material of the second layer region 206 of the drain region 203 and the material of the semiconductor layer both include monocrystalline silicon or polycrystalline silicon.

[0241] It should be noted that in actual process operation, the source region 202 can be formed first and then the drain region 203 can be formed; or the drain region 203 can be formed first and then the source region 202 can be formed. The actual process operation flow can be selected and set according to actual needs.

[0242] Here, the thickness of the second layer region 206 of the drain region 203 is less than the thickness of the third layer region 207 of the drain region 203.

[0243] In some embodiments, the third layer region 207 of the drain region 203 is the drain, which is a heavily doped region; the first layer region 205 of the drain region 203 is a lightly doped region. In other words, the doping concentration of the third layer region 207 of the drain region 203 is greater than the doping concentration of the first layer region 205 of the drain region 203. Here, the doping concentration of the first layer region 205 of the drain region 203 is greater than or equal to the doping concentration of the second layer region 206 of the drain region 203.

[0244] In some embodiments, the dopant ions in the first layer region 205 and the third layer region 207 of the drain region 203 can be N-type ions or P-type ions; the dopant ions in the second layer region 206 of the drain region 203 can be P-type ions or N-type ions; however, the doping type of the second layer region 206 of the drain region 203 is different from that of the first layer region 205 and the third layer region 207 of the drain region 203; therefore, when the dopant ions in the first layer region 205 and the third layer region 207 of the drain region 203 are N-type ions, the dopant ions in the second layer region 206 of the drain region 203 are P-type ions; when the dopant ions in the first layer region 205 and the third layer region 207 of the drain region 203 are P-type ions, the dopant ions in the second layer region 206 of the drain region 203 are N-type ions.

[0245] Furthermore, in the transistor, the third layer region 207 of the source region 202 and the third layer region 207 of the drain region 203 have the same doping type. Based on this, the following example will be used: the first layer region 205 of the source region 202, the third layer region 207 of the source region 202, the first layer region 205 of the drain region 203, and the third layer region 207 of the drain region 203 are doped with N-type ions, while the second layer region 206 of the source region 202 and the second layer region 206 of the drain region 203 are doped with P-type ions.

[0246] It should be noted that in some other embodiments, the second layer region 206 of the drain region 203 can also be an intrinsically undoped region, which has the same function as the above-mentioned P-type ion, and will not be described again here.

[0247] The following is in conjunction with the appendix Figures 6a-6c The method described is to form the source region 202 and the drain region 203 using the second method.

[0248] The process includes forming a source region 202 at the first end of the active pillar and forming a drain region 203 at the second end of the active pillar; comprising:

[0249] like Figure 6a As shown, ion implantation is performed on the first end of the active pillar near the first surface of the semiconductor layer to form the first layer region 205 of the source region 202.

[0250] like Figure 6b As shown, a first material layer 209a is formed on the first layer region 205 of the source region 202, and ion implantation is performed on the first material layer 209a to form the second layer region 206 of the source region 202; as Figure 6c As shown.

[0251] like Figure 6dAs shown, a second material layer 209b is formed on the second layer region 206 of the source region 202, and ion implantation is performed on the second material layer 209b to form the third layer region 207 of the source region 202. (Refer to...) Figure 6e .

[0252] Here, the material of the second layer region 206 of the source region 202 includes silicon germanide, polycrystalline silicon, or a composite material of silicon germanide and polycrystalline silicon; the material of the semiconductor layer includes monocrystalline silicon.

[0253] Next, a gate 204 and a gate oxide layer 208 are formed on at least one side of the channel region 201; the formation process and technology of the gate 204 and the gate oxide layer 208 have been described previously and will not be repeated here. Please refer to [link to relevant documentation]. Figure 6e .

[0254] Next, the semiconductor layer is thinned from its second surface and in a direction perpendicular to the semiconductor layer to expose the second end of the active pillar away from the first surface of the semiconductor layer; wherein the second surface is the opposite of the first surface.

[0255] like Figure 6f As shown, ion implantation is performed on the second end of the active column to form the first layer region 205 of the drain region 203;

[0256] like Figure 6g As shown, a third material layer 209c is formed on the first layer region 205 of the drain region 203, and ion implantation is performed on the third material layer 209c to form the second layer region 206 of the drain region 203; Reference Figure 6h As shown.

[0257] like Figure 6i As shown, a fourth material layer 209d is formed on the second layer region 206 of the drain region 203, and ion implantation is performed on the fourth material layer 209d to form the third layer region 207 of the drain region 203; Reference Figure 6j .

[0258] Here, the material of the second layer region 206 of the drain region 203 includes silicon germanide, polycrystalline silicon, or a composite structure of silicon germanide and polycrystalline silicon; the material of the semiconductor layer includes monocrystalline silicon.

[0259] Here, the thicknesses of the first layer region 205, the second layer region 206, and the third layer region 207 of the drain region 203 can be the same or different, and their specific dimensions can be set according to actual needs.

[0260] In other embodiments, a second layer region 206 is provided in the drain region 203, while when the second layer region 206 is not provided in the source region 202, the third layer region 207 of the source region 202 is in direct contact with the first layer region 205 of the source region 202, such as... Figure 7 As shown; the total thickness of the source region 202 in the first direction can be the same as or different from the total thickness of the drain region 203 in the first direction; the specific dimensions can be set according to actual needs.

[0261] It should be noted that the simulation processing of the transistor (T1) without the second layer region 206 and the transistor (T2) with the second layer region 206 in the embodiments of the present invention is as follows: Figure 8 As shown.

[0262] In some embodiments of the present invention, reference is made to Figure 8 The transistors with a second layer region 206 in the source region 202 and / or drain region 203 have smaller capacitances during accumulation and inversion than the transistors without a second layer region 206 in the source region 202 and / or drain region 203.

[0263] Based on this, it is understandable that adding a second layer region 206 with a different doping type than the first layer region 205 and the third layer region 207 to the source region 202 and / or drain region 203 can reduce the parasitic capacitance of the transistor and improve the reliability of the transistor.

[0264] The semiconductor structure formed by the semiconductor structure fabrication method provided in the above embodiments of the present invention, by setting a first layer region and a second layer region in the source region and / or drain region, and setting a third layer region in both the source region and drain region, and making the doping type of the second layer region different from that of the first layer region and the third layer region, can form a capacitor between the third layer region and the first layer region and the second layer region. This capacitor is connected in series with the parasitic capacitance of the bit line, thereby reducing the parasitic capacitance of the transistor. This increases the sensing margin of the transistor and improves the reliability of the readout security factor. At the same time, it can also reduce the formation rate of minority carriers in the inversion layer between the gate and the channel region, thereby reducing the parasitic capacitance of the gate, increasing the sensing margin, and improving reliability. In addition, it can also reduce the junction depth of the bit line connected to the drain region or the source region, thereby improving the response speed of the transistor.

[0265] On the other hand, the projections of the gate and the second layer region in the second direction do not completely overlap, so that the projections of the gate and the drain region, or the gate and the source region, in the second direction do not overlap; this can reduce the overlapping area, thereby reducing the probability of gate-induced drain leakage problems and improving the reliability of the transistor.

[0266] This invention also provides another semiconductor structure. Figure 9This is a three-dimensional structural diagram of another semiconductor structure provided in an embodiment of the present invention; as shown below. Figure 9 As shown, the semiconductor structure 60 includes:

[0267] A memory cell array; each memory cell in the memory cell array includes a transistor extending in a first direction and a memory cell coupled to the transistor, wherein the transistor includes a semiconductor body extending in the first direction and a gate contacting at least one side of the semiconductor body;

[0268] Multiple bit lines; the multiple bit lines are coupled to the memory cell and extend in a second direction perpendicular to the first direction, and a corresponding bit line and a corresponding memory cell are coupled to the opposite end of each memory cell in the memory cell in the first direction;

[0269] The semiconductor body includes:

[0270] The channel region is located within the semiconductor layer;

[0271] Source region;

[0272] Drain region; wherein the source region and the drain region are respectively the two opposite ends of the channel region in a first direction, the first direction being the direction of the semiconductor layer thickness;

[0273] At least one of the source region and the drain region includes a first layer region and a second layer region, and both the source region and the drain region contain a third layer region; the first layer region is located on the side closer to the channel region; the third layer region is located on the side farther from the channel region; the second layer region is located between the first layer region and the third layer region;

[0274] The doping type of the second layer region is different from that of the first layer region and the third layer region, or the second layer region is an intrinsically undoped region.

[0275] In some embodiments, the angle between the first direction and the second direction is 90 degrees, that is, the first direction and the second direction are perpendicular.

[0276] In some embodiments, the doping type of both the first layer region and the second layer region is N-type doping;

[0277] The second layer region is P-type doped.

[0278] In some embodiments, the doping type of the first layer region and the second layer region is either N-type doping or P-type doping, and the second layer region is an intrinsically undoped region.

[0279] In some embodiments, the doping concentration of the third layer region is greater than the doping concentration of the first layer region; the doping concentration of the first layer region is greater than or equal to the doping concentration of the second layer region.

[0280] In some embodiments, one of the third-layer regions of the source region and the drain region of the transistor is coupled to the memory cell in the corresponding memory cell.

[0281] In some embodiments, another of the third-layer regions of the source and drain regions of the transistor is coupled to a corresponding bit line.

[0282] In some embodiments, the semiconductor structure provided by the present invention includes various types of memory. For example, NAND flash memory, Nor flash memory, static random access memory, dynamic random access memory, ferroelectric memory, phase-change memory, magnetically variable memory, or resistive random access memory. In some embodiments, the semiconductor structure includes dynamic random access memory, and the memory cell includes a storage capacitor;

[0283] One end of the storage capacitor is coupled to the third layer region of the source region of the transistor;

[0284] The bit line is coupled to the third layer region of the drain region of the transistor.

[0285] In some embodiments of the present invention, the storage capacitor may have various structures. In some embodiments, the storage capacitor includes a cup-shaped, cylindrical, or pillar-shaped capacitor.

[0286] For example, the storage capacitor may include a cup-shaped capacitor (CUP), a cylindrical capacitor (CYL), and a pillar-shaped capacitor (PIL). Each of the cup-shaped capacitor (CUP), the cylindrical capacitor (CYL), and the pillar-shaped capacitor (PIL) includes a bottom electrode, a top electrode, and a dielectric layer located between the bottom electrode and the top electrode.

[0287] It should be noted that the bottom electrode is connected to the source region 202 of a transistor in the semiconductor structure, the top electrode of the cup-shaped capacitor CUP is grounded, and the cup-shaped capacitor CUP is used to store the written data.

[0288] It should be noted that, when the areas of the bottom electrodes of the cup-shaped capacitor (CUP), cylindrical capacitor (CYL), and pillar-shaped capacitor (PIL) are equal, the area of ​​the top electrode of the cylindrical capacitor (CYL) is the largest, followed by the top electrode areas of the cylindrical capacitor (CYL) and pillar-shaped capacitor (PIL). Based on this, in some embodiments of the present invention, the cylindrical capacitor (CYL) can be used as the storage unit of the memory, which is beneficial for achieving extremely high memory integration.

[0289] In some embodiments, the semiconductor structure includes a resistive random access memory (RRAM), and the memory cell includes an adjustable resistor connected between the bit line and the source region 202 of a transistor in the semiconductor structure; or, the adjustable resistor is connected between the bit line and the drain region 203 of a transistor in the semiconductor structure, and the adjustable resistor is used to adjust the state of the stored data by the bit line voltage provided by the bit line.

[0290] In the embodiments of the present invention, some common memories are merely exemplified and the scope of protection of the present invention is not limited thereto. Any memory that includes the semiconductor structure provided in the embodiments of the present invention is within the scope of protection of the present invention.

[0291] Another semiconductor structure provided in this embodiment of the invention is formed by the fabrication method of another semiconductor structure provided in the above embodiments. For technical features not disclosed in detail in this embodiment of the invention, please refer to the above embodiments for understanding, and will not be repeated here.

[0292] In some embodiments, the semiconductor structure further includes a resistor;

[0293] The resistor is connected between the bit line and the third layer region of the source region of the transistor, or the resistor is connected between the bit line and the third layer region of the drain region of the transistor. The resistor is used to adjust the state of the data stored in the memory array by the bit line voltage provided by the bit line.

[0294] In the several embodiments provided by this invention, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the various components shown or discussed are coupled or directly coupled to each other.

[0295] The features disclosed in the several method or device embodiments provided by the present invention can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0296] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: At least one transistor, the transistor comprising: The channel region is located within the semiconductor layer; The gate is located at least on one side of the channel region; The source region is located at the first end of the channel region; A drain region is located at the second end of the channel region; wherein the first end and the second end are opposite ends of the channel region in a first direction, the first direction being the direction of the semiconductor layer thickness; At least one of the source region and the drain region includes a first layer region and a second layer region, and both the source region and the drain region contain a third layer region; the first layer region is located on the side closer to the channel region; the third layer region is located on the side farther from the channel region; the second layer region is located between the first layer region and the third layer region; The doping type of the second layer region is different from that of the first layer region and the third layer region, or the second layer region is an intrinsically undoped region.

2. The semiconductor structure according to claim 1, characterized in that, Both the first layer and the third layer are N-type doped. The second layer region is doped with P-type doping.

3. The semiconductor structure according to claim 1, characterized in that, The maximum doping concentration of the third layer is greater than the maximum doping concentration of the first layer; the maximum doping concentration of the first layer is greater than or equal to the maximum doping concentration of the second layer.

4. The semiconductor structure according to claim 1, characterized in that, The projection of the gate along the second direction does not completely overlap with the projection of the second layer region along the second direction; the second direction is perpendicular to the first direction and extends from the gate to the channel region.

5. The semiconductor structure according to claim 4, characterized in that, The projection of the gate along the second direction does not overlap with the projection of the second layer region along the second direction.

6. The semiconductor structure according to claim 1, characterized in that, The material of the second layer region and the material of the semiconductor layer both include monocrystalline silicon or polycrystalline silicon.

7. The semiconductor structure according to claim 1, characterized in that, The material of the second layer region includes silicon germanide, polycrystalline silicon, or a composite material of silicon germanide and polycrystalline silicon; the material of the semiconductor layer includes monocrystalline silicon.

8. The semiconductor structure according to claim 1, characterized in that, The at least one transistor includes a first transistor and a second transistor arranged side by side and separated by an insulating layer; The gate of the first transistor is located on the side of the first transistor that is furthest from the insulating layer; the gate of the second transistor is located on the side of the second transistor that is furthest from the insulating layer.

9. The semiconductor structure according to claim 1, characterized in that, The transistor type includes one of the following: Columnar gate transistor; Semi-surround gate transistor; All-around gate transistor.

10. A semiconductor structure, characterized in that, include: Memory cell array; Each memory cell in the memory cell array includes a transistor extending in a first direction and a memory cell coupled to the transistor, wherein the transistor includes a semiconductor body extending in the first direction and a gate contacting at least one side of the semiconductor body. Multiple bit lines; the multiple bit lines are coupled to the memory cell and extend in a second direction perpendicular to the first direction, and a corresponding bit line and a corresponding memory cell are coupled to the opposite end of each memory cell in the memory cell in the first direction; The semiconductor body includes: The channel region is located within the semiconductor layer; The source region is located at the first end of the channel region; A drain region is located at the second end of the channel region; wherein the first end and the second end are opposite ends of the channel region in a first direction, the first direction being the direction of the semiconductor layer thickness; At least one of the source region and the drain region includes a first layer region and a second layer region, and both the source region and the drain region contain a third layer region; the first layer region is located on the side closer to the channel region; the third layer region is located on the side farther from the channel region; the second layer region is located between the first layer region and the third layer region; The doping type of the second layer region is different from that of the first layer region and the third layer region, or the second layer region is an intrinsically undoped region.

11. The semiconductor structure according to claim 10, characterized in that, Both the third layer and the first layer are N-type doped. The second layer region is doped with P-type doping.

12. The semiconductor structure according to claim 10, characterized in that, The maximum doping concentration of the third layer is greater than the maximum doping concentration of the first layer; the maximum doping concentration of the first layer is greater than or equal to the maximum doping concentration of the second layer.

13. The semiconductor structure according to claim 10, characterized in that, One of the source region and the drain region of the transistor is coupled to the memory cell in the corresponding memory cell.

14. The semiconductor structure according to claim 13, characterized in that, The other of the source region and the drain region of the transistor is coupled to the corresponding bit line.

15. The semiconductor structure according to claim 10, characterized in that, The semiconductor structure includes: dynamic random access memory, ferroelectric memory, phase change memory, magnetic variable memory, or resistive variable memory.

16. The semiconductor structure according to claim 15, characterized in that, The semiconductor structure includes a dynamic random access memory, and the memory cell includes a storage capacitor. One end of the storage capacitor is coupled to the third layer region of the source region of the transistor; The bit line is coupled to the third layer region of the drain region of the transistor.

17. A method for fabricating a semiconductor structure, characterized in that, A memory cell array is formed; each memory cell in the memory cell array includes a transistor extending in a first direction and a memory cell coupled to the transistor; Multiple bit lines are formed; The multiple bit lines are coupled to the memory cell and extend in a second direction perpendicular to the first direction, and a corresponding bit line and a corresponding memory cell are coupled to the opposite end of each memory cell in the memory cell in the first direction; The method for manufacturing the transistor includes: A semiconductor layer is provided, wherein the semiconductor layer has at least one active pillar; A source region is formed at the first end of the active pillar; A gate is formed on at least one side of the active pillar; A drain region is formed at the second end of the active pillar; wherein the first end and the second end are opposite ends of the active pillar in a first direction, the first direction being the thickness direction of the semiconductor layer; the active pillar between the source region and the drain region constitutes the channel region of the transistor; At least one of the source region and the drain region includes a first layer region and a second layer region, and both the source region and the drain region contain a third layer region; the first layer region is located on the side closer to the channel region; the third layer region is located on the side farther from the channel region; the second layer region is located between the first layer region and the third layer region; The doping type of the second layer region is different from that of the first layer region and the third layer region, or the second layer region is an intrinsically undoped region.

18. The method for fabricating a semiconductor structure according to claim 17, characterized in that, The second layer region is formed, including: The second layer region is formed through diffusion or in-situ doping processes.

19. The method for fabricating a semiconductor structure according to claim 18, characterized in that, The material of the second layer is the same as the material of the semiconductor layer; The source region is formed at the first end of the active column; A drain region is formed at the second end of the active post; including: Different concentrations of ions are implanted sequentially at the first end of the active pillar near the first surface of the semiconductor layer to form the first layer region, the second layer region, and the third layer region of the source region, respectively. The semiconductor layer is thinned from its second surface and in a direction perpendicular to the semiconductor layer to expose the second end of the active pillar away from the first surface of the semiconductor layer; wherein the second surface is the opposite of the first surface. Different concentrations of ions are implanted sequentially at the second end of the active column to form the first, second, and third layers of the drain region, respectively.

20. The method for fabricating a semiconductor structure according to claim 18, characterized in that, The material of the second layer is different from the material of the semiconductor layer; The source region is formed at the first end of the active column; A drain region is formed at the second end of the active post; including: Ion implantation is performed on the first end of the active pillar near the first surface of the semiconductor layer to form the first layer region of the source region; A first material layer is formed on the first layer of the source region, and ion implantation is performed on the first material layer to form the second layer of the source region; A second material layer is formed on the second layer of the source region, and ion implantation is performed on the second material layer to form the third layer of the source region; The semiconductor layer is thinned from its second surface and in a direction perpendicular to the semiconductor layer to expose the second end of the active pillar away from the first surface of the semiconductor layer; wherein the second surface is the opposite of the first surface. Ion implantation is performed on the second end of the active post to form the first layer of the drain region. A third material layer is formed on the first layer of the drain region, and ion implantation is performed on the third material layer to form the second layer of the drain region; A fourth material layer is formed on the second layer of the drain region, and ion implantation is performed on the fourth material layer to form the third layer of the drain region.

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