Inverter circuit control method, inverter device, and energy storage apparatus

Abstract

The application belongs to the technical field of inverter control, and provides an inverter circuit control method, an inverter device and an energy storage equipment. The second lower switch tube is controlled to be kept on in the rising stage of the positive half cycle of the output waveform of the voltage output signal, and is kept off in other stages of the whole cycle. The second upper switch tube is controlled to be kept on in the falling stage of the negative half cycle of the output waveform, and is kept off in other stages of the whole cycle. When it is detected that the output waveform enters the rising stage of the positive half cycle or the negative half cycle, the first upper switch tube is controlled to be on or off, and the first lower switch tube is kept off. When it is detected that the output waveform enters the falling stage of the positive half cycle or the negative half cycle, the first lower switch tube is controlled to be on or off, and the first upper switch tube is kept off. The embodiments of the application improve the switching control logic of the first bridge arm and the second bridge arm, and reduce the loss of the inverter circuit under no load.

Description

Technical Field

[0001] This application belongs to the field of converter control technology, and particularly relates to no-load wave generation methods, inverter devices, and energy storage devices applied to converters. Background Technology

[0002] An inverter is a converter that transforms direct current (DC) energy into alternating current (AC). Its principle is to adjust the current direction by turning semiconductor switches on or off, thus converting DC to AC output. In the operation of a traditional inverter, the frequency of the output waveform (e.g., the output voltage waveform) is the power frequency. To improve efficiency, slow semiconductor switches (i.e., slow transistors) that operate at the power frequency and fast semiconductor switches (i.e., fast transistors) that operate at high-frequency switching frequencies are typically used. The slow and fast transistors operate simultaneously and work together.

[0003] However, the simultaneous operation of multiple semiconductor switches during each power frequency operating cycle increases the overall circuit loss, especially when the converter is unloaded, the loss rate will be very significant, resulting in low conversion efficiency. Summary of the Invention

[0004] The purpose of this application is to provide an inverter circuit control method, an inverter device, and an energy storage device, which aims to solve the problem that maintaining multiple transistors in operation when the inverter circuit is unloaded will lead to increased losses and low conversion efficiency.

[0005] The first aspect of this application provides an inverter circuit control method, wherein the inverter circuit includes a first bridge arm formed by a first upper switch and a first lower switch connected in series, and a second bridge arm formed by a second upper switch and a second lower switch connected in series, the method comprising:

[0006] When the output waveform of the voltage output signal of the inverter circuit is in the rising phase of the positive half-cycle, the second lower switch is controlled to remain on during the rising phase of the positive half-cycle, and the second lower switch is controlled to remain off during the other phases of the entire cycle of the output waveform.

[0007] When the output waveform is in the falling phase of the negative half-cycle, the second upper switch is controlled to remain on during the falling phase of the negative half-cycle, and the second upper switch is controlled to remain off during the other phases of the entire cycle.

[0008] When the output waveform is detected to enter the rising phase of the positive half-cycle or the negative half-cycle, the output PWM signal controls the first upper switch to turn on or off, and controls the first lower switch to remain off.

[0009] When the output waveform is detected to enter the falling phase of the positive half-cycle or the negative half-cycle, the output PWM signal controls the first lower switch to turn on or off, and controls the first upper switch to remain off.

[0010] In one embodiment, the output PWM signal controlling the first upper switch to turn on or off includes:

[0011] The voltage output signal of the inverter circuit is sampled to obtain the sampled voltage;

[0012] If the sampled voltage is greater than the target voltage, then the first upper switch is turned off.

[0013] If the sampled voltage is less than the target voltage, then the first upper switch is turned on.

[0014] In one embodiment, the output PWM signal controlling the first lower switch to turn on or off includes:

[0015] The voltage output signal of the inverter circuit is sampled to obtain the sampled voltage;

[0016] If the sampled voltage is greater than the target voltage, then the first lower switch is turned on.

[0017] If the sampled voltage is less than the target voltage, then the first lower switch is turned off.

[0018] In one embodiment, the voltage output signal is a sinusoidal AC voltage with a frequency of 50Hz.

[0019] In one embodiment, before controlling the second lower switch to remain on during the rising phase of the positive half-cycle when the output waveform of the voltage output signal of the inverter circuit is detected to enter the rising phase of the positive half-cycle, the method further includes:

[0020] The system detects whether a load is connected to the output terminal of the inverter circuit. If no load is detected, the system executes the following steps: when the output waveform of the voltage output signal of the inverter circuit is in the rising phase of the positive half-cycle, the system controls the second lower switch to remain on during the rising phase of the positive half-cycle, and controls the second lower switch to remain off during the other phases of the entire cycle of the output waveform.

[0021] In one embodiment, the method further includes:

[0022] If a load is detected connected to the output of the inverter circuit, then

[0023] When the output waveform is detected to enter the positive half-cycle, the second lower switch is controlled to remain on during the positive half-cycle, and the second upper switch is controlled to remain off during the positive half-cycle.

[0024] When the output waveform is detected to enter the negative half-cycle, the second upper switch is controlled to remain on during the negative half-cycle, and the second lower switch is controlled to remain off during the negative half-cycle.

[0025] During each cycle of the output waveform, the output PWM signal controls the first upper switch and the first lower switch to conduct complementaryly.

[0026] In one embodiment, detecting whether a load is connected to the output of the inverter circuit includes:

[0027] The output current of the inverter circuit is detected to determine whether the inverter circuit is connected to a load.

[0028] A second aspect of this application also provides an inverter device, which includes an inverter circuit and a controller.

[0029] The inverter circuit includes a first bridge arm formed by a first upper switch and a first lower switch connected in series, and a second bridge arm formed by a second upper switch and a second lower switch connected in series; and

[0030] The controller is used to execute the inverter circuit control method as described in any of the above.

[0031] In one embodiment, the first bridge arm and the second bridge arm are connected in parallel to form a full-bridge unit, wherein the input terminal of the full-bridge unit is a DC input terminal and the output terminal of the full-bridge unit is an AC output terminal.

[0032] A third aspect of this application also provides an energy storage device, which includes the inverter device described in any of the preceding claims.

[0033] This application provides an inverter circuit control method, inverter device, and energy storage device. The method controls a second lower switch to remain on during the rising phase of the positive half-cycle of the output waveform and off during the rest of the output waveform cycle. Similarly, it controls a second upper switch to remain on during the falling phase of the negative half-cycle of the output waveform and off during the rest of the cycle. When the output waveform enters the rising phase of either the positive or negative half-cycle, the method controls the first upper switch to turn on or off, while keeping the first lower switch off. Conversely, when the output waveform enters the falling phase of either the positive or negative half-cycle, the method controls the first lower switch to turn on or off, while keeping the first upper switch off. By improving the switching control logic of the first and second bridge arms, the switching loss of the fast transistor is reduced to half its original value, while the conduction time of the slow transistor is reduced from the traditional half-cycle to a quarter-cycle, thus reducing conduction losses and lowering the inverter circuit's losses under no-load conditions. Attached Figure Description

[0034] Figure 1 A schematic flowchart of an inverter circuit provided for one embodiment of this application;

[0035] Figure 2 A schematic flowchart of an inverter circuit control method provided in one embodiment of this application;

[0036] Figure 3 A schematic diagram of the output waveform provided for one embodiment of this application;

[0037] Figure 4a , Figure 4b A schematic diagram of the current flow direction when the inverter circuit control method provided in one embodiment of this application is applied to interval A;

[0038] Figure 4c A schematic diagram of the current waveforms of each device in the inverter circuit when the inverter circuit control method provided in one embodiment of this application is applied to interval A;

[0039] Figure 5a , Figure 5b A schematic diagram of the current flow direction when the inverter circuit control method provided in one embodiment of this application is applied to interval B;

[0040] Figure 5c A schematic diagram of the current waveforms of each device in the inverter circuit when the inverter circuit control method provided in one embodiment of this application is applied to interval A;

[0041] Figure 6a , Figure 6b A schematic diagram of the current flow direction when the inverter circuit control method provided in one embodiment of this application is applied to interval C;

[0042] Figure 6c A schematic diagram of the current waveforms of each device in the inverter circuit when the inverter circuit control method provided in one embodiment of this application is applied to interval C;

[0043] Figure 7a , Figure 7b A schematic diagram of the current flow direction when the inverter circuit control method provided in one embodiment of this application is applied to interval D;

[0044] Figure 7c A schematic diagram of the current waveforms of each device in the inverter circuit when the inverter circuit control method provided in one embodiment of this application is applied to interval D;

[0045] Figure 8 A schematic flowchart of another inverter circuit control method provided in one embodiment of this application;

[0046] Figure 9 This is a schematic diagram of the structure of an inverter device provided in one embodiment of this application. Detailed Implementation

[0047] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present application.

[0048] The term "comprising," and any variations thereof, in the specification, claims, and accompanying drawings of this application are intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or apparatus that comprises a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such processes, methods, products, or apparatus. Furthermore, the terms "first," "second," and "third," etc., are used to distinguish different objects, not to describe a specific order.

[0049] This application provides an inverter circuit control method, see [link to relevant documentation] Figure 1 As shown, the inverter circuit includes a first bridge arm 11 formed by a first upper switch Q1 and a first lower switch Q2 connected in series, and a second bridge arm 21 formed by a second upper switch Z1 and a second lower switch Z2 connected in series. The first bridge arm 11 and the second bridge arm 21 are connected in parallel with the DC power supply DC.

[0050] Furthermore, in the inverter circuit, the first bridge arm 11 is connected to an output inductor L. The first end of the output inductor L is connected to the common point of the first upper switch Q1 and the first lower switch Q2 in the first bridge arm 11, and the second end of the output inductor L is connected to an external load, such as load R0.

[0051] Furthermore, in the inverter circuit, a capacitor C is provided between the output inductor L and the load R0. This capacitor C is connected in parallel with the load R0, which can filter the voltage output signal in the inverter circuit and also store energy.

[0052] In one specific application embodiment, the first bridge arm 11, formed by the first upper switch Q1 and the first lower switch Q2 connected in series, can be used to receive high-frequency PWM signals. By sending high-frequency PWM signals to the first upper switch Q1 and the first lower switch Q2, the switching duty cycle of their respective switches is controlled to adjust the output power of the inverter circuit. The second bridge arm 21, formed by the second upper switch Z1 and the second lower switch Z2 connected in series, can be used to receive power frequency PWM signals. By sending power frequency PWM signals to the second upper switch Z1 and the second lower switch Z2, the current direction of their output voltage signals is controlled, thereby adjusting the frequency of the output voltage signals.

[0053] In practical applications, the frequency of the power frequency PWM signal is determined based on the frequency of the voltage output signal of the inverter circuit. For example, if the frequency of the voltage output signal of the inverter circuit is 50Hz, then the frequency of the power frequency PWM signal is 50Hz.

[0054] For details, see Figure 2 As shown, the inverter circuit control method in this embodiment includes steps S100 to S400.

[0055] In step S100, when the output waveform of the voltage output signal of the inverter circuit is in the rising phase of the positive half-cycle, the second lower switch is controlled to remain on in the rising phase of the positive half-cycle, and the second lower switch is controlled to remain off in the other phases of the entire cycle of the output waveform.

[0056] Combined with the waveform diagram of the voltage output signal of the inverter circuit (e.g.) Figure 3 The working principle of the inverter circuit is explained as shown in the figure.

[0057] like Figure 3As shown, for example, the output waveform of the inverter circuit's voltage output signal is divided into four continuous intervals, A, B, C, and D, according to the period T. The X-axis represents time, and the Y-axis represents the amplitude of the voltage output signal. Intervals A and B represent the positive half-cycle waveform of the voltage output signal, while intervals C and D represent the negative half-cycle waveform. Specifically, interval A represents the rising phase of the positive half-cycle, interval B represents the falling phase, interval C represents the falling phase of the negative half-cycle, and interval D represents the rising phase of the negative half-cycle.

[0058] When the output waveform of the detected voltage output signal enters the rising phase of the positive half-cycle (interval A), the second lower switch Z2 of the second bridge arm 21 remains on. At the same time, the second lower switch Z2 remains off during the other phases of the entire cycle of the output waveform (intervals B, C, and D).

[0059] In step S200, when the output waveform is in the falling phase of the negative half-cycle, the second upper switch is controlled to remain on during the falling phase of the negative half-cycle, and the second lower switch is controlled to remain off during the other phases of the entire cycle.

[0060] In this embodiment, if the output waveform is in the falling phase (interval C) of the negative half-cycle, the second upper switch Z1 is controlled to remain on during the falling phase (interval C) of the negative half-cycle, and the second upper switch Z1 is controlled to remain off during the other phases of the entire cycle (intervals A, B, and D).

[0061] In step S300, when the output waveform is detected to enter the rising phase of the positive half-cycle or the negative half-cycle, a PWM signal is output to control the first upper switch to turn on or off, and to control the first lower switch to remain off.

[0062] In this embodiment, when the output waveform enters the rising phase of the positive half-cycle (interval A) or the rising phase of the negative half-cycle (interval D), a corresponding PWM signal is sent to the first upper switch Q1 to control its turn-on or turn-off, while simultaneously controlling the first lower switch Q2 to remain off. By controlling the first lower switch Q2 to remain off, the switching loss of the first switch Q2 in the inverter circuit can be reduced, while the first upper switch Q1 can be turned on or off as needed to adjust the output power of the inverter circuit in the rising phase of the positive half-cycle (interval A) or the rising phase of the negative half-cycle (interval D).

[0063] In step S400, when the output waveform is detected to enter the falling phase of the positive half-cycle or the negative half-cycle, a PWM signal is output to control the first lower switch to turn on or off, and the first upper switch to remain off.

[0064] In this embodiment, when the output waveform enters the falling phase (interval B) of the positive half-cycle or the falling phase (interval C) of the negative half-cycle, a corresponding PWM signal is sent to the first lower switch Q2 to control its turn-on or turn-off, while simultaneously controlling the first upper switch Q1 to remain off. By controlling the first upper switch Q1 to remain off, the switching loss of the first upper switch Q1 in the inverter circuit can be reduced, while the first lower switch Q2 can be turned on or off as needed to adjust the output power of the inverter circuit in the falling phase (interval B) of the positive half-cycle or the falling phase (interval C) of the negative half-cycle.

[0065] In one specific application embodiment, combined with Figure 4a and Figure 4b As shown, when the output waveform enters the rising phase (interval A) of the positive half-cycle, the second upper switch Z1 remains off, the second lower switch Z2 remains on, the first upper switch Q1 is controlled to turn on or off by the PWM signal, and the first lower switch Q2 remains off. When the first upper switch Q1 is on, the current flow is as follows: Figure 4a As shown, the current flowing through the output inductor L continuously increases at this time. When the first upper switch Q1 is turned off, the current flow direction is as follows. Figure 4b As shown, since both the first upper switch Q1 and the first lower switch Q2 are turned off, the current forms a loop through the body diode of the first lower switch Q2, and the current flowing through the output inductor L continues to decrease.

[0066] Combination Figure 4c As shown, the horizontal axis represents the time period, and the vertical axis represents the amplitude. The voltage output signal Vout gradually increases. The current IL flowing through the output inductor L increases when the first upper switch Q1 is turned on and decreases when the first upper switch Q1 is turned off. Simultaneously, the current IC flowing through the capacitor C decreases when the first upper switch Q1 is turned on and increases when the first upper switch Q1 is turned off. The current Idc flowing through the DC power supply DC and the current IQ1 flowing through the first upper switch Q1 decrease to 0 when the first upper switch Q1 is turned off. When the first upper switch Q1 is turned off, the current freewheels through the body diode of the first lower switch Q2, so the current IQ2 flowing through the first lower switch Q2 is reversed. The second upper switch Z1 remains off, and the current IZ1 flowing through the second upper switch Z1 remains 0. The current flowing through the second lower switch Z2 decreases when the first upper switch Q1 is turned off.

[0067] In one specific application embodiment, combined with Figure 5a and Figure 5b As shown, when the output waveform enters the falling phase (interval B) of the positive half-cycle, the second upper switch Z1, the second lower switch Z2, and the first upper switch Q1 are all turned off, while the first lower switch Q2 is controlled to turn on or off by the PWM signal. When the first lower switch Q2 is turned on, the current flow is as follows: Figure 5a As shown, at this time, the current forms a circuit through the body diode of the second lower switch Z2, the first lower switch Q2, the output inductor L, and the capacitor C, and the current flowing through the output inductor L is reversed. When the first lower switch Q2 is turned off, the current flow direction is as follows. Figure 5b As shown, since both the first upper switch Q1 and the first lower switch Q2 are turned off, the current forms a loop through the body diode of the first upper switch Q1, the DC power supply DC, the output inductor L, and the capacitor C. At this time, the current flowing through the output inductor L gradually decreases and approaches 0.

[0068] Combination Figure 5c As shown, the horizontal axis represents the time period and the vertical axis represents the amplitude. The voltage output signal Vout gradually decreases during the falling phase (interval B) of the positive half-cycle. The current IL flowing through the output inductor L reverses when the first lower switch Q2 is turned on, and freewheels through the body diode of the first upper switch Q1 when the first lower switch Q2 is turned off. The first upper switch Q1, DC power supply DC, second lower switch Z2, capacitor C, and output inductor L form a loop, and the current gradually decreases to 0. The current IC flowing through capacitor C gradually decreases to 0 after the first lower switch Q2 is turned off.

[0069] In one specific application embodiment, combined with Figure 6a and Figure 6b As shown, when the output waveform enters the falling phase (interval C) of the negative half-cycle, the second upper switch Z1 remains on, the second lower switch Z2 remains off, the first upper switch Q1 remains off, and the first lower switch Q2 is controlled to turn on or off by the PWM signal. When the first lower switch Q2 is on, the current flow is as follows: Figure 6a As shown, at this time, the current forms a loop through the second upper switch Z1, capacitor C, output inductor L, first lower switch Q2, and DC power supply DC, and the current flowing through the output inductor L gradually increases. When the first lower switch Q2 is turned off, the current flow direction is as follows... Figure 6b As shown, since both the first upper switch Q1 and the first lower switch Q2 are turned off, the current flows through the second upper switch Z1, the capacitor C, the output inductor L, the body diode of the first upper switch Q1, and the second upper switch Z1 to form a circuit. The current flowing through the output inductor L gradually decreases.

[0070] Combination Figure 6cAs shown, the horizontal axis represents the time period and the vertical axis represents the amplitude. During the falling phase (interval C) of the negative half-cycle, the voltage of the voltage output signal Vout gradually decreases from 0V to a negative voltage. At this time, the current IL flowing through the output inductor L reverses when the first switch Q2 is turned on, and gradually decreases to 0 when the first switch Q2 is turned off. The current IC flowing through the capacitor C gradually decreases to 0 after the first switch Q2 is turned off.

[0071] In one specific application embodiment, combined with Figure 7a and Figure 7b As shown, when the output waveform enters the rising phase (interval D) of the negative half-cycle, the second upper switch Z1, the second lower switch Z2, and the first lower switch Q2 are all kept off, while the first upper switch Q1 is controlled to be turned on or off by the PWM signal. When the first upper switch Q1 is turned on, the current flow is as follows: Figure 7a As shown, at this time, the current flows sequentially through the first upper switch Q1, the output inductor L, the capacitor C, the body diode of the second upper switch Z1, and the first upper switch Q1 to form a loop. The current flowing through the output inductor L gradually decreases. When the first upper switch Q1 is turned off, the current flow direction is as follows: Figure 7b As shown, since both the first upper switch Q1 and the first lower switch Q2 are turned off, the current flows sequentially through the body diode of the first lower switch Q1, the output inductor L, the capacitor C, the body diode of the second upper switch Z1, and the DC power supply DC to form a circuit.

[0072] Combination Figure 7c As shown, the horizontal axis represents the time period and the vertical axis represents the amplitude. During the rising phase (interval C) of the negative half-cycle, the voltage of the voltage output signal Vout gradually rises from a negative voltage to 0V. At this time, the current IL flowing through the output inductor L gradually increases through the first upper switch Q1 and gradually decreases to 0 when the first lower switch Q2 is turned off. The current IC flowing through the capacitor C reverses and gradually decreases to 0 after the first upper switch Q1 is turned off.

[0073] In one embodiment, step S300, controlling the first upper switch to turn on or off by outputting a PWM signal, includes:

[0074] The voltage output signal of the inverter circuit is sampled to obtain the sampled voltage;

[0075] If the sampled voltage is greater than the target voltage, then the first upper switch is turned off.

[0076] If the sampled voltage is less than the target voltage, then the first upper switch is turned on.

[0077] During the rising phase of the positive half-cycle (interval A), the voltage of the inverter circuit's output signal is monitored and sampled to obtain a sample voltage. If the sampled voltage is greater than the target voltage, the first upper switch Q1 is turned off. At this time, the current flow in the inverter circuit is as shown in the attached diagram. Figure 4b As shown, the current flowing through the output inductor L decreases, and the voltage of the output signal drops. If the sampled voltage is less than the target voltage, the first upper switch Q1 is turned on. At this time, the current flow in the inverter circuit is as shown in the attached diagram. Figure 4a As shown, as the current flowing through the output inductor L increases, the voltage of the output signal rises.

[0078] During the rising phase of the negative half-cycle (interval D), the voltage of the inverter circuit's output signal is monitored and sampled to obtain a sample voltage. If the sample voltage is greater than the target voltage, the first upper switch Q1 is turned off. At this time, the current flow in the inverter circuit is as shown in the attached diagram. Figure 7b As shown, the current flowing through the output inductor L decreases, and the voltage of the output signal drops. If the sampled voltage is less than the target voltage, the first upper switch Q1 is turned on. At this time, the current flow in the inverter circuit is as shown in the attached diagram. Figure 7a As shown, as the current flowing through the output inductor L increases, the voltage of the output signal rises.

[0079] In one embodiment, step S400, controlling the first lower switch to turn on or off by outputting a PWM signal, includes:

[0080] The voltage output signal of the inverter circuit is sampled to obtain the sampled voltage;

[0081] If the sampled voltage is greater than the target voltage, then the first lower switch is turned on.

[0082] If the sampled voltage is less than the target voltage, then the first lower switch is turned off.

[0083] During the falling phase of the positive half-cycle (interval B), the voltage of the inverter circuit's output signal is monitored and sampled to obtain a sample voltage. If the sample voltage is greater than the target voltage, the first switching transistor Q2 is turned on. At this time, the current flow in the inverter circuit is as shown in the attached diagram. Figure 5a As shown, the current flowing through the output inductor L decreases, and the voltage of the output signal drops. If the sampled voltage is less than the target voltage, the first switch Q2 is turned off. At this time, the current flow in the inverter circuit is as shown in the attached diagram. Figure 5b As shown, as the current flowing through the output inductor L increases, the voltage of the output signal rises.

[0084] During the falling phase of the negative half-cycle (interval C), the voltage of the inverter circuit's output signal is monitored and sampled to obtain a sample voltage. If the sample voltage is greater than the target voltage, the first switching transistor Q2 is turned on. At this time, the current flow in the inverter circuit is as shown in the attached diagram. Figure 6a As shown, the current flowing through the output inductor L decreases, and the voltage of the output signal drops. If the sampled voltage is less than the target voltage, the first switch Q2 is turned off. At this time, the current flow in the inverter circuit is as shown in the attached diagram. Figure 6b As shown, as the current flowing through the output inductor L increases, the voltage of the output signal rises.

[0085] In one embodiment, the target voltage in the above embodiment can be determined by a voltage function relationship. For example, the target voltage can be a sine wave, and its function relationship can be Vref=A*sinα, where A is the amplitude of the target voltage and α is a variable related to the period T.

[0086] In one embodiment, the voltage output signal is a sinusoidal AC voltage with a frequency of 50Hz.

[0087] In this embodiment, by sending a PWM modulation wave with a frequency of power frequency (e.g., 50Hz) to the second bridge arm 21, the voltage output signal of the inverter circuit is a sine wave AC voltage with a frequency of 50Hz.

[0088] Specifically, the switching states of the first upper switch Z1 and the first lower switch Z2 in the second bridge arm 21 can be used to determine the current direction of the voltage output signal of the inverter circuit, and combined with the conduction and cutoff of the first upper switch Q1 and the first lower switch Q2 in the first bridge arm 11, the output waveform can be adjusted, thereby adjusting the output power of the inverter circuit.

[0089] In one embodiment, see Figure 8 As shown, before controlling the second lower switch to remain on during the rising phase of the positive half-cycle when the output waveform of the voltage output signal of the inverter circuit is detected to enter the rising phase of the positive half-cycle, the method further includes step S101.

[0090] In step S101, it is detected whether a load is connected to the output terminal of the inverter circuit. If no load is detected, the following steps are performed: when the output waveform of the voltage output signal of the inverter circuit is in the rising phase of the positive half-cycle, the second lower switch is controlled to remain on during the rising phase of the positive half-cycle, and the second lower switch is controlled to remain off during the other phases of the entire cycle of the output waveform.

[0091] In practical applications, if the load power of the inverter circuit is less than the preset no-load power value (e.g., 2W), it can be considered that the inverter circuit is not connected to a load and is in a no-load state.

[0092] In a specific embodiment, the preset no-load power value can be determined by the output power provided by the inverter circuit. For example, 1 / 100 of the rated power of the inverter circuit can be used as the preset no-load power value.

[0093] In this embodiment, when the output waveform of the voltage output signal of the inverter circuit enters the rising phase of the positive half-cycle, it is detected whether a load is connected to the output terminal of the inverter circuit. If no load is detected, steps S100 to S300 are executed, and the switching transistors of the first and second bridge arms are controlled by the above control method. Because the current is extremely small under no-load conditions, it will not cause excessive conduction losses of the body diode, thus reducing the switching losses of the inverter circuit under no-load conditions.

[0094] In one embodiment, the method further includes:

[0095] If a load is detected connected to the output of the inverter circuit, then

[0096] When the output waveform is detected to enter the positive half-cycle, the second lower switch is controlled to remain on during the positive half-cycle, and the second upper switch is controlled to remain off during the positive half-cycle.

[0097] When the output waveform is detected to enter the negative half-cycle, the second upper switch is controlled to remain on during the negative half-cycle, and the second lower switch is controlled to remain off during the negative half-cycle.

[0098] During each cycle of the output waveform, the output PWM signal controls the first upper switch and the first lower switch to conduct complementaryly.

[0099] In this embodiment, when the output waveform of the inverter circuit's voltage output signal enters the rising phase of the positive half-cycle, if a load is detected connected to the output terminal of the inverter circuit, then when the output waveform enters the positive half-cycle (intervals A and B), the second lower switch Z1 is controlled to remain on during the positive half-cycle, while the second upper switch Z1 remains off during the positive half-cycle, ensuring that the current of the output inductor L is output in the positive direction. When the output waveform enters the negative half-cycle (intervals C and D), the second upper switch Z1 is controlled to remain on during the negative half-cycle, while the second lower switch Z2 is controlled to remain off during the negative half-cycle, controlling the current of the output inductor L to be output in the reverse direction. Furthermore, a PWM signal is output to the first upper switch Q1 and the first lower switch Q2 in each cycle of the output waveform, controlling the first upper switch Q1 and the first lower switch Q2 to conduct complementaryly. When a load is connected to the output of the inverter circuit, if the first lower switch Q2 is not turned on, the voltage will drop too quickly, making effective voltage control impossible. Therefore, it is necessary to keep the first upper switch Q1 and the first lower switch Q2 complementary in conduction to ensure that the load can be powered normally.

[0100] In one embodiment, detecting whether a load is connected to the output of the inverter circuit includes:

[0101] The output current of the inverter circuit is detected to determine whether the inverter circuit is connected to a load.

[0102] In this embodiment, it can be determined whether the output terminal of the inverter circuit is connected to a load based on the output current of the inverter circuit. For example, in a specific application, by continuously monitoring the output current of the inverter circuit, if the output current changes, it is determined that the output terminal of the inverter circuit is connected to a load. At this time, a PWM signal can be output in each cycle of the output waveform to control the first upper switch and the first lower switch to conduct complementaryly, thereby increasing their output power.

[0103] This application embodiment also provides an inverter device, which includes an inverter circuit and a controller 31, in conjunction with... Figure 9 As shown, the inverter circuit includes a first bridge arm 11 formed by a first upper switch Q1 and a first lower switch Q2 connected in series, and a second bridge arm 21 formed by a second upper switch Z1 and a second lower switch Z2 connected in series; the controller 31 is used to execute the inverter circuit control method as described in any of the above.

[0104] In one embodiment, the first bridge arm 11 and the second bridge arm 21 are connected in parallel to form a full-bridge unit, wherein the input terminal of the full-bridge unit is a DC input terminal and the output terminal of the full-bridge unit is an AC output terminal.

[0105] In some specific application embodiments, the positions of the first bridge arm 11 and the second bridge arm 21 can be interchanged. The second bridge arm 21 is controlled by the controller 31 to turn on and off in order to control the direction of the output signal at the AC output terminal, and the first bridge arm 11 is controlled by the controller 31 to turn on and off in order to control the output power of the inverter circuit.

[0106] This application also provides an energy storage device, which includes the inverter device described in any of the above claims.

[0107] In some specific application embodiments, the energy storage power supply in the energy storage device can be the DC power supply in the above embodiments. The energy storage power supply is connected through the inverter circuit in the above embodiments, and the controller executes the inverter circuit control method as described in any of the above embodiments to drive the inverter circuit to convert the DC signal into an AC signal.

[0108] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0109] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0110] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0111] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0112] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An inverter circuit control method, the inverter circuit including a first bridge arm formed by connecting a first upper switch and a first lower switch in series, and a second bridge arm formed by connecting a second upper switch and a second lower switch in series, characterized by, The method comprises: controlling the second lower switch to keep on during the rising stage of the positive half cycle of the output waveform of the voltage output signal of the inverter circuit, and controlling the second lower switch to keep off during other stages of the whole cycle of the output waveform; controlling the second upper switch to keep on during the falling stage of the negative half cycle of the output waveform, and controlling the second upper switch to keep off during other stages of the whole cycle; outputting a PWM signal to control the first upper switch to turn on or off, and control the first lower switch to keep off when detecting that the output waveform enters the rising stage of the positive half cycle or the rising stage of the negative half cycle; outputting a PWM signal to control the first lower switch to turn on or off, and control the first upper switch to keep off when detecting that the output waveform enters the falling stage of the positive half cycle or the falling stage of the negative half cycle.

2. The inverter circuit control method of claim 1, wherein The output PWM signal controlling the first upper switch to turn on or off comprises: sampling the voltage output signal of the inverter circuit to obtain a sampling voltage; controlling the first upper switch to turn off if the sampling voltage is greater than a target voltage; controlling the first upper switch to turn on if the sampling voltage is less than the target voltage.

3. The inverter circuit control method of claim 1, wherein The output PWM signal controlling the first lower switch to turn on or off comprises: sampling the voltage output signal of the inverter circuit to obtain a sampling voltage; controlling the first lower switch to turn on if the sampling voltage is greater than a target voltage; controlling the first lower switch to turn off if the sampling voltage is less than the target voltage.

4. The inverter circuit control method according to any one of claims 1, wherein The voltage output signal is a sine wave alternating voltage with a frequency of 50 Hz.

5. The inverter circuit control method according to any one of claims 1 to 4, characterized by, Before the controlling the second lower switch to keep on during the rising stage of the positive half cycle of the output waveform of the voltage output signal of the inverter circuit when detecting that the output waveform of the voltage output signal of the inverter circuit enters the rising stage of the positive half cycle, the method further comprises: detecting whether the output end of the inverter circuit is connected to a load, and performing the controlling the second lower switch to keep on during the rising stage of the positive half cycle of the output waveform of the voltage output signal of the inverter circuit, and controlling the second lower switch to keep off during other stages of the whole cycle of the output waveform if no load is detected.

6. The inverter circuit control method according to any one of claims 1 to 4, characterized by, The method further comprises: if the output end of the inverter circuit is detected to be connected to a load, controlling the second lower switch to keep on during the positive half cycle, and controlling the second upper switch to keep off during the positive half cycle when detecting that the output waveform enters the positive half cycle; controlling the second upper switch to keep on during the negative half cycle, and controlling the second lower switch to keep off during the negative half cycle when detecting that the output waveform enters the negative half cycle; outputting a PWM signal to control the first upper switch and the first lower switch to turn on complementarily during each cycle of the output waveform.

7. The inverter circuit control method of claim 5, wherein The detecting whether the output end of the inverter circuit is connected to a load comprises: detecting the output current of the inverter circuit to determine whether the inverter circuit is connected to a load.

8. An inverter device, characterized by comprising: The inverter device comprises an inverter circuit and a controller, The inverter circuit comprises a first bridge arm formed by a first upper switch and a first lower switch connected in series, and a second bridge arm formed by a second upper switch and a second lower switch connected in series; and The controller is configured to perform the inverter circuit control method of any one of claims 1-7.

9. The inverter device according to claim 8, wherein The first bridge arm and the second bridge arm form a full-bridge unit in parallel, an input end of the full-bridge unit is a direct-current input end, and an output end of the full-bridge unit is an alternating-current output end.

10. An energy storage device, characterized by, The energy storage device comprises the inverter device of claim 8 or 9.

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