Discarding a value stored in a register in a processor based on processing of a discard register encoding instruction

Abstract

Discarding values ​​stored in registers in a processor based on processing discard register encoding instructions is disclosed. The processor is configured to support the execution of read and / or write instructions, the instructions include discard encoding, and the discard encoding indicates that one or more of its source and / or target register operands will be discarded by the processor. Registers encoded as discarded mean that the data value stored in such registers will not be used by subsequent instructions in the instruction stream, and therefore do not need to be retained. Therefore, such registers can be set to a discard state so that the data values ​​stored in such registers can be ignored to improve performance. As an example, data values ​​for registers with a discard state can be ignored and therefore not stored in a saved context for a process to be switched out, thereby saving memory and improving processing time for process switching.

Description

Technical Field

[0001] The present technology relates to a processor-based system employing a central processing unit (CPU) including one or more processors, each processor being configured to execute computer instructions, and more particularly, including general purpose registers (GPRs) in the processors for storing and accessing values ​​that are source and destination operands of executed instructions. Background Art

[0002] A microprocessor, also referred to as a "processor," performs computing tasks for a variety of applications. A conventional microprocessor includes a central processing unit (CPU) that includes one or more processor cores, also referred to as "processors" or "CPU cores," that execute software instructions. The software instructions instruct the processor to perform operations based on data. The processor executes computer program instructions ("instructions"), also referred to as "software instructions," to perform operations based on data and generate results, which are generated values. Instructions that generate or write generated values ​​are "producer" instructions. The generated values ​​may then be stored in memory to be provided as output to an input / output (I / O) device, or available (i.e., transmitted) as input values ​​to another "consumer" (e.g., read / load) instruction executed by the processor.

[0003] The processor includes instruction processing circuitry configured to decode instructions fetched for a given software process executed by the corresponding processor into decoded instructions to determine the instruction type and the action required. The decoded instructions are placed in one or more instruction pipelines and processed based on the source and destination operands of the decoded instructions in accordance with the instruction set architecture (ISA) of the processor. Traditionally, ISAs have revolved around the use of general purpose registers (GPRs) as source and destination operands, where the ISA encoded in the instruction specifies its source and destination by encoding the GPR number. The values ​​stored in these GPRs are "persistent", meaning that for each GPR, once a given instruction writes a result to it, that value in that GPR remains as an "architecturally required" value for any subsequent instruction that uses that GPR as a source operand. The value stored in the GPR remains available until either a subsequent instruction writes a new value to that GPR, or the processor is "reset". Essentially, for any given software "process", the value in the GPR is considered part of the "state" of that process. Therefore, the processor hardware must maintain the values ​​of the GPRs, and the software must take care of saving and restoring these values ​​when the processor switches between different processes.

[0004] Figure 1is an exemplary set of computer software instructions 100 of a software process 102 that can be executed by a processor. The computer software instructions 100 include instructions I1-11, which include instructions that name a GPR as a source and / or target operand. In this example, instructions I1 and I2 are move (MOV) instructions that move immediate values ​​into registers R0 and R1, respectively. The values ​​in registers R0 and R1 are consumed by an add (ADD) write instruction I3, which loads the values ​​stored in registers R0 and R1, adds the two values ​​together, and stores (i.e., writes) the result in register R2. As seen in the computer software instructions 100, registers R0 and R1 are overwritten by instructions I10 and I11 before the values ​​stored in registers R0 and R1 are accessed again after writing instruction I3. Therefore, in this example, after the execution of instruction I3 is completed, instructions I4-I9 in the software process 102 no longer need the values ​​stored in registers R0 and R1. In short, after the execution of instruction I3 is completed, the values ​​stored in registers R0 and R1 have become obsolete.

[0005] For example, if the instruction execution of computer software instructions 100 is interrupted after executing instruction I3, the operating system software executing on the processor will decide to switch the software process executing on the processor. Before the new software process and its context are switched to the processor for execution, the software handling the process switch will be obliged to save the values ​​currently stored in registers R0-RP, including the values ​​in registers R0 and R1, as part of the context of the software process 102 at the time of the interruption. This allows the previously stored context of the software process 102 that existed at the time of the interruption to be restored in the processor (switched into the processor) when the software process 102 is switched back to the processor to be executed, so that the software process 102 can be executed based on the correct context where it was left at the time of the interruption. This context restoration will include restoring the values ​​stored in registers R0-RP (including registers R0 and R1) of the software process 102 that existed at the time of the interruption. The operating system software must extend the processing cycle, and therefore the performance of the processor, to store and restore the complete context of the interrupted software process 102, even if some values ​​stored in the context, such as the values ​​stored in registers R0 and R1, are never reused after executing instruction I3. Summary of the invention

[0006] Aspects disclosed herein include discarding values ​​stored in registers in a processor based on processing of discard register encoding instructions. Related methods and computer-readable media are also disclosed. The processor is located in a central processing unit (CPU), which may include other processors (also referred to as CPU cores) as a multi-processor CPU. In an exemplary aspect disclosed herein, the processor is configured to support the execution of instructions including discard encoding, which indicates that one or more of its source and / or target register operands will be discarded by the processor. Such instructions may require reading source registers and / or writing target registers. Registers encoded as discarded mean that the data value stored in such registers will not be used by subsequent instructions in the instruction stream, so there is no need to retain. For example, if a particular instruction is the last instruction in the instruction stream to read a data value from a source register indicated by a source operand before the source register is overwritten by another instruction, the data value stored in the source register will not be used after such last instruction. Therefore, such source registers can be discarded by the processor. In response to the processor processing an instruction with a discard encoding, a discard indicator associated with a register indicated as discarded can be set to a discarded state by processing such an instruction to indicate that the data value stored in such a register is no longer used.

[0007] In this way, as an example, the processor sets the discard indicator of the register to the discard state in response to the processing of the discarded encoding instruction, which allows the processor to ignore the data value stored in such a register to improve performance. For example, the data value of the source register with the discarded state can be ignored and not stored in the saved context of the process to be switched out, thereby saving memory and improving the processing time of executing the process switch. As another example, the processor can be configured to release the rename register mapped to the register with the discarded state in the physical register stack, so that such a rename register can be reallocated before such a register is overwritten to reduce the possibility of no available registers that may cause the pipeline to stall. As another example, the processor can be configured to ignore and not use the data value stored in the register with the discarded state when processing subsequent instructions to speculate the use of such data value, because such data value may be invalid. This can reduce the re-execution process that may occur due to the use of invalid data values ​​as the source value of the instruction. The processor can also be configured to generate an exception and / or use a default value of the data value read from the source register in the discarded state.

[0008] As described above, the processor supports instructions that use discard coding as part of its instruction set architecture (ISA). As an example, the ISA can support discard coding of instructions so that the processor discards registers immediately after executing such discard coding instructions. The processor can be configured to recognize such coding as discarding registers immediately after executing such discard coding instructions. As another example, the ISA can support discard coding of instructions so that the processor discards registers after executing a given number of instructions in the instruction stream after such discard coding instructions. The processor can be configured to recognize such coding as discarding registers after executing a given number of instructions encoded in the discard coding instructions in the instruction stream after the discard coding instructions. As another example, the ISA can support discard coding of instructions so that the processor discards registers after a specified event after executing such discard coding instructions. The processor can be configured to recognize such coding as discarding registers after such event occurs, and synchronize the setting of the discard indicator of such registers after such event occurs.

[0009] In this regard, in an exemplary aspect, a processor is provided. The processor is configured to receive a plurality of instructions to be executed in an instruction stream from an instruction memory, the plurality of instructions including at least one instruction, the at least one instruction including a register operand. The processor is also configured to process an instruction from the plurality of instructions and determine whether the processed instruction includes a discard code, the discard code identifying at least one register operand associated with at least one of a plurality of registers in the processor to be discarded. In response to determining that the processed instruction includes a discard code identifying at least one register operand to be discarded, the processor is also configured to set a discard indicator associated with at least one register associated with the at least one register operand to a discard state, the discard state indicating that the at least one register is discarded.

[0010] In another exemplary aspect, a method for discarding a data value stored in a register in a processor is provided. The method includes receiving a plurality of instructions to be executed in an instruction stream from an instruction memory, the plurality of instructions including at least one computer instruction, the at least one computer instruction including a register operand. The method also includes processing an instruction from the plurality of instructions, and determining whether the processed instruction includes a discard code, the discard code identifying at least one register operand associated with at least one of the plurality of registers in the processor to be discarded. In response to determining that the processed instruction includes a discard code identifying at least one register operand to be discarded, the method also includes setting a discard indicator associated with at least one register associated with the at least one register operand to a discard state, the discard state indicating that the at least one register is discarded.

[0011] In another exemplary aspect, a non-transitory computer-readable medium having an instruction program stored thereon is provided, the instruction program including a plurality of computer-executable instructions for execution by a processor. The plurality of computer-executable instructions include: a discard register encoding instruction including an instruction type, one or more register operands, and a discard instruction type, the discard instruction type identifying that at least one register of the one or more register operands is to be discarded by the processor when executed.

[0012] Those skilled in the art will understand the scope of the present disclosure and recognize additional aspects thereof after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0014] Figure 1 is an exemplary set of computer software instructions executable by a processor as an instruction stream, wherein the computer software instructions include named registers in the processor as source and destination operands;

[0015] Figure 2 is an illustration of an exemplary processor-based system including a central processing unit (CPU) including a plurality of CPU cores (i.e., processors), wherein each processor is configured to process a discard register encoding instruction indicating that one or more registers are to be discarded and to set discard indicator(s) for such registers to cause data values ​​stored in such registers to be ignored;

[0016] Figure 3 is a diagram of an exemplary instruction processing circuit that may be included in Figure 2 in each processor of a CPU in the processor, and comprising one or more instruction pipelines for processing computer instructions based on named source and / or destination operands that may be registers in the processor (e.g., general purpose registers (GPRs)), and wherein the processor is configured to process a discard register encoding instruction indicating that one or more registers are to be discarded;

[0017] Figure 4 is a set of computer software instructions executable by a processor as an instruction stream, wherein the computer software instructions include a discard register encoding instruction encoded to instruct the processor to discard a source register identified by a source register operand;

[0018] Figure 5A-5D An example of the instruction format of an operand discard register encoding instruction is shown, which can be used by Figure 2The processor processing in causes the processor to set the discard indicator of the source register to a discard state;

[0019] Figure 6 It shows that it can be Figure 2 A flowchart of an exemplary process executed by a processor in to process a discard register encoding instruction to set a discard indicator for a source register encoded as discard;

[0020] Figure 7 yes Figure 2 Schematic diagram of instruction processing circuitry in which a processor sets a discard indicator for a source register indicated as discarded in response to processing a discard register encoding instruction;

[0021] Figure 8 is another set of computer software instructions executable by a processor as an instruction stream, wherein the computer software instructions include a discard register encoding instruction encoded to instruct the processor to discard a target register identified by a target register operand;

[0022] Fig. 9A An exemplary discard register encoding instruction is shown, which may be used by Figure 2 a processor in the instruction stream to process such that after the processor executes a given number of subsequent instructions in the instruction stream, a discard indicator of the target register is set to a discard state;

[0023] Fig. 9B An exemplary operand discard register encoding instruction is shown, which may be used by Figure 2 The processor in the instruction stream processes to cause the processor to set a discard indicator of a target register to a discarded state after a specified event occurs; and

[0024] Fig.10 is a block diagram of an exemplary processor-based system including a processor configured to process a discard register encoding instruction indicating that one or more registers are to be discarded and to set discard indicators (multiple) for such registers so that data values ​​stored in such registers are ignored, including but not limited to Figure 2 , Figure 3 and Figure 7 The processor in. DETAILED DESCRIPTION

[0025] Aspects disclosed herein include discarding values ​​stored in registers in a processor based on processing of discard register encoding instructions. Related methods and computer-readable media are also disclosed. A processor is located in a central processing unit (CPU), which may include other processors (also referred to as CPU cores) as a multiprocessor CPU. In an exemplary aspect disclosed herein, the processor is configured to support the execution of instructions including discard encoding, which indicates that one or more of its source and / or target register operands will be discarded by the processor. Such instructions may require reading source registers and / or writing target registers. Registers encoded as discarded mean that the data value stored in such registers will not be used by subsequent instructions in the instruction stream, so there is no need to retain. For example, if a particular instruction is the last instruction in the instruction stream that reads a data value from a source register indicated by a source operand before the source register is overwritten by another instruction, the data value stored in the source register will not be used after such last instruction. Therefore, such source registers can be discarded by the processor. In response to the processor processing an instruction with a discard encoding, a discard indicator associated with a register indicated as discarded can be set to a discard state by processing such an instruction to indicate that the data value stored in such a register is no longer used.

[0026] In this way, as an example, the processor sets the discard indicator of the register to the discard state in response to the processing of the discarded encoding instruction, allowing the processor to ignore the data value stored in such a register to improve performance. For example, the data value of the source register with the discarded state can be ignored and not stored in the saved context of the process to be switched out, thereby saving memory and improving the processing time of executing the process switch. As another example, the processor can be configured to release the rename register mapped to the register with the discarded state in the physical register stack, so that such a rename register can be reallocated before such a register is overwritten to reduce the possibility of no available registers that may cause the pipeline to stall. As another example, the processor can be configured to ignore the data value stored in the register with the discarded state and not use it for the speculative use of such data value when processing subsequent instructions, because such data value may be invalid. This can reduce the re-execution process that may occur due to the use of invalid data values ​​as the source value of the instruction. The processor can also be configured to generate an exception and / or use a default value of the data value read from the source register in the discarded state.

[0027] Before discussing an example in which a processor discards a value stored in a register in the processor based on processing a discard register encoding instruction, reference is first made to Figure 2 and Figure 3 An exemplary processing-based system including a CPU having one or more processors is discussed.

[0028] Figure 2 2 is a diagram of an exemplary processor-based system 200 including a central processing unit (CPU) 202. The CPU 202 is configured to issue memory requests (i.e., data read and data write requests) to a memory system 204 including a cache memory system 206 and a main memory 208. For example, the main memory 208 may be a dynamic random access memory (DRAM) provided in a separate DRAM chip. The CPU 202 includes one or more corresponding processors 210(1)-210(N), where 'N' is a positive integer representing the number of processors included in the processor 210. As will be discussed in more detail below, each of the processors 210(1)-210(N) is configured to discard values ​​stored in its registers (e.g., general purpose registers (GPRs)) based on a discard register encoding instruction in a processing instruction stream. The CPU 202 may be packaged in an integrated circuit (IC) chip 212. The cache memory system 206 includes one or more cache memories 214(1)-214(X), which may be at different levels in the processor-based system 200 and are logically located between the processors 210(1)-210(N) and the main memory 208, where 'X' is a positive integer representing the number of processors included in the CPU 202. A memory controller 216 controls access to the main memory 208.

[0029] For example, a processor 210(1)-210(N) as a requesting device may issue a data request 218 to read data in response to processing a load instruction. The data request 218 includes a target address of the data to be read from the memory. Taking the processor 210(1) as an example, if the requested data is not in the dedicated cache memory 214(1), which can be considered as a level 1 (L1) cache memory (i.e., a cache miss to the cache memory 214(1)), the dedicated cache memory 214(1) sends the data request 218 to the shared cache memory 214(X) shared with all processors 210(1)-210(N) via the interconnection bus 220 in this example, which can be a level (3) cache memory. The data requested in the data request 218 is ultimately either implemented in the cache memory 214(1)-214(X) or implemented in the main memory 208 if it is not contained in any cache memory 214(1)-214(X).

[0030] Figure 3 It shows that it can be Figure 2 The instruction processing circuit 300 is provided in the processor 210 of the CPU 202 in the embodiment. The instruction processing circuit 300 includes one or more instruction pipelines 10-1 N, for processing the retrieved computer instruction 306F, for example, the instruction is retrieved by the instruction fetch circuit 308 from a series of instructions 306 stored in the instruction cache memory 310 or the instruction memory 312 for execution. The instruction fetch circuit 308 is configured to provide the retrieved instruction 306F to one or more instruction pipelines 10-1 before the retrieved instruction 306F reaches the execution circuit 316 to be executed. N In the example, the instruction stream 314 in the instruction processing circuit 300 is pre-processed. The instruction pipeline 10-1 is provided across different processing circuits or stages of the instruction processing circuit 300. N , to pre-process and process the fetched instruction 306F in a series of steps that can be executed concurrently to increase throughput before the execution circuit 316 executes the fetched instruction 306F.

[0031] As will be discussed in more detail below, instruction 306F in instruction stream 314 may include a discard register encoding instruction that is encoded such that when processed by processor 210, the encoded register operand in the discard register encoding instruction is discarded by processor 210. This allows data values ​​stored in registers indicated as having discarded data to be ignored in various processes to improve performance of CPU 202.

[0032] Continue to refer Figure 3 The instruction processing circuit 300 includes an instruction decoding circuit 318 configured to decode the retrieved instruction 306F retrieved by the instruction fetch circuit 308 into a decoded instruction 306D to determine the required instruction type and action. The decoded instruction 306D is placed in the instruction pipeline I0-I N, and is subsequently provided to a renaming circuit 320 in the instruction processing circuit 300 to determine whether any register names in the decoded instruction 306D need to be renamed to break any register dependencies that would prevent parallel or out-of-order processing. The renaming circuit 320 is configured to call a register mapping table (RMT) 322 to rename logical source register operands and / or write destination register operands of the decoded instruction 306D to available physical registers 324(0)-324(X) (P0, P1, ..., PX) in a physical register file (PRF) 326. The RMT 322 includes a plurality of mapping entries 323(0)-323(P), each mapping entry mapping to (i.e., associated with) a corresponding logical register R0-RP. Each of the mapping entries 323(0)-323(P) is configured to store corresponding mapping information PR(0)-PR(P) in the form of address pointers in this example to point to physical registers 324(0)-324(X) in the PRF 326. Each physical register 324(0)-324(X) in the PRF 326 is configured to store data entries for source and / or destination register operands of the decoded instruction 306D.

[0033] The instruction processing circuit 300 further includes a register access (RACC) circuit 328 configured to access physical registers 324(0)-324(X) in the PRF 326 based on mapping entries of logical registers R0-RP in the RMT 322 that are mapped to source register operands of the decoded instruction 306D to retrieve the values ​​generated from the executed instruction 306E in the execution circuit 316. In addition, in the instruction processing circuit 300, at the instruction pipelines I0-I N A scheduler circuit 330 is provided in the instruction processing circuit 300 and is configured to store the decoded instruction 306D in the reserved entry until all source register operands for the decoded instruction 306D are available. A write circuit 332 is also provided in the instruction processing circuit 300 to write or commit the resulting value from the executed instruction 306E back to a memory, such as the PRF 326, the cache memory system 206 ( Figure 2 ) or main memory 208 ( Figure 2 ).

[0034] Continue to refer Figure 3 , the instruction processing circuit 300 also includes a flow control prediction circuit 334. The flow control prediction circuit 334 is configured to speculatively predict the result of the condition of the fetched conditional flow control instruction 306F, such as a conditional branch instruction, which controls whether the taken or not taken path in the instruction control flow path of the instruction stream 314 is fetched back to the instruction pipeline 10-1. NIn this way, the condition of the fetched conditional flow control instruction 306F does not have to be resolved when executed by the execution circuit 316 before the instruction processing circuit 300 can continue to speculatively process the fetched instruction 306F. The prediction made by the flow control prediction circuit 334 can be provided to the instruction fetch circuit 308 as prediction information 337 for use by the instruction fetch circuit 308 in determining the next instruction 306 to fetch.

[0035] However, if it is determined that the condition of the conditional flow control instruction 306F is mispredicted when the conditional flow control instruction 306F is executed in the execution circuit 316, the instruction 306F is interrupted. The speculatively retrieved instructions 306F processed in the instruction processing circuit 300 after the conditional flow control instruction 306F are flushed because the direction of the program flow changes and will not include the processing of these instructions. Load or store instructions 306F that may be invalid or cannot be accessed for some other reason for the calculated memory location may also cause the flushing of subsequent instructions 306F. Under these conditions, the program flow of the instruction processing circuit 300 is interrupted, and the instruction processing circuit 300 returns to the previous state. The previous state to which the processor is restored depends on the type of the interrupt instruction 306F, and can be a state that exists before the interrupted instruction 306F ("interrupt instruction") or as a result of the interrupted instruction 306F. In particular, the present disclosure relates to restoring a previous state of the RMT 322 to restore a logical register to physical register mapping that has been altered by instructions entering the instruction processing circuitry 300 after the interrupt instruction 306 (“younger instructions”).

[0036] Continue to refer Figure 3 , the instruction processing circuitry 300 also includes an optional re-order buffer (ROB) 336 that contains an entry ("ROB entry") 338(1)-338(N) assigned to each instruction 306 that the instruction processing circuitry 300 is processing but has not yet committed. The ROB 336 may be used if the CPU is an out-of-order processor that is configured to execute instructions 306F out of order. A ROB index identifies the location of each ROB entry 338(1)-338(N) in the ROB 336. The ROB entries 338(1)-338(N) are assigned to the instructions 306 in program order. When the ROB entries 338(1)-338(N) are initially assigned, the ROB index for each instruction 306 is reported back to the instruction processing circuitry 300. In this way, the instruction processing circuitry 300 may associate a ROB index with an interrupt instruction. Information regarding changes to the mapping of logical registers R0 -RP as a result of instruction 306 is stored in ROB entries 338 ( 1 )- 338 (N) corresponding to instruction 306 .

[0037] The ROB 336 includes a read pointer RD_PTR pointing to the ROB index of the ROB entry 338(1)-338(N), from which information about the oldest uncommitted instruction 306 is read when the oldest uncommitted instruction 306 is committed. The read pointer RD_PTR is updated each time the uncommitted instruction 306 is committed. The ROB 336 also includes a write pointer WR_PTR, which indicates the ROB index of the last ROB entry 338(1)-338(N) to which the information about the youngest uncommitted instruction 306 is written. When the instruction 306 updates the logical register to physical register mapping of the logical registers R0-RP in the RMT 322, the ROB index of the ROB entry 338(1)-338(N) of the instruction 306 is associated with the logical register R0-RP. Therefore, the ROB index corresponding to the last instruction 306 that updates the mapping of the logical registers R0-RP is stored in the RMT 322 together with the entry for the logical registers R0-RP.

[0038] Continue to refer Figure 3 , the instruction processing circuit 300 also includes a commit mapping table (CMT) 340 that stores a logical register to physical register mapping for each logical register R0-RP of the processor 210 as a result of committing the instruction 306. The CMT 340 is updated only when the instruction 306 is committed. The CMT 340 is not changed by restoring the RMT 322 in response to a flush. The instruction processing circuit 300 also includes a mapping control circuit 342 that includes a register renaming recovery circuit (RRRC) 344 for controlling the recovery of the RMT flush. The mapping control circuit 342 is configured to distribute the new ROB entries 338(1)-338(N) to the instruction pipelines I0-I1. N The mapping control circuit 342 also de-allocates the ROB entries 338(1)-338(N) when the oldest uncommitted instruction 306 is committed. This includes moving the read pointer RD_PTR to the next oldest uncommitted instruction.

[0039] As described above and discussed in more detail below, the processor 210 may be configured to process the discard register encoding instruction 306 in the instruction stream 314 to indicate that the logical registers R0-RP are discarded. In this example, the RMT 322 is appended with the discard indicators 346(0)-346(P) to provide storage for recording and tracking the discard status of the logical registers R0-RP by the processor 210 based on the processing of the discard register encoding instruction 306. For example, the discard indicators 346(0)-346(P) may be one bit in size and configured to store a '1' bit to indicate that the associated logical register R0-RP is in a discarded state, which is intended to be discarded, and a '0' bit to indicate that the associated logical register R0-RP is in a non-discarded state, which is intended to be non-discarded. The processor 210 may be configured to set the discard indicators 346(0)-346(P) of the logical registers R0-RP to the discarded state when so encoded in the processed discard register encoding instruction 306. The processor 210 may be configured to set the discard indicators 346(0)-346(P) of the logical registers R0-RP to a non-discarded state when the logical registers R0-RP are overwritten by a subsequent instruction after executing the discard register encoding instruction 306, which causes the discard indicators 346(0)-346(P) to be set to a discarded state.

[0040] Continue to refer Figure 3As described above and discussed in more detail below, the processor 210 may also be configured to record a discard state in response to processing a discard register encoding instruction 306 in the instruction stream 314 within the ROB 336. In this example, the ROB 336 may be appended with a discard indicator 348(0)-348(P) associated with the corresponding ROB entry 338(1)-338(N) to provide an indication to the processor 210 that the instruction in the given ROB entry 338(1)-338(N) has a register operand that is set to be discarded by the processor 210 in response to processing the discard register encoding instruction 306. For example, the discard indicator 348(0)-348(P) may be one bit in size and configured to store a '1' bit to indicate that the associated instruction having the operand of the logical register R0-RP is in a discard state intended to be discarded, and a '0' bit to indicate that the associated instruction having the operand of the logical register R0-RP is in a non-discarded state intended to be non-discarded. In this manner, if the processor 210 performs a flush operation in response to an interrupt event, the discard indicators 348(0)-348(P) may be referenced to restore the RMT 322 to a state that existed prior to the interrupt. The discard indicators 348(0)-348(P) may be used by the processor 210 to determine the ROB entry 338(1)-338(N) having, for example, the oldest instruction entry that has the discard indicators 348(0)-348(P) set to a non-discarded state, such that the RMT 322 is restored to instruction values ​​that have been committed and not executed on discarded data values ​​from the logical registers R0-RP.

[0041] Figure 4 It can be done by Figure 3 The instruction processing circuit 300 of the processor 210 in the embodiment of the present invention is a set of computer software instructions 400 of an instruction stream 402 executed as an instruction stream 314 by the instruction processing circuit 300 of the processor 210, wherein the computer software instructions 400 include a discard register encoding instruction. The computer software instructions 400 include instructions I1-11, which include instructions that name GPR as source and / or target operands. In this example, instructions I1 and I2 are move (MOV) instructions that move immediate values ​​as data values ​​to source registers R0 and R1 identified by corresponding source register operands in instructions I1 and I2, respectively. These data values ​​loaded into registers R0 and R1 are consumed by an add (ADD) instruction I3, which accesses the values ​​stored in registers R0 and R1 and adds the two values ​​together to store (i.e., write) the result into a target register R2 identified by a target register operand R2 in instruction I3.

[0042] As seen in computer software instructions 400, registers R0 and R1 are overwritten by instructions I10 and I11 before the values ​​stored in registers R0 and R1 are accessed again after writing instruction I3. At this point, in this example, instruction I3 is encoded as a discarded register encoding instruction. In this example, this is represented by their instruction type "ADD.OS", which indicates an add instruction with a ".O" tag, and the ".O" tag indicates a discarded register encoding instruction, while ".S" means a source register. As an example, this tag can be used for a compiler compatible with ISA, which includes a discarded register encoding instruction according to the required format. As will be discussed below, other discarded encoding formats are also possible. In this example, instruction I3 is encoded as a discarded register encoding instruction with an "ADD.OS" instruction type, which means that after processing instruction I3, processor 210 will discard all provided source registers, which are registers R0 and R1 in this example. As described below, in response to processor 210 processing instruction I3, registers R0 and R1 will be indicated as containing discarded data values, so that these data values ​​can be ignored for various performance reasons. The reason this is possible in this example is because, as shown in computer software instructions 400, after execution of instruction I3 is complete, instructions I4-I9 do not access registers R0 and R1 as source registers before the data values ​​stored in registers R0 and R1 are overwritten by instructions I10 and I11.

[0043] As will be discussed in more detail below, the processor 210's ability to handle discarded register encoding instructions allows the processor 210 to later ignore data values ​​stored in such registers to improve performance. For example, data values ​​of source registers marked as discarded may be ignored and not stored in the saved context of the process being switched out, thereby saving memory and improving processing time for performing process switches. For example, if execution of computer software instructions 400 is interrupted after executing instruction I3, the operating system software executing on the processor 210 may decide to switch the software process executing on the processor 210. Before the new software process and its context are switched to the processor 210 for execution, the software handling the process switch will be obligated to save the values ​​currently stored in the physical registers P0-PX at the time of the interruption, including mappings to RMT 322 ( Figure 3) as part of the context of the current process. This allows the previously stored context of the software process that existed at the time of the interruption to be restored (switched to) in the processor 210 when the previous software process is switched back to the processor 210 for execution, so that the software process can be executed based on the current context where it was left at the time of the interruption. However, if registers R0 and R1 in RMT 322 are designated as obsolete, the data values ​​stored in the physical registers P0-PX mapped to registers R0 and R1 will be obsolete and therefore do not need to be stored for the current context. Therefore, the operating system software can avoid spending processing cycles storing data for obsolete registers to save processing time and memory.

[0044] Figure 5A An exemplary instruction format 500 of a register discard register encoding instruction 502 according to an exemplary ISA is shown. In this example, the instruction format 500 has an instruction type of "INST.OS". The '.O' extension in the instruction type INST indicates to the processor 210 that the instruction 502 has discard register encoding information. The '.S' extension in the instruction type INST indicates to the processor 210 that the instruction 502 has been encoded to discard all source registers identified by the source register operand. The instruction format 500 includes a destination register operand OP.T 508. The instruction format 500 also includes one or more source register operands OP.S1-OP.S X 510, which indicates 'X' source register operands. In this example, the '.O.S' extension appended to the instruction type INST indicates that the source register operands OP.S1-OP.S X All source registers identified by 510 will be discarded by the processor 210 . Figure 5A Also shown is an example of an ADD instruction 504 encoded with instruction type "ADD.OS" according to instruction format 500, which names a target source operand R2 and two source register operands R1 and R0 as being discarded. As an example, processor 210 may be configured to cause source register operands OP.S1-OP.S0 to be discarded after executing register discard register encoding instruction 502. X The identified source register is discarded.

[0045] Figure 5BAnother exemplary instruction format 520 of a register discard register encoding instruction 522 according to an exemplary ISA is shown. In this example, the instruction format 520 has an instruction type of "INST.OS#". The '.O' extension in the instruction type INST indicates to the processor 210 that the instruction 522 has discard register encoding information. The '.S' extension in the instruction type INST indicates to the processor 210 that the instruction 522 has been encoded to discard all source registers identified by the source register operand. The '.#' extension in the instruction type INST indicates to the processor 210 that the source registers identified by the source register operand to be discarded will be discarded by the processor 210 after the processor 210 executes the instruction after the identified number of instructions (#). The instruction format 520 includes one or more source register operands OP.S1-OP.S X 530 , which represents 'X' source register operands. The instruction format 520 includes a target register operand OP.T 528 . Figure 5A Also shown is an example of an ADD instruction 524 encoded with an instruction type "ADD.OS3" 526 according to an instruction format 520 that names a target source operand R2 and two source register operands R1 and R0 as discarded. The encoding of the ADD instruction 524 instructs the processor 210 to discard the source registers identified by the source register operands R1, R0 to be discarded after executing the third instruction after the ADD instruction 524 in the instruction stream.

[0046] Figure 5C Another exemplary instruction format 540 of a register discard register encoding instruction 542 according to an exemplary ISA is shown. In this example, the instruction type INST of the instruction format 540 is not like Figure 5A The instruction format 540 includes one or more source register operands OP.O.S1-OP.OS X 550, which indicates 'X' source register operands. The '.O' extension is optional and is used when needed to encode instruction 542 to indicate that the source registers identified by such encoded source register operands are to be discarded. Instruction format 540 includes a destination register operand OP.T 548, which in this example is register R2. Figure 5C Also shown is an example of an ADD instruction 544 encoded with instruction type 'ADD' 546 according to the instruction format 540 naming the source register R0 as being discarded. This is encoded by the source register operand encoding 'R0.0' in the ADD instruction 544.

[0047] Figure 5DAnother exemplary instruction format 560 of a register discard register encoding instruction 562 according to an exemplary ISA is shown. In this example, the instruction type INST of the instruction format 560 is not like Figure 5A The instruction format 560 includes one or more source register operands OP.O.#S1-OP.O.#S2. X 570, which indicates 'X' source register operands. The '.O' extension is optional and is needed to encode the instruction 562 to indicate that the source register identified by such encoded source register operand is to be discarded. The '.#' extension in the instruction type INST indicates to the processor 210 that the source register identified by the source register operand to be discarded will be discarded by the processor 210 after the processor 210 executes the instructions after the identified number of instructions (#). The instruction format 560 includes a destination register operand OP.T 568, which in this example is register R2. Figure 5D Also shown is an example of an ADD instruction 564 encoded with instruction type 'ADD' 566 according to instruction format 560, register R0 will be discarded after the processor 210 executes three (3) instructions following the ADD instruction 564 in the instruction stream. This is encoded by the source register operand encoding 'R0.0.3' in the ADD instruction 564.

[0048] Figure 6 It shows that it can be Figure 2 Flowchart of an exemplary process 600 executed by the processor 210 in the embodiment of the present invention to process a discard register encoding instruction to set a discard indicator for a source register encoded as discard. The process includes the processor 210 receiving a plurality of instructions 306 in an instruction stream 314 from the instruction memory 312 or the instruction cache memory 310 to be executed ( Figure 6 602 in FIG. 60). Instruction 306 may include at least one instruction including a register operand as a source and / or a destination operand. Processor 210 processes instruction 306 in its instruction processing circuit 300 ( Figure 6 The processor 210 may also be configured to determine whether the processed instruction 306 includes a source register operand ( Figure 6 In response to determining that the processed instruction 306 includes a source register operand ( Figure 6 ), the processor 210 may optionally be configured to first determine whether the discard indicators 346(0)-346(P) associated with the source registers R0-RP associated with the source register operands in the processed instruction 306 indicate a discard state ( Figure 6In response to determining that the discard indicators 346(0)-346(P) associated with the source registers R0-RP associated with the source register operands in the processed instruction 306 indicate a discard state ( Figure 6 ), the processor 210 may, for example, generate an exception for the processed instruction 306 or use a default value for the value of the source operand ( Figure 6 ), and the process ends ( Figure 6 Alternatively, the processor 210 may be configured to generate and return a predetermined data value (eg, all zeros) for the processed instruction 306 that associates a source register operand with a source register R0-RP in a discarded state.

[0049] However, in response to determining that the discard indicators 346(0)-346(P) associated with the source registers R0-RP associated with the source register operands in the processed instruction 306 do not indicate a discard state ( Figure 6 ), the processor 210 determines whether the processed instruction 306 includes a discard code that identifies at least one register operand ( R0 -RP ) associated with at least one logical register in the processor 210 that is to be discarded. Figure 6 In response to the processor 210 determining that the processed instruction 306 includes a discard encoding that identifies at least one register operand to be discarded, the processor 210 sets the discard indicators 346(0)-346(P) associated with the logical registers R0-RP associated with the register operands identified as being discarded to a discard state, indicating that the data values ​​stored in such logical registers R0-RP are discarded ( Figure 6 ), and the process ends ( Figure 6 As an example, once it has been determined that the instruction identifying the register operand to be discarded has itself been submitted or executed, the processor 210 may be configured to set the discard indicators 346(0)-346(P) associated with the logical registers R0-RP associated with the register operand identified as being discarded to a discarded state. This information may be provided by the scheduler circuit 330, for example, at Figure 3 The instruction processing circuit 300 is provided in.

[0050] Processor 210 may also be configured to set discard indicators 348 ( 0 )- 348 (P) associated with processed instructions 306 entered in ROB entries 338 ( 1 )- 338 (N) in ROB 336 to be referenced in the event that ROB 336 is used to restore an instruction flush of RMT 322 .

[0051] As previously described and described below, the processor 210 may also refer to the discard indicators 346(0)-346(P) when processing an instruction 306 that includes a source register operand that names a logical register R0-RP as a source to determine whether a data value stored in the source logical register R0-RP is discarded. The source logical register R0-RP should not be discarded because the instruction stream 314 should only have a discard register encoding instruction 306 that encodes a discarded logical register R0-RP when it is known that no other accesses will be made to the logical register R0-RP in subsequent instructions as a source before the logical register R0-RP is overwritten. For example, a compiler or programmer would be accused of encoding an instruction as a discard register encoding instruction 306 when it is known that no other instructions will name the discarded logical register R0-RP as a source operand in subsequent instructions before the logical register R0-RP is overwritten. However, in the event that an error is introduced by a programmer, compiler, or other source, processor 210 may also be configured to generate an exception in response to an instruction 306 being processed that names a logical register R0-RP as a source operand that is determined to be discarded based on its associated discard indicators 346(0)-346(P).

[0052] If the instruction 306 subsequently processed by the processor 210 is an instruction for a target register operation that names a logical register R0-RP to be written, the processor 210 may also be configured to set the discard indicators 346(0)-346(P) associated with the target register R0-RP associated with the target register operand to a non-discarded state. This is because the data value that the processor 210 writes to the target register R0-RP associated with the target register operand of the subsequent instruction 306 is current and not discarded. In this way, if the logical register R0-RP being written is named in the source register operand in the subsequent instruction 306 to be executed, the data value stored in the logical register R0-RP will not be returned, but an abnormal or predetermined data value will be returned, as described above.

[0053] As described above, the processing of the discard register encoding instruction 306 in the processor 210 records the logical registers R0-RP as discarded and available for other applications. For example, the logical registers R0-RP in the discarded state allow the processor 210 to determine such state and ignore the data values ​​stored in such logical registers R0-RP to improve performance. For example, the data values ​​stored in the logical registers R0-RP are indicated as being in the discarded state according to their corresponding discard indicators 346 (0)-346 (P), and these data values ​​can be ignored and not stored in the saved context for the process being switched out, thereby saving memory and improving the processing time of performing process switching. For example, the operating system software executed by the processor 210 can enable the processor 210 to determine that the currently executed process is scheduled to switch to the next process. In response, the processor 210 can be configured to store the current context of the currently executed process. The stored context can include the data values ​​in the logical registers R0-RP stored in the PRF 326 and the mapping information PR (0)-PR (P) stored in the RMT 322. In this way, when the currently executed process that was switched out is later switched back to the instruction processing circuit 300 for execution, the state of the processor 210 for such process including the logical registers R0-RP previously stored in the PRF 326 and the mapping information PR(0)-PR(P) stored in the RMT 322 can be restored. In this way, the discard indicator 346(0)-346(P) of each logical register R0-RP can be referenced to determine whether it indicates a discarded state when saving the current context. The data value of any logical register R0-RP having an associated discard indicator 346(0)-346(P) indicating a discarded state can be ignored and not saved, thereby saving memory storage space and saving memory access processing time in process switching.

[0054] As another example of how the processor 210 can ignore data values ​​associated with logical registers R0-RP in a discarded state, the processor 210 can be configured to release renamed physical registers 324(0)-324(X) in the PRF 326 that are mapped to logical registers R0-RP with a discarded state so that such renamed physical registers 324(0)-324(X) can be reallocated before being overwritten. This can reduce the likelihood that no physical registers 324(0)-324(X) are available for an instruction 306 being processed that has a target register (which can cause a pipeline stall) until the physical registers 324(0)-324(X) become available. In response to the processor 210 determining that the processed instruction 306 includes a target register operand associated with a logical register R0-RP in a discarded state, the processor 210 can be configured to reclaim the mapping information PR(0)-PR(P) in the RMT 322 associated with the target logical register R0-RP so that it can be used to rename another target operand in another processed instruction 306. As another example of how the processor 210 can ignore data values ​​associated with logical registers R0-RP that indicate being in a discarded state, the processor 210 can be configured to ignore and not use data values ​​stored in physical registers 324(0)-324(X) associated with logical registers R0-RP that have a discarded state when processing subsequent instructions for speculative use of such data values ​​because such data values ​​may be invalid. This can reduce re-execution processing that may occur due to using invalid data values ​​as source values ​​for instructions 306.

[0055] As described above, processor 210 may be configured to set discard indicators 348(1)-348(P) in ROB 336 to restore the state of RMT 322 in response to an exception that causes an instruction flush. Figure 7 yes Figure 3322, ROB 336, CMT 340, and mapping control circuit 342 of instruction processing circuit 300 in FIG. 324. When a flush occurs due to an interrupt instruction 306, as described above, instruction processing circuit 300 provides a flush indicator 347 indicating one or more instructions 306 in instruction processing circuit 300. Instruction processing circuit 300 also provides a ROB index of ROB entries 338(1)-338(N) of the interrupt instruction 306, which may be referred to herein as an "interrupt instruction indicator." The flush indicator 347 and the interrupt instruction indicator are received by RRRC 344 to control RMT flush recovery. The interrupt instruction indicator points to the ROB index of ROB entries 338(1)-338(N) of the interrupt instruction 306 that caused the flush. Based on the interrupt instruction indicator, the oldest flush instruction entry identified by the oldest flush instruction pointer indicates the oldest instruction in ROB 336 to be flushed. In the recovery of RMT 322, the oldest flush instruction 306 indicated by the oldest flush instruction entry in ROB entries 338(1)-338(N) and any younger instructions identified in ROB 336 will be flushed. Depending on the instruction type of interrupt instruction 306, interrupt instruction 306 may be the oldest instruction to be flushed. Alternatively, depending on the instruction type, interrupt instruction 306 may not be flushed. In this case, interrupt instruction 306 is the youngest surviving instruction. Any logical register to physical register mapping changes caused by the flushed instruction must be negated (i.e., undone) to restore RMT 322 to the desired previous state. As described above, processor 210 can be configured to also check the obsolete indicators 348(0)-348(P) in instructions that are not determined to be flushed in ROB entries 338(1)-338(N) to ensure that their corresponding instructions are not obsolete. If they are obsolete, such instructions should also be flushed to restore RMT 322.

[0056] Further references Figure 7 , illustrating example states of the RMT 322 , the ROB 336 , and the CMT 340 . Figure 7The RMT 322 in has entries assigned to logical registers R0-R5. The column entries in each row indicate, for each of the logical registers R0-R5, the logical register number (LOG), the physical register number (PHY) to which the logical register R0-R5 is mapped, and the ROB index (IDX) of the ROB entry 338(1)-338(N) of the instruction 306 that caused the logical register to physical register mapping of the logical registers R0-R5. The ROB 336 is a table including rows for each ROB entry 338(1)-338(N). Each of the ROB entries 338(1)-338(N) includes a corresponding index (IDX), a logical register number (LOG) of a logical register R0-RP whose mapping is changed by the instruction 306 associated with the ROB entry 338(1)-338(N), a new physical register (P_NEW) to which the logical register R0-RP is mapped, and an old physical register (P_OLD) to which the logical register R0-RP was previously mapped. The ROB 336 is shown as ROB entries 338(1)-338(N) with ROB index AI. The CMT 340 includes an entry for each logical register R0-RP, with logical registers R0-R5 shown. Each entry in the CMT 340 includes a logical register number (LOG) and a corresponding physical register (PHY) to which its associated logical register R0-RP is mapped.

[0057] As the last committed instruction 306 is stored in program order in ROB entries 338(1)-338(N), information about any logical register to physical register mappings of logical registers R0-RP is updated. The logical register to physical register mapping of each logical register R0-RP whose mapping is updated as a result of the instruction 306 to be flushed must be restored to the state of the mapping that existed at the time of the interrupt instruction 306. Each ROB entry 338(1)-338(N) contains information about the logical register mapping changes caused by the particular instruction 306 to which that ROB entry 338(1)-338(N) is assigned. Because the information in the ROB entries 338(1)-338(N) includes both the new physical registers (P_NEW) and the old physical registers (P_OLD) to which the logical registers R0-RP are mapped, the information from the ROB entries 338(1)-338(N) can be used to negate ("undo") or recreate ("redo") the logical mappings of any (multiple) logical registers R0-RP that were updated since the last instruction 306 was submitted. All ROB entries 338(1)-338(N) that have ROB indexes from the oldest flushed instruction 306 and younger instructions 306 may have changed the logical register to physical register mappings of the logical registers R0-RP. Therefore, when the flush indicator 347 is received from the instruction processing circuitry 300, the ROB index associated with each logical register mapping in the RMT 322 is compared with the oldest flush instruction pointer to identify all logical registers R0-RP that are mapped to new physical registers P0-PX due to the instruction 306 to be flushed.

[0058] The instruction may also be encoded as a discard register encoding instruction to instruct the processor 210 to discard a target register to be used as a source register by a subsequent instruction 306. For example, Figure 8 It can be done by Figure 3 The instruction processing circuit 300 of the processor 210 in the embodiment of the present invention is a set of computer software instructions 800 of an instruction stream 802 executed as an instruction stream 314 by the instruction processing circuit 300 of the processor 210, wherein the computer software instructions 800 include a discard register encoding instruction. The computer software instructions 800 include instructions I1-I11, which include instructions that name GPR as source and / or target operands. In this example, instructions I1 and I2 are move (MOV) instructions, which move immediate values ​​as data values ​​into registers R0 and R1, respectively. These data values ​​loaded into registers R0 and R1 are consumed by an add (ADD) instruction I3, which is an instruction and loads the data values ​​stored in registers R0 and R1, and adds the two values ​​together, and stores (i.e., writes) the result in register R2.

[0059] As seen in computer software instructions 800, register R2 written by add instruction I3 is named by the source register operand in load (LOAD) instruction I4. Register R2 is not used as a source register in any other instruction after instruction I4 until register R2 is overwritten by instruction I10. At this point, in this example, instruction I3 is encoded as a discard register encoding instruction. After instruction I4 is executed, target register operand R2 is encoded as discarded. This is represented in this example by "R2.0.1" encoded for target register operand R2 in instruction I3, where '0' means discarding logical register R2 for processor 210, and '1' means that processor 210 discards register R2 after executing the next (1) instruction in instruction stream 802 (in this example, instruction I4).

[0060] Fig. 9A Another exemplary instruction format 900 of a register discard register encoding instruction 902 according to an exemplary ISA is shown. In this example, the instruction format 900 has an instruction type INST. The instruction format 900 includes a target register operand OP.TO# 908 in the instruction 902. The 'O' in the target register operand OP.TO# 908 indicates a discard encoding of the target register OP.T, and the '#' is encoded with a number that indicates the number of subsequent instructions in the instruction stream following the instruction encoded in the instruction format 900 to discard the named target register OP.T. The instruction format 900 also includes one or more source register operands OP.S1-OP.S X 910, which represents 'X' source register operands. Fig. 9A Also shown is an example of an ADD instruction 904. In the example of instruction 904, there are two source register operands, R1 and R0. According to the instruction format 900 that the named target register R2 is to be discarded, the ADD instruction 904 is encoded as an instruction type 'ADD' 906. This is encoded by the source register operand encoding 'R2.0.1' in the ADD instruction 904. The encoding '1' indicates the number of subsequent instructions in the instruction stream after the ADD instruction 904 to discard the named target register R2.

[0061] Fig. 9BAnother exemplary instruction format 920 of a register discard register encoding instruction 922 according to an exemplary ISA is shown. In this example, the instruction format 920 has an instruction type INST. The instruction format 920 includes a target register operand OP.TOE# 928 in the instruction 922. The 'O' in the target register operand OP.TOE# 928 represents a discard encoding of the target register OP.T, and the "E#" is encoded with an event number corresponding to an event that occurs in the processor 210, which, when the event occurs, triggers the processor 210 to discard the named target register OP.T. Examples of such events include the next read of a register. For example, a given instruction may declare its target register to become discarded after the next instruction that reads such a register completes, which is consistent with Fig. 9A In contrast to the instruction format 900 in the example, Fig. 9A In this example, the destination register becomes obsolete after '#' subsequent instructions are completed. Instruction format 920 also includes one or more source register operands OP.S1-OP.S X 930, which represents 'X' source register operands. In the example of instruction 922, there are two source register operands R1 and R0. Fig. 9B Also shown is an example of an ADD instruction 924 encoded with instruction type 'ADD' 926 according to the instruction format 920 that names the target register R2 to be discarded. This is encoded by the source register operand encoding 'R2.O.E4' in the ADD instruction 544. The encoding '.E4' indicates event number '4' and the processor 210 will discard the target register R2 after event number '4' occurs.

[0062] Fig.10 is a block diagram of an exemplary processor-based system 1000 including a processor 1002 (e.g., a microprocessor) including an instruction processing circuit 1004 configured to process a discard register encoding instruction indicating that one or more registers are to be discarded and to set discard indicators (multiple) for such registers to cause data values ​​stored in such registers to be ignored, including but not limited to Figure 2 , Figure 3 and Figure 7 The processor 210 and the instruction processing circuit 300 in FIG. As an example, the instruction processing circuit 1004 may be Figure 3 and Figure 7 The processor-based system 1000 may be one or more circuits included in an electronic board, such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing pad, a mobile device, or any other device, and may represent, for example, a server or a user's computer.

[0063] In this example, the processor-based system 1000 includes a processor 1002. The processor 1002 represents one or more general-purpose processing circuits, such as a microprocessor, a central processing unit, etc. More specifically, the processor 1002 may be an EDGE instruction set microprocessor or other processor that implements an instruction set that supports explicit consumer naming to pass the value generated by the execution of the producer instruction. The processor 1002 is configured to execute the processing logic in the instruction to perform the operations and steps discussed herein. In this example, the processor 1002 includes an instruction cache 1008 for temporary, fast access memory storage of instructions accessible to the instruction processing circuit 1004. Instructions retrieved or pre-retrieved from a memory (such as from the main memory 1010 via the system bus 1012) are stored in the instruction cache 1008. The instruction processing circuit 1004 is configured to process instructions retrieved into the instruction cache memory 1008 and process the instructions for execution. The processor 1002 may include a local cache memory 1014 to store cache data in the main memory 1010. A cache memory 1016 external to the processor 1002 may also be provided between the local cache memory 1014 and the main memory 1010 to provide a cache memory system 1018 .

[0064] The processor 1002 and the main memory 1010 are coupled to a system bus 1012 and may interconnect peripheral devices included in the processor-based system 1000. As is well known, the processor 1002 communicates with these other devices by exchanging address, control, and data information on the system bus 1012. For example, the processor 1002 may transmit a bus transaction request to a memory controller 1019 in the main memory 1010 as an example of a slave device. Although not shown in FIG. Fig.10 1010, but multiple system buses 1012 may be provided, each of which constitutes a different structure. In this example, the memory controller 1019 is configured to provide memory access requests to the memory array 1020 in the main memory 1010. The memory array 1020 is composed of an array of storage bit cells for storing data. As non-limiting examples, the main memory 1010 may be a read-only memory (ROM), a flash memory, a dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM)), and a static memory (e.g., a flash memory, a static random access memory (SRAM), etc.).

[0065] Other devices may be connected to the system bus 1012. Fig.10As shown, as examples, these devices may include main memory 1010, one or more input devices 1022, one or more output devices 1024, a modem 1026, and one or more display controllers 1028. (Multiple) input device 1022 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. (Multiple) output device 1024 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Modem 1026 may be any device configured to allow data to be exchanged to and from network 1030. Network 1030 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LAN), wireless local area networks (WLAN), wide area networks (WAN), Bluetooth TM The modem 1026 may be configured to support any type of communication protocol desired. The processor 1002 may also be configured to access the display controller(s) 1028 via the system bus 1012 to control information sent to one or more displays 1032. The display(s) 1032 may include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.

[0066] Fig.10 The processor-based system 1000 in the embodiment of the present invention may include a set of instructions 1034, which are to be executed by the processor 1002 for any application desired according to the instructions. The instructions 1034 may include discard register encoding instructions and may be stored in the main memory 1010, the processor 1002 and / or the instruction cache 1008 as examples of non-transitory computer-readable media 1036. The instructions 1034 may also reside completely or at least partially within the main memory 1010 and / or within the processor 1002 during their execution. The instructions 834 may also be sent or received over the network 1030 via the modem 1026, so that the network 1030 includes the computer-readable medium 1036.

[0067] Although the computer-readable medium 1036 is shown as a single medium in the exemplary embodiment, the term "computer-readable medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of instructions. The term "computer-readable medium" should also be taken to include any medium that can store, encode, or carry a set of instructions for execution by a processing device and cause the processing device to perform any one or more methods of the embodiments disclosed herein. Therefore, the term "computer-readable medium" should be taken to include, but is not limited to, solid-state memories, optical media, and magnetic media.

[0068] The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be formed by hardware components, or may be implemented in machine executable instructions, which may be used to cause a general or special purpose processor programmed with the instructions to perform the steps. Alternatively, the steps may be performed by a combination of hardware and software.

[0069] The embodiments disclosed herein may be provided as a computer program product or software, which may include a machine-readable medium (or computer-readable medium) having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform a process according to the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes: a machine-readable storage medium (e.g., a ROM, a random access memory ("RAM"), a disk storage medium, an optical storage medium, a flash memory device, etc.); etc.

[0070] Unless otherwise specifically noted and as is apparent from the foregoing discussion, it is understood that throughout the specification, discussions utilizing terms such as "processing," "computing," "determining," "displaying," and the like refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within a computer system's registers and memories into other data similarly represented as physical quantities within a computer system's memories or registers or other such information storage, transmission, or display devices.

[0071] The algorithms and displays presented herein are not inherently related to any particular computer or other device. According to the teachings herein, various systems can be used together with the program, or it may prove convenient to construct a more specialized device to perform the required method steps. The structures required for various these systems will be apparent from the above description. In addition, the embodiments described herein are not described with reference to any particular programming language. It should be understood that various programming languages ​​can be used to implement the teachings of the embodiments described herein.

[0072] Those skilled in the art will further recognize that the various illustrative logical blocks, modules, circuits, and algorithms described in conjunction with the embodiments disclosed herein may be implemented as electronic hardware, instructions stored in a memory or another computer-readable medium and executed by a processor or other processing device, or a combination of the two. As an example, the components of the distributed antenna system described herein may be used in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein may be any type and size of memory and may be configured to store any type of information required. In order to clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functions. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the entire system. A technician may implement the described functionality in different ways for each specific application, but such implementation decisions should not be interpreted as causing a deviation from the scope of the present embodiment.

[0073] The various illustrative logical blocks, modules, and circuits described in conjunction with the embodiments disclosed herein may be implemented or executed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. In addition, the controller may be a processor. The processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0074] The embodiments disclosed herein may be embodied in hardware and in instructions stored in hardware, and may reside in, for example, RAM, flash memory, ROM, electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. Alternatively, the storage medium may be integrated into the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and the storage medium may reside in a remote station, a base station, or a server as discrete components.

[0075] It should also be noted that the operational steps described in any exemplary embodiment of this article are described to provide examples and discussions. The described operations can be performed in many different sequences other than the sequence shown. In addition, the operations described in a single operational step can actually be performed in multiple different steps. In addition, one or more operational steps discussed in the exemplary embodiment can be combined. Those skilled in the art will also understand that any of a variety of technologies and techniques can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be cited throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0076] Unless otherwise stated, any method presented herein should not be construed as requiring that its steps be performed in a specific order. Therefore, in the event that a method claim does not actually recite the order in which its steps are to be followed, or in the event that the steps are not otherwise explicitly stated in the claims or specification to be limited to a specific order, no specific order is intended to be implied.

[0077] It is obvious to those skilled in the art that various modifications and changes may be made without departing from the spirit or scope of the present invention. Since those skilled in the art may think of modifications, combinations, sub-combinations and changes of the disclosed embodiments that contain the spirit and essence of the present invention, the present invention should be interpreted as including everything within the scope of the attached claims and their equivalents.

Claims

1. A processor configured to: receiving, from an instruction memory, a plurality of instructions to be executed in an instruction stream, the plurality of instructions including at least one instruction including a register operand; processing an instruction from the plurality of instructions; determining whether the processed instruction includes a discard code identifying at least one register operand associated with at least one of a plurality of registers in the processor that is to be discarded; as well as responsive to determining that the processed instruction includes the discard encoding identifying at least one register operand to be discarded, setting a discard indicator associated with the at least one register associated with the at least one register operand to a discard state, the discard state indicating that the at least one register is discarded; determining whether the processed instruction includes a source register operand; as well as In response to determining that the processed instruction includes the source register operand, determining whether the discard indicator associated with a source register associated with the source register operand indicates a discard state: In response to determining that the discard indicator associated with the source register associated with the source register operand indicates a discard status: An exception is generated for the processed instruction.

2. The processor of claim 1 , further configured to execute an operating system process to: determining that a current process in the processor is to be switched to a next process to be executed in the processor; In response to determining that the current process in the processor is to be switched to the next process to be executed in the processor, storing a current context for the current process includes: For each physical register of a plurality of physical registers in the processor, determining whether the discard indicator is set to a discard state for the physical register; as well as In response to the discard indicator being set to a discard state for the physical register: A data value is not stored in the physical register in the current context for the current process.

3. The processor of claim 1 , further comprising: a plurality of physical registers, each physical register being configured to store a data value; a register mapping table including a plurality of mapping entries associated with a corresponding plurality of logical registers, each mapping entry of the plurality of mapping entries being configured to store mapping information mapping its corresponding logical register to a physical register of the plurality of physical registers; The processor is further configured to: determining whether the processed instruction includes a target register operand; and In response to determining that the processed instruction includes the target register operand: renaming a mapping entry in the plurality of mapping entries in the register mapping table for a logical register associated with the target register operand to a logical register in the plurality of logical registers; as well as The processor is configured to: In response to determining that the processed instruction includes the discard encoding identifying at least one register operand to be discarded, at least one mapping entry of the plurality of mapping entries in the register mapping table associated with the at least one register operand is retired.

4. The processor of claim 1 , configured to: in response to determining that the processed instruction includes the discard encoding identifying at least one register operand to be discarded: determining whether all instructions of the plurality of instructions that depend on the at least one register associated with the at least one register operand have been committed; and In response to determining that all instructions of the plurality of instructions that depend on the at least one register associated with the at least one register operand have been committed: The discard indicator associated with the at least one register associated with the at least one register operand is set to a discard state, the discard state indicating that the at least one register is discarded.

5. The processor of claim 1 , further configured to: determining whether the processed instruction is an instruction having a destination register operand; and In response to determining that the processed instruction is an instruction having the target register operand: writing a data value indicated by the processed instruction for the target register operand to a target register of the plurality of registers associated with the target register operand; and The discarding indicator associated with the at least one register associated with the target register operand is set to a non-discarding state, the non-discarding state indicating that the target register is non-discarding.

6. The processor of claim 1, wherein the plurality of registers comprises a plurality of general purpose registers (GPRs).

7. The processor of claim 1 , further comprising: a plurality of physical registers, each physical register being configured to store a data value; as well as a register mapping table comprising a plurality of mapping entries associated with a corresponding plurality of logical registers and a plurality of discard indicators, each of the plurality of mapping entries being configured to store mapping information mapping its corresponding logical register to a physical register of the plurality of physical registers, wherein each of the plurality of discard indicators is associated with a mapping entry of the plurality of mapping entries; The processor is configured to, in response to determining that the processed instruction includes the discard encoding identifying at least one register operand to be discarded, set a discard indicator in the register mapping table associated with the logical register associated with the at least one register operand to a discard state, the discard state indicating that the logical register is discarded.

8. The processor of claim 7, further comprising: a plurality of re-order buffer (ROB) entries, each ROB entry being assigned to an instruction processed in the processor that has not yet been committed, each ROB entry in the plurality of ROB entries further comprising a discard indicator configured to store a discard status; The processor is further configured to, in response to determining that the processed instruction includes an obsolete encoding that identifies at least one register operand as obsolete, set an obsolete indicator in a ROB entry in the reorder buffer to be obsoleted, the ROB entry having an instruction having a register operand associated with the logical register.

9. The processor of claim 8, further configured to: receiving a flush indicator indicating a flush event for one or more instructions in the processor based on an interrupt instruction; In response to receiving the flush indicator, determining whether the instruction in the ROB entry in the reorder buffer that is later than the interrupting instruction has a discard indicator indicating a discard status for a logical register; and In response to the instruction in the ROB entry in the reorder buffer that is later than the interrupt instruction having the discard indicator indicating the discard status, the plurality of mapping entries in the register mapping table from the next oldest ROB entry to the ROB entry in the reorder buffer that is later than the next oldest ROB entry and has the discard indicator indicating the discard status are restored to previous mapping information.

10. The processor of claim 1, configured to: determining whether the processed instruction includes the discard code, the discard code identifying at least one register operand associated with at least one register of the plurality of registers, the at least one register operand to be discarded after execution of the instruction in the instruction stream following the processed instruction; and In response to determining that the processed instruction includes the discard encoding identifying at least one register operand to be discarded, setting the discard indicator associated with the at least one register associated with the at least one register operand to a discard state, the discard state indicating that the at least one register is discarded after execution of the processed instruction.

11. The processor according to claim 1 , configured to: determining whether the processed instruction includes the discard code, the discard code identifying all register operands associated with at least one register of the plurality of registers that are to be discarded following execution of the instruction in the instruction stream following the processed instruction; and In response to determining that the processed instruction includes the discard encoding identifying that all register operands are to be discarded, setting a discard indicator associated with a register associated with each of the register operands to a discard state, the discard state indicating that, following execution of the processed instruction, the at least one register is discarded.

12. The processor of claim 1, configured to: determining whether the processed instructions include a processed instruction including the discard code, the discard code identifying at least one register operand associated with at least one register of the plurality of registers, the at least one register operand to be discarded after a certain number of instructions in the instruction stream following the processed instruction in the instruction stream; and In response to determining that the processed instruction includes the discard code, the discard code identifying that at least one register operand is to be discarded after the certain number of instructions in the instruction stream that follow the processed instruction in the instruction stream, setting the discard indicator associated with the at least one register associated with the at least one register operand to a discard state, the discard state indicating that the at least one register is discarded after execution of the certain number of instructions in the instruction stream that follow the processed instruction in the instruction stream.

13. The processor of claim 1, configured to: determining whether the processed instructions include a processed instruction including the discard code, the discard code identifying at least one register operand associated with at least one register of the plurality of registers, the at least one register operand to be discarded after an event occurs; and In response to determining that the processed instruction includes the abandonment code, the abandonment code identifying at least one register operand that is to be abandoned after a certain number of instructions in the instruction stream after the event occurs: In response to the occurrence of the event, the discarding indicator associated with the at least one register associated with the at least one register operand is set to a discarding state, the discarding state indicating that the at least one register is discarded.

14. A method of discarding a data value stored in a register in a processor, comprising: receiving, from an instruction memory, a plurality of instructions to be executed in an instruction stream, the plurality of instructions including at least one computer instruction, the at least one computer instruction including a register operand; processing an instruction from the plurality of instructions; determining whether the processed instruction includes a discard code identifying at least one register operand associated with at least one of a plurality of registers in the processor that is to be discarded; responsive to determining that the processed instruction includes the discard encoding identifying at least one register operand to be discarded, setting a discard indicator associated with the at least one register associated with the at least one register operand to a discard state, the discard state indicating that the at least one register is discarded; determining whether the processed instruction includes a source register operand; as well as In response to determining that the processed instruction includes the source register operand, determining whether the discard indicator associated with a source register associated with the source register operand indicates a discard state: In response to determining that the discard indicator associated with the source register associated with the source register operand indicates a discard status: An exception is generated for the processed instruction.

15. The method according to claim 14, further comprising: determining that a current process in the processor is to be switched to a next process to be executed in the processor; as well as In response to determining that the current process in the processor is to be switched to the next process to be executed in the processor, storing a current context for the current process, comprising: for each of a plurality of physical registers in the processor, determining whether a discard indicator is set to the discard state for the physical register; as well as In response to the discard indicator being set to a discard state for the physical register: A data value is not stored in the physical register in the current context for the current process.

16. The method according to claim 14, further comprising: determining whether the processed instruction includes a target register operand; as well as In response to determining that the processed instruction includes the target register operand: renaming a mapping entry in the plurality of mapping entries in the register mapping table for a logical register associated with the target register operand to a logical register in the plurality of logical registers; as well as And also include: In response to determining that the processed instruction includes the discard encoding identifying at least one register operand to be discarded, at least one mapping entry of the plurality of mapping entries in the register mapping table associated with the at least one register operand is retired.

17. The method according to claim 14, comprising: In response to determining that the processed instruction includes the discard encoding identifying at least one register operand to be discarded: determining whether all instructions of the plurality of instructions that depend on the at least one register associated with the at least one register operand have been committed; as well as In response to determining that all instructions of the plurality of instructions that depend on the at least one register associated with the at least one register operand have been committed: The discard indicator associated with the at least one register associated with the at least one register operand is set to a discard state, the discard state indicating that the at least one register is discarded.

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