Processor, method, device and storage medium for data processing

Abstract

According to an embodiment of the present disclosure, a processor and a method, device and storage medium for data processing are provided. The processor includes an instruction decoder configured to decode a target instruction for a vector operation. The target instruction involves a target opcode, a source operand and a target operand. The target opcode indicates the vector operation specified by the target instruction. The source operand specifies a source storage location in the memory for reading data to be processed. The target operand specifies a target storage location in the memory for writing a processing result. The processor also includes an arithmetic logic unit coupled to the instruction decoder and the memory. The arithmetic logic unit is configured to: read data to be processed from a source storage location in the memory; perform an arithmetic logic operation associated with the vector operation specified by the target instruction on the data to be processed; and write the processing result to a target storage location in the memory. In this way, the efficiency of vector calculations can be improved.

Description

Technical Field

[0001] Example embodiments of the present disclosure generally relate to the field of computers, and more particularly, to processors, and methods, devices, and computer-readable storage media for data processing. Background Art

[0002] With the development of information technology, various processors can be applied in a wide variety of scenarios. Different instruction set architectures (ISAs) have been proposed for processors to address various application scenarios. These ISAs often need to be compatible with a wide range of usage scenarios. For vector calculations with high instruction repetition and large data volumes, a better ISA is needed to enable the processor to better handle such vector calculations. Summary of the Invention

[0003] In a first aspect of the present disclosure, a processor is provided. The processor includes an instruction decoder configured to decode a target instruction for a vector operation. The target instruction includes a target opcode, a source operand, and a target operand. The target opcode indicates the vector operation specified by the target instruction. The source operand specifies a source storage location in a memory for reading data to be processed. The target operand specifies a target storage location in the memory for writing a processing result. The processor also includes an arithmetic logic unit coupled to the instruction decoder and the memory. The arithmetic logic unit is configured to: read the data to be processed from the source storage location in the memory; perform an arithmetic logic operation associated with the vector operation specified by the target instruction on the data to be processed; and write the processing result to the target storage location in the memory.

[0004] In a second aspect of the present disclosure, a method for data processing is provided. The method includes decoding a target instruction for a vector operation. The target instruction includes a target opcode, a source operand, and a destination operand. The destination opcode indicates the vector operation specified by the target instruction. The source operand specifies a source storage location in a memory for reading data to be processed. The destination operand specifies a destination storage location in a memory for writing a processing result. The method also includes reading the data to be processed from the source storage location in the memory; performing an arithmetic and logical operation associated with the vector operation specified by the target instruction on the data to be processed; and writing the processing result to the destination storage location in the memory.

[0005] In a third aspect of the present disclosure, an electronic device is provided, which includes at least the processor according to the first aspect.

[0006] In a fourth aspect of the present disclosure, a computer-readable storage medium is provided, wherein a computer program is stored on the computer-readable storage medium, and the computer program can be executed by a processor to implement the method of the second aspect.

[0007] It should be understood that the content described in this content section is not intended to limit the key features or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, wherein:

[0009] Figure 1 A schematic diagram illustrating an example environment in which embodiments of the present disclosure can be implemented;

[0010] Figure 2 A schematic diagram illustrating example instructions according to some embodiments of the present disclosure is shown;

[0011] Figure 3 A schematic diagram illustrating storage locations corresponding to example source operands according to some embodiments of the present disclosure is shown.

[0012] Figure 4 A flowchart illustrating a process for data processing according to some embodiments of the present disclosure; and

[0013] Figure 5 A block diagram of an electronic device in which a processor according to one or more embodiments of the present disclosure may be included is shown. DETAILED DESCRIPTION

[0014] The following describes embodiments of the present disclosure in more detail with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the scope of protection of the present disclosure.

[0015] In the description of the embodiments of the present disclosure, the term "including" and similar terms should be understood as open inclusion, i.e., "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may be included below.

[0016] It is understandable that the data involved in this technical solution (including but not limited to the data itself, the acquisition or use of the data) must comply with the requirements of relevant laws, regulations and relevant provisions.

[0017] As mentioned above, with the development of information technology, various processors can be applied to a wide variety of scenarios. Different instruction set architectures (ISAs) have been proposed for various application scenarios. These ISAs often need to be compatible with a wide range of usage scenarios. However, the usage scenarios of these conventional ISAs do not align with those of vector computing, such as neural network computing. Therefore, for vector computing with high instruction repetitiveness and large data volumes, a better ISA is needed to enable the processor to better handle such vector computing.

[0018] A common approach is to use standard processor instruction sets, such as the Reduced Instruction Set Computer (RISC)-V instruction set. While these general-purpose instruction sets can perform various vector calculations, such as neural network operators, they struggle to guarantee high execution efficiency due to their need to be compatible with a wide variety of usage scenarios. For example, neural network operator calculations typically involve a large number of vector calculations, which are not well-suited to general-purpose instruction sets.

[0019] Research has found that the instruction set architecture of conventional solutions is not applicable to certain large-scale vector calculations. For example, conventional solutions can use a digital signal processor (DSP) architecture, such as a single instruction multiple data (SIMD) architecture, or a vector processor (Vector) architecture. However, the instruction sets of the above-mentioned DSP architectures are generally not public. As for vector processor architectures, such as the vector instruction set under the RISC-V standard (referred to as the RISC-V vector instruction set), these instruction sets are generally more complex and appear redundant for vector calculations such as neural network operators.

[0020] In summary, for some vector calculations with high instruction repetitiveness and large data volumes, it is necessary to design an instruction set that is more suitable for vector calculations to improve the computing efficiency of the processor.

[0021] According to an embodiment of the present disclosure, an improved solution for a processor is proposed. In this solution, the processor includes an instruction decoder and an arithmetic logic unit. The instruction encoder is used to receive a target instruction for processing a vector operation. The target instruction is applicable to a memory-to-memory (MEM to MEM) processor architecture. For example, the target instruction involves a target opcode, a source operand, and a target operand. The target opcode indicates the vector operation specified by the target instruction, the source operand at least specifies a source storage location in the memory for reading data to be processed, and the target operand at least specifies a target storage location in the memory for writing a processing result.

[0022] The arithmetic logic unit (ALU) of the processor is coupled to an instruction decoder and a memory. The ALU is configured to execute a vector operation of a target instruction based on information decoded by the instruction decoder. For example, the ALU is configured to read data to be processed from a source storage location in the memory; perform an arithmetic logic operation associated with the vector operation specified by the target instruction on the data to be processed; and write a result of the processing of the data to a target storage location in the memory.

[0023] This solution simplifies processor operation by employing a processor adapted for a memory-to-memory architecture. This allows the processor to perform a large number of vector calculations using a simple instruction set. For example, the processor can use a simple instruction set to perform neural network vector calculations. This allows the solution to improve the efficiency of vector calculations performed by the processor using a simple instruction set.

[0024] Figure 1 A schematic diagram of an example environment 100 in which embodiments of the present disclosure can be implemented is shown. In this environment 100, processor 110 can represent any type of instruction processing device. For example, processor 110 can be a general-purpose processor or any other suitable processor. Processor 110 is configured to receive instructions 140 and perform operations indicated by the instructions 140, such as vector operations. For example, processor 110 can receive instructions 140 from other devices in environment 100. In some embodiments, instructions 140 are SIMD instructions.

[0025] The processor 110 includes an instruction decoder 120 and an arithmetic logic unit 130. Alternatively or additionally, the processor 110 may further include a memory (not shown) or be communicatively coupled to the memory. For example, the memory may be a data memory (such as a vector closely coupled memory (VCCM)). The instruction decoder 120, the arithmetic logic unit 130, and the memory are communicatively coupled. That is, the instruction decoder 120, the arithmetic logic unit 130, and the memory may communicate with each other according to an appropriate data transmission protocol and / or standard. During operation, the instruction decoder 120 receives an instruction 140 and decodes the instruction 140. For example, the instruction decoder 120 may decode the instruction 140 into an arithmetic operation and / or a logical operation that can be processed by the arithmetic logic unit 130. The instruction decoder 120 may be implemented using various different mechanisms. For example, the instruction decoder 120 may be implemented using a hardware circuit, or at least partially implemented with the aid of a software module.

[0026] The arithmetic logic unit 130 is configured to operate based on information obtained by the instruction decoder 120 when decoding the instruction 140. The arithmetic logic unit 130 can perform various arithmetic operations, logical operations, etc. The arithmetic logic unit 130 can be implemented using a variety of different mechanisms. For example, the arithmetic logic unit 130 can be implemented using hardware circuits, or at least partially implemented with the help of software modules.

[0027] It should be understood that the structure and function of the environment 100 are described for exemplary purposes only and do not imply any limitation on the scope of the present disclosure. For example, the processor 110 can be applied to various existing or future computing platforms or computing systems. The processor 110 can be implemented in various embedded applications (for example, data processing systems of mobile network base stations, etc.) to provide services such as large-scale vector calculations. The processor 110 can also be integrated or embedded in various electronic devices or computing devices to provide various computing services. The application environment and application scenarios of the processor 110 are not limited here.

[0028] In some embodiments, the instruction decoder 120 decodes the received instruction 140. Instruction 140 is sometimes referred to herein as a "target instruction," and the two are used interchangeably in this context. Figure 2 Schematic diagram of example instructions 140 according to some embodiments of the present disclosure is shown. Figure 2 As shown, instruction 140 includes a target opcode 210, a source operand 220, and a destination operand 230. Target opcode 210 is sometimes referred to herein as an "operation code (opcode)" and the two are used interchangeably in this context. Target opcode 210 may indicate the vector operation specified by instruction 140. Source operand 220 is used to specify at least a source storage location in memory for reading data to be processed. Destination operand 230 is used to specify at least a destination storage location in memory for writing processing results.

[0029] In some embodiments, the instruction decoder 120 decodes the information indicated by the target opcode 210, the source operand 220, and the target operand 230 for processing by the arithmetic logic unit 130. For example, the arithmetic logic unit 130 is configured to read data to be processed from a source storage location in the memory specified by the source operand 220. The arithmetic logic unit 130 performs an arithmetic logic operation associated with the vector operation specified by the instruction 140 on the data to be processed. The arithmetic logic unit 130 then writes the processing result of the data to be processed to the target storage location specified by the target operand 230.

[0030] In some embodiments, the instruction 140 may be encoded using, for example, binary. In other embodiments, the instruction 140 may be encoded using other encoding formats or other bases. In this document, unless otherwise specified, the encoding format and encoding representation of the instruction 140 described below are all based on binary as an example. For example, the binary instruction 140 may be defined using the format shown in Table 1 below.

[0031] Table 1 Instruction format definition

[0032]

[0033] As shown in Table 1, the 86th to the 95th are used to represent the target operation code 210 of instruction 140. Each operand from the 22nd to the 85th is used to represent the source operand 220 of instruction 140. Each parameter from the 0th to the 21st is used to represent the target operand 230 of instruction 140. Of course, it should be understood that, unless otherwise stated, any specific numerical value or the number of places that occur here and elsewhere in this paper are exemplary. For example, the number of places at which each operation code and / or operand listed above are located is exemplary, rather than restrictive. The target operation code 210, source operand 220 and target operand 230 of instruction 140 can be located at other appropriate number of places.

[0034] For example, the source operand A_vaddr from the 70th to the 85th bit is used to represent the address index of the data of the A channel (also referred to as the first storage space of the memory) in the memory, for example, a data memory (such as, VCCM), that is, the address index of VCCM[A_vaddr]. The address index is in units of a vector word. A vector word can represent a storage unit of a channel in the memory, and the storage unit is in the width of a SIMD. That is, the address index is in units of a SIMD width. In some embodiments, the depth of the memory is, for example, 1024. In this example, only 10 bits from the 70th to the 85th bit can be used to represent the address index of the A channel. Of course, it should be understood that the memory can have other appropriate depths, and the address index can also have other appropriate number of bits.

[0035] For another example, the source operand A_index from the 60th to the 69th bit is used to represent the element index of the vector word of the A channel in the memory. Each vector word can have, for example, 64 elements. The element index can be used to indicate a certain element in the vector word in the A channel. In some embodiments, if the vector word of the A channel is divided into, for example, 64 elements, only 6 bits from the 60th to the 69th bit can be used to represent A_index. For another example, the source operand A_vm from the 54th to the 59th bit is used to represent the index of the vector mask (VM) register of the A channel. In some embodiments, the A channel has 16 VM registers. In such an example, only 4 bits from the 54th to the 59th bit can be used to represent A_vm.

[0036] Similarly, the source operand B_vaddr from bits 38 to 53 is used to represent the address index of the B channel (also known as the second storage space of the memory) in the memory (e.g., the data memory VCCM), that is, the address index of VCCM[B_vaddr]. The address index is in units of one vector word. That is, the address index is in units of one SIMD width. The source operand B_index from bits 28 to 37 is used to represent the element index of the vector word of the B channel. The source operand B_vm from bits 22 to 27 is used to represent the index of the vector mask register of the B channel.

[0037] The example of the target operand 230 in Table 1 includes C_vaddr from bits 6 to 21, which can represent the address index of the C channel of the data memory VCCM, that is, the address index of VCCM[C_vaddr]. The address index is in units of one vector word. That is, the address index is in units of one SIMD width. The example of the target operand 230 also includes C_vm from bits 0 to 5, which represents the index of the vector mask register of the C channel.

[0038] Figure 3 Schematic diagram showing the storage locations corresponding to example source operands according to some embodiments of the present disclosure. Figure 3In the example of , the storage space of the memory is divided into multiple channels, such as channel 310-1, channel 310-2, ..., channel 310-N, etc., where N is an integer greater than 1. For ease of discussion, channel 310-1, channel 310-2, ..., channel 310-N will be collectively referred to as or individually referred to as channel 310 below. In some embodiments, the value of N can be pre-set. For example, N can be set to different values ​​such as 1024, 512, etc. Each channel 310 includes, for example, 1024 bits or other appropriate bit numbers. The address index 330 (for example, the source operand A_vaddr, B_vaddr or the destination operand C_vaddr) can indicate the address of channel 310-1. The address of channel 310 can be in units of vector words. The address index 330 can be 16 bits. For example, if the address index 330 is "0b0000_0000_0000_0000", then the address index 330 can indicate channel 310-1. For another example, in some embodiments, when the memory depth or number of channels is 1024, the address index 330 may also be 10 bits, such as the address "0b00_0000_0000" indicating channel 310-1. Note that all encodings beginning with "0b" herein represent binary representations and will not be repeated below. The "_" that appears in the binary representation is for ease of reference only and has no actual meaning and does not occupy a binary bit.

[0039] In some embodiments, the vector word of each channel 310 can be divided into multiple elements, such as element 320. Element 320 may include, for example, 64 bits. An element index 340 (e.g., source operand A_index or B_index) may indicate an index of an element, such as element 320. The element index 340 may be 10 bits. For example, if the element index 340 is "0b00_0000_0000", the element index 340 may indicate element 320. For another example, in an example where the number of elements in the vector word of each channel 310 is 64, the element index may be 6 bits, such as the element index "0b00_0000" may indicate element 320.

[0040] It should be understood that, unless otherwise specified, any specific numerical values, bit numbers, and binary representations appearing here and elsewhere in this document are exemplary. For example, in other embodiments, each channel may have a different number of bits, and each vector word may also use a different number of bits. Accordingly, address indices and element indices may also have different number of bits and different encoding representations. The scope of this disclosure is not limited in this respect.

[0041] Several examples of source operands 220 are listed above with reference to Table 1. More examples of source operands 220 will be described below with reference to Table 2.

[0042] Table 2 Instruction format definition

[0043] Bit [95:86] [85:54] [53:22] [21:6] [5:0] Opcode A_imm B_imm C_vaddr C_vm

[0044] As shown in Table 2, the source operand 220 may include A_imm located at bits 54 to 85, which represents an immediate value in the instruction 140. Similarly, the source operand 220 may also include B_imm located at bits 22 to 53, which represents another immediate value in the instruction 140. Similar to Table 1, the destination operand 230 in Table 2 may also include C_vaddr and / or C_vm.

[0045] Should be understood that, above in conjunction with each source operand and / or each destination operand described in Table 1 and Table 2 is merely exemplary, rather than restrictive. The source operand 220 and / or destination operand 230 adopted by the disclosure can comprise above any one or more source operands and / or destination operands. In certain embodiments, source operand 220 and / or destination operand 230 can comprise other any suitable operand types different from above source operand and / or destination operand.

[0046] Table 3 below describes an example encoding of the opcode of instruction 140. For example, if bit 0 is 0, it indicates that the instruction 140 is a variable type. If bit 0 is 1, it indicates that the instruction 140 is an immediate type. Bits 1 to 2 indicate the sub-function encoding of instruction 140. Bits 3 to 7 indicate the function encoding of instruction 140. Bits 8 to 9 indicate the calculation precision of instruction 140. For example, binary "00" can indicate that the calculation precision is single-precision floating point. Other binary values ​​can indicate other reserved calculation precisions.

[0047] Table 3 Example opcode encoding

[0048]

[0049] Of course, it should be understood that the encoding method of the opcode of the instruction 140 shown in Table 3 is merely exemplary and not restrictive. For example, in other embodiments, other encoding methods may be used to encode the instruction 140.

[0050] In some embodiments, the vector operation specified by the instruction 140 can be determined based on the target opcode 210 of the instruction 140. For example, the processor 110 can pre-store the opcodes of each instruction. The instruction decoder 120 can determine the vector operation specified by the instruction 140 based on the target opcode 210 of the received instruction 140. For example, if the target opcode 210 of the instruction 140 is encoded as "0b00_00110_01_0", the instruction decoder 120 can determine the instruction 140 as a v2indexr instruction. It should be understood that the examples of opcodes and instruction types listed above are merely exemplary and not restrictive. Instructions encoded as "0b00_00110_01_0" can also specify other vector operations.

[0051] Several examples of instruction 140 and exemplary execution methods of processor 110 for executing instruction 140 are described below. In some embodiments, source operand 220 may include two source operands, such as A_vaddr and B_vaddr, or A_vaddr and B_imm. The width of each source operand may be a SIMD width. Alternatively or additionally, in some embodiments, source operand 220 may include only one source operand, such as B_vaddr. Destination operand 230, such as C_vaddr, may specify a target storage location for writing the processing result back to the memory, i.e., VCCM[C_vaddr].

[0052] In some embodiments, the target storage location of instruction 140 includes a processing result vector. The target operand 230 also indicates a target VM register, such as C_vm or vm3. The value at each position of the target VM register indicates whether the corresponding position of the processing result vector is to be written with the corresponding processing result. For example, if the target register vm3[i] is 1, it means that the i-th element of the processing result vector word is write-enabled and can be written with the corresponding processing result. Conversely, if the target register vm3[i] is 0, the i-th element of the processing result vector word cannot be written with the corresponding processing result.

[0053] Table 4 describes several example instructions that the processor 110 can support. The instructions in Table 4 can be described with reference to the instruction definitions of Table 1 or Table 2, and can be encoded with reference to the example encoding method of Table 3. In the example of Table 4, the target operand 230 includes C_vaddr (i.e., &v3) and C_vm (i.e., vm3). The reserved bits in Table 4 represent one or more reserved bits. These reserved bits can be encoded or used later.

[0054] Table 4 Example instructions

[0055]

[0056]

[0057] As one embodiment, the instruction 140 includes a first index determination instruction (e.g., v2index1 or v2indexr in Table 4). In this example, the source operand 220 specifies a location in the first storage space of the memory, i.e., the address index of channel A (A_vaddr is &v1). The source operand 220 also specifies a given index value of the data to be processed in the second storage space of the memory, i.e., the element index within the vector word of channel B (B_vaddr is &v2, and B_index is index2). In this example, the arithmetic logic unit 130 is configured to determine a first index. The first index indicates the storage location in the first storage space of the value at the location indicated by the given index value in the data to be processed.

[0058] For example, the opcode of instruction v2index1 can be encoded as "0b00_00110_00_0", and the instruction v2index1 v1,v2,index2,v3,vm3 means assigning v3[i] to indext, where indext is the index of the first element from left to right that can make v1[indext] equal to v2[index2]. If no element meets the above conditions, indext is set to "-1" represented by binary complement. In some embodiments, the target operand 230 also indicates the target vector mask register. The values ​​at each position of the target vector mask register indicate whether the corresponding position of the processing result vector is to be written with the corresponding processing result. For example, if vm3[i] is equal to 1, then v3[i] is write-enabled.

[0059] For another example, the opcode of the instruction v2indexr can be encoded as "0b00_00110_01_0". The instruction v2indexr v1,v2,index2,v3,vm3 means assigning v3[i] to indext, where indext is the index of the first element from the right to the left that can make v1[indext] equal to v2[index2]. If no element meets the above conditions, indext is set to "-1" represented by the two's complement. In this example, if vm3[i] is equal to 1, then v3[i] is write-enabled.

[0060] As another example, instruction 140 includes a second index determination instruction (e.g., v2indexli or v2indexri in Table 4). In this example, source operand 220 specifies a location in the first storage space of the memory, i.e., the address index of channel A (A_vaddr is &v1). Source operand 220 also specifies a first immediate value, i.e., the immediate value imm2. In this example, the arithmetic logic unit 130 is configured to determine a second index. The second index indicates the storage location of the first immediate value in the first storage space.

[0061] For example, the opcode for the instruction v2indexli is encoded as "0b00_00110_00_1." The instruction v2indexliv1,imm2,v3,vm3 assigns v3[i] to indext, where indext is the index of the first element from left to right that makes v1[indext] equal to imm2. If no element satisfies the above condition, indext is set to "-1" represented by the two's complement. In this example, if vm3[i] is equal to 1, then v3[i] is write-enabled.

[0062] For another example, the opcode of the instruction v2indexri can be encoded as "0b00_00110_01_1". The instruction v2indexri v1,imm2,v3,vm3 means assigning v3[i] to indext, where indext is the index of the first element from the right to the left that can make v1[indext] equal to imm2. If no element meets the above conditions, indext is set to "-1" represented by the two's complement. In this example, if vm3[i] is equal to 1, then v3[i] is write-enabled.

[0063] As another example, the instruction 140 may include a first value determination instruction, such as the instruction sindex2v in Table 4. The source operand 220 specifies the location of the first storage space of the memory, that is, the address index of channel A (A_vaddr is &v1). The source operand 220 also specifies a given index value of the data to be processed in the second storage space of the memory, that is, the element index in the vector word of channel B (B_vaddr is &v2, B_index is index2).

[0064] In this example, the arithmetic logic unit 130 is configured to determine a given value of the data to be processed at a location indicated by a given index value, and to determine a first value in the first memory space at a location indexed by the given value. For example, the instruction sindex2v v1,v2,index2,v3,vm3 has an opcode encoded as "0b00_00110_10_0". This instruction indicates that v3[i] is assigned to v1[v2[index2]]. If vm3[i] is equal to 1, then v3[i] is write-enabled.

[0065] In some embodiments, instruction 140 includes a second value determination instruction. In this example, source operand 220 specifies a given index value of the data to be processed within the second storage space of the memory, i.e., B_vaddr is &v2 and B_index is index2. The arithmetic logic unit 130 is configured to determine the second value at the location indicated by the given index value in the data to be processed. For example, the instruction s2v v2,index2,v3,vm3 has an opcode encoded as "0b00_00110_10_1". This instruction indicates that v3[i] is assigned to v2[index2]. If vm3[i] is equal to 1, then v3[i] is write-enabled.

[0066] By using one or more of the first index determination instruction, the second index determination instruction, the first value determination instruction, and the second value determination instruction described above, the processor 110 can better handle some operators such as coordinate determination, such as the maximum index (ArgMax) operator, the minimum index (ArgMin) operator, or the highest ranked K values ​​(TopK) operator. Taking ArgMax as an example, it is used to find the index that makes the value v[index] in the vector v the maximum value. The instructions required for ArgMax of 64 elements are as follows: First, v2smax v1,vm1,v2,vm2 (this instruction will be described in Tables 5 and 6 below), which finds the maximum element value in v1 and writes it to v2, where all bits of vm1 and vm2 storage values ​​are 1; next, v2indexl v1,v2,0,v3,vm3, which finds index so that v1[index] is equal to v2[0] and writes the value of index to v3, where all bits of vm3 storage value are 1.

[0067] In some embodiments, the target instruction includes a vector transpose instruction, such as the vtranspose or vstranspose instructions. Source operand 220 specifies a first location in a first storage space in the memory, i.e., A_vaddr is &v1 and A_index is index1. Source operand 220 also specifies source vector mask registers vm1 and optionally vm2. In this example, the arithmetic logic unit 130 is configured to perform a vector transposition on the data to be processed at the first location in the first storage space to obtain transposed data to be processed.

[0068] For example, the vector transpose instruction vtranspose v1,index1,vm1,vm2,v3,vm3 has an opcode encoded as 0b00_00111_11_0, which is used to transpose a vector (or matrix) of, for example, 32*32. In this example, the values ​​of vm1 and vm2 enable the read lane; the value of vm3 enables the write lane. The number R of consecutive 1 bits in vm1 is used to represent the number of rows of the matrix, and the number C of consecutive 1 bits in vm2 is used to represent the number of columns of the matrix, where R and C are both arbitrary natural numbers, and R and C can be the same or different. The valid bits of vm1, vm2, and vm3 must be continuous, otherwise the first 1 in the lowest bit shall prevail. The above-mentioned vector transpose instruction vtranspose can be used to transpose an R*C matrix.

[0069] For example, in some embodiments, a vector transpose instruction vstranspose v1, index1, vm1, v3, vm3 can be used to transpose a square matrix. In this example, the value of vm1 is the read channel enable; the value of vm3 is the write channel enable. The number R of consecutive 1 bits in vm1 is used to represent the number of rows (or columns) of the square matrix. This vector transpose instruction vstranspose can be used to transpose an R*R square matrix.

[0070] The vector transpose instruction is not a standard RISC instruction. In conventional standard RISC instruction sets, vector transposition must be performed using multiple consecutive transpose instructions. This solution, by using the vector transpose instruction, can improve the computational power of some networks. For example, neural network training typically involves numerous matrix or square matrix transpose operations. Utilizing the vector transpose instruction in this solution can improve the computational efficiency of neural network training.

[0071] In some embodiments, the target instruction includes an exponential instruction, such as vexp. In this example, the source operand 220 specifies a source storage location, i.e., A_vaddr is &v1. The arithmetic logic unit 130 is configured to determine an exponential value with a predetermined value (e.g., a natural base e) as the base, using the data to be processed at the source storage location as a power. For example, vexp v1,v3,vm3, with an opcode encoded as "0b00_01000_01_0", indicates that v3[i] is assigned to exp(v1[i]). If vm3[i] is equal to 1, then v3[i] is write-enabled.

[0072] The above exponential instructions are applicable to the sigmoid operator and hyperbolic functions such as sinh, cosh, and tanh. For example, the sigmoid operator, sinh operator, cosh operator, and tanh operator can be represented by the following equations (1) to (4).

[0073]

[0074]

[0075]

[0076]

[0077] In equations (1)-(4), x represents the data to be processed.

[0078] For example, sigmoid and hyperbolic functions are common in neural network activation functions. By using the exponential instruction of this solution, the efficiency of such calculations can be improved.

[0079] In some embodiments, instruction 140 includes a VM register instruction, such as a vm2index instruction. Source operand 220 indicates a source VM register in memory, namely vm1. The arithmetic logic unit is configured to store the index of the enabled location in the source VM register at the target storage location. For example, the instruction vm2index vm1,v3,vm3 has an opcode encoded as "0b00_01100_01_0", which means v3[i]=vm1[i]? i:-1. That is, if the value of vm1[i] is 1, v3[i] is assigned to i, otherwise, if the value of vm1[i] is 0, v3[i] is assigned to -1 (e.g., "-1" in binary complement representation). If vm3[i] is equal to 1, v3[i] is write-enabled.

[0080] In some embodiments, instruction 140 includes a one-hot code conversion instruction, such as vindex2vm. This is a VM register operation instruction. In this example, source operand 220 specifies a given index value of the data to be processed in the second storage space of the memory, that is, B_vaddr is &v2, and B_index is index2. The behavior of reading the vector mask register involved in this instruction is not a write enable for writing to the memory (other instructions that write to the memory require reading the vector mask register as a write enable). The target operand 230 specifies the target VM register, that is, vm3. The arithmetic logic unit is configured to: convert the value of the data to be processed at the given index value into a one-hot code, and store the one-hot code in the target VM register. For example, the instruction vindex2vm v2,index2,vm3 has an opcode encoded as "0b00_10000_01_0". This instruction indicates that vm3 is assigned to onehot(v2[index2]), where onehot() represents a one-hot code conversion function.

[0081] The one-hot encoding conversion instruction described above is applicable to index instructions and supports one-hot encoding operators. Convert a number to one-hot encoding form. For example, in actual use, it can be implemented with the following two instructions: vindex2vm v1,0,vm 1 and vmload vm1,v2,vm2, where the first instruction is used to convert the value of v1[0] to one-hot encoding form and write it to vm1, and the second instruction (vmload will be described in Tables 7 and 8 below) is used to store the value in vm1 to v2, where all bits of the stored value of vm2 are 1.

[0082] Table 4 above describes examples of various types of instructions 140 supported by the processor 110 of the present disclosure. It should be understood that the processor 110 of the present disclosure may also support more instructions. Table 5 below shows examples of more common instructions 140 supported by the processor 110. The instructions in Table 5 can be described with reference to the instruction definitions in Table 1 or Table 2, and the opcodes are encoded using the example encoding method in Table 3.

[0083] Table 5 Example of general instructions

[0084]

[0085]

[0086]

[0087]

[0088] The functions and definitions of the various instructions in Table 5 are shown in Table 6. The functions of these instructions include various additions, subtractions, multiplications, divisions, maximum values, minimum values, reciprocals (only supports immediate values), shifting operands according to given values, etc. These instructions provide basic calculations for the processor 110 and will not be described in detail here.

[0089] Table 6 shows the functions of common instructions.

[0090]

[0091]

[0092]

[0093]

[0094]

[0095] The MAX() and MIN() functions in Table 6 represent functions for finding the maximum and minimum values, respectively. DW represents the width of a vector word, LANE_NUM represents the number of elements in a vector word, the mod() function represents the remainder function, the ceil() and floor() functions represent rounding up and rounding down, respectively, and the SUM() function represents the sum function.

[0096] In some embodiments, the instructions supported by processor 110 also include various vector mask register access and operation instructions. Table 7 shows several examples of vector mask register access and operation instructions. The functions and definitions of the various instructions in Table 7 are shown in Table 8. The functions of these instructions include reading, writing and operating vector mask registers. The behavior of reading vector mask registers involved in these instructions is not a write enable for memory writes (other instructions that write to memory all require reading vector mask registers as write enables). These instructions are not described in detail here.

[0097] Table 7 Example vector mask register instruction encoding

[0098]

[0099]

[0100]

[0101] Table 8 Example vector mask register instruction functions

[0102]

[0103]

[0104] In some embodiments, the instructions 140 supported by the processor 110 also include internal register access and operation instructions. These instructions handle internal register access and special operations. For example, they write to the internal control and status (CSR) register, write a fixed value, or write SIMD-length data in the data memory VCCM. Another example is reading from the internal CSR register or reading from the data memory VCCM; and null instructions (i.e., no operation is performed and a one-cycle wait is performed).

[0105] Table 9 below shows several examples of internal register access and manipulation instructions. Table 10 shows the functions of the various instructions in Table 9. These instructions are not described in detail herein. Note that for the vwcsr instruction in Table 9, the source operand is in channel A, while for the vwcsri instruction, the immediate operand is in channel B.

[0106] Table 9 Example Internal Register Instructions

[0107]

[0108]

[0109] Table 10 shows the functions of the internal register instructions.

[0110]

[0111] The above descriptions of the various instructions supported by the processor 110 are described in conjunction with Tables 4-10. These instructions may be decoded by the instruction decoder 120 of the processor 110 and executed by the arithmetic execution unit 130. These instructions may constitute an instruction set supported by the processor 110. It should be understood that in some embodiments, an instruction set may be constructed using only some or all of the various instructions described above. Alternatively or additionally, other appropriate instructions not described above may also be used to construct an instruction set supported by the processor 110.

[0112] In addition, it should be understood that although the example instruction definitions and example opcode encodings specified in Tables 1 to 3 above list the various instructions in Tables 4 to 10, this is merely exemplary and not restrictive. The instruction set supported by the processor of the present disclosure can be defined and encoded in any appropriate manner. For example, each bit of each instruction can have a meaning different from that represented by each bit in Table 1 or Table 2. For another example, the encoding representation of the opcode of each instruction can have a different number of bits from that in Table 3, and each bit can also have a different meaning from that of each bit in Table 3. The encoding representation of the opcode of each instruction in Tables 4 to 10 above can be changed or interchanged. Each instruction can also be represented by other names. The scope of the present disclosure is not limited in this respect.

[0113] The instructions described above do not include branch type instructions or load / store type instructions. Unlike traditional SIMD processors such as vector register files, the registers used in the present disclosure are memory-to-memory SIMD processor architectures. The above instruction set defines multiple (e.g., 64 or more or less) vector mask registers for indicating the specific vectors that each SIMD instruction needs to process.

[0114] This solution simplifies the operation of the processor 110 by adopting a SIMD processor suitable for a memory-to-memory architecture. In this way, the processor 110 can use a simple instruction set to complete a large number of vector calculations. For example, the processor 110 can use a simple instruction set to perform tasks such as vector calculations of neural network operators. In this way, this solution can use a simple instruction set to improve the efficiency of the processor in performing vector calculations. For calculations such as neural network training and / or reasoning, the solution of the present disclosure can greatly improve the computational efficiency. For example, the processor according to an embodiment of the present disclosure can support various index determination instructions, thereby improving the efficiency of various vector calculations such as obtaining coordinates. For another example, the processor of the present disclosure can process instructions such as vector transpose, thereby improving the computational efficiency of corresponding calculations in the neural network training process. For another example, the processor of the present disclosure can support exponential instructions, thereby improving and optimizing the computational efficiency of operations such as sigmoid operators and hyperbolic function operators.

[0115] Figure 4 FIG. 4 is a flow chart showing a process 400 for data processing according to some embodiments of the present disclosure. The process 400 may be implemented at the processor 110. For ease of discussion, reference will be made to FIG. Figure 1 The process 400 is described with reference to the environment 100 of FIG.

[0116] At block 410, a target instruction for a vector operation, such as instruction 140, is decoded by processor 110. For example, instruction 140 may be decoded by instruction decoder 120 of processor 110. Instruction 140 includes a target opcode 210, a source operand 220, and a destination operand 230. Target opcode 210 indicates the vector operation specified by instruction 140. Source operand 220 specifies at least a source storage location in memory from which to read data to be processed. Destination operand 230 specifies at least a destination storage location in memory from which to write a result of the processing.

[0117] At block 420, the processor 110 reads the data to be processed from a source storage location in the memory. For example, the arithmetic logic unit 130 of the processor 110 may read the data to be processed from the source storage location in the memory. At block 430, the processor 110 performs an arithmetic logic operation associated with the vector operation specified by the target instruction on the data to be processed. For example, the arithmetic logic operation may be performed by the arithmetic logic unit 130 of the processor 110. At block 440, the processor 110 writes the processing result of the data to be processed to a target storage location in the memory. For example, the arithmetic logic unit 130 of the processor 110 may write the processing result to the target storage location.

[0118] In some embodiments, instruction 140 includes an index determination instruction. The index determination instruction may be a first index determination instruction (v2index1 or v2indexr) or a second index determination instruction (v2indexli or v2indexri). Source operand 220 specifies a location in a first storage space of a memory. Source operand 220 also specifies a given index value of data to be processed or a first immediate value within a second storage space of the memory. At block 430, the arithmetic logic operation performed by processor 110 includes determining a first index or determining a second index. The first index indicates the storage location in the first storage space of the value at the location indicated by the given index value in the data to be processed. The second index indicates the storage location in the first storage space of the first immediate value.

[0119] In some embodiments, the instruction 140 includes a first value determination instruction (e.g., the instruction sindex2v), the source operand 220 specifies a location in a first storage space of the memory, and the source operand 220 further specifies a given index value of data to be processed in a second storage space of the memory. At block 430, the arithmetic and logical operations performed by the processor 110 include: determining a given value of the data to be processed at the location indicated by the given index value; and determining a first value in the first storage space at the location indexed by the given value.

[0120] In some embodiments, instruction 140 includes a second value determination instruction, such as instruction s2v. Source operand 220 specifies a given index value of the data to be processed within the second storage space of the memory. At block 430, the arithmetic logic operation performed by processor 110 includes determining a second value at a location in the data to be processed indicated by the given index value.

[0121] In some embodiments, instruction 140 includes a vector transpose instruction, such as vtranspose or vstranspose. Source operand 220 specifies a first location in a first storage space in memory. At block 430, the arithmetic and logical operation performed by processor 110 includes performing a vector transposition on the data to be processed at the first location in the first storage space to obtain transposed data to be processed.

[0122] In some embodiments, the instruction 140 includes an exponential instruction, such as the instruction vexp. The source operand 220 specifies a source storage location. At block 430, the arithmetic logic operation performed by the processor 110 includes determining an exponential value with a predetermined value as the base by raising the processed data at the source storage location to a power.

[0123] In some embodiments, instruction 140 includes a VM register instruction, such as vm2index. Source operand 220 of instruction 140 indicates a source VM register in memory. At block 430, processor 110 performs an arithmetic logic operation including storing the index of the enabled location in the source VM register at the target memory location.

[0124] In some embodiments, the target storage location of each instruction 140 described above includes a processing result vector. The target operand 230 also indicates a target VM register. The value at each location of the target VM register indicates whether the corresponding location of the processing result vector is to be written with the corresponding processing result. For example, if the target register vm3[i] is 1, it means that the i-th element of the processing result vector word is write-enabled and can be written with the corresponding processing result. Conversely, if the target register vm3[i] is 0, the i-th element of the processing result vector word cannot be written with the corresponding processing result.

[0125] In some embodiments, instruction 140 includes a one-hot encoding conversion instruction, such as instruction vindex2vm. Source operand 220 specifies a given index value of the data to be processed within the second storage space of the memory. Destination operand 230 specifies a target VM register. At block 430, processor 110 converts the value of the data to be processed at the given index value into a one-hot encoding. Processor 110 is further configured to store the one-hot encoding in the target VM register.

[0126] Figure 51 shows a block diagram of an electronic device 500 in which a processor 110 according to one or more embodiments of the present disclosure may be included. It should be understood that Figure 5 The illustrated electronic device 500 is merely exemplary and should not be construed as limiting the functionality and scope of the embodiments described herein.

[0127] like Figure 5 As shown, electronic device 500 is in the form of a general electronic device or computing device. Components of electronic device 500 may include, but are not limited to, one or more processors 110, memory 520, storage device 530, one or more communication units 540, one or more input devices 550, and one or more output devices 560. In some embodiments, processor 110 may perform various processes according to programs stored in memory 520. Processor 110 may be a multi-core processor that can execute computer-executable instructions in parallel to improve the parallel processing capabilities of electronic device 500.

[0128] The electronic device 500 typically includes a plurality of computer storage media. Such media can be any available media accessible to the electronic device 500, including but not limited to volatile and non-volatile media, removable and non-removable media. The memory 520 can be a volatile memory (e.g., registers, cache, random access memory (RAM)), a non-volatile memory (e.g., read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory), or some combination thereof. The storage device 530 can be a removable or non-removable medium and can include a machine-readable medium, such as a flash drive, a disk, or any other medium that can be used to store information and / or data (e.g., training data for training) and can be accessed within the electronic device 500.

[0129] The electronic device 500 may further include additional removable / non-removable, volatile / non-volatile storage media. Figure 5 As shown in , a disk drive for reading or writing from a removable, non-volatile disk (e.g., a "floppy disk") and an optical drive for reading or writing from a removable, non-volatile optical disk can be provided. In these cases, each drive can be connected to a bus (not shown) by one or more data media interfaces. The memory 520 may include a computer program product 525 having one or more program modules that are configured to perform various methods or actions of various embodiments of the present disclosure. For example, these program modules can be configured to implement various functions or actions of the processor 110, such as implementing the functions of the instruction decoder 120 and the arithmetic logic unit 130.

[0130] The communication unit 540 enables communication with other electronic devices or computing devices via a communication medium. Additionally, the functions of the components of the electronic device 500 can be implemented as a single computing cluster or multiple computing machines that can communicate via a communication connection. Thus, the electronic device 500 can operate in a networked environment using a logical connection to one or more other servers, a network personal computer (PC), or another network node.

[0131] Input device 550 may be one or more input devices, such as a mouse, keyboard, or trackball. Output device 560 may be one or more output devices, such as a display, a speaker, or a printer. Electronic device 500 may also communicate with one or more external devices (not shown) via communication unit 540 as needed, such as a storage device, a display device, or the like, with one or more devices that allow a user to interact with electronic device 500, or with any device that allows electronic device 500 to communicate with one or more other electronic devices or computing devices (e.g., a network card, a modem, etc.). Such communication may be performed via an input / output (I / O) interface (not shown).

[0132] According to an exemplary implementation of the present disclosure, a computer-readable storage medium is provided, on which computer-executable instructions are stored, wherein the computer-executable instructions are executed by a processor to implement the method described above. According to an exemplary implementation of the present disclosure, a computer program product is also provided, which is tangibly stored on a non-transitory computer-readable medium and includes computer-executable instructions, and the computer-executable instructions are executed by a processor to implement the method described above.

[0133] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices, and computer program products implemented according to the present disclosure. It should be understood that each block of the flowcharts and / or block diagrams, and the combination of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0134] These computer-readable program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, such that when these instructions are executed by the processing unit of the computer or other programmable data processing device, a device is generated that implements the functions / actions specified in one or more blocks in the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, where these instructions cause the computer, programmable data processing device, and / or other device to operate in a specific manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing various aspects of the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0135] Computer-readable program instructions can be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0136] According to one or more embodiments of the present disclosure, Example 1 describes a processor comprising an instruction decoder configured to decode a target instruction for a vector operation. The target instruction involves a target opcode, a source operand, and a target operand. The target opcode indicates the vector operation specified by the target instruction. The source operand specifies at least a source storage location in a memory for reading data to be processed. The target operand specifies at least a target storage location in a memory for writing a processing result. The processor further comprises an arithmetic logic unit coupled to the instruction decoder and the memory. The arithmetic logic unit is configured to: read data to be processed from a source storage location in the memory; perform an arithmetic logic operation associated with the vector operation specified by the target instruction on the data to be processed; and write the processing result of the data to be processed to a target storage location in the memory.

[0137] According to one or more embodiments of the present disclosure, Example 2 includes the processor described in Example 1, wherein the target instruction includes a first index determination instruction, a source operand specifies a location in a first storage space of a memory, and the source operand further specifies a given index value of data to be processed in a second storage space of the memory. The arithmetic logic unit is configured as follows to perform the arithmetic logic operation associated with the vector operation specified by the target instruction: determining a first index indicating a storage location in the first storage space of a value at a location indicated by the given index value in the data to be processed.

[0138] According to one or more embodiments of the present disclosure, Example 3 includes the processor described in Example 1, wherein the target instruction includes a second index determination instruction, a source operand specifies a location in a first storage space of the memory, and the source operand further specifies a first immediate value. The arithmetic logic unit is configured to perform the arithmetic logic operation associated with the vector operation specified by the target instruction as follows: determine the second index indicating the storage location of the first immediate value in the first storage space.

[0139] According to one or more embodiments of the present disclosure, Example 4 includes the processor described in Example 1, wherein the target instruction includes a first value determination instruction, a source operand specifies a location in a first storage space of a memory, and the source operand further specifies a given index value of data to be processed in a second storage space of the memory. The arithmetic logic unit is configured as follows to perform the arithmetic logic operation associated with the vector operation specified by the target instruction: determining a given value of the data to be processed at a location indicated by the given index value; and determining a first value in the first storage space at a location indexed by the given value.

[0140] According to one or more embodiments of the present disclosure, Example 5 includes the processor described in Example 1, wherein the target instruction includes a second value determination instruction, and the source operand specifies a given index value of data to be processed in a second storage space of the memory. The arithmetic logic unit is configured to perform the arithmetic logic operation associated with the vector operation specified by the target instruction as follows: determine a second value at a location indicated by the given index value in the data to be processed.

[0141] According to one or more embodiments of the present disclosure, Example 6 includes the processor described in Example 1, wherein the target instruction includes a vector transpose instruction, and the source operand specifies at least a first location in a first storage space in the memory. The arithmetic logic unit is configured to perform the arithmetic logic operation associated with the vector operation specified by the target instruction as follows: vector transpose the data to be processed at the first location in the first storage space to obtain transposed data to be processed.

[0142] According to one or more embodiments of the present disclosure, Example 7 includes the processor described in Example 1, wherein the target instruction includes an exponent instruction, and the source operand specifies a source storage location. The arithmetic logic unit is configured to perform the arithmetic logic operation associated with the vector operation specified by the target instruction as follows: determining an exponent value with a predetermined value as a base by raising the data to be processed at the source storage location to a power.

[0143] According to one or more embodiments of the present disclosure, Example 8 includes the processor described in Example 1, wherein the target instruction includes a vector mask VM register instruction, the source operand indicates a source VM register in a memory, and the arithmetic logic unit is configured to perform the arithmetic logic operation associated with the vector operation specified by the target instruction as follows: store an index at an enabled location in the source VM register at a target memory location.

[0144] According to one or more embodiments of the present disclosure, Example 9 includes a processor described according to any one of Examples 2 to 8, wherein the target storage location includes a processing result vector, the target operand also indicates a target vector mask VM register, and the values ​​at each position of the target VM register indicate whether the corresponding processing result is to be written to the corresponding position of the processing result vector.

[0145] According to one or more embodiments of the present disclosure, Example 10 includes the processor described in Example 1, wherein the target instruction includes a one-hot code conversion instruction, the source operand specifies a given index value of the data to be processed in the second storage space of the memory, and the target operand specifies a target vector mask VM register. The arithmetic logic unit is configured as follows to perform the arithmetic logic operation associated with the vector operation specified by the target instruction: converting the value of the data to be processed at the given index value into a one-hot code; and storing the one-hot code in the target VM register.

[0146] According to one or more embodiments of the present disclosure, Example 11 describes a method for data processing. The method includes: decoding a target instruction for a vector operation, the target instruction involving a target opcode, a source operand, and a target operand. The target opcode indicates the vector operation specified by the target instruction. The source operand at least specifies a source storage location in the memory for reading the data to be processed. The target operand at least specifies a target storage location in the memory for writing the processing result. The method also includes: reading the data to be processed from the source storage location in the memory; performing an arithmetic and logical operation associated with the vector operation specified by the target instruction on the data to be processed; and writing the processing result of the data to be processed to the target storage location in the memory.

[0147] According to one or more embodiments of the present disclosure, Example 12 includes the method described according to Example 11, wherein the target instruction includes an index determination instruction, a source operand specifies a location in a first storage space of a memory, and the source operand further specifies at least one of the following: a given index value of data to be processed in a second storage space of the memory, and a first immediate value. Executing the arithmetic and logical operation associated with the vector operation specified by the target instruction includes at least one of the following: determining a first index indicating a storage location in the first storage space of a value at a location indicated by the given index value in the data to be processed; and determining a second index indicating a storage location in the first storage space of the first immediate value.

[0148] According to one or more embodiments of the present disclosure, Example 13 includes the method described according to Example 11, wherein the target instruction includes a first value determination instruction, a source operand specifies a location in a first storage space of a memory, and the source operand further specifies a given index value of data to be processed in a second storage space of the memory. Executing the arithmetic and logical operation associated with the vector operation specified by the target instruction includes: determining a given value of the data to be processed at a location indicated by the given index value; and determining a first value in the first storage space at a location indexed by the given value.

[0149] According to one or more embodiments of the present disclosure, Example 14 includes the method described according to Example 11, wherein the target instruction includes a second value determination instruction, and the source operand specifies a given index value of data to be processed in a second storage space of the memory. Executing the arithmetic and logical operation associated with the vector operation specified by the target instruction includes determining a second value at a location indicated by the given index value in the data to be processed.

[0150] According to one or more embodiments of the present disclosure, Example 15 includes the method described according to Example 11, wherein the target instruction includes a vector transpose instruction, wherein a source operand specifies at least a first location in a first storage space in a memory. Executing the arithmetic and logical operation associated with the vector operation specified by the target instruction includes: performing a vector transposition on the data to be processed at the first location in the first storage space to obtain transposed data to be processed.

[0151] According to one or more embodiments of the present disclosure, Example 16 includes the method described in Example 11, wherein the target instruction includes an exponent instruction, the source operand specifies a source storage location, and performing the arithmetic and logical operation associated with the vector operation specified by the target instruction includes: raising the data to be processed at the source storage location to a power to determine an exponent value with a predetermined value as a base.

[0152] According to one or more embodiments of the present disclosure, Example 17 includes the method described in Example 11, wherein the target instruction includes a vector mask VM register instruction, the source operand indicates a source VM register in memory, and performing the arithmetic and logical operations associated with the vector operation specified by the target instruction includes storing an index of an enabled location in the source VM register at the target memory location.

[0153] According to one or more embodiments of the present disclosure, Example 18 includes the method described in Example 11, wherein the target instruction includes a one-hot code conversion instruction, the source operand specifies a given index value of the data to be processed in the second storage space of the memory, and the target operand specifies a target vector mask VM register. Executing the arithmetic and logical operation associated with the vector operation specified by the target instruction includes: converting the value of the data to be processed at the given index value into a one-hot code; and storing the one-hot code in the target VM register.

[0154] According to one or more embodiments of the present disclosure, Example 19 describes an electronic device, which includes at least the processor according to any one of Examples 1 to 10.

[0155] According to one or more embodiments of the present disclosure, Example 20 describes a computer-readable storage medium having a computer program stored thereon, wherein the computer program is executed by a processor to implement the method according to any one of Examples 11 to 18.

[0156] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the systems, methods and computer program products according to multiple implementations of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a part for a module, program segment or instruction, and a part for a module, program segment or instruction comprises one or more executable instructions for realizing the logical function of the specification. In some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be realized by a special hardware-based system that performs the function or action of the specification, or can be realized by a combination of special hardware and computer instructions.

[0157] While various implementations of the present disclosure have been described above, the foregoing description is intended to be illustrative, not exhaustive, and not limited to the disclosed implementations. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described implementations. The terminology used herein is selected to best explain the principles of the implementations, their practical applications, or improvements to existing technologies, or to enable others skilled in the art to understand the various implementations disclosed herein.

Claims

1. A processor, comprising: an instruction decoder configured to decode at least one target instruction to obtain at least one source storage location in a memory for reading at least one to-be-processed data, at least one target storage location in the memory for writing at least one processing result, and at least one vector operation to be performed on the at least one to-be-processed data, wherein each target instruction involves a target opcode, a source operand, and a target operand, the target opcode indicating a corresponding vector operation, the source operand at least specifying a corresponding source storage location, and the target operand at least specifying a corresponding target storage location; as well as an arithmetic logic unit, coupled to the instruction decoder and the memory, and configured to: reading the at least one data to be processed from the at least one source storage location of the memory; performing, on the at least one data to be processed, at least one arithmetic-logical operation associated with at least one vector operation specified by the at least one target instruction; as well as writing at least one processing result of the at least one data to be processed into the at least one target storage location of the memory, The target storage location corresponding to the first target instruction among the at least one target instruction includes a corresponding processing result vector, and the target operand of the first target instruction also indicates a corresponding target vector mask VM register, and the values ​​at each position of the target vector mask VM register indicate whether the corresponding position of the corresponding processing result vector is to be written with the corresponding processing result.

2. The processor according to claim 1 , wherein the first target instruction comprises a first index determination instruction, a source operand corresponding to the first index determination instruction specifies a location of a first storage space of the memory, and the source operand further specifies a given index value of corresponding data to be processed in a second storage space of the memory, and The arithmetic logic unit is configured to perform the arithmetic logic operation associated with the vector operation specified by the first target instruction as follows: A first index corresponding to the first index determination instruction is determined, where the first index indicates a storage position of a value at a position indicated by a given index value in the data to be processed in the first storage space.

3. The processor according to claim 1 , wherein the first target instruction comprises a second index determination instruction, a source operand corresponding to the second index determination instruction specifies a location in a first storage space of the memory, and the source operand further specifies a first immediate value, and The arithmetic logic unit is configured to perform the arithmetic logic operation associated with the vector operation specified by the first target instruction as follows: A second index corresponding to the second index determination instruction is determined, where the second index indicates a storage location of the first immediate value in the first storage space.

4. The processor according to claim 1 , wherein the first target instruction comprises a first value determination instruction, a source operand corresponding to the first value determination instruction specifies a location in a first storage space of the memory, and the source operand further specifies a given index value of corresponding data to be processed in a second storage space of the memory, and The arithmetic logic unit is configured to perform the arithmetic logic operation associated with the vector operation specified by the first target instruction as follows: determining a given value of the data to be processed at a position indicated by the given index value; and A first value in the first memory space at a location indexed by the given value is determined.

5. The processor according to claim 1 , wherein the first target instruction comprises a second value determination instruction, a source operand corresponding to the second value determination instruction specifies a given index value of corresponding data to be processed in the second storage space of the memory, and The arithmetic logic unit is configured to perform the arithmetic logic operation associated with the vector operation specified by the first target instruction as follows: A second value at a position indicated by a given index value in the data to be processed is determined.

6. The processor of claim 1 , wherein the first target instruction comprises a vector transpose instruction, a source operand corresponding to the vector transpose instruction at least designates a first location in a first storage space in the memory, and The arithmetic logic unit is configured to perform the arithmetic logic operation associated with the vector operation specified by the first target instruction as follows: Perform vector transposition on the corresponding to-be-processed data at the first position in the first storage space to obtain transposed to-be-processed data.

7. The processor of claim 1 , wherein the first target instruction comprises an exponent instruction, a source operand corresponding to the exponent instruction designating the source storage location, and The arithmetic logic unit is configured to perform the arithmetic logic operation associated with the vector operation specified by the first target instruction as follows: The corresponding to-be-processed data at the source storage location is raised to a power to determine an exponent value with a predetermined value as a base.

8. The processor of claim 1 , wherein the first target instruction comprises a vector mask VM register instruction, a source operand corresponding to the vector mask VM register instruction indicates a source VM register in the memory, and The arithmetic logic unit is configured to perform the arithmetic logic operation associated with the vector operation specified by the first target instruction as follows: An index of an enabled location in the source VM register is stored at the target storage location.

9. The processor according to claim 1 , wherein the at least one target instruction comprises a one-hot code conversion instruction, a source operand corresponding to the one-hot code conversion instruction specifies a given index value of corresponding to-be-processed data in the second storage space of the memory, and the target operand specifies a target vector mask VM register, and The arithmetic logic unit is configured to perform the arithmetic logic operation associated with the vector operation specified by the target instruction as follows: Convert the value of the to-be-processed data at a given index value into a one-hot code; and The one-hot code is stored in the target vector mask VM register.

10. A data processing method, comprising: decoding at least one target instruction for a vector operation to obtain at least one source storage location in a memory for reading at least one datum to be processed, at least one target storage location in the memory for writing at least one processing result, and at least one vector operation to be performed on the at least one datum to be processed, wherein each target instruction includes a target opcode, a source operand, and a target operand, the target opcode indicating a corresponding vector operation, the source operand specifying at least a corresponding source storage location, and the target operand specifying at least a corresponding target storage location; reading the at least one data to be processed from the at least one source storage location of the memory; performing, on the at least one data to be processed, at least one arithmetic-logical operation associated with at least one vector operation specified by the at least one target instruction; as well as writing at least one processing result of the at least one data to be processed into the at least one target storage location of the memory, The target storage location corresponding to the first target instruction among the at least one target instruction includes a corresponding processing result vector, and the target operand of the first target instruction also indicates a corresponding target vector mask VM register, and the values ​​at each position of the target vector mask VM register indicate whether the corresponding position of the corresponding processing result vector is to be written with the corresponding processing result.

11. The method according to claim 10, wherein the first target instruction comprises an index determination instruction, a source operand corresponding to the index determination instruction specifies a location of the first storage space of the memory, and the source operand further specifies at least one of the following: a given index value of corresponding to-be-processed data in the second storage space of the memory, a first immediate value, and Wherein performing at least one arithmetic-logical operation associated with at least one vector operation specified by the at least one target instruction comprises at least one of the following: determining a first index, where the first index indicates a storage location in the first storage space of a value at a location indicated by a given index value in the data to be processed; A second index is determined, where the second index indicates a storage location of the first immediate value in the first storage space.

12. The method according to claim 10 , wherein the first target instruction comprises a first value determination instruction, a source operand corresponding to the first value determination instruction specifies a location in a first storage space of the memory, and the source operand further specifies a given index value of corresponding data to be processed in a second storage space of the memory, and Wherein performing at least one arithmetic-logical operation associated with at least one vector operation specified by the at least one target instruction comprises: Determining a given value of the data to be processed at a position indicated by the given index value; as well as A first value in the first memory space at a location indexed by the given value is determined.

13. The method according to claim 10 , wherein the first target instruction comprises a second value determination instruction, a source operand corresponding to the second value determination instruction specifies a given index value of corresponding data to be processed in the second storage space of the memory, and Wherein performing at least one arithmetic-logical operation associated with at least one vector operation specified by the at least one target instruction comprises: A second value at a position indicated by a given index value in the data to be processed is determined.

14. The method according to claim 10, wherein the first target instruction comprises a vector transpose instruction, a source operand corresponding to the vector transpose instruction at least specifies a first location in a first storage space in the memory, and Wherein performing at least one arithmetic-logical operation associated with at least one vector operation specified by the at least one target instruction comprises: Perform vector transposition on the corresponding to-be-processed data at the first position in the first storage space to obtain transposed to-be-processed data.

15. The method of claim 10, wherein the first target instruction comprises an exponent instruction, a source operand corresponding to the exponent instruction designating the source storage location, and Wherein performing at least one arithmetic-logical operation associated with at least one vector operation specified by the at least one target instruction comprises: The corresponding to-be-processed data at the source storage location is raised to a power to determine an exponent value with a predetermined value as a base.

16. The method of claim 10, wherein the first target instruction comprises a vector mask VM register instruction, a source operand corresponding to the vector mask VM register instruction indicates a source VM register in the memory, and Wherein performing at least one arithmetic-logical operation associated with at least one vector operation specified by the at least one target instruction comprises: An index of an enabled location in the source VM register is stored at the target storage location.

17. The method according to claim 10, wherein the at least one target instruction comprises a one-hot code conversion instruction, a source operand corresponding to the one-hot code conversion instruction specifies a given index value of corresponding to-be-processed data in the second storage space of the memory, and the target operand specifies a target vector mask VM register, and Wherein performing at least one arithmetic-logical operation associated with at least one vector operation specified by the at least one target instruction comprises: Convert the value of the data to be processed at a given index value into a one-hot code; as well as The one-hot code is stored in the target vector mask VM register.

18. An electronic device comprising at least the processor according to any one of claims 1 to 9.

19. A computer-readable storage medium having a computer program stored thereon, wherein the computer program is executed by a processor to implement the method according to any one of claims 10 to 17.

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