Capacitorless dram cell

Abstract

A capacitorless DRAM cell (200) includes a heterostructure, a gate structure (106, 107) adjoining the heterostructure in a first direction, a drain structure (108) adjoining the heterostructure in a second direction perpendicular to the first direction, and a source structure (104) adjoining the heterostructure in a direction opposite the second direction, the heterostructure including one or more semiconducting channel layers (610, 612) and one or more electrically insulating barrier layers (620, 622, 624), the channel layers (610, 612) and the barrier layers (620, 622, 624) being alternately stacked in the first direction.

Description

BACKGROUND

[0001] The present invention relates to integrated semiconductor memory devices, and more specifically, to a capacitorless dynamic random access memory (DRAM) cell.

[0002] DRAMs store data as a positive or negative charge in a capacitive structure. The structure that provides the capacitance, along with the transistor that controls access to it, is collectively referred to as a DRAM cell. They are the basic building blocks in a DRAM array. There are multiple DRAM memory cell variants, but the most commonly used variant in modern DRAMs is the single transistor, single capacitor (IT1C) cell. The transistor is used to admit current into the capacitor during a write operation, and to discharge the capacitor during a read operation. SUMMARY

[0003] In one aspect, the present invention relates to a capacitorless DRAM cell. The cell includes a heterostructure, a gate structure adjoining the heterostructure in a first direction, a drain structure adjoining the heterostructure in a second direction perpendicular to the first direction, and a source structure adjoining the heterostructure in a direction opposite the second direction. The heterostructure includes one or more semiconducting channel layers and one or more electrically insulating barrier layers, the channel layers and the barrier layers being alternately stacked in the first direction.

[0004] Embodiments of the capacitorless DRAM cell (referred to simply as "cell") can have advantages that arise from the heterostructure replacing a conventional MOSFET-type channel. Although each channel layer can still be viewed as a volume of material that, depending on the configuration of voltages applied to the adjoining source, gate, and drain structures, can allow for the storage of charge carriers (electrons and / or holes) or their transport in the positive or negative second direction, each barrier layer is electrically insulating and thus can prevent the transport of charge carriers across the barrier layer (i.e., in the positive or negative first direction). Thus, each barrier layer can contribute to increasing the retention time of electrons and / or holes by suppressing or impeding loss effects (e.g., by recombination or tunneling out of the heterostructure) that involve movement of the carriers in the positive or negative first direction.

[0005] In this embodiment, the heterostructure includes a single barrier layer and two channel layers. The alternating configuration of the channel layers and barrier layers in the heterostructure means that the barrier layer separates the two channel layers into one channel layer facing the gate structure and one channel layer facing away from the gate structure. For example, if a negative voltage is applied to the gate structure, the gate structure becomes attractive to holes and repulsive to electrons; therefore, the channel layer facing the gate structure can be referred to as the "hole channel" and the channel layer facing away from the gate structure as the "electron channel." Conversely, if a positive voltage is applied to the gate structure, the gate structure becomes attractive to electrons and repulsive to holes; therefore, in this case, the channel layer facing the gate structure can be referred to as the "electron channel" and the channel layer facing away from the gate structure as the "hole channel."

[0006] In another aspect, the present invention relates to a method for manufacturing a capacitor-free DRAM cell. The method includes:

[0007] A heterostructure is formed, the heterostructure comprising one or more semiconductor channel layers and one or more electrically insulating barrier layers, wherein the channel layers and barrier layers are stacked alternately in a first direction;

[0008] A gate structure is formed in which heterogeneous structures are adjacent in the first direction;

[0009] A drain structure with adjacent heterostructures is formed in a second direction perpendicular to the first direction; and

[0010] A source structure with adjacent heterostructures is formed in a direction opposite to the second direction. Attached Figure Description

[0011] In the following description, embodiments of the invention will be explained in more detail by way of example only, with reference to the accompanying drawings, in which:

[0012] Figure 1a) shows a schematic cross-sectional view of a capacitor-less DRAM cell storing logic state '0';

[0013] Figure 1b) shows a schematic cross-sectional view of a capacitorless DRAM cell storing logic state '1';

[0014] Figure 1c) shows a graph of two IV curves with a capacitor-free DRAM cell;

[0015] Figure 1d) shows a schematic cross-sectional view of a capacitorless DRAM cell during a write operation in logic state '0';

[0016] Figure 1e) shows a schematic cross-sectional view of a capacitorless DRAM cell during a write operation in logic state '1';

[0017] Figure 2A schematic cross-sectional view of an exemplary capacitor-free DRAM cell is shown, characterized by a barrier layer that connects the gate structure and the channel layer at the interface.

[0018] Figure 3 A schematic cross-sectional view of an exemplary capacitor-free DRAM cell is shown, characterized by a barrier layer that connects two channel layers at the interface.

[0019] Figure 4 A schematic cross-sectional view of an exemplary capacitor-free DRAM cell is shown, characterized by a barrier layer that connects the substrate and the channel layer at the interface.

[0020] Figure 5 A schematic cross-sectional view of an exemplary capacitor-free DRAM cell characterized by two barrier layers and one channel layer is shown.

[0021] Figure 6 A schematic cross-sectional view of an exemplary capacitor-free DRAM cell characterized by three barrier layers and two channel layers is shown.

[0022] Figure 7a) shows a diagram with two input signals used for testing a capacitorless DRAM cell; and

[0023] Figures 7b) through 7d) all show diagrams illustrating the output signals of a capacitorless DRAM cell in response to receiving two input signals used for testing; and

[0024] Figure 8 The drain current response of a capacitorless DRAM cell tested using two input signals is shown. Detailed Implementation

[0025] Over the past few decades, significant research efforts have been made to reduce the size of memory cells in volatile memories such as DRAM. Until now, DRAM cells have been limited by the size of their external capacitors. One promising approach to achieving further miniaturization is to eliminate the capacitors and use the blind capacitance of transistors instead of storing charge carriers representing information. The transistor structure used in DRAM cells is typically a derivative of the metal-oxide-semiconductor field-effect transistor (MOSFET), which implements a source structure, a channel structure, and a drain structure arranged in sequence, along with a gate structure adjacent to the channel structure.

[0026] Several candidates for such capacitor-free single-transistor (“1T”) DRAM cells, such as ARAM and MSDRAM, have been proposed. These devices utilize a so-called floating-body effect to inject holes and electrons into the channel via band-to-band tunneling when the gate and drain, or gate and source, are subjected to bias voltages of opposite signs. During the subsequent retention time, a sufficient portion of the injected carriers remain in the channel, and the cell state can be read out using the memory effect of the drain-source current flowing through the transistor. This promising concept has been used to demonstrate functional 1T DRAM cells and is considered one of only a few ways forward for DRAM scaling.

[0027] Key challenges of this technology include increasing via retention time and increasing drain-source current (or, alternatively, reducing the required drive bias voltage). Another challenge is scalability—the total channel thickness cannot be highly scaled because recombination rates typically increase with carrier density.

[0028] Several designs for capacitor-less DRAM cells have been demonstrated. Currently, the expectation is to increase carrier retention time and drain-to-source current to achieve sufficient market viability.

[0029] For clarity, several terms or implied conditions used throughout this disclosure will be defined below.

[0030] Materials used for heterostructures in capacitor-free DRAM cells also include semiconductors and insulators. The channel layer of each semiconductor can be made of pure (undoped) semiconductor, intrinsic semiconductor (i-type, doped or undoped, with equal numbers of excited electrons n and holes p), or doped semiconductor (with 10... 18 cm -3 It can be made with a lower dopant concentration. Each insulating (non-conductive) barrier layer can be made of a material whose conductivity cannot be improved using techniques such as doping or gating.

[0031] This capacitor-free DRAM cell is characterized by a heterogeneous structure comprising channel layers and barrier layers alternately stacked in a first direction. The terms "stacked," "stacked," etc., do not necessarily imply that the first direction is perpendicular to the vertical. In fact, the layers of the heterogeneous structure can be stacked on top of each other in any first direction, including the horizontal direction.

[0032] Memory cells can (but do not necessarily) be formed on a substrate such as a semiconductor wafer. Specifically, a memory cell can be a semiconductor-on-insulator (SOI) device. If formed on a substrate, a bias voltage can be provided to the substrate; that is, the substrate can serve as a second gate or a back gate. Similarly, the source structure, the gate structure, the drain structure, and (if applicable) the substrate can be implemented with electrical contacts to enable the provision of (bias) voltage and / or the establishment of current, and can include any suitable known or future material structures, such as n-type doped semiconductors, p-type doped semiconductors, intrinsic or i-type semiconductors, metals, high-k or low-k dielectrics, and / or insulators, which are adapted, respectively, for implementing the source, gate, drain, and optionally back gate of a field-effect transistor.

[0033] A capacitor-less DRAM cell can operate as follows: charge carriers residing in the channel layer of a heterostructure can encode at least two states, '1' and '0', for one bit of information. In a purely illustrative, non-limiting example, writing a '1' operation may include providing a gate structure with a negative voltage and a drain structure with a positive voltage, such that holes are injected into the channel layer or region facing the gate structure via band-to-band tunneling, and electrons are injected into the channel layer or region away from the gate structure via band-to-band tunneling. The number of injected electrons is electrostatically coupled to the number of injected holes. Due to the buoyancy effect, the charge carriers remain in the heterostructure for a period of time. In this example, writing a '0' operation includes clearing the charge carriers from the heterostructure by a near-flat band bias condition (i.e., setting the gate structure to a slightly positive voltage and the source and drain structures to zero voltage).

[0034] During the read operation, a small drain bias is applied, and the drain current is measured. The excess charge carriers within the heterostructure in the '1' state cause an increase in the drain current (in absolute value) compared to the current in the '0' state. In this example, the state '0' or '1' is maintained by also providing a negative bias voltage to the gate structure. If the cell were implemented on the back gate, it would be set to a positive back gate bias voltage throughout this example.

[0035] According to an embodiment, the heterostructure includes a single barrier layer and a single channel layer. The alternating configuration of the channel and barrier layers in the heterostructure means that the barrier layer insulates the channel layer from the gate structure or any structure adjacent to the heterostructure on a side facing away from the gate structure. This provides the benefit of increased charge carrier retention time by suppressing spontaneous movement and / or tunneling of charge carriers out of the heterostructure and / or their spontaneous recombination with other charge carriers from any structure adjacent to the heterostructure in a positive or negative first direction.

[0036] According to an embodiment, the heterostructure includes two barrier layers and two channel layers. The alternating configuration of the channels and barrier layers in the heterostructure means that one of the barrier layers separates the two channel layers from each other, and the other barrier layer either insulates the gate-facing barrier layer from the gate structure or insulates the barrier layer facing away from the gate structure from other structures adjacent to the heterostructure. This can have the advantages of increased charge carrier retention time and / or improved miniaturization capability due to the barrier layers separating the two channel layers; and further increased charge carrier retention time by suppressing spontaneous movement and / or tunneling of charge carriers out of the heterostructure and / or their spontaneous recombination with other charge carriers from any structure adjacent to the heterostructure in a positive or negative first direction. If the gate structure includes an oxide layer or other insulating layer adjacent to the heterostructure, and the heterostructure already provides significant suppression of charge carrier migration out of the heterostructure, then the configuration in which one of the barrier layers is placed facing away from the gate structure may be useful.

[0037] According to embodiments, the heterostructure includes at least two barrier layers made of different barrier layer materials. The selection of different barrier layer materials may include, but is not limited to, materials suitable for fabricating barrier layers as mentioned herein. Implementing barrier layers made of different barrier layer materials can provide the benefit of improved ability to restrict the movement of charge carriers in a first direction, either positive or negative, within the heterostructure. More precisely, some or all of the barrier layers may be made of a barrier layer material that suppresses the movement of one type of charge carrier (i.e., electrons or holes) more effectively than the other.

[0038] This can be useful if it can be anticipated that, during the operation of the cell, the types of charge carriers to be selectively confined by a given barrier layer will typically be confined to the location of that barrier layer. For example, if the cell is designed to hold the cell in its programmed state by providing a negative voltage to the gate structure, i.e., maintaining the set of injected charge carriers representing '0' or '1' states within the heterostructure, it can be expected that any injected holes will move closer to the gate structure, i.e., closer to the channel layer facing the gate structure, while correspondingly injected electrons will move to the side of the heterostructure opposite the gate structure, i.e., to the channel layer away from the gate structure. In this example, holes can be confined to their hole channel layer by providing a barrier layer that is selectively impermeable to holes between the gate structure and the hole channel layer, and / or electrons can be confined to their electron channel layer by providing a barrier layer that is selectively impermeable to electrons between any structure adjacent to the heterostructure on the side opposite the gate structure. The specific choice of material for a selectively impermeable barrier layer may depend on the material of the corresponding trench layer to be insulated or any other structure adjacent to the given barrier layer.

[0039] According to embodiments, the heterostructure includes at least two channel layers made of different channel layer materials. The selection of different channel layer materials may include, but is not limited to, the materials suitable for fabricating channel layers mentioned herein. Implementing channel layers made of different channel layer materials can provide the possibility of designing some or all of the channel layers with specific properties tailored for a single charge carrier (i.e., electrons or holes).

[0040] For example, it is possible to optimize the increased carrier mobility in each channel layer of a heterostructure characterized by two channel layers; that is, to select a channel layer material with high electron mobility for one channel layer and a channel layer material with high apparent hole mobility for the other. This can increase the conductivity of the heterostructure in the positive or negative second direction, and thus increase the drain-source current of the cell. However, other criteria, either specific or non-specific, for the type of charge carriers, such as spin characteristics affecting charge carriers or lattice properties that promote compatibility with adjacent structures, can be considered for selecting suitable different channel layer materials.

[0041] If it can be anticipated that, during cell operation, a certain type of charge carrier to be selectively stored within a given channel layer will generally be located at the position of the channel layer, then implementing different channel layers with carrier-specific properties can be useful. For example, if the cell is designed to remain in its programmed state by providing a negative voltage to the gate structure, i.e., maintaining the binding of injected charge carriers representing '0' or '1' states within the heterostructure, then any injected holes can be expected to move closer to the gate structure, i.e., closer to the channel layer facing the gate structure, while correspondingly injected electrons will move to the side of the heterostructure opposite the gate structure, i.e., to the channel layer away from the gate structure. In this example, a material with desired properties relative to holes can be selected as the channel layer material for the channel layer facing the gate structure, and / or a material with desired properties relative to electrons can be selected as the channel layer material for the channel layer away from the gate structure. It is possible that the specific choice of selectively optimized channel layer material depends on the material of the adjacent barrier layer or any other structure adjacent to the given channel layer that insulates it.

[0042] According to embodiments, the bandgap energies of different channel layer materials differ by at least 0.5 eV. This allows for the optimization of some or all of the channel layers through bandgap engineering. For example, a channel layer dedicated to hole transport can be implemented using a channel layer material with a lower bandgap energy (or more generally, a relatively low bandgap energy, or in other words, a relatively narrow bandgap), because the narrower bandgap can increase the apparent hole transport rate due to tunneling. This can result in shorter times for injecting and clearing holes from a dedicated hole channel layer, and thus increase the cell read / write cycle time.

[0043] According to an embodiment, the electron mobility of these different channel layer materials differs by at least 10 times. This can result in one or more channel layers specifically designed for implementing channel layers dedicated to electron transport (i.e., those channel layers with higher electron mobility). When used, for example in a readout device, this can increase the drain-source current of the cell.

[0044] According to an embodiment, the gate structure is adjacent to one of the barrier layers. In this way, the channel layer(s) of the heterostructure can be insulated from the gate structure, thereby preventing the accumulation of gate current. It should be noted that in the case where the barrier layer is adjacent to the gate structure, it may not be necessary to provide a gate structure with a gate insulating layer (e.g., an oxide layer), although this is generally the case throughout FET fabrication today. This can simplify the fabrication process of capacitor-less DRAM cells. Furthermore, this can prevent or hinder the spontaneous movement or tunneling of charge carriers from the heterostructure into the gate structure and / or spontaneous recombination with charge carriers from the gate structure.

[0045] According to an embodiment, the gate structure includes a gate insulator layer adjacent to a barrier layer. The gate insulator layer can be made of an electrical insulator such as an oxide and can prevent the exchange of charge carriers between the heterostructure and the gate structure, so that the charge carriers in the heterostructure can be controlled by a field effect when the gate structure is biased. As mentioned above, although it may not be necessary to provide a gate structure with a gate insulator layer if the heterostructure is adjacent to the gate structure with a barrier layer, it may still be useful to implement a gate structure with a gate insulator layer, as this can increase the total insulation thickness between the channel layer facing the gate structure and the conductive material implemented in the gate structure, so that the gate structure can be set to a desired voltage. A higher total insulation thickness can reduce the probability of leakage current between the gate and the heterostructure and / or enable a higher voltage for the gate structure.

[0046] According to an embodiment, the cell is disposed on a substrate, and the heterostructure is adjacent to the substrate. This can increase the mechanical stability of the cell and provide the possibility of applying a back gate voltage to the heterostructure, making the capacitorless DRAM cell a dual-gate device.

[0047] According to an embodiment, one of these barrier layers is adjacent to the substrate. In this way, the channel layer(s) of the heterostructure can be insulated from the substrate, thereby preventing the accumulation of back gate current. It should be noted that in the case where the barrier layer is adjacent to the substrate, it may not be necessary to provide a substrate insulating layer (e.g., a buried oxide layer) for the substrate, although this is often done throughout the fabrication of semiconductor-on-insulator (SOI) devices today. This can simplify the fabrication process of capacitor-less DRAM cells. Furthermore, this can prevent or hinder the spontaneous movement or tunneling of charge carriers out of the heterostructure into the substrate and / or the spontaneous recombination with charge carriers from the substrate.

[0048] According to an embodiment, the substrate includes a substrate insulating layer, and the heterostructure is adjacent to the substrate insulating layer. The substrate insulating layer may be made of an electrical insulator such as an oxide (including, but not limited to, a buried oxide layer) and may prevent the exchange of charge carriers between the heterostructure and the substrate. This may be advantageous for implementing the substrate as a back-gate structure to achieve field-effect control of charge carriers in the heterostructure when the back-gate structure is biased. As mentioned above, although a substrate with a substrate insulating layer may not be necessary if the heterostructure is adjacent to the substrate with a barrier layer, it may still be useful to additionally implement a back-gate structure with a gate insulating layer if the substrate is implemented as a back-gate structure, as this can increase the total insulating thickness between the channel layer facing the back-gate structure and the conductive material implemented in the back-gate structure, making it possible to set the back-gate structure to a desired voltage. A higher total insulating thickness can reduce the probability of leakage current between the back gate and the heterostructure, and / or enable a higher voltage to be provided for the back-gate structure.

[0049] According to an embodiment, the gate structure is adjacent to the heterostructure only in a first direction. Applying a voltage bias to the gate structure allows for the application of a more uniform, directional electric field on the heterostructure. Therefore, this reduces the likelihood of leakage current due to charge carriers bypassing one or more barrier layers due to field asymmetry.

[0050] According to an embodiment, the gate structure buries the heterostructure. This prevents the gate structure from undercutting the heterostructure and thus increases the efficiency of charge carrier injection, retention, and evacuation. In other words, compared to a cell with a gate structure having an undercut heterostructure, the number and velocity of charge carriers can be increased during injection, the retention time of charge carriers in the heterostructure can be increased, and the evacuation of charge carriers from the heterostructure can be accelerated.

[0051] According to an embodiment, the gate structure is aligned with the heterostructure in a second direction and in a direction opposite to the second direction. This prevents the gate structure from undercutting the heterostructure and from overlapping with the source and / or drain structures. While avoiding undercutting the gate structure can improve the efficiency of charge carrier injection, retention, and discharge (as described above), avoiding overlapping gate structures can reduce the probability of affecting charge carriers in the source and / or drain regions through field effects, and thus can increase the drain-to-source current.

[0052] According to an embodiment, each of the channel layer and each of the barrier layer is adjacent to both the source and drain structures. This can reduce the probability of leakage current caused by carriers in the heterostructure bypassing the barrier layer.

[0053] According to an embodiment, each of the barrier layers is made of a barrier layer material selected from the group consisting of silicon, silicon oxide, indium oxide, and indium phosphide for each of the barrier layers. According to an embodiment, each of the channel layers is made of a channel layer material selected from the group consisting of indium arsenide, gallium arsenide, indium gallium arsenide, indium tin oxide, germanium, and silicon germanium for each of the channel layers.

[0054] These materials enable the efficient storage and transport of charge carriers in heterostructures. It may be useful to adjoin chemically and / or crystallographically similar materials in the heterostructure to reduce the probability of defects in the crystal structure. In an illustrative example, the heterostructure includes a channel layer made of indium gallium arsenide adjacent to a barrier layer made of indium oxide adjacent to a channel layer made of indium arsenide. It should be emphasized that the capacitor-less DRAM cells disclosed herein primarily concern the structure of the cell and are generally of unknown materials.

[0055] According to an embodiment, the heterostructure has a total length between 1 nanometer and 75 nanometers, measured in a second direction. This size range allows for operation of the cell at higher read / write cycle speeds and / or lower voltages to be applied to the source, gate, and / or drain structures, and reduces the probability of electrostatic induction between the source and drain.

[0056] According to an embodiment, the thickness of each channel layer measured in the first direction is between 1.5 and 5 times the thickness of each barrier layer measured in the first direction. This size range provides additional volume for the channel layers to store charge carriers, and thus increases the capacitance of the heterostructure. This may also result in an increase in the difference and / or ratio of the readout drain current representing the '1' and '0' states of the cell.

[0057] Turning now to the accompanying drawings, Figure 1 illustrates the general principle of operation of a capacitorless DRAM cell. Figures 1a), 1b), 1d), and 1e) all show schematic cross-sectional views of a capacitorless DRAM cell 100. Cell 100 is formed on a substrate 102 and includes a source structure 104, a channel structure 110, a drain structure 108, and gate structures 106 and 107. Source structure 104 and drain structure 108 are adjacent to channel structure 110. Source structure 104, channel structure 110, and drain structure 108 are adjacent to substrate 102. Gate structures 106 and 107 include a gate electrode 106 and a gate insulator 107, with the gate insulator 107 interface connecting the gate electrode 106 to the channel structure 110. Source structure 104, gate electrode 106, drain structure 108, and substrate 102 are electrically contacted via terminals for providing a source voltage V to source structure 104. S Provide the front gate voltage V to the gate electrode 106 FG Provide drain voltage V to drain structure 108 D and providing the post-gate voltage V to the substrate 102 BG .

[0058] Cell 100 is adapted to encode logic states '0' and '1' by capturing holes (illustrated as small circles marked '+') in channel structure 110. Figures 1a) and 1b) both show cell 100 in a 'hold' state, in which voltage V... S =0V (volts), V FG <0V, V D =0V and V BG A combination of values ​​greater than 0V is applied to retain the holes trapped in the channel structure 110. V is set... FG <0V and V BG A voltage <0V ensures that holes are collected near the gate insulator 107 and any electrons (illustrated as small circles marked '-') are collected near the substrate 102. Both Figures 1a) and 1b) show a significantly greater number of trapped electrons compared to the number of trapped holes. In the '0' state (Figure 1a), the number of holes is negligible compared to the number of electrons, while in the '1' state (Figure 1b), both the number of holes and electrons increases. Figure 1b) also shows that electrons occupy a large volume of the channel structure 110, thus the distributions of electrons and holes begin to overlap.

[0059] Figure 1c) shows the back gate voltage V according to the applied back gate voltage V BG Drain-source current I DS The graph shows the two curves 130 and 131. Figure 1c) also shows the graph when V... BG Set to read voltage V RThe measured currents observed at different times. Curve 130 represents the measured current I in the '0' state. DS =I0 is significantly lower than the measured current I of curve 131, which represents the '1' state. DS =I1.

[0060] Figures 1d) and 1e) show the cell 100 of Figures 1a) and 1b), but different combinations of voltages are applied to program the cell 100 to have a '0' state (Figure 1d) or a '1' state (Figure 1e). For clarity, electrons have been omitted in Figures 1d) and 1e). By setting V S =0V、V FG >0V, V D =0V and V BG >0V to write the '0' state. V FG >0V and V BG The combination of >0V creates an attractive potential for electrons in the channel structure 110, allowing them to fill the main portion of the channel structure 110 and recombine with any holes that may be present. Statistically, this corresponds to a lack of electrons at the boundaries of the channel structure 110 and in the source and drain structures 104 and 108 (essentially outside the electric field between the front gate structures 106, 107 and the substrate 102 acting as the rear gate). Therefore, holes concentrate in the source and drain structures 104 and 108 (indicated by the arrows in Figure 1d). In other words, if holes are free charge carriers, the potential created within the channel structure 110 acts as a repulsive potential. Eventually, the channel structure 110 reaches a '0' state when it is essentially depleted of holes.

[0061] Figure 1e) illustrates the injection of holes into channel structure 110 during a write operation in logic state '1'. This is achieved by setting the voltage to V. S =0V、V FG <0V, V D >0V and V BG A value greater than 0V is used to program this state. In the lower part of the diagram, two dashed lines parallel to the boundary between drain structure 108 and channel structure 110 indicate the depletion region where there are no free carriers. V FG <0V and V D Combinations with values ​​greater than 0V cause bound electrons in the depletion region to leave their carrier atoms and tunnel into the conduction band of the drain structure 108, where V D A voltage greater than 0V creates an attractive potential for electrons. Similarly, the remaining aperture is repositioned within the channel structure 110, where the voltage Vfront is influenced by the gate voltage. FG<0V, these pores are trapped in the channel structure 110. The carrier creation process is indicated by the opposite arrows in the figure. Finally, when the hole density in the channel structure 110 reaches saturation, dynamic equilibrium, or V D When it is set back to 0V, it reaches the '1' state.

[0062] Figures 2 to 6 All figures show schematic cross-sectional views of an illustrative capacitor-free DRAM cell 200. In each figure, the depicted cell 200 includes a heterostructure, gate structures 106, 107 adjacent to the heterostructure in a first direction, a drain structure 108 adjacent to the heterostructure in a second direction perpendicular to the first direction, and a source structure 104 adjacent to the heterostructure in a direction opposite to the second direction. The heterostructure includes channel layers 210, 310, 312, 410, 510, 610, 612 of one or more semiconductors arranged in alternating stacks, and one or more electrically insulating barrier layers 220, 320, 420, 520, 522, 620, 622, 624. Without limitation, [the following is a description of the process, not a direct translation]... Figures 2 to 6 Specific examples depicted show gate structures 106, 107 including a gate electrode 106 and a gate insulating layer 107 adjacent to the heterostructure, and components of cell 200 are disposed on substrate 102. Detailed embodiments of the heterostructure vary between the figures and are discussed below.

[0063] exist Figure 2 In this heterostructure, a channel layer 210 and a barrier layer 220 are used to interface the channel layer 210 and the gate insulating layer 107. The insulating effect of the barrier layer 220 can impede or prevent charge carriers (electrons or holes) that may be present in the channel layer 210 from leaving the channel layer 210 by moving or tunneling into the gate structures 106, 107. Therefore, the use of a channel layer 210 with a barrier layer 220 adjacent to the gate structures 106, 107 can result in an increased retention time of charge carriers in the channel layer 210.

[0064] exist Figure 3In this heterostructure, two channel layers 310 and 312 are included, and a barrier layer 320 connects the channel layers 310 and 312 at the interface. The insulating effect of the barrier layer 320 can prevent charge carriers that may be present in the channel layer 310 from leaving the channel layer 310 by moving into the channel layer 312, and can also prevent charge carriers that may be present in the channel layer 312 from leaving the channel layer 312 by moving into the channel layer 310. Therefore, it can also prevent the recombination of charge carriers that may be present in the channel layer 310 with charge carriers of opposite charge that may be present in the channel layer 312. Thus, the use of two channel layers 310 and 312 with a barrier layer 320 can result in an increased retention time of charge carriers in the channel layers 310 and 312.

[0065] exist Figure 4 In this heterostructure, a channel layer 410 and a barrier layer 420 are used to interface the channel layer 410 and the substrate 102. The insulating effect of the barrier layer 420 can impede or prevent charge carriers that may be present in the channel layer 410 from leaving the channel layer 410 by moving or tunneling into the substrate 102. Therefore, using a channel layer 410 with a barrier layer 420 adjacent to the substrate can result in an increased retention time of charge carriers in the channel layer 410.

[0066] Typically, barrier layers implemented at different non-adjacent locations within a heterogeneous structure can be combined with each other. Figure 5 and 6 Each example shows one of these possible combinations.

[0067] exist Figure 5 In this heterostructure, a channel layer 510 is included, a barrier layer 522 connecting the channel layer 510 and the gate insulating layer 107, and a barrier layer 520 connecting the channel layer 510 and the substrate 102. The insulating effect of the barrier layer 522 can hinder or prevent charge carriers that may be present in the channel layer 510 from leaving the channel layer 510 by moving or tunneling into the gate structures 106, 107. Similarly, the insulating effect of the barrier layer 520 can hinder or prevent these charge carriers from leaving the channel layer 510 by moving or tunneling into the substrate 102. Therefore, the use of a channel layer 510 with two barrier layers 520, 522 can result in an increased retention time of charge carriers in the channel layer 510.

[0068] exist Figure 6In this heterostructure, two channel layers 610 and 612 are included, a barrier layer 624 connecting the channel layer 612 and the gate insulating layer 107, a barrier layer 622 connecting the channel layers 610 and 612, and a barrier layer 620 connecting the channel layer 610 and the substrate 102. The insulating effect of the barrier layer 624 can hinder or prevent charge carriers that may exist in the channel layer 612 from leaving the channel layer 612 by moving or tunneling into the gate structures 106 and 107. Similarly, the insulating effect of barrier layer 620 can prevent or inhibit the departure of charge carriers from channel layer 610 by moving or tunneling into substrate 102, and the insulating effect of barrier layer 622 can prevent or inhibit charge carriers that may be present in channel layer 610 from leaving channel layer 610 by moving into channel layer 612, and can prevent or inhibit charge carriers that may be present in channel layer 612 from leaving channel layer 612 by moving into channel layer 610, and can therefore prevent or inhibit the recombination of charge carriers that may be present in channel layer 610 with charge carriers of opposite charge that may be present in channel layer 612. Therefore, the use of two channel layers 610, 612 with three barrier layers 620, 622, 624 can result in an increased retention time of charge carriers in channel layers 610, 612.

[0069] Figures 7a) through 7d) illustrate the effects of the width and length of the channel structure 110 on the performance of the capacitorless DRAM cell 100, measured on prototypes implementing the channel structure 110 at different sizes. The length of the channel structure 110 is defined as the total dimension of the channel structure 110 in the second direction, which may be equal to the distance between the source structure 104 and the gate structures 106, 107. The width of the channel structure 110 is defined as the total dimension of the channel structure 110 in the main direction of its longitudinal extension, which is perpendicular to the first direction and different from the second direction, and is not limited to being perpendicular to the second direction.

[0070] Figure 7a) shows a graph with two input signals 700 and 702 used for testing a capacitorless DRAM cell. Curve 700 shows the front gate voltage V as a function of time. FG And curve 702 shows the drain voltage V as a function of time. D Both curves 700 and 702 show rectangular pulse sequences with a period of approximately 40 microseconds (µs). Each pulse shifts the corresponding voltage from a specific bias level to a temporary, constant pulse voltage level with a duty cycle of approximately 50%. The bias level is V FG It is -0.5V (volts) and for V D It is 0.0V.

[0071] In the first cycle (marked as 'W0' for 'Write 0'), V FG Increase to +1.0V and V D Maintain at the bias level. This causes holes to be drained from channel structure 110, making the ready logic state '0'. In cycles 2-6, for 'read' marked 'R', V FG Maintain at the bias level and V D The voltage rises to +0.5V. This allows for the reading of the current state of cell 100 over five cycles by measuring the drain current. In cycle 7, 'Write 1' is labeled 'W1', and V... FG Dropped to -1.0V and V D The voltage rises to +1.0V. This causes holes to be injected into channel structure 110, preparing logic state '1'. Loops 8-12 are five other read loops labeled 'R' with the same characteristics as loops 2-6. This allows for a comparative observation of the drain current response to the programming cycles W0 and W1 over time.

[0072] Figures 7b) through 7d) show the drain current response of specific capacitorless DRAM cell prototypes tested using signals 700 and 702 as input signals. The back gate voltage V is used. BG Perform all measurements at 2.0V.

[0073] The prototype used for the measurements in Figure 7b) implemented a nominal channel length of 90 nanometers (nm) (equivalent to a gate length L). g The channel width W is 2 micrometers (µm). The drain current I in the '0' state and the '1' state... D The phase difference Δ of the response of (curve 710) I =I1-I0=0.7µA (microamps), and has a ratio I R =I1 / I0=2.5. The prototype used for the measurement in Figure 7c implemented the nominal channel length L. g =20nm and 1μm channel width W. Drain current I in '0' state and '1' state. D The response (curve 712) differs by Δ I =17µA and has a ratio I R =7.9. ​​The prototype used for the measurement in Figure 7d) implemented the nominal channel length L. g =10nm and 1µm channel width W. Drain current I in '0' state and '1' state. D The response phase difference Δ of (curve 714) I =17µA and has a ratio I R =4.3.

[0074] Figure 8The drain current response of a capacitorless DRAM cell 200 tested using signals 700 and 702 as input signals is shown. Figure 8 The prototype for the measurement implemented a heterostructure comprising a channel layer 410 and two barrier layers 420, 422. In each logic state (i.e., in logic state '0', I...) D = I0 and I in logic state '1' D The drain current I during the five repeated read cycles under = I1) D The comparison of the time development (curve 800) with the corresponding time development observed in Figures 7b) to 7d) shows that the read current level of curve 800 has a larger relaxation time constant for spontaneous carrier capture or loss than the relaxation time constants of curves 710, 712, and 714.

[0075] Various embodiments of the invention have been described for illustrative purposes, but this description is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the invention. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements over those found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0076] The invention will be described again below by a list of terms highlighting several possible, non-exclusive combinations of the features disclosed herein:

[0077] 1. A capacitor-free DRAM cell, the cell comprising a heterostructure, a gate structure adjacent to the heterostructure in a first direction, a drain structure adjacent to the heterostructure in a second direction perpendicular to the first direction, and a source structure adjacent to the heterostructure in a direction opposite to the second direction, the heterostructure comprising one or more semiconductor channel layers and one or more electrically insulating barrier layers, the channel layers and the barrier layers being alternately stacked in the first direction.

[0078] 2. The DRAM cell according to Clause 1, wherein the heterostructure comprises a single barrier layer and a single channel layer.

[0079] 3. The DRAM cell according to Clause 1, wherein the heterostructure comprises a single barrier layer and two channel layers.

[0080] 4. The DRAM cell according to Clause 1, wherein the heterostructure comprises two barrier layers and a single channel layer.

[0081] 5. The DRAM cell according to Clause 1, wherein the heterostructure includes two barrier layers and two channel layers.

[0082] 6. The DRAM cell according to Clause 1, wherein the heterostructure comprises three barrier layers and two channel layers.

[0083] 7. The DRAM cell according to any one of the preceding clauses, wherein the heterostructure comprises at least two barrier layers made of different barrier layer materials.

[0084] 8. The DRAM cell according to any one of the preceding clauses, wherein the heterostructure comprises at least two channel layers made of different channel layer materials.

[0085] 9. In the DRAM cell described in Clause 8, the bandgap energy of different channel layer materials differs by at least 0.5 electron volts.

[0086] 10. In the DRAM cells described in Clause 8 or 9, the electron mobility of different channel layer materials differs by at least 10 times.

[0087] 11. The DRAM cell according to any one of the preceding clauses, wherein the gate structure is adjacent to one of the barrier layers.

[0088] 12. The DRAM cell according to Clause 11, wherein the gate structure includes a gate insulating layer adjacent to the barrier layer.

[0089] 13. The DRAM cell according to any one of the preceding clauses, wherein the cell is disposed on a substrate and the heterostructure is adjacent to the substrate.

[0090] 14. The DRAM cell according to Clause 13, wherein the substrate includes a substrate insulating layer, and the heterostructure is adjacent to the substrate insulating layer.

[0091] 15. A DRAM cell according to Clause 13 or 14, wherein one of the barrier layers is adjacent to the substrate.

[0092] 16. In any of the preceding clauses, the gate structure is adjacent to the heterostructure only in the first direction.

[0093] 17. In any of the preceding clauses, the gate structure of the DRAM cell buries the heterostructure.

[0094] 18. The DRAM cell according to Clause 17, wherein the gate structure is aligned with the heterostructure in the second direction and in a direction opposite to the second direction.

[0095] 19. In any of the preceding clauses, each of the channel layers and each of the barrier layers is adjacent to both the source structure and the drain structure.

[0096] 20. In any of the preceding clauses, each of the barrier layers is made of a barrier layer material, and for each of the barrier layers, the barrier layer material is selected from the group consisting of silicon, silicon oxide, indium oxide and indium phosphide.

[0097] 21. In any of the preceding clauses, each of the DRAM cells is made of a channel layer material, wherein for each of the channel layers, the channel layer material is selected from the group consisting of indium arsenide, gallium arsenide, indium gallium arsenide, indium tin oxide, germanium, and silicon germanium.

[0098] 22. The DRAM cell according to any one of the preceding clauses, wherein the heterostructure has a total length between 1 nanometer and 75 nanometers, measured in the second direction.

[0099] 23. In any of the preceding clauses, the total width of the heterostructure measured in a third direction perpendicular to the first and second directions is between 20 and 200 times the total length of the heterostructure measured in the second direction.

[0100] 24. In any of the preceding clauses, the thickness of each channel layer measured in the first direction is between 1.5 and 5 times the thickness of each barrier layer measured in the first direction.

[0101] 25. A method for manufacturing a capacitor-free DRAM cell, the method comprising:

[0102] A heterostructure is formed, the heterostructure comprising one or more semiconductor channel layers and one or more electrically insulating barrier layers, the channel layers and the barrier layers being stacked alternately in a first direction;

[0103] A gate structure is formed adjacent to the heterostructure in the first direction;

[0104] A drain structure adjacent to the heterostructure is formed in a second direction perpendicular to the first direction; and

[0105] A source structure is formed adjacent to the heterostructure in a direction opposite to the second direction.

Claims

1. A capacitor-free DRAM cell, the cell comprising: A heterostructure comprising a channel layer of one or more semiconductors and at least two electrically insulating barrier layers, wherein the channel layer and the barrier layers are stacked alternately in a first direction, and each barrier layer is made of a different material; A gate structure adjacent to the heterostructure in the first direction, wherein the gate structure includes a gate insulating layer adjacent to the barrier layer; A drain structure, wherein the drain structure is adjacent to the heterostructure in a second direction perpendicular to the first direction; as well as A source structure, wherein the source structure is adjacent to the heterostructure in a direction opposite to the second direction.

2. The DRAM cell according to claim 1, wherein the heterostructure comprises two barrier layers and a single channel layer.

3. The DRAM cell according to claim 1, wherein the heterostructure comprises two barrier layers and two channel layers.

4. The DRAM cell according to claim 1, wherein the heterostructure comprises three barrier layers and two channel layers.

5. The DRAM cell of claim 1, wherein the heterostructure comprises at least two channel layers, wherein each channel layer is made of a different material.

6. The DRAM cell according to claim 5, wherein the bandgap energies of the different channel layer materials differ by at least 0.5 electron volts.

7. The DRAM cell according to claim 5, wherein the electron mobility of different channel layer materials differs by at least 10 times.

8. The DRAM cell of claim 1, wherein the gate structure is adjacent to one of the barrier layers.

9. The DRAM cell of claim 1, wherein the cell is disposed on a substrate, and wherein the heterostructure is adjacent to the substrate.

10. The DRAM cell of claim 9, wherein the substrate includes a substrate insulating layer, and wherein the heterostructure is adjacent to the substrate insulating layer.

11. The DRAM cell of claim 9, wherein one of the barrier layers is adjacent to the substrate.

12. The DRAM cell of claim 1, wherein the gate structure is adjacent to the heterostructure only in the first direction.

13. The DRAM cell of claim 1, wherein the gate structure buries the heterostructure.

14. The DRAM cell of claim 13, wherein the gate structure is aligned with the heterostructure in the second direction.

15. The DRAM cell of claim 1, wherein each of the channel layers and each of the barrier layers is adjacent to both the source structure and the drain structure.

16. The DRAM cell of claim 1, wherein the heterostructure has a total length between 1 nanometer and 75 nanometers, measured in the second direction.

17. The DRAM cell of claim 1, wherein the total width of the heterostructure measured in a third direction perpendicular to the first direction and the second direction is between 20 and 200 times the total length of the heterostructure measured in the second direction.

18. The DRAM cell of claim 1, wherein the thickness of each channel layer measured in the first direction is between 1.5 and 5 times the thickness of each barrier layer measured in the first direction.

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