Tunable Inductor Device

Abstract

This invention discloses a tunable inductor device having a substrate, a planar helical conductor, and a phase change switch (PCS). The planar helical conductor has a plurality of spaced-apart turns disposed on the substrate. The PCS has a patch of phase change material (PCM) disposed on the substrate and in contact with a pair of adjacent segments of the plurality of spaced-apart turns. The patch of PCM is electrically insulating in an amorphous state and conductive in a crystalline state. The PCS further includes a thermal element disposed adjacent to the patch of PCM, wherein the thermal element is configured to maintain the patch of PCM within a first temperature range until the patch of PCM transitions to the amorphous state, and within a second temperature range until a first patch of PCM transitions to the crystalline state.

Description

[0001] Related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 940,365, filed November 26, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a tunable inductor having a switching winding. Background Technology

[0004] Despite the availability of practical switched capacitor arrays and high-quality-factor (Q) varactor diodes in mainstream semiconductor integrated circuit (IC) technologies, practical tunable integrated circuit inductor elements remain a coveted missing component in IC design. The application of active IC inductors is limited by nonlinearity, noise, and power consumption constraints. While switched-turn planar spiral inductors integrated in silicon semiconductors have been implemented in monolithic amplifiers, they result in modest quality factors, low operating frequencies, and large implementation sizes. To date, low-noise amplifiers (LNAs) employing switched-turn planar spiral inductors have resulted in very modest and negligible noise factor performance compared to LNAs matched with fixed inductors. These less practical results are attributed to a combination of moderate switching field-effect transistor (FET) quality factors, active transistor performance, and significant substrate and interconnect losses. Coarse-grained switched inductor arrays have been implemented in gallium nitride high electron mobility (HEMT) technology, resulting in better amplifier performance due to the use of superior HEMT FET devices and lower silicon carbide substrates and gold metal interconnect losses. However, the implementation scale of switch-group inductors is large and ultimately limited by the GaN switching quality factor, which is an order of magnitude lower than that of tunable inductor devices based on microelectromechanical systems (MEMS). Therefore, the implementation of conventional switch-group inductors for tuning inductors in monolithic microwave integrated circuits remains elusive. Thus, a high-performance tunable inductor device in monolithic microwave integrated circuits is still needed. Summary of the Invention

[0005] A tunable inductor device is disclosed, comprising a substrate, a planar helical conductor, and a phase-change switch (PCS). The planar helical conductor has a plurality of spaced-apart turns disposed on the substrate. The PCS has a patch of phase change material (PCM) disposed on the substrate and in contact with a pair of adjacent segments of the plurality of spaced-apart turns, wherein the patch of PCM is electrically insulating in an amorphous state and conductive in a crystalline state. The PCS further includes a thermal element disposed adjacent to the patch of PCM, wherein the thermal element is configured to maintain the patch of PCM within a first temperature range until the patch of PCM transitions to an amorphous state, and within a second temperature range until the patch of PCM transitions to a crystalline state.

[0006] On the other hand, any of the foregoing aspects, individually or together, and / or the various individual aspects and features as described herein, may be combined to obtain additional advantages. Any of the various features and elements disclosed herein may be combined with one or more other disclosed features and elements, unless otherwise indicated herein.

[0007] After reading the following detailed description of preferred embodiments in conjunction with the accompanying drawings, those skilled in the art will understand the scope of this disclosure and implement its additional aspects. Attached Figure Description

[0008] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0009] Figure 1 This is a cross-sectional view of a first exemplary embodiment of a phase change switch (PCS) made of phase change material (PCM) according to the present disclosure.

[0010] Figure 2 This is a cross-sectional view of a second embodiment of a PCM-based PCS according to the present disclosure.

[0011] Figure 3 This is a plan view of a first embodiment of a tunable inductor device having a substrate having a planar helical conductor having a plurality of spaced-apart turns disposed on the substrate.

[0012] Figure 4 This is a plan view of a second embodiment of a tunable inductor device with reduced on-state resistance loss.

[0013] Figure 5 This is a plan view of a third embodiment of a tunable inductor device with reduced thermal coupling between PCS.

[0014] Figure 6 It is a graph showing the effective inductance provided by the tunable inductor device at four different state settings between 0.7 nanohenries and 4 nanohenries.

[0015] Figure 7 yes Figure 6 The graphs of quality factor (Q factor) versus frequency for each of the four different inductor state settings are shown, illustrating the actual peak Q factor > 10.

[0016] Figure 8 It is a graph of inductance versus frequency, showing the effective inductance of a tunable inductor device suspended in an air chamber at four different settings between 0.7 nanohenries and 4 nanohenries.

[0017] Figure 9 It is a graph of Q factor versus frequency, which provides the Q factor of the tunable inductor device suspended in the air chamber for each of the four different inductance settings.

[0018] Figure 10 It is a graph of effective inductance versus frequency that compares the performance of the tunable inductor device of this disclosure with that of a tunable inductor in a microelectromechanical system.

[0019] Figure 11 The graph shows the Q factor versus frequency, illustrating that, under the same size constraints, the tunable inductor device significantly outperforms the microelectromechanical system (MEMS) implementation in terms of Q factor. Detailed Implementation

[0020] The embodiments described below represent the necessary information to enable those skilled in the art to practice these embodiments and illustrate the best mode for practicing these embodiments. Those skilled in the art will understand the concepts of this disclosure and recognize the application of these concepts not specifically set forth herein when reading the following description in conjunction with the accompanying drawings. It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

[0021] It should be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements are not limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0022] It should be understood that when an element, such as a layer, region, or substrate, is referred to as "on another element" or "extending to another element," it may be directly on or directly extended to the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly on another element" or "directly extending to another element," no intermediate elements are present. Similarly, it should be understood that when an element, such as a layer, region, or substrate, is referred to as "on top of another element" or "extending over another element," it may be directly on top of or directly extended over the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly on top of another element" or "extending directly on top of another element," no intermediate elements are present. It should also be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, no intermediate elements are present.

[0023] Relative terms such as “below,” “above,” “upper,” “lower,” “horizontal,” or “vertical” may be used herein to describe the relationship between one element, layer, or region and another element, layer, or region as shown in the figure. It should be understood that these terms, and those discussed above, are intended to cover different orientations of the device other than those shown in the figure.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprises,” “comprising,” “includes,” and / or “including” as used herein specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0025] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that the terms used herein shall be interpreted as having the same meaning as they have in the context of this specification and related art, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0026] This document describes embodiments with reference to schematic diagrams of embodiments of this disclosure. Similarly, the actual dimensions of layers and elements may vary and are expected to differ from the illustrated shapes, for example, due to manufacturing techniques and / or tolerances. For instance, areas illustrated or described as squares or rectangles may have circular or curved features, while areas shown as straight lines may have some irregularity. Therefore, the areas shown in the figures are schematic, and their shapes are not intended to show the precise shapes of areas of the device, nor are they intended to limit the scope of this disclosure. Additionally, for illustrative purposes, the dimensions of structures or areas may be enlarged relative to other structures or areas, and thus provide dimensions of structures or areas to illustrate the general structure of the subject matter, and may be drawn to scale or not. Common elements between the figures may be indicated herein by common element numbers and may not be described again subsequently.

[0027] Figure 1This is a cross-sectional view of a first exemplary embodiment of a phase change switch (PCS) 10 made of phase change material (PCM) 12 according to this disclosure. The phase change material is such as a chalcogenide phase change material, including but not limited to vanadium dioxide (VO2), germanium telluride (GeTe), and antimony germanium telluride (GST). The PCS 10 includes a substrate 14 made of a semiconductor material such as silicon or silicon carbide.

[0028] A thermally insulating layer 16 is disposed on the substrate 14. The thermally insulating layer 16 has a thermal conductivity between 0.1 W / m Kelvin and 0.4 W / m Kelvin. The thermally insulating layer 16 may be made of silicon dioxide, and a suspension layer 18 may optionally be sandwiched between the substrate 14 and the thermally insulating layer 16. The suspension layer 18 may be particularly useful in embodiments where the thermally insulating layer 16 includes one or more air chambers for additional thermal insulation and / or reduction of the dielectric constant. The suspension layer 18 may be made of a semiconductor material such as a nitride compound.

[0029] A thermal element 20 is disposed on the substrate 14 and the thermal insulating layer 16. The thermal element 20 may be made of a thermoelectric semiconductor material or an ohmic material, such as those used to manufacture resistors. Such materials include, but are not limited to, metals and carbon compounds.

[0030] A first dielectric layer 22 is disposed above the thermal insulation layer 16 and the thermal element 20. The first dielectric layer 22 typically has a thermal conductivity of at least 30 W / m Kelvin. In this exemplary embodiment, the first dielectric layer 22 is made of silicon nitride.

[0031] The PCM 12 patch is disposed on the thermal element 20, and in this exemplary embodiment, the PCM 12 patch is disposed on the thermal element 20 such that the PCM 12 patch is spaced tens to hundreds of nanometers away from the thermal element 20. In some embodiments, the PCM 12 patch may reside directly on the thermal element 20.

[0032] A first metal layer segment 24 is disposed on the substrate 14 and electrically contacts the leftmost portion of the PCM 12 patch. A second metal layer segment 26 is disposed on the substrate 14 and electrically contacts the rightmost portion of the PCM 12 patch, and is separated from the first metal layer segment 24 by a gap on the PCM 12 patch. In this exemplary embodiment, the gap is between 1 micrometer and 7 micrometers. In some embodiments, the gap is between 1 micrometer and 4 micrometers. In other embodiments, the gap is between 4 micrometers and 7 micrometers.

[0033] A first external electrical contact 28 is disposed on and conductively ...

[0034] In the operation of PCS 10, in order to put PCS 10 into the off state, a current within a first current range is driven through the thermal element 20 to reduce the temperature of the PCM 12 patch from the crystallization temperature T for a duration of approximately 100 nanoseconds. c Raise to melting temperature T m In this case, the melting temperature T m This causes the PCM 12 patch to change from crystalline to amorphous. Conversely, to put PCS 10 into the conducting state, current in the second current range is driven through the thermal element 20 to maintain the temperature of the PCM 12 patch at the crystallization temperature T for a duration of approximately 1 microsecond. c In this case, the crystallization temperature T c This transforms the PCM 12 patch from amorphous to crystalline. The crystallization temperature T... c and melting temperature T m Depending on the type of PCM. In some embodiments, the crystallization temperature T c The temperature range is between 100℃ and 300℃, and the melting temperature T m The temperature range is between 500°C and 800°C. In some embodiments, the first current range is between 200 mA and 500 mA, and the second current range is between 700 mA and 1000 mA.

[0035] Figure 2 This is a cross-sectional view of a second embodiment of a PCS 10 based on PCM 12 according to this disclosure. In this exemplary embodiment, a first patch of PCM 12 is sandwiched between a thermal element 20 and a substrate 14, and a thermally insulating layer 16 is disposed above the thermal element 20. In this second embodiment, the optional levitation layer 18 may be made of a semiconductor material such as a nitride compound. The operation of the second embodiment of PCS 10 is substantially the same as... Figure 1 The operation is the same as that of the first embodiment of PCS 10 shown.

[0036] Figure 3This is a plan view of a tunable inductor device 34 having a substrate 36 having a planar helical conductor 38 having a plurality of spaced-apart turns T1, T2, T3, and T4 disposed on the substrate 36. The plurality of spaced-apart turns T1, T2, T3, and T4 are laterally spaced by a distance D. In some embodiments, the distance D is between 10 micrometers and 50 micrometers. In other embodiments, the distance D is between 50 micrometers and 100 micrometers. In other embodiments, the distance D is between 100 micrometers and 500 micrometers. In yet another embodiment, the distance D is between 1 micrometer and 5 micrometers. The width W of the planar helical conductor 38 may be equal to the distance D. Furthermore, it should be understood that the distance D and the width W do not need to be uniform across the entire planar helical conductor 38. The planar helical inductor 38 has a first port P1 at one end and a second port P2 at the other end. The first port P1 and the second port P2 are configured to receive and output signals such as radio frequency signals. In at least some embodiments, substrate 36 includes a monolithic microwave integrated circuit, to which planar spiral conductor 38 is integrated.

[0037] In an exemplary embodiment, the planar helical conductor 38 is a rectangular helix, wherein each of the plurality of spaced-apart turns T1, T2, T3, and T4 has two segments aligned with the X direction and two segments aligned with the Y direction. The segments aligned with the X direction are orthogonal to the segments aligned with the Y direction within ±5 degrees. It should be noted that the plurality of spaced-apart turns T1, T2, T3, and T4 may have a greater than Figure 1 The four spaced-out turns shown may have more or fewer spaced-out turns. For example, in some embodiments, the number of spaced-out turns may be dozens. In other embodiments, the number of spaced-out turns may be hundreds.

[0038] In this first embodiment, the tunable inductor device 34 includes a first phase-change switch (PCS) 40. The first PCS 40 may have a... Figure 1 The PCS 10 shown has the same structure as the first embodiment or is similar to it. Figure 2 The second embodiment of PCS 10 shown has the same structure. (As...) Figure 3As shown, the first PCS 40 includes a first patch of phase change material (PCM) 42 disposed on a substrate 36, located between and in contact with adjacent segments of a first pair of spaced-apart turns T1 and T2. The first patch of PCM 42 is electrically insulating in its amorphous state and conductive in its crystalline state. A first thermal element 44 is disposed adjacent to the first patch of PCM 42. The first thermal element 44 is configured to maintain the first patch of PCM 42 within a first temperature range when a current flows through the first thermal element 44 in a first current range until the first patch of PCM 42 converts to an amorphous state, and to maintain the first patch of PCM 42 within a second temperature range when a current flows through the first thermal element 44 in a second current range until the first patch of PCM 42 converts to a crystalline state.

[0039] In this first embodiment, the tunable inductor device 34 further includes a second PCS 46. The second PCS 46 may have the same characteristics as... Figure 1 The PCS 10 shown has the same structure as the first embodiment or is similar to it. Figure 2 The second embodiment of PCS 10 shown has the same structure. (As...) Figure 3 As shown, the second PCS 46 includes a second patch of PCM 48 disposed on the substrate 36, located between and in contact with adjacent segments of the second pair of spaced-apart turns T2 and T3. The second patch of PCM 48 is electrically insulating in its amorphous state and conductive in its crystalline state. A second thermal element 50 is disposed adjacent to the second patch of PCM 48. The second thermal element 50 is configured to maintain the second patch of PCM 48 within a first temperature range when a current flows through the second thermal element 50 within a first current range until the second patch of PCM 48 becomes amorphous, and to maintain the second patch of PCM 48 within a second temperature range when a current flows through the second thermal element 50 within a second current range until the second patch of PCM 48 becomes crystalline.

[0040] Furthermore, in this first embodiment, the tunable inductor device 34 also includes a third PCS 52. The third PCS 52 may have the same characteristics as... Figure 1 The PCS 10 shown has the same structure as the first embodiment or is similar to it. Figure 2 The second embodiment of PCS 10 shown has the same structure. (As...) Figure 3As shown, the third PCS 52 includes a third patch of PCM 54 disposed on the substrate 36, located between and in contact with adjacent segments of the spaced-apart third pair of turns T3 and T4. The third patch of PCM 54 is electrically insulating in its amorphous state and conductive in its crystalline state. A third thermal element 56 is disposed adjacent to the third patch of PCM 54. The third thermal element 56 is configured to maintain the third patch of PCM 54 within a first temperature range when a current flows through the third thermal element 56 in a first current range until the third patch of PCM 54 becomes amorphous, and to maintain the third patch of PCM 54 within a second temperature range when a current flows through the third thermal element 56 in a second current range until the third patch of PCM 54 becomes crystalline.

[0041] First thermal element 44, second thermal element 50, and third thermal element 56 are configured to be coupled to outputs B0, B1, and B2 of controller 58. In operation, when controller 58 generates a first output voltage range at outputs B0, B1, and B2 for a first duration, current flows through each of the first thermal element 44, second thermal element 50, and third thermal element 56 within a first current range for the first duration. Conversely, when controller 58 generates a second output voltage range at outputs B0, B1, and B2 for a second duration, current flows through each of the first thermal element 44, second thermal element 50, and third thermal element 56 within a second current range for the second duration. In both cases, the current flowing from outputs B0, B1, and B2 returns to controller 58 via ground connection GND.

[0042] During operation, the inductance of the tunable inductor device 34 is reduced by selectively short-circuiting adjacent segments of multiple spaced-apart turns T1, T2, T3, and T4 of the planar helical conductor 38. To reduce the inductance of the tunable inductor device 34 by a first amount, the controller 58 drives the first thermal element 44 at a second current level for a second duration to maintain the first patch of the PCM 42 within a second temperature range until the first patch of the PCM 42 becomes crystalline. In the crystalline state, the first patch of the PCM 42 is conductive, causing the segments of turns T1 and T2 contacted by the first patch of the PCM 42 to be short-circuited together, which reduces the inductance of the tunable inductor device 38. To further reduce the inductance of the tunable inductor device 34 by a second amount, the controller 58 drives the second thermal element 50 at a second current level for a second duration to maintain the second patch of the PCM 48 within a second temperature range until the second patch of the PCM 48 becomes crystalline. In the crystalline state, the second patch of PCM 48 is conductive, causing the segments of turns T2 and T3 contacted by the second patch of PCM 48 to be shorted together, which further reduces the inductance of the tunable inductor device 38. To further reduce the inductance of the tunable inductor device 34 by a third amount, the controller 58 drives the third thermal element 56 with a current at a second current level for a second duration to maintain the third patch of PCM 54 within a second temperature range until the third patch of PCM 54 transitions to the crystalline state. In the crystalline state, the third patch of PCM 54 is conductive, causing the segments of turns T3 and T4 contacted by the third patch of PCM 54 to be shorted together, which further reduces the inductance of the tunable inductor device 38. It should be understood that the inductor tuning arrangement can be achieved through the arrangement of the logic states of outputs B0, B1, and B2.

[0043] During further operation, the inductance of the tunable inductor device 34 is increased by selectively breaking short circuits between adjacent segments of a plurality of spaced-apart turns T1, T2, T3, and T4 of the planar helical conductor 38. To increase the inductance of the tunable inductor device 34 by a first amount, the controller 58 drives the first thermal element 44 at a first current level for a first duration to maintain the first patch of the PCM 42 within a first temperature range until the first patch of the PCM 42 transitions to an amorphous state. In the amorphous state, the first patch of the PCM 42 is non-conductive, causing the segments of turns T1 and T2 in contact with the first patch of the PCM 42 to be electrically disconnected from each other, which increases the inductance of the tunable inductor device 38. To further increase the inductance of the tunable inductor device 34 by a second amount, the controller 58 drives the second thermal element 50 at a first current level for a first duration to maintain the second patch of the PCM 48 within a first temperature range until the second patch of the PCM 48 transitions to an amorphous state. In the amorphous state, the second patch of PCM 48 is non-conductive, causing the segments of turns T2 and T3 contacted by the second patch of PCM 48 to be electrically disconnected from each other, which further increases the inductance of the tunable inductor device 38. To further increase the inductance of the tunable inductor device 34 by a third amount, controller 58 drives a third thermal element 56 at a first current level for a first duration to maintain the third patch of PCM 54 within a first temperature range until the third patch of PCM 54 transitions to the amorphous state. In the amorphous state, the third patch of PCM 54 is non-conductive, causing the segments of turns T3 and T4 contacted by the third patch of PCM 54 to be electrically disconnected from each other, which further increases the inductance of the tunable inductor device 38.

[0044] Figure 4 This is a plan view of a second embodiment of a tunable inductor device 34 with reduced on-state resistance loss. In this embodiment, each of a plurality of spaced-apart turns T1, T2, T3, and T4 has a first segment, such as SEG1, longitudinally aligned in a first direction, and a second segment, such as SEG2, longitudinally aligned in a second direction different from the first direction. Figure 4In this embodiment, the first direction is the X direction, and the second direction is the Y direction. This embodiment includes a plurality of first PCS 60 segments, each having a first patch of phase change material (PCM) 62 disposed on a substrate 36 between and in contact with a pair of adjacent first segments such as spaced-apart turns T1 and T2, wherein the first patch of PCM 62 is electrically insulating in an amorphous state and conductive in a crystalline state. Each of the plurality of PCS 60 has a first thermal element 64 disposed adjacent to the first patch of PCM 62. Each first thermal element 64 is configured to maintain each first patch of PCM 64 within a first temperature range when a current flows through each first thermal element 64 in a first current range until each first patch of PCM 62 becomes amorphous, and to maintain each first patch of PCM 62 within a second temperature range when a current flows through each first thermal element 64 in a second current range until each first patch of PCM 62 becomes crystalline.

[0045] A second embodiment of the tunable inductor device 34 further includes a plurality of second segments PCS 66, each having a second patch of PCM 68 disposed on and in contact with a pair of adjacent second segments such as spaced-out turns T1 and T2 on a substrate 36, wherein the second patch of PCM 68 is electrically insulating in an amorphous state and conductive in a crystalline state. Each of the plurality of second segments PCS 66 has a second thermal element 70 disposed adjacent to the second patch of PCM 68. Each second thermal element 70 is configured to maintain each second patch of PCM 68 within a first temperature range when a current flows through each second thermal element 70 in a first current range until the second patch of PCM 68 becomes amorphous, and to maintain each second patch of PCM 68 within a second temperature range when a current flows through each second thermal element 70 in a second current range until the second patch of PCM 68 becomes crystalline. The currents flowing out from outputs B0, B1, and B2 return to controller 58 through ground connections G0, G1, and G2, respectively.

[0046] In some embodiments, the lengths of the plurality of first PCS 60 are between 30% and 50% of the length of the shortest of the adjacent segments between them, with each individual PCS 60 being between 50% and 100% of the length of the shortest of the adjacent segments between them. Similarly, the lengths of the plurality of second PCS 66 are between 30% and 50% of the length of the shortest of the adjacent segments between them, with each individual PCS 66 being between 50% and 100% of the length of the shortest of the adjacent segments between them. In other embodiments, the lengths of the plurality of second PCS 66 are between 50% and 100% of the length of the shortest of the adjacent segments between them.

[0047] Figure 5 This is a plan view of a third embodiment of a tunable inductor device 34 with reduced thermal coupling between PCS. Figure 4 The difference between the third embodiment and the second embodiment is that the plurality of first PCS 60 and the plurality of second PCS 66 are divided into a series of longitudinally spaced PCS segments 72. However, the operation of the third embodiment is actually the same as that of the first and second embodiments.

[0048] Figure 6 and 7 yes Figure 3 A graph simulating the electromagnetic model of an embodiment of the tunable inductor device 34. Figure 6 It is a graph showing the effective inductance provided by the tunable inductor device 34 under four different state settings between 0.7 nanohenries and 4 nanohenries. Figure 6 The self-resonant frequency (SRF) for each setting is also shown. For each PCS tuned inductor state, the actual operating frequency is approximately half of this self-resonant frequency. Figure 7 The graphs plot the quality factor (Q factor) versus frequency for each of the four different inductance state settings, showing the actual peak Q factor > 10. These Q factors are comparable to those of static passive inductors manufactured in the same process, and the lower values ​​of the load Q factor for the Ron resistance of the tunable inductor device 34 in PCS 10 only constitute about 10% to 15% of the Q factor. It should also be observed that the peak Q factor occurs at... Figure 6 The SRF given is approximately half of that. For an inductance value of approximately 4 nanohenries, the usable operating frequency is approximately up to 4 GHz, which is about half of the 8.3 GHz SRF at that inductance setting. Although the Q factor can be increased by increasing the switching perimeter of PCS switch 10 ( Figure 1 and 2However, this did not improve the SRF and the actual operating frequency. It has been determined that the SRF is largely determined by the substrate parasitic capacitance. Another feature of this disclosure is the provision of a planar helical conductor contained in the support material of the suspension layer 18 on top of an effective low-dielectric material (Er<9) rather than directly on a substrate 36 that may have Er>9.

[0049] Figure 8 and 9 Provided Figure 3 Electromagnetic model simulation of an air suspension embodiment. Figure 8 It is a graph of inductance versus frequency, showing the effective inductance at four different state settings between 0.7 nanohenries and 4 nanohenries. Figure 8 This indicates that for the tunable inductor device 34 suspended above the air chamber, the self-resonant frequency (SRF) of each configuration is almost twice as high as that of the tunable inductor device without suspension above the air chamber. This suggests that the monolithic microwave integrated circuit embodiment of the tunable inductor device 34 suspended above the air chamber may be more practical for higher microwave frequency tuning circuits. Figure 9 It is a graph of Q factor versus frequency, providing the Q factor of the tunable inductor device 34 suspended above the air chamber in each of the four different inductance state settings. Figure 9 The graphs illustrate a higher peak Q factor and a wider Q factor operating range, where Q > 10. In fact, for the lowest inductance state of 0.7 nH, the Q factor and SRF have been significantly improved compared to the non-floating embodiment of the tunable inductor device 34, achieving a peak Q factor > 17 at operating frequencies > 20 GHz.

[0050] Figure 10 and 11 It shows Figure 3 The graph depicts a comparison of electromagnetic simulation results between the tunable inductor device 34 and a tunable inductor device based on microelectromechanical systems (MEMS) technology. The comparison uses the lowest inductance state that produces the lowest Q factor for the tuning range. Figure 10 This is a graph showing the effective inductance versus frequency of the tunable inductor device 34 and the MEMS-based tunable inductor. Figure 10 The graph illustrates the effective inductance provided by the tunable inductor device 34 between 3 GHz and 18 GHz, tracking the effective inductance of the MEMS-based tunable inductor. Figure 11 The diagram illustrates that, under the same size constraints, the tunable inductor device 34 significantly outperforms the MEMS implementation in terms of Q factor.

[0051] It is conceivable that any of the foregoing aspects and / or the various individual aspects and features described herein can be combined to obtain additional advantages. Any of the various embodiments disclosed herein can be combined with one or more other disclosed embodiments, unless otherwise indicated herein.

[0052] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of this disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the subsequent claims.

Claims

1. A tunable inductor device, comprising: ●Substrate; ● A planar helical conductor having a plurality of spaced turns disposed on the substrate, wherein each of the plurality of spaced turns has a first segment longitudinally aligned in a first direction and a second segment longitudinally aligned in a second direction different from the first direction; as well as ●At least one first-stage phase change switch (PCS), comprising: ● A first patch of phase change material (PCM) is disposed on the substrate, located between and in contact with a pair of adjacent first segments, wherein the first patch of PCM is electrically insulating in the amorphous state and conductive in the crystalline state. as well as ● A first thermal element is disposed adjacent to the first patch of the PCM, wherein the first thermal element is configured to maintain the first patch of the PCM within a first temperature range when a current within a first current range flows through the first thermal element, until the first patch of the PCM converts to the amorphous state, and When current flows through the first thermal element within the second current range, the first patch of the PCM is maintained within the second temperature range until the first patch of the PCM transforms into the crystalline state; and ●At least one second-stage phase change switch (PCS), comprising: ●A second patch of the PCM is disposed on the substrate, located between and in contact with a pair of adjacent second segments, wherein the second patch of the PCM is electrically insulating in the amorphous state and conductive in the crystalline state; as well as ● A second thermal element is disposed in thermal contact with the second patch of the PCM, wherein the second thermal element comprises an ohmic material configured to maintain the second patch of the PCM within the first temperature range when a current flows through the second thermal element within the first current range until the second patch of the PCM is converted to the amorphous state, and to maintain the second patch of the PCM within the second temperature range when a current flows through the second thermal element within the second current range until the second patch of the PCM is converted to the crystalline state.

2. The tunable inductor device according to claim 1, wherein, The first thermal element is configured to be coupled to one or more outputs of a controller, wherein when the controller generates a first output voltage range at the one or more outputs during a first duration, current flows through the first thermal element within the first current range during the first duration, and when the controller generates a second output voltage range at the one or more outputs during a second duration, current flows through the first thermal element within the second current range during the second duration.

3. The tunable inductor device according to claim 1, wherein, The first current range is between 200 mA and 500 mA, and the second current range is between 700 mA and 1000 mA.

4. The tunable inductor device according to claim 1, wherein, The first patch of the PCM is vanadium dioxide (VO2).

5. The tunable inductor device according to claim 1, wherein, The first patch of the PCM is germanium telluride (GeTe).

6. The tunable inductor device according to claim 1, wherein, The at least one first-stage phase change switch (PCS) has an on-state resistance between 0.1Ω and 1.0Ω.

7. The tunable inductor device according to claim 1, wherein, The at least one first-stage phase change switch (PCS) has a turn-off resistance between 1,000 Ω and 1,000,000 Ω.

8. The tunable inductor device according to claim 1, wherein, The at least one first-stage phase change switch (PCS) has a turn-off state capacitance between 0.5 picofarads and 0.001 picofarads.

9. The tunable inductor device according to claim 1, wherein, The first temperature range is between 500°C and 800°C.

10. The tunable inductor device according to claim 9, wherein, The second temperature range is between 100°C and 300°C.

11. The tunable inductor device according to claim 1, wherein, The substrate comprises silicon carbide.

12. The tunable inductor device according to claim 1, wherein, The at least one first-segment phase change switch (PCS) includes a plurality of first-segment phase change switch (PCS) and the length of each of the plurality of first-segment phase change switch (PCS) is set between 30% and 50% of the length of the shortest of the adjacent segments in the plurality of first-segment phase change switch (PCS) among the plurality of first-segment phase change switch (PCS).

13. The tunable inductor device according to claim 1, wherein, The at least one first-segment phase change switch (PCS) includes a plurality of first-segment phase change switch (PCS) and the length of each of the plurality of first-segment phase change switch (PCS) is set between 50% and 100% of the length of the shortest of the adjacent segments in the plurality of first-segment phase change switch (PCS) among the plurality of first-segment phase change switch (PCS).

14. The tunable inductor device according to claim 1, wherein, The second direction is orthogonal to the first direction within ±5 degrees.

15. The tunable inductor device according to claim 2, wherein, The second thermal element is configured to be coupled to one or more outputs of the controller, wherein when the controller generates the first output voltage range at the one or more outputs during the first duration, current flows through the second thermal element within the first current range during the first duration, and when the controller generates the second output voltage range at the one or more outputs during the second duration, current flows through the second thermal element within the second current range during the second duration.

16. The tunable inductor device according to claim 1, wherein, The at least one first-stage phase change switch (PCS) includes a plurality of first-stage phase change switch (PCS) and the at least one second-stage phase change switch (PCS) includes a plurality of second-stage phase change switch (PCS) and the length of each of the plurality of second-stage phase change switch (PCS) is set between 30% and 50% of the length of the shortest of the adjacent segments in the plurality of first-stage phase change switch (PCS) between them.

17. The tunable inductor device according to claim 1, wherein, The at least one first-stage phase change switch (PCS) includes a plurality of first-stage phase change switch (PCS) and the at least one second-stage phase change switch (PCS) includes a plurality of second-stage phase change switch (PCS) and the length of each of the plurality of second-stage phase change switch (PCS) is set between 50% and 100% of the length of the shortest of the adjacent segments in the plurality of first-stage phase change switch (PCS) between them.

18. The tunable inductor device according to claim 1, wherein, The at least one first-stage phase change switch (PCS) includes a plurality of first-stage phase change switches (PCS), and the at least one second-stage phase change switch (PCS) includes a plurality of second-stage phase change switches (PCS), and the plurality of first-stage phase change switches (PCS) and the plurality of second-stage phase change switches (PCS) are divided into spaced-apart segments.

19. The tunable inductor device according to claim 1, wherein, The planar helical conductor is integrated into a monolithic microwave integrated circuit.

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