Waveguide bus and method, system for automatically generating a layout of a waveguide bus

Abstract

The invention relates to a waveguide bus and a method, system for automatically generating a layout of a waveguide bus, a system, method, software tool, etc. for generating a layout indicative of paths of balanced optical waveguides of a waveguide bus is disclosed. A grid is used for routing the paths, which extend between respective first and second input / output nodes, respectively, and within boundaries defining an area. The paths are automatically rerouted to balance length and number of bends without unduly increasing the length or number of bends in these paths, nor further moving the input / output nodes or beyond the established boundaries. The automatic rerouting of the paths is iteratively performed based on results of various intersection operations related to different path-specific sets of points on the grid to determine when and where to insert additional straight segments and bends into the paths. A layout indicative of the balanced paths is then generated. A waveguide bus structure having balanced optical waveguides is also disclosed.

Description

TECHNICAL FIELD

[0001] The present invention relates to optical waveguides, and more particularly, to embodiments of a design method, system, and software tool for automatically generating a layout of a waveguide bus, and embodiments of a waveguide bus manufactured according to the layout. BACKGROUND

[0002] More particularly, a silicon photonic integrated chip (PIC) can include a waveguide (WG) bus (i.e., a set of optical WGs). Each WG in the WG bus transports an optical signal between a pair of input / output nodes. During PIC design, the paths of the optical WGs are automatically laid out (e.g., by a WG layout generation tool) according to design rules, e.g., for critical dimensions, minimizing area consumption, etc. Typically, each path in the automatically generated layout has the shortest length and the fewest number of bends possible between its corresponding input / output nodes. However, some PIC designs require that the WGs in the WG bus be balanced. For purposes of the present invention, a "balanced WG" refers to a WG that subjects an optical signal passing therethrough to substantially the same transmission loss and phase shift. Those skilled in the art will recognize that the transmission loss and phase shift of an optical signal passing through a WG will depend on the length of the WG and the number of bends within the WG. That is, both the transmission loss and the phase shift are caused by the length and the bends. Typically, if balanced WGs are required, the automatically generated layout (e.g., each path having the shortest length and the fewest number of bends possible between its corresponding input / output nodes, as described above) is then manually altered in length of one or more paths and / or in the number of bends in one or more paths so that all of the paths have approximately the same length and number of bends. Ideally, the WG balancing is performed so that not only are the transmission loss and phase shift equalized, but also the transmission loss and phase shift are minimized. Unfortunately, manually altering the paths of the layout with these goals in mind can be very time consuming, inconsistent, error prone, etc. SUMMARY

[0003] An embodiment of a design system is disclosed herein for automatically generating a layout indicative of balanced optical waveguide (WG) paths of a WG bus. The system can include a storage medium storing a design (e.g., a schematic diagram) including a WG bus having a plurality of optical WGs. The system can also include a processor in communication with the storage medium. The processor can access the design from the storage medium and route paths for the optical WGs according to the design. Specifically, the processor can route the paths such that they each extend between corresponding first and second input / output nodes and such that they are within defined boundaries of a rectangular region. The processor can further automatically re-route the paths to reduce any disparity between the total lengths and the total number of bends of the paths (i.e., balance the lengths and the number of bends of the paths). Specifically, the processor can insert an additional straight segment and / or an additional bend, each equal to one length unit, into at least one of the paths without moving either of the first and second input / output nodes and without exceeding the defined boundaries. Inserting the additional straight segment and / or the additional bend in the paths will create balanced paths. The techniques, and in particular, the algorithms for determining when and where to automatically insert the additional straight segment and / or the additional bend (as discussed further in the detailed description section below) ensure that the balanced paths extend between the same corresponding first and second input / output nodes, within the same defined boundaries, and with minimal, if any, disparity in length and the same number of bends. The processor can further generate a layout indicative of the balanced paths of the optical WGs.

[0004] Also disclosed herein is an embodiment of a method of designing for automatically generating a layout indicative of balanced paths of optical waveguides (WGs) of a WG bus. The method can include accessing, by a processor from a storage medium, a design (e.g., a schematic) including a WG bus having a plurality of optical WGs. The method can also include routing, by the processor, paths for the optical WGs based on the design. The process of routing the paths can be performed such that the paths extend between corresponding first and second input / output nodes, respectively, and such that they are within defined boundaries of a rectangular region. The method can further include automatically re-routing, by the processor, the paths to reduce any disparity between the total lengths and the total number of bends of the paths (i.e., to balance the lengths and the number of bends of the paths). The process of automatically re-routing the paths can include inserting into at least one of the paths an additional straight segment and / or an additional bend equal to one length unit, without moving the first and second input / output nodes and without exceeding the defined boundaries. Inserting the additional straight segment and / or the additional bend in the paths will create balanced paths. The techniques, and in particular the algorithms for determining when and where to automatically insert the additional straight segment and / or the additional bend (discussed further in the detailed description section below), ensure that the balanced paths extend between the same corresponding first and second input / output nodes as the paths, are within the same defined boundaries, and have minimal, if any, disparity in length and the same number of bends. The method can also include generating, by the processor, a layout indicative of the balanced paths of optical WGs.

[0005] Also disclosed herein is an embodiment of a computer program product. The computer program product can include a computer readable storage medium having at least a software tool having program instructions for waveguide (WG) layout generation. The program instructions for WG layout generation can be readable by a processor that can execute the instructions to perform the above-described method for automatically generating a layout indicative of balanced paths of optical waveguides (WGs) of a WG bus.

[0006] Embodiments of structures (e.g., silicon photonic integrated circuit (PIC) chips) are also disclosed herein. The structures can include a substrate and a waveguide (WG) bus having a plurality of optical WGs on the substrate. For example, the optical WGs can be WGs fabricated according to a particular layout that is automatically generated by any of the above-described system, method, or computer program product embodiments. In particular, the WG bus can be located within a rectangular region having a defined boundary. The WG bus can include a plurality of optical WGs. The optical WGs can respectively extend between corresponding first and second input / output nodes. The first and second input / output nodes of different WGs can be separated by different distances. That is, a first WG can extend between first and second input / output nodes that are separated by a first distance; a second WG can extend between different first and second input / output nodes that are separated by a second distance that is greater than the first distance; and so on. The optical WGs can include different combinations of straight segments and bends such that a total length of the optical WGs is within a threshold difference in a number of length units, and such that a total number of bends in the optical WGs is equal. Finally, because the WG bus is fabricated according to a layout that is automatically generated by any of the above-described system, method, or computer program product embodiments, a particular optical WG that extends between first and second input / output nodes that are separated by a longest distance can include a particular combination of straight segments and bends, and this particular combination can include a cascade of bends having a stair shape. BRIEF DESCRIPTION OF DRAWINGS

[0007] The application will be better understood from the following detailed description taken in conjunction with the accompanying drawings, which are not necessarily drawn to scale, in which:

[0008] FIG. 1A A schematic diagram of four paths of four optical waveguides (WGs) of a WG bus for automatically generating a layout;

[0009] FIG. 1B A schematic diagram of an exemplary modified layout in which, FIG. 1A the paths shown in FIG. 1 have been manually re-routed;

[0010] FIG. 2 A schematic diagram of a disclosed embodiment of a computer-aided design (CAD) system for automatically generating a layout indicating paths of balanced optical WGs of a WG bus;

[0011] FIG. 3 A schematic diagram of an initial placement of paths of optical WGs of a WG bus according to a disclosed embodiment;

[0012] FIG. 4a graph showing a path automatically re-routed according to the disclosed embodiments to reduce the total length and the difference in the total number of bends of the path;

[0013] FIG. 5A-FIG. 5B a graph showing an automatic adjustment of type 1 in which the path length can be increased without increasing the number of bends in the path;

[0014] FIG. 6A-FIG. 6B a graph showing an automatic adjustment of type 2 in which the length of the path is increased and the number of bends in the path is also increased;

[0015] FIG. 7A-FIG. 7B a graph showing an automatic adjustment of type 3 of the path in which the number of bends of the path can be increased without increasing the length of the path;

[0016] FIG. 8A-FIG. 8B a graph showing an automatic adjustment of type 4 of the path in which the straight segments of the path are moved without increasing the length of the path or the number of bends in the path;

[0017] FIG. 9A-FIG. 9B a graph showing an automatic adjustment of type 5 of the path in which both the length of the path and the number of bends are reduced;

[0018] FIG. 10A-FIG. 10E a graph showing the iterative process for automatically re-routing the path of the optical WG from FIG. 3 the path shown to FIG. 4 the path shown;

[0019] FIG. 11 a graph showing similar results for the path re-routing of a heterogeneous optical WG;

[0020] FIG. 12 a flow chart showing a disclosed method embodiment for automatically generating a layout indicating the path of a balanced optical WG of a WG bus;

[0021] FIG. 13A and FIG. 13B show exemplary embodiments of structures (e.g., silicon photonic integrated circuit (PIC) chips) formed using the disclosed systems and methods; and

[0022] FIG. 14 a schematic diagram showing an exemplary computer system that can be used to implement the disclosed systems and method embodiments. DETAILED DESCRIPTION

[0023] As noted above, a silicon photonic integrated chip (PIC) can include an optical waveguide (WG) bus (i.e., a set of optical WGs). Each WG in the WG bus transports an optical signal between a pair of input / output nodes. During PIC design, the paths of the optical WGs are automatically laid out (e.g., by a WG layout generation tool) according to design rules, e.g., for critical dimensions, minimizing area consumption, etc. Typically, each path in the generated, automatically-generated layout has the shortest length and the fewest number of bends possible between its corresponding input / output nodes. However, some PIC designs require that the WGs in the WG bus be balanced. For purposes of the present invention, a "balanced WG" refers to a WG that subjects an optical signal passing therethrough to substantially the same transmission loss and phase shift. Those skilled in the art will recognize that the transmission loss and phase shift of an optical signal passing through a WG will depend on the length of the WG and the number of bends within the WG. That is, both the transmission loss and the phase shift are caused by the length and the bends. Typically, if balanced WGs are required, the automatically-generated layout (e.g., each path has the shortest length and the fewest number of bends possible between its corresponding input / output nodes, as described above) is then manually altered in length of one or more paths and / or in the number of bends in one or more paths so that all of the paths have approximately the same length and number of bends. Ideally, the WG balancing is performed so that not only are the transmission loss and phase shift equalized, but also the transmission loss and phase shift are minimized. Unfortunately, manually altering the paths of the layout, taking into account these goals, can be very time consuming, inconsistent, error prone, etc.

[0024] For example, FIG. 1Ais a diagram showing an example auto-generated layout 100 showing four paths pi-p4 of four optical WGs of a WG bus. The layout generation (e.g., by a conventional WG layout tool) is performed after the first and second input / output nodes are placed for each path (e.g., see first input / output nodes 101.1-101.4 of paths pi-p4, and second input / output nodes 102.1-102.4 of paths pi-p4). As shown, the first input / output nodes 101.1-101.4 and the second input / output nodes 102.1-102.4 have been placed such that the first input / output nodes are all aligned in a first direction, and such that the second input / output nodes are all aligned in a second direction perpendicular to the first direction. The routing of the paths between the corresponding first and second input / output nodes is generally based on design rules directed to CDs (critical dimensions), etc., such that each path follows the shortest route with the fewest number of bends possible between its first and second input / output nodes. Thus, at least the lengths of the paths differ (e.g., the length of p4 is greater than the length of p3, which is greater than the length of p2, etc.). Thus, if the WG bus were fabricated according to this auto-generated layout, the optical signals through the different optical WGs would suffer different amounts of transmission loss and phase shift. FIG. 1B is a diagram showing an example manually modified layout 100MR in which the paths pi-p4 of the optical WGs of the WG bus have been manually re-routed in an attempt to balance them (i.e., to attempt to make them all equal in length and have the same number of bends) without moving the input / output nodes. While these manually re-routed paths pi-p4 all have the same number of bends (i.e., nine bends), the lengths can still differ, the solution is random, and alternative solutions with smaller and / or fewer bends for the lengths of paths pi-p4 are possible.

[0025] In view of the foregoing, embodiments of a design system, method, software tool, etc. are disclosed herein for automatically generating a layout indicative of balanced waveguide (WG) paths of a WG bus. In particular, these embodiments can use a grid to route paths of optical WGs, which respectively extend between corresponding first and second input / output nodes and within a boundary defining a region. These embodiments can further automatically re-route the paths to reduce any disparity in length and number of bends (i.e., balance the paths with respect to bend length and bend number) without unduly increasing the bend length or bend number in these paths and further without moving the input / output nodes or exceeding the previously established boundary. For example, the automatic re-routing of the paths can be performed using an algorithm that employs an iterative process and results of various intersection operations related to different path-specific sets of points on the grid to determine where and when to insert additional straight segments and bends into the paths. Finally, these embodiments can generate a layout indicative of the balanced paths of the optical WGs. Embodiments of a structure are also disclosed herein that includes a WG bus having balanced optical WGs and is fabricated in accordance with the above-described automatically generated layout.

[0026] More particularly, FIG. 2 is a schematic diagram illustrating disclosed embodiments of a computer-aided design (CAD) system 200. The CAD system 200 can include a plurality of system components. These system components can include, but are not limited to, one or more processors 250, one or more monitors 260, and one or more computer-readable storage media 210. The system components can be interconnected by a system bus 201 (as shown) and / or by a wired or wireless network (not shown). For purposes of illustration, the CAD system 200 is described below and illustrated in FIG. 2 as having a single processor and a single storage medium. However, it should be understood that, FIG. 2 this is not intended to be limiting. Alternatively, the CAD system 200 can include multiple processors and / or multiple storage media accessible by the processors for performing one or more different processes in a design flow, which store the required data, software tools, etc. for performing the different processes in the design flow.

[0027] The storage media 210 can store electronic design automation (EDA) tools 230 (e.g., specialized software programs). Each EDA tool 230 includes program instructions executable by the processor 250 to cause the processor 250 to perform a process step in a computer-aided design flow. At least one of the EDA tools 230 stored by the storage media 210 and accessible by the processor 250 can be a novel waveguide (WG) layout generation tool 231 (also referred to herein as a WG layout generator), as described in greater detail below.

[0028] The storage medium 210 can also store general design information 240 that can be accessed and used by one or more of the EDA tools 230 during the execution of the process steps. The design information 240 can be in the form of, for example, a process design kit (PDK). In any case, the design information 240 can include, but is not limited to, technology files for a particular technology node, design rule sets for a particular technology node, various databases, etc. Those skilled in the art will recognize that, in general, technology files for a particular technology node refer to files that define the layers and devices available in a particular technology node as well as the general physical and electrical rules for the particular technology node. Design rule sets for a particular technology node refer to discrete sets of design rules (also referred to as run sets). Each rule set includes a set of design rules that are applicable to one or more particular processes in the design flow. The design rules are determined based on the process assumptions associated with the particular technology node in question and based on various failure mechanisms that can occur given those process assumptions.

[0029] The storage medium 210 can also store a preliminary design 220 (e.g., a schematic or a basic diagram) of a silicon photonic integrated circuit (PIC) or portions thereof that can be accessed by the processor 250. The preliminary design 220 illustrates at least one waveguide (WG) bus having a plurality of optical WGs that, by design, are to be balanced. For example, such a schematic or basic diagram can show the connections and functionality of the WG bus by graphical symbols without regard to the actual physical layout. As previously mentioned, one of the EDA tools 230 stored on the storage medium 210 and accessible by the processor 250 can be a new type of waveguide (WG) layout generation tool 231 (also referred to herein as a WG layout generator). The WG layout generator 231 can include program instructions for WG layout generation and, in particular, program instructions for automatically generating a layout that indicates the paths of the balanced optical WGs of the WG bus.

[0030] Accordingly, in the disclosed system 200, the processor 250 can execute the program instructions of the WG layout generator 231 to cause the processor 250 to automatically generate a layout that represents the paths of the optical waveguides (WGs) of the WG bus referenced in the PIC design 220 to ensure that the optical WGs will be substantially balanced to achieve minimal transmission loss and phase shift. That is, when the WG bus is manufactured according to the layout, the optical signals passing through the optical WGs will experience substantially the same transmission loss and phase shift and the transmission loss and phase shift will be minimized.

[0031] In particular, the processor 250 can access the PIC design 220 (or portions thereof that show the WG bus) from the storage medium 210. Based on the design 220, the processor 250 can route (i.e., establish the placement of) the paths for the optical WGs of the WG bus, respectively (see, e.g., FIG. 2B). For example, the processor 250 can route the paths for the optical WGs of the WG bus based on the design 220 and the design information 240 (e.g., the technology files for the particular technology node and the design rule sets for the particular technology node) stored on the storage medium 210. FIG. 3The exemplary paths pi - p4) are shown in the figure. For ease of illustration, four paths are shown for four optical WGs; however, it should be understood that any number of two or more paths can be provided for any number of two or more optical WGs in the WG bus, depending on the PIC design 220.

[0032] In any case, to route the paths pi - p4, the processor 250 can form a grid 310 (e.g., a Cartesian grid) of cells 311 arranged in columns and rows. The cells 311 can be square and of equal size. To measure the total length of a path, the length of a side of each cell can correspond to one unit of length (UL), which should be equal to twice a fixed bend radius (BR). For the purposes of the present invention, the bends in the optical WGs of the WG bus can all have the same fixed arc angle (0), the same fixed BR, and the same fixed arc length (S). The 0, BR, and S can be specified in the design information 240 or the design 220. The outer lines of the grid 310 can define the side boundaries of a rectangular region within which the paths pi - p4are to be routed (e.g., see top side boundary 321, left side boundary 322, bottom side boundary 323, and right side boundary 324). Finally, the number of columns and rows within the grid 310 can define the size of the rectangular region (i.e., the width and length, respectively, measured in ULs).

[0033] The processor 250 can arrange the first and second input / output nodes of each optical WG on the grid 310, respectively. The first and second input / output node arrangement can be performed such that the first input / output nodes 301.1-301.4 for the optical WGs (to be used for paths pi-p4, respectively) are arranged at different grid points on one side boundary of the rectangular region, and such that the second input / output nodes 302.1-302.4 for the optical WGs (to be used for paths pi-p4, respectively) are arranged at different grid points of an adjacent side boundary of the rectangular region, which is perpendicular to the side boundary with the first input / output nodes 301.1-301.4. For example, the first input / output nodes 301.1-301.4 can be arranged at different grid points on the top side boundary 321, and the second input / output nodes 302.1-302.4 can be arranged at different grid points on the left side boundary 322. The arrangement and, in particular, the pitch of the first input / output nodes 301.1-301.4 on the top side boundary 321 of the grid 310, and the arrangement and, in particular, the pitch of the second input / output nodes 302.1-302.4 on the left side boundary 322, can be based on the design 220 and the design rules (e.g., design rules specifying CDs) in the design information 240. Thus, the pitch of the first input / output nodes 301.1-301.4 can be the same or different (e.g., smaller or larger) than the pitch of the second input / output nodes 302.1-302.4. For example, as shown, the first input / output nodes 301.1-301.4 have a smaller pitch (e.g., 1 UL pitch) than the second input / output nodes 302.1-302.4 (e.g., 12 UL pitch). As mentioned above, each UL is equal to the edge length of one cell 311 within the grid 310. Each first input / output node 301.1-301.4 in left-to-right order can be paired with a second input / output node 302.1-302.4 in top-to-bottom order. Thus, the separation distance between each pair of first and second input / output nodes for each optical WG will gradually increase. For example, as shown, the first and second input / output nodes 301.1 / 302.1 for the first optical WG will have the shortest separation distance; the first and second input / output nodes 301.2 / 302.2 for the second optical WG will have the next shortest separation distance; and so on, with the first and second input / output nodes 301.4 / 302.4 for the fourth optical WG having the longest separation distance. FIG. 3

[0034] ​After the first and second input / output nodes are arranged, the processor 250 can route paths pi-p4 for the optical WGs on the grid 310 such that each path extends between the corresponding first and second input / output nodes, respectively. That is, the paths can be routed such that the first path pi extends between the first and second input / output nodes 301.1-302.1, such that the second path p2 extends between the first and second input / output nodes 301.2-302.2, and so on. These paths pi-p4 can be routed such that they align with and extend along the vertical and horizontal lines of the grid 310, with each path generally following the shortest route with the fewest number of 90-degree turns between its first and second input / output nodes.

[0035] It should be appreciated that the execution of the routing causes the paths to not cross each other and to not violate the critical distance design rules (e.g., such that the paths remain spaced apart by at least a minimum spacing distance). It should also be noted that during the routing, each 90-degree turn of a path on the grid 310 corresponds to one bend in the optical WG. That is, as noted above, while the actual bends in the optical WG will have an arc angle (0), a same fixed bend radius (BR), and a same fixed arc length (S), these bends are snapped to cell angles for simplicity during the routing. Thus, for example, as shown in FIG. 3 the path pi between the first and second input / output nodes 301.1-302.1 has a length of 4UL and one 90-degree turn representing one bend. The path p2 between the first and second input / output nodes 301.2-302.2 has a length of 17UL and one 90-degree turn representing one bend. The path p3 between the first and second input / output nodes 301.3-302.3 has a length of 30UL and one 90-degree turn representing one bend. Finally, the path p4 between the first and second input / output nodes 301.4-302.4 has a length of 42UL and one 90-degree turn representing one bend. Thus, while the paths pi-p4 have the same number of 90-degree turns (i.e., bends), they have different lengths.

[0036] As shown in FIG. 4 the processor 250 can further automatically re-route the paths pi-p4 to reduce any disparity in the total length and the total number of bends between the paths, and then generate the layout 400 indicating balanced paths bp1-bp4 for the optical WGs. For the purposes of this disclosure, a “balanced path” refers to a path whose length is all within a pre-set threshold length difference (e.g., a length difference of less than 1UL (ideally), a length difference of less than 2UL, a length difference of less than 3UL, etc.) and the number of bends in the path is all equal (e.g., a difference in the number of bends of 0).

[0037] In particular, the processor 250 can insert into at least one path each additional straight segment and / or additional bend equal to one UL without moving the first and second input / output nodes and without exceeding the defined boundaries. The insertion of additional straight segments and / or additional bends in the paths will create balanced paths. The techniques and in particular the algorithms for determining when and where to automatically insert additional straight segments and / or additional bends ensure in particular that the balanced paths bp1-bp4 extend between the same pairs of corresponding first and second input / output nodes 301.1 / 302.1, 301.2 / 302.2, 301.3 / 302.3, 301.4-302.4 of the paths p1-p4, lie within the same defined boundaries 321-324 of the grid 310, and have minimal differences, if any, in length and same number of bends. Moreover, said techniques can be used to achieve the shortest possible length and / or the least number of bends for each path.

[0038] More specifically, to balance the length and the number of bends of the paths p1-p4 (e.g., as shown in FIG. 3 ), and to generate the layout 400 with balanced paths bp1-bp4 (e.g., as shown in FIG. 4 ), the processor 250 can re-route the paths p1-p4 in an iterative manner given the following data sets, integers and rules applicable thereto:

[0039] Data sets and integers:

[0040] P is the set of all paths p i (initially indexed by length, so that p1 is the shortest path of the paths, p |P| is the longest path).

[0041] A i is the set of all grid points on the path p i . B i is the set of all bends (i.e., 90-degree turns or corners) on the path p i .

[0042] S i is the set of all grid points of the selected cell (i.e., the selected square so that |S i | = 4) that can lie on the path p i and extend in a bend b that is an element of B i .

[0043] K is the set of differences k i between the number of bends in the most bendy path and the number of bends in the path p i .

[0044] |P| is the actual number of paths.

[0045] l i is the difference between the length of the longest path in length units (UL) and the length of path p i .

[0046] k i is the difference between the number of bends in the most winding path and the number of bends in path p i .

[0047] Rules:

[0048] Rule 1 : Path length difference update: XOR(B i , S i ) updates 1 i by 2x(3-|A i ∩ S i |).

[0049] Rule 2: |B i ∩ S i | lower / upper bound: |A i ∩ S i | - 2 ≤ |B i ∩ S i | ≤ |A i ∩ S i |.

[0050] Rule 3: Bend path number update: XOR(B i , S i ) updates |B i | by 2x(2-|B i ∩ S i |).

[0051] Thus, for any particular path p i under consideration, the above rules can be applied in order to insert additional straight segments and / or additional bends into the particular path p i on the grid 310, and these insertions will be based on the results of intersection operations between the set of all grid points on the particular path (i.e., set A i ) and the set of all corners of the particular cell that have at least one corner aligned with at least one bend in the particular path (i.e., set S i ), and intersection operations between the set of all bends in the particular path (i.e., set B i ) and the set of all corners of the particular cell (i.e., the same set S i ).

[0052] For example, when a particular path p ithe length of the longest path (i.e., when l i > 1), the processor 250 can re-route the particular path p i its length in one of two ways: (a) an adjustment of Type 1, the path length is increased without increasing the number of bends within the path (if possible), as shown in FIG. 5A-FIG. 5B ; or (b) an adjustment of Type 2, the length and the number of bends in the path are increased (if necessary), as shown in FIG. 6A-FIG. 6B . Specifically, when l i > 1, Rules 1 and 3 are applied to identify particular cells that can be used to increase the length of the particular path p i (e.g., the shortest path) without increasing the number of bends in the particular path p i . That is, the particular path p i can be scanned to attempt to identify (i.e., find, locate, etc.) a particular cell (referred to herein as a first cell 501) that has at least one corner aligned with at least one bend in the particular path p i and that satisfies a set of first conditions. The set of first conditions can include: the intersection between the set of all grid points on the particular path and the set of all corners of the first cell 501 is equal to 2; and the intersection between the set of all bends in the particular path p i and the set of all corners of the first cell 501 is also equal to 2 (i.e., |A i ∩ S i | = 2 A |B i ∩ S i | = 2). If such a first cell 501 is identified (as shown in FIG. 5A ), the processor 250 can drag (i.e., move, pull, etc.) the particular path p i around the first cell 501 to effectively insert two additional straight line segments into the path to increase the total number of U Ls by 2 while keeping the total number of bends constant (as shown in FIG. 5B ). However, if no first cell 501 as described above is identified, it is still possible to increase the length of the particular path p i (e.g., the shortest path). Specifically, the particular path p i can be scanned to attempt to identify (i.e., find, locate, etc.) another particular cell (referred to herein as a second cell 602) that has at least one corner aligned with at least one bend in the particular path and that satisfies a set of second conditions. The set of second conditions can include: the intersection between the set of all grid points on the particular path and the set of all corners of the second cell is equal to 2; and the intersection between the set of all bends in the particular path and the set of all corners of the second cell is equal to 1 (i.e., |A i ∩ Si | = 2 A | B i ∩ S i | = 1). If such a second cell 602 is identified (as shown in FIG. 6A , the processor 250 can drag (i.e., move, pull, etc.) the particular path p i around the second cell 602 to effectively insert two additional straight segments and two additional bends into the path to increase the total number of ULs by two and also increase the total number of bends by two (as shown in FIG. 6B .

[0053] Further, when the particular path p i has fewer bends than the most-bendy path (i.e., when max(K) > k i , the processor 250 can re-route the path by using adjustment type 3 to increase the number of bends in the particular path p i without increasing the length of the path (if possible), as shown in FIG. 7A-FIG. 7B . Specifically, when max(K) > k i , the processor 250 can scan the particular path p i to attempt to identify (i.e., find, locate, etc.) a particular cell 703 (referred to herein as a third cell) that has at least one corner aligned with at least one bend in the particular path p i and that satisfies a set of third conditions. The set of third conditions can include: the intersection between the set of all grid points on the particular path and the set of all corners of the third cell is equal to 3; and the intersection between the set of all bends in the particular path and the set of all corners of the third cell is equal to 1 (i.e., | A i ∩ S i | = 3 A | B i ∩ S i | = 1). If such a third cell 703 is identified (as shown in FIG. 7A , the processor 250 can drag (i.e., move, pull, etc.) the particular path p i around the third cell 703 to effectively insert two additional bends into the path to increase the total number of bends in the path by two while keeping the total number of ULs constant (as shown in FIG. 7B .

[0054] It should be noted that when l i > 1 and / or max(K) > k i , but there is not enough space within the boundaries of the defined region to perform the necessary re-routing (i.e., by dragging the particular path p i around the identified cell that satisfies the set of conditions to increase the particular path p ithe middle re-routing can be done by using adjustment type 4 to simply move the particular path p without changing the total number of ULs or the total number of bends i , thereby providing additional space for further path re-routing changes within the rectangular region, as shown in FIG. 8A-FIG. 8B For example, the processor 250 can scan the particular path p i to attempt to identify (i.e., find, locate, etc.) another particular cell 804 (referred to herein as a fourth cell) that has at least one corner aligned with at least one bend in the particular path and that satisfies a set of fourth conditions. The set of fourth conditions can include: the intersection between the set of all grid points on the particular path and the set of all corners of the fourth cell equals 3, and the intersection between the set of all bends in the particular path and the set of all corners of the fourth cell 804 equals 2 (i.e., |A i ∩ S i | = 3 A |B i ∩ S i | = 2). If such a fourth cell 804 is identified, as shown in FIG. 8A , the processor 250 can drag (i.e., move, pull, etc.) the particular path p i around the fourth cell 804, thereby moving a portion of the particular path p i while keeping the total number of length units and the total number of bends unchanged, as shown in FIG. 8B

[0055] Optionally, the processor 250 can also automatically re-route the paths pi-p4 to reduce any differences in the total length and the total number of bends between the paths by using adjustment type 5 to remove a portion of the particular path p i (e.g., the longest path), as shown in FIG. 9A-FIG. 9B For example, the processor 250 can scan the particular path pi to locate another particular cell 905 (referred to herein as a fifth cell) that has at least one corner aligned with at least one bend in the particular path pi and that satisfies a fifth condition, including: the intersection between the set of all grid points on the particular path pi and the set of all corners of the fifth cell 905 equals 4, and the intersection between the set of all bends in the particular path pi and the set of all corners of the fifth cell 905 equals 2, 3, or 4 (i.e., |A i ∩ S i | = 4 A |B i ∩ S i | = 2, 3, or 4). If such a fifth cell 905 is found, as shown in FIG. 9A , the processor 250 can drag the particular path pi away from the fifth cell 905 so as to pull it to one side of the cell instead of being wrapped around three sides, thereby reducing the length by 2, and depending on |B​i ∩S i The value of | reduces or maintains the total number of bends (e.g.) FIG. 9B As shown). Specifically, if |A i ∩S i |=4∧|B i ∩S i If | = 3 (see Example A), then the length of a specific path pi decreases by 2, and the total number of bends decreases by 2. If |A i ∩S i |=4∧|B i ∩S i If | = 2 (see Example B), then the length of a specific path pi increases by 2, while maintaining the total number of bends. If |A i ∩S i |=4∧|B i ∩S i If | = 4 (see Example C), then the length of a specific path pi is reduced by 2, and the total number of bends is reduced by 4.

[0056] The path adjustment operations described above can be applied during iterative processing to determine when and where to automatically insert additional straight segments and / or additional bends (or, if applicable, remove straight segments and / or additional bends).

[0057] For example, in an exemplary embodiment, when paths p1-p4 have different lengths and / or different numbers of bends, processor 250 can evaluate paths p1-p4 and adjust the paths to balance the length and / or number of bends in the following manner: Processor 250 can apply adjustment type 1 to increase the length of the shorter paths without increasing the number of bends in the shorter paths, if possible. Adjustment type 1 can be performed until the length of the second longest path is balanced, or further adjustments cannot be made due to insufficient space. If it is initially not possible to apply adjustment type 1, processor 250 can apply adjustment type 2 to increase the length of the shorter paths and the number of bends in the shorter paths. Processor 250 can then apply adjustment type 1 until the length of the second longest path is balanced, or further adjustments to the length cannot be made due to insufficient space. Once the length of the second longest path is balanced, or further adjustments cannot be made due to insufficient space, processor 250 can apply adjustment type 3 to add bends to those paths that have fewer bends than the most bend path, until all paths have the same number of bends, or further adjustments cannot be made due to insufficient space. Processor 250 can further determine whether additional space is needed for adjustment. If so, adjustment type 4 can be applied to reconstruct one or more paths without increasing the path length or the number of bends in the path. Processor 250 can then iteratively repeat these steps until all paths are balanced in terms of length and number of bends.

[0058] FIG. 10A-FIG. 10E Further illustrating the exemplary iterative process for automatic re-routing of paths pi-p4.

[0059] In particular, starting from FIG. 10A , the processor 250 can determine that paths pi-p4 all have different lengths and, as a result, can initiate an iterative process for automatic re-routing to balance the paths. Since adjustment type 1 is initially not possible, the processor 250 can apply adjustment type 2 to increase the length of the shorter paths (i.e., pi-p3) by two ULs and also to increase the number of bends in those paths by 2. The processor 250 can then repeatedly apply adjustment type 1 to the shorter paths (i.e., pi-p3) to increase the length of those paths without further increasing the number of bends until the second longest path (i.e., p3) is balanced (i.e., has the same length as the longest path p4). The processor 250 can then apply adjustment type 3 to add bends to path p4, which is the only path having a lesser number of bends than the other paths (see FIG. 10B ).

[0060] In the next iteration, the processor 250 can determine that there are still paths having different lengths, in particular, paths pi-p2 are still shorter than the longest paths (now pi-p4), and repeat the above process steps. In particular, starting from FIG. 10B and going to FIG. 10C , the processor 250 can apply adjustment types 1 and 2 as needed to increase the length of paths pi and p2 and the number of bends in paths pi and p2. The processor 250 can then apply adjustment type 3 to add bends to paths p3 and p4 without increasing the length of paths p3 and p4, thereby causing all paths to have the same number of bends (see FIG. 10C ).

[0061] In the next iteration, the processor 250 can determine that there are still paths having different lengths, in particular, path pi is still shorter than the longest paths (now p2-p4), and repeat the above process steps. In particular, starting from FIG. 10C and going to FIG. 10D , the processor 250 can apply adjustment types 1 and 2 as needed to increase the length of path pi and the number of bends in path pi. The processor 250 can further determine that paths p2-p4 all have fewer bends, but there is not enough space available to add bends to paths p3 or p4. As a result, the processor 250 can apply adjustment type 3 to add bends to path p2 and can apply adjustment type 4 to retrofit paths p3 and p4 (see FIG. 10D ).

[0062] In the next iteration, processor 250 can determine that paths of different lengths still exist, specifically that path p1 is still shorter than the longest path (now p2-p4), and repeat the above process steps. Specifically, from FIG. 10D Start and go to FIG. 10E Processor 250 can apply adjustment type 1 to further increase the length of path p1 without increasing the number of bends within path p1. Processor 250 can also determine that paths p3 and p4 still have relatively few bends, and can apply adjustment type 3 to add bends to paths p3 and p4 without increasing their respective lengths (see [link]). FIG. 10E ).therefore, FIG. 10E The path shown is balanced in terms of both length and number of bends (i.e., balanced path bp1-bp4).

[0063] It should be understood that the rerouting is performed so that paths do not intersect and do not violate critical distance design rules (e.g., ensuring that paths maintain an interval of at least minimum distance).

[0064] It should also be noted that the optical WGs used in the design for the WG bus can be homogeneous WGs. That is, they can be made entirely of the same material (i.e., at the same mask level). For example, they can be silicon WGs, silicon nitride WGs, or WGs of any other suitable optical WG material. Alternatively, the optical WGs used in the design for the WG bus can be heterogeneous WGs. That is, the design can indicate that the WGs should include different sections made of different WG materials (i.e., fabricated at different mask levels). For example, each WG can include silicon sections and silicon nitride sections. In this case, the processor 250 can also balance the length and number of bends in the paths of the different sections. Specifically, the processor 250 can first perform a balancing of the total length and the total number of bends in the paths (as discussed above). FIG. 10A-FIG. 10E (As shown). Then, for different sections with different materials (i.e., the main material or the first material 381 and the second material 382), the processor 250 may, for example, do the following: first, associate the balancing path bp1-bp4 with the main material 381; determine the different lengths of the different sections (i.e., the first length of the section with the main material and the second length of the section with the second material); and in each path, replace the same number of equal-length straight line segments of the first material 381 with the second material 382 to achieve the first length of the first material 381 and the second length of the second material 382 in each path (e.g., ...). FIG. 11 (As shown). It should be understood that, FIG. 11 The discussion is not intended to be restrictive. A similar balance can be performed for a WG bus with heterogeneous optical WGs, where the WG has different parts made of two or more different materials.

[0065] In any case, once the balanced paths bp1-bp4 have been achieved, the processor 250 can generate a modified layout 300R (as shown in FIG. 4 The generation of the modified layout 300R includes un-snapping the bends in each path from the corners of the grid cells 311 such that the bends have the same arc angle (0) (e.g., 90 degrees), the same fixed BR, and the same fixed arc length (S). That is, the processor 250 can reshape all 90-degree turns within all of the balanced paths bp1-bp4 to form curvilinear bends having the same arc angle (0) (e.g., 90 degrees), the same fixed BR, and the same fixed arc length (S). Since the edge length of each grid cell 311 is twice the fixed BR, un-snapping the bends in this way will reduce the length of the paths bp1-bp4, but the length of all paths will be reduced by exactly the same amount since each path bp1-bp4 has the same number of bends. Thus, any length difference across the paths will remain within the set threshold length difference (e.g., within 1 UL, within 2 UL, etc.).

[0066] It should be noted that although the disclosed technology is described above with reference to a defined rectangular region in which the first and second input / output nodes are arranged on the top and left side boundaries, all other cases in which the input / output nodes are arranged on different adjacent side boundaries (e.g., the bottom and right side boundaries, etc.) can be considered as a rotation or cascaded composite of this basic case.

[0067] Thus, when a WG bus is manufactured according to a layout (e.g., the modified layout 300R) that is automatically generated by the disclosed system 200 as described above, any optical signals passing through different optical WGs will experience substantially equal amounts of transmission loss and phase shift. Moreover, the amounts of transmission loss and phase shift will be minimized since the solution proposed in the layout will be optimal, with the balanced paths bp1-bp4 being relatively short and having fewer bends.

[0068] With reference to the flowchart of FIG. 12 , embodiments of a design method for automatically generating a waveguide (WG) bus layout having balanced paths to achieve substantially equal and minimal transmission loss and phase shift are also disclosed herein.

[0069] Specifically, the method may include accessing a preliminary design 220 (e.g., a schematic or basic diagram) of a silicon photonic integrated circuit (PIC) or a portion thereof from a storage medium 210 by a processor 250. The silicon photonic integrated circuit or a portion thereof includes at least one waveguide (WG) bus having multiple optical waveguides (WGs), which, according to the design, should be balanced (see process step 1202). The method may also include routing paths for the optical WGs of the WG bus (see process steps 1204 and...). FIG. 3 The exemplary paths p1-p4 shown are automatically rerouted to balance the path length and the number of bends in the path (see process step 1214), and a layout of balanced paths indicating the optical WG of the WG bus is generated (e.g., see the example with balanced paths bp1-bp4). FIG. 4 (Exemplary modified layout 300R). For ease of illustration, four paths for four optical WGs are shown in the figure; however, it should be understood that, depending on the PIC design 220, any number of two or more optical WGs in the WG bus can have any number of two or more paths.

[0070] More specifically, processing step 1204 may include forming a grid 310 (e.g., a Cartesian grid) of cells 311, arranged in columns and rows (see process step 1206). Cells 311 may be square and of uniform size. To measure the total length of the path, the side length of each cell may correspond to a length unit (UL), and this UL should be equal to twice the fixed radius of curvature (BR) (as discussed above regarding the system embodiment). The outer lines of grid 310 may define the side boundaries of a rectangular region where paths p1-p4 will be routed (e.g., see top side boundary 321, left side boundary 322, bottom side boundary 323, and right side boundary 324) (see process step 1208). Finally, the number of columns and rows within grid 310 may define the size of this rectangular region (i.e., the width and length measured in UL, respectively).

[0071] Process step 1204 may further include arranging the first and second input / output nodes of each optical WG on grid 310 (see process step 1210). The arrangement of the first and second input / output nodes may be performed at process step 1210 such that the first input / output nodes 301.1-301.4 for the optical WG (for paths p1-p4 respectively) are arranged at different grid points on one side boundary (e.g., top side boundary 321) of the rectangular region, and the second input / output nodes 302.1-302.4 for the optical WG (for paths p1-p4 respectively) are arranged at different grid points on adjacent side boundaries (e.g., left side boundary 322) of the rectangular region, perpendicular to the side boundary having the first input / output nodes 301.1-301.4.

[0072] Process step 1204 can also include routing paths pi-p4 of the optical WGs along the grid 310 such that each path extends between a corresponding first and second input / output node (see process step 1212). These paths pi-p4 can be routed such that they align with and extend along the vertical and horizontal lines of the grid 310, with each path generally following the shortest route having the fewest number of 90-degree turns between its first and second input / output nodes. It should be appreciated that the routing at step 1204 is performed such that the paths do not cross one another and do not violate the critical distance design rules (e.g., such that the paths remain at least a minimum separation distance apart). It should also be noted that each 90-degree turn of a path on the grid 310 corresponds to one bend in the optical WG during the routing at process step 1204. That is, as discussed above, while the actual bends in the optical WG will have an arc angle (0), a same fixed bend radius (BR), and a same fixed arc length (S), these bends are collapsed to unit angles for purposes of reducing complexity during routing.

[0073] After process step 1204, the paths pi-p4 can be automatically re-routed to reduce any differences in the total length and the total number of bends between the paths (see process step 1214). For purposes of this disclosure, "balancing the paths" means that the lengths of the paths are all within a pre-set threshold length difference (e.g., less than a 1 UL length difference (ideally), less than a 2 UL length difference, less than a 3 UL length difference, etc.) and the number of bends in the paths are all equal (i.e., a difference of 0 in the number of bends). The process step 1214 of automatically re-routing the paths can include inserting at least one additional straight line segment and / or additional bend into each path equal to one UL without moving the first and second input / output nodes and without falling outside of the defined boundaries. Inserting the additional straight line segment and / or additional bend into the paths will create balanced paths.

[0074] The techniques used, and in particular the algorithms, to determine when and where to automatically insert the additional straight line segment and / or additional bend in process 1214 employ certain adjustment operations (e.g., see adjustment types 1-5 shown in FIG. 5A-FIG. 5B to FIG. 9A-FIG. 9B . As discussed in more detail above with respect to the CAD system 200, these adjustment operations are based on certain rules (e.g., rules 1-3) that apply to certain sets of data (e.g., P, A i , S i , K) and certain integers (e.g., |P|, |A i , |p i , and |k i ). The techniques further iteratively apply these adjustment operations.

[0075] For example, when paths pi-p4 have different lengths and / or different numbers of bends, paths pi-p4 can be evaluated and the lengths and / or numbers of bends in the paths can be adjusted as follows. If possible, adjustment type 1 can be applied to increase the length of the shorter paths without increasing the number of bends in the shorter paths (see process step 1216). Adjustment type 1 can be performed until the length of the second longest path reaches equilibrium, or further adjustment is not possible due to lack of space. If it is not initially possible to apply adjustment type 1, adjustment type 2 can be applied to increase the length of the shorter paths as well as the number of bends in the shorter paths (see process step 1218). Adjustment type 1 can then be applied until the length of the second longest path reaches equilibrium, or further adjustment is not possible due to lack of space (see process step 1216). Once the length of the second longest path reaches equilibrium, or further adjustment is not possible due to lack of space, adjustment type 3 can be applied to add bends to those paths that have fewer bends than the most bent path until all paths have the same number of bends, or further adjustment is not possible due to lack of space (see process step 1220). It can be determined whether additional space is currently needed for adjustment, and if so, adjustment type 4 can be applied to reshape one or more paths without increasing the length of the paths or the number of bends in the paths (see process step 1222). Process steps 1216-1222 can then be iteratively repeated until the lengths and numbers of bends of all paths reach equilibrium. That is, until the balanced paths bp1-bp4 extend between the same corresponding pairs of first and second input / output nodes 301.1 / 302.1, 301.2 / 302.2, 301.3 / 302.3, 301.4 / 302.4, as do paths pi-p4, within the same defined boundaries 321-324 of the grid 310, and have minimal differences, if any, in length and the same number of bends.

[0076] See also FIG. 10A-FIG. 10E And the above detailed discussion further illustrates this iterative application of adjustment operations.

[0077] It will be appreciated that performing the above re-routing causes the paths to not cross each other and to not violate the critical distance design rule (e.g., causes the paths to remain spaced apart by at least a minimum spacing distance).

[0078] It should also be noted that the optical WGs used in the design for the WG bus can be homogeneous WGs. That is, they can be made entirely of the same material (i.e., at the same mask level). For example, they can be silicon WGs, silicon nitride WGs, or WGs of any other suitable optical WG material. Alternatively, the optical WGs used in the design for the WG bus can be heterogeneous WGs. That is, the design can indicate that the WGs should include different sections made of different WG materials (i.e., fabricated at different mask levels). For example, each WG can include both silicon and silicon nitride sections. In this case, the path can also be balanced for the length and number of bends in the different sections. Specifically, a balance can be performed on the total length and the total number of bends in the path (as discussed above). FIG. 10A-FIG. 10E (As shown in the diagram). Then, for different sections with different materials (i.e., the main material or the first material 381 and the second material 382), the method can be performed, for example, by: first associating the balancing paths bp1-bp4 with the main material 381; determining different lengths for the different sections (i.e., a first length for the section with the main material and a second length for the section with the second material); and in each path, replacing the same number of equal-length straight segments of the first material 381 with the second material 382 to achieve a first length of the first material and a second length of the second material in each path (as shown in the diagram). FIG. 11 (As shown). It should be understood that, FIG. 11 The discussion is not intended to be restrictive. A similar balance can be performed for a WG bus with heterogeneous optical WGs, where the WG has different parts made of two or more different materials.

[0079] In any case, once the balanced paths bp1-bp4 are implemented (e.g., as...), FIG. 10E As shown), the modified layout 300R can be generated (see process steps 1226 and...). FIG. 4 The generation of the modified layout 300R can include non-bending bends in each path from the corners of grid cell 311, such that the bends have the same arc angle (θ) (e.g., 90 degrees), the same fixed BR, and the same fixed arc length (S). That is, all 90-degree turns within all balanced paths bp1-bp4 can be reshaped to form curved bends with the same arc angle (θ) (e.g., 90 degrees), the same fixed BR, and the same fixed arc length (S). Since the side length of each grid cell 311 is twice the fixed BR, non-bending bends in this way will reduce the length of paths bp1-bp4, but the length of all paths will be reduced by exactly the same amount because each path bp1-bp4 has the same number of bends. Therefore, any length difference on the paths will remain within a set threshold length difference (e.g., within 1UL, within 2UL, etc.).

[0080] It should be noted that although the disclosed technology is described above with reference to the first and second input / output nodes being arranged on the defined rectangular region on the top and left side borders, all other cases where the input / output nodes are arranged on different adjacent side borders (e.g., bottom and right side borders, etc.) can be considered as a rotation or concatenated composition of this basic case.

[0081] The method can further include fabricating the WG bus according to the automatically generated modified layout 300R (see process step 1228). As a result of the formation according to the layout 300R, during operation of the WG bus, any optical signals passing through the different optical WGs will experience substantially equal amounts of transmission loss and phase shift. Furthermore, the amounts of transmission loss and phase shift will be minimized because the solution proposed in the layout will be optimal, balancing the paths bp1-bp4 to be relatively short and less curved.

[0082] With reference to FIG. 13A and 13B Embodiments of structures 1390A, 1390B (e.g., silicon photonic integrated circuit (PIC) chips) are also disclosed herein. The structures 1390A, 1390B can include a substrate 1391, and a waveguide (WG) bus 1392A, 1392B having a plurality of optical WGs on the substrate 1391 (e.g., see optical WGs bwgl-bwg4). For illustrative purposes, four optical WGs are shown in FIG. 13A and 13B ; however, it should be understood that alternatively, there can be any number of two or more WGs in the WG bus. For example, the optical WGs bwgl-bwg4 can be WGs fabricated according to a particular layout that is automatically generated by any of the above-described system, method, or computer program product embodiments, such that they are balanced with respect to length and the number of bends, as described below.

[0083] In particular, the WG buses 1392A, 1392B can be located within a rectangular region 1310 having defined boundaries 1321-1324. The first and second input / output nodes of each optical WG can be located on adjacent side boundaries, respectively. That is, the first input / output nodes 1301.1-1301.4 for the optical WGs bwgl-bwg4, respectively, can be located on one side boundary (e.g., the top side boundary 1321), and the second input / output nodes 1302.1-1302.4 for the optical WGs bwgl-bwg4, respectively, can be located on an adjacent side boundary (e.g., the left side boundary 1322) that is perpendicular to the side boundary having the first input / output nodes 1301.1-1301.4. The pitch of the first input / output nodes 1301.1-1301.4 can be the same or different (e.g., less than or greater than) than the pitch of the second input / output nodes 1302.1-1302.4. The separation distance between each pair of first and second input / output nodes is different for each optical WG, and the separation distance gradually increases for each optical WG. For example, as shown, the first and second input / output nodes 1301.1 / 1302.1 for the first optical WG bwgl are separated by the shortest distance; the first and second input / output nodes 1301.2 / 1302.2 for the second optical WG bwg2 are separated by the next shortest separation distance; and so on, with the first and second input / output nodes 1301.4 / 1302.4 for the fourth optical WG bwg4 being separated by the longest separation distance.

[0084] The optical WGs bwgl-bwg4 can extend between the corresponding first and second input / output nodes, respectively. That is, the first optical WG bwgl can extend between the first and second input / output nodes 1301.1 / 1302.1; the second optical WG bwg2 can extend between the first and second input / output nodes 1301.2 / 1302.2; the third optical WG bwg3 can extend between the first and second input / output nodes 1301.3 / 1302.3; and the fourth optical WG bwg4 can extend between the first and second input / output nodes 1301.4 / 1302.4. Furthermore, each of these optical WGs bwgl-bwg4 can include different combinations of straight segments and bends, such that they are balanced in length and number of bends. That is, such that the lengths of the paths bwgl-bwg4 are all within a pre-set threshold length difference (e.g., a length difference of less than 1 length unit (UL) (ideally), a length difference of less than 2 ULs, a length difference of less than 3 ULs, etc.), and the number of bends in the paths are equal (i.e., a difference of 0 in the number of bends).

[0085] It should be understood that the optical WG bwg1-bwg4 do not intersect each other and do not violate critical distance design rules (e.g., the paths are separated by at least a minimum spacing distance). Furthermore, it should be noted that the bends in the optical WG bwg1-bwg4 of either the WG bus 1392A or 1392B can all have the same 90-degree fixed arc angle (θ), the same fixed BR, and the same fixed arc length (S). Additionally, each length unit (UL) discussed above can be equal to twice the fixed BR.

[0086] In any case, since the WG buses 1390A and 1390B are manufactured according to a layout automatically generated by any of the above-described system, method, or computer program product embodiments, at least one particular optical WG extending between the first and second input / output nodes separated by the longest distance may include a particular combination of straight segments and bends, and said particular combination may include a cascade of bends having a stepped shape. The same optical WG may also include the longest single straight segment of all straight segments of all optical WGs bwg1-bwg4, which extends along one side boundary of the rectangular area from its first input / output node to the first end of the bend cascade. In some embodiments, an additional straight segment may extend from its second input / output node along an adjacent side boundary to the second end of the bend cascade. In other embodiments, the second end of the bend cascade may be connected to a second input / output node.

[0087] For example, such as FIG. 13A and FIG. 13B As shown, the optical WG bwg4 extends between the first and second input / output nodes 1301.4 / 1302.4, separated by the longest distance of all pairs of first and second input / output nodes. The optical WG bwg4 includes a specific combination of straight segments and bends, including a bend cascade 1370 with a stepped shape. Within the combination of straight segments and bends, the same optical WG bwg4 includes two straight segments. The two straight segments include the longest single straight segment 1371 of all straight segments of all optical WG bwg1-bwg4, which extends from the first input / output node 1301.4 of the optical WG bwg4 along the right boundary 1324 of the rectangular region 1310 to the first end of the bend cascade 1370, and an additional straight segment 1372, which is shorter than the straight segment 1371 and extends from the second input / output node 1302.4 of the optical WG bwg4 along the bottom boundary 1323 of the rectangular region 1310 to the second end of the bend cascade 1310.

[0088] It should also be noted that the optical WGs bwg1-bwg4 of the WG bus 492A can be homogeneous WGs (see...). FIG. 13Aand structure 1390A). That is, they can be made entirely of the same material (i.e., at the same mask level). For example, they can be silicon WGs, silicon nitride WGs, or WGs of any other suitable WG material. Alternatively, the optical WGs bwgi-bwg4 of the WG bus 1392B can be heterogeneous WGs (see FIG. 13B and structure 1390B). That is, in the WG bus 1392B, the optical WGs bwgi-bwg4 can include different portions made of different WG materials. For example, each optical WG bwgi-bwg4 can include a silicon portion and a silicon nitride portion. In this case, the optical WG bwgi-bwg4 is balanced for the number of lengths and bends in the different material portions as well. That is, the same material in each WG can have the same total length and the same number of bends. For example, each optical WG bwgi-bwg4 can have a primary or first material segment 1381 and a second material segment 1382. In each optical WG bwgi-bwg4, the combined primary first segment 1381 and second material segment 1382 can follow the balanced path recited in the layout. Moreover, each pair of first material segments 1381 can be connected by a second material segment 1382, all of the second material segments 1382 can be straight and can have the same length, and all of the optical WGs bwgi-bwg4 can include the same number of second material segments 1382. Thus, the total length and the total number of bends in the first material segments 1381 of each WG will be the same, and similarly, the total length and the total number of bends in the second material segments 1382 of each WG will be the same.

[0089] Embodiments of a computer program product are also disclosed herein. The computer program product can include a computer readable storage medium having (e.g., stored on) at least one software tool having program instructions for waveguide (WG) layout generation. The program instructions for waveguide layout generation can be readable by a processor, which can execute the instructions in order to perform the above-described method for automatically generating a layout indicative of a balanced optical waveguide (WG) path for a WG bus.

[0090] More specifically, as described above, the present application can be implemented as a system or a method. In addition, embodiments of the present application (e.g., a controller, as described above) can be implemented in the form of a computer program product. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out embodiments of the present application.

[0091] A computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch cards or raised structures in grooves of a groove having indications recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

[0092] Computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0093] Computer readable program instructions for carrying out operations of the present application can be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate array (FPGA), or programmable logic array (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry in order to perform various aspects of the present application.

[0094] Various aspects of the present application are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer readable program instructions.

[0095] These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and / or other

[0096] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer, other programmable data processing apparatus or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0097] The diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart and / or block diagrams can represent a module, segment, or portion of instructions, which includes one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks can sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flowchart illustrations, and combinations thereof, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

[0098] FIG. 14 A representative hardware environment (i.e., computing system) for implementing the various disclosed embodiments of the system and method is depicted in FIG. 1. This schematic drawing illustrates a schematic diagram of the hardware used in a computing device 100, in accordance with the embodiments of the present disclosure. The computing device 100 includes at least one processor or central processing unit (CPU) 10, which is connected to a communication bus 12. The CPU 10 can process instructions for execution, parameters stored in the memory, and generate data as output. The system also includes various devices and memory that connect to the bus 12, including mass storage element 11 and magnetic disk drive 13, or other program storage devices readable by the system. The system can read the inventive instructions on the program storage devices and follow these instructions to perform the methods of the embodiments herein. The system also includes a user interface adapter 19 that connects a keyboard 15, a mouse 17, a speaker 24, a microphone 22, and / or other user interface devices such as a touch screen device (not shown) to the bus 12 to gather user input for the system. Additionally, a communication adapter 20 connects the bus 12 to a data processing network 25, and a display adapter 21 connects the bus 12 to a display device 23, which can be implemented as an output device such as a monitor, a printer, or a transmitter.

[0099] It is to be understood that the terminology used herein is for the purpose of describing the disclosed structures and methods and is not intended to be limiting. For example, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, to the extent that the terms "including", "includes", "having", "has", "with", or variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprising". Additionally, as used herein, terms such as "right", "left", "vertical", "horizontal", "top", "bottom", "upper", "lower", "under", "below", "bottom", "above", "over", "parallel", "perpendicular", and the like, are used to describe relative positions as shown in the figures (unless otherwise indicated), and terms such as "contacting", "directly contacting", "adjacent", "directly adjacent", "immediately adjacent", and the like, are intended to mean that at least one element is in physical contact with another element (without other elements being interposed therebetween). The term "laterally" is used herein to describe the relative position of elements and more specifically indicates that one element is located to the side of another component rather than above or below the other element as the elements are oriented and shown in the figures. For example, an element laterally adjacent to another element will be located next to the other element, an element laterally immediately adjacent to another element will be directly next to the other element, and an element laterally surrounding another element will be adjacent to and border the outer sidewalls of the other element. All corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the following claims are intended to include any structures, materials, or acts for performing the function in combination with other claimed claim elements.

[0100] The description of various embodiments of the present application is given for the purpose of illustrating the general principles of the application and is not intended to limit the present application to particular embodiments nor to exhaust the scope of the present application. Numerous modifications and variations are possible in light of the above teachings without departing from the scope and spirit of the described embodiments. The terminology used is for the purpose of describing particular embodiments only and is not intended to be limiting. The use of singular or plural forms of terms is not intended to limit the scope of the present application to only one of the possibilities.

Claims

1. A design method for optical waveguides, the design method comprising: The processor routes the optical waveguide path for the waveguide bus, where... The path is routed within the boundary of the rectangular region and extends between the corresponding first and second input / output nodes, respectively; The processor automatically reroutes the path to reduce the difference in either the total length or the total number of bends, wherein the automatic rerouting of the path includes inserting either an additional straight segment or an additional bend into at least one of the path to create a balanced path that extends between the corresponding first and second input / output nodes and within the boundary. as well as The processor generates a layout that indicates the balanced path of the optical waveguide.

2. The design method according to claim 1, wherein, Reducing the difference between the total length and the total number of bends balances the transmission loss and phase shift of the optical signal transmitted through the optical waveguide.

3. The design method according to claim 1, wherein, The route of the path includes: A grid of cells is formed, wherein each cell is square, and each side of each cell corresponds to a length unit, which is twice the fixed bending radius set for all bends in the optical waveguide; The boundary of the rectangular region is established along the lines on the grid; The first and second input / output nodes for the optical waveguide are arranged on the grid such that all first input / output nodes are located at grid points on one side boundary of the rectangular region, and all second input / output nodes are located at grid points on adjacent side boundaries of the rectangular region; and The paths along the grid are such that each path between the first input / output node and the second input / output node represents the shortest route with the minimum number of 90-degree turns, where each 90-degree turn corresponds to a bend.

4. The design method according to claim 3, wherein, The rerouting of the path is performed iteratively, wherein, for any particular path under consideration, the additional straight segment insertion and the additional bend insertion are the results of the intersection operation between the set of all grid points on the particular path and the set of all angles of the identified cells having at least one angle aligned with at least one bend in the particular path, and the intersection operation between the set of all bends in the particular path and the set of all angles of the identified cells.

5. The design method according to claim 3, in, The rerouting of the path includes increasing the length of the specific path, and Wherein, the increase in the length of the specific path includes any one of the following: Scan a first unit, the first unit having at least one corner aligned with at least one bend in the specific path and satisfying a first condition, the first condition including: the intersection of the set of all grid points on the specific path and the set of all corners of the first unit is equal to 2, and the intersection of the set of all bends on the specific path and the set of all corners of the first unit is equal to 2. When the first unit is identified, drag the specific path around the first unit to effectively insert two additional straight line segments into the specific path, increasing the total length by two length units while keeping the total number of bends unchanged; When no first unit is identified, a second unit is scanned, the second unit having at least one corner aligned with at least one bend in the specific path and satisfying a second condition, the second condition comprising: the intersection of the set of all grid points on the specific path and the set of all corners of the second unit is equal to 2, and the intersection of the set of all bends in the specific path and the set of all corners of the second unit is equal to 1; and When the second unit is identified, drag the specific path around the second unit to effectively insert two additional straight segments and two additional bends into the specific path, thereby effectively increasing the total length by two length units and increasing the total number of bends by two.

6. The design method according to claim 3, in, The rerouting of the path includes increasing the number of bends in a specific path, and The increase in the number of bends in the specific path includes: Scan a third unit, the third unit having at least one corner aligned with at least one bend in the specific path and satisfying a third condition, the third condition comprising: the intersection of the set of all grid points on the specific path and the set of all corners of the third unit is equal to 3, and the intersection of the set of all bends on the specific path and the set of all corners of the third unit is equal to 1; and When the third unit is identified, the specific path is dragged around the third unit to effectively insert two additional bends into the specific path, thereby increasing the total number of bends by two while keeping the total length unchanged.

7. The design method according to claim 3, in, The rerouting of the path includes moving a specific path to provide additional space for further path routing changes; as well as The movement along the specific path includes: Scan a fourth cell, the fourth cell having at least one corner aligned with at least one bend in the specific path and satisfying a fourth condition, the fourth condition comprising: the intersection of the set of all grid points on the specific path and the set of all corners of the fourth cell equals 3, and the intersection of the set of all bends on the specific path and the set of all corners of the fourth cell equals 2; and When the fourth unit is identified, the specific path is dragged around the fourth unit to move the specific path while keeping the total length and the total number of bends constant.

8. The design method according to claim 3, wherein, The generation of the layout includes reshaping all 90-degree turns within all the balance paths to form a curved bend with the fixed bending radius.

9. A design system for optical waveguides, the design system comprising: Storage medium, storing a schematic diagram of a waveguide bus comprising multiple optical waveguides; as well as The processor communicates with the storage medium; in, The processor accesses the schematic diagram and, based on the schematic diagram, routes the optical waveguide within the boundary of the rectangular region, wherein the paths extend between the first and second input / output nodes, respectively. The processor further automatically reroutes the path to reduce the difference between the total length and the total number of bends by inserting either an additional straight segment or an additional bend into at least one of the paths, thereby creating balanced paths extending between the corresponding first and second input / output nodes within the boundary; and The processor also generates a layout that indicates the balanced path of the optical waveguide.

10. The design system according to claim 9, wherein, The reduction in the difference between the total length and the total number of bends balances the transmission loss and phase shift of the optical signal transmitted through the optical waveguide.

11. The design system according to claim 9, wherein, The processor routes the path through the following steps: A grid of cells is formed, wherein each cell is square, and each side of each cell corresponds to a length unit, which is twice the fixed bending radius set for all bends in the optical waveguide; The boundary of the rectangular region is established along the lines on the grid; The first and second input / output nodes for the optical waveguide are arranged on the grid such that all first input / output nodes are located at grid points on one side boundary of the rectangular region, and all second input / output nodes are located at grid points on adjacent side boundaries of the rectangular region; and The paths along the grid are such that each path between the first input / output node and the second input / output node represents the shortest route with the minimum number of 90-degree turns, where each 90-degree turn corresponds to a bend.

12. The design system according to claim 11, wherein, The processor reroutes the path iteratively, and wherein, for any particular path under consideration, additional line segments and additional bends are inserted based on the result of the intersection operation between the set of all grid points on the particular path and the set of all corners of the identified unit having at least one corner aligned with at least one bend in the particular path, and the intersection operation between the set of all bends in the particular path and the set of all corners of the identified unit.

13. The design system according to claim 11, wherein, The processor reroutes the path by increasing the length of a specific path through the following steps: Scan a first unit, the first unit having at least one corner aligned with at least one bend in the specific path and satisfying a first condition, the first condition including: the intersection of the set of all grid points on the specific path and the set of all corners of the first unit is equal to 2, and the intersection of the set of all bends on the specific path and the set of all corners of the first unit is equal to 2. When the first unit is identified, drag the specific path around the first unit to effectively insert two additional straight line segments in the specific path to increase the total length by two length units while keeping the total number of bends unchanged; When no first unit is identified, a second unit is scanned, the second unit having at least one corner aligned with at least one bend in the specific path and satisfying a second condition, the second condition comprising: the intersection of the set of all grid points on the specific path and the set of all corners of the second unit is equal to 2, and the intersection of the set of all bends on the specific path and the set of all corners of the second unit is equal to 1; and When the second unit is identified, drag the specific path around the second unit to effectively insert two additional straight segments and two additional bends into the specific path, thereby effectively increasing the total length by two length units and increasing the total number of bends by two.

14. The design system according to claim 11, wherein, The processor reroutes the path by increasing the number of bends in a specific path through the following steps: Scan a third unit, the third unit having at least one corner aligned with at least one bend in the specific path and satisfying a third condition, the third condition comprising: the intersection of the set of all grid points on the specific path and the set of all corners of the third unit is equal to 3, and the intersection of the set of all bends on the specific path and the set of all corners of the third unit is equal to 1; and When the third unit is identified, the specific path is dragged around the third unit to effectively insert two additional bends into the specific path, thereby increasing the total number of bends by two while keeping the total length unchanged.

15. The design system according to claim 11, wherein, The processor reroutes the path by moving a specific path through the following steps, in order to provide additional space for further path routing changes: Scan a fourth cell, the fourth cell having at least one corner aligned with at least one bend in the specific path and satisfying a fourth condition, the fourth condition comprising: the intersection of the set of all grid points on the specific path and the set of all corners of the fourth cell equals 3, and the intersection of the set of all bends on the specific path and the set of all corners of the fourth cell equals 2; and When the fourth unit is identified, the specific path is dragged around the fourth unit to move the specific path while keeping the total length and the total number of bends constant.

16. The design system according to claim 11, wherein, The processor generates the layout by reshaping all 90-degree turns within all the balance paths to form a curved bend with the fixed bending radius.

17. An optical waveguide bus structure, comprising: Substrate; as well as A waveguide bus, located on the substrate and including an optical waveguide; The optical waveguides extend between corresponding first and second input / output nodes that are separated by different distances. The optical waveguide includes different combinations of straight segments and bends, such that the total length of the optical waveguide is within a threshold difference of a unit length, and that the total number of bends in the optical waveguide is equal; and The specific optical waveguide extending between the first and second input / output nodes and separated by the longest distance includes a specific combination of straight segments and bends, wherein the bends include cascaded bends having a stepped shape.

18. The optical waveguide bus structure according to claim 17, wherein, The specific combination of straight segments and bends also includes the longest straight segment of all straight segments of all said waveguides, wherein the longest straight segment extends from the first input / output node to the first end of the bend cascade.

19. The optical waveguide bus structure according to claim 18, wherein, The specific combination of straight segments and bends also includes: an additional straight segment extending from the second input / output node to the second end of the bend cascade.

20. The optical waveguide bus structure according to claim 17, wherein, All bends in all the waveguides have a fixed bend radius, and each length unit is equal to twice the fixed bend radius.

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