Wafer detection method, device, equipment and storage medium

Abstract

The present application provides a wafer detection method, device, equipment and storage medium, wherein the detection method includes: receiving an original wafer image to be detected, segmenting the original wafer image to obtain multiple first images; scaling the original wafer image and the multiple first images to obtain a second image and multiple third images respectively, wherein the second image and the third image both meet the size requirements of the wafer detection model for the input image; inputting the second image and the multiple third images into the wafer detection model in sequence to obtain a first detection result corresponding to the second image, and a second detection result corresponding to each third image; and then determining the total detection result of the original wafer image based on the first detection result and the multiple second detection results. The above scheme can avoid the loss of defect information caused by image compression, and greatly improves the detection accuracy of small-size defects while ensuring the detection accuracy of large-size defects.

Description

Technical Field

[0001] The present application relates to the field of semiconductor production, and in particular to a wafer detection method, device, equipment and storage medium. Background Art

[0002] Wafers are the basic raw materials for manufacturing semiconductor devices. High-purity semiconductors are prepared into wafers through processes such as crystal pulling and slicing. Wafers undergo a series of semiconductor manufacturing processes to form extremely small circuit structures, which are then cut, packaged, and tested to become chips, which are widely used in various electronic devices.

[0003] The wafer manufacturing process is extremely complex, mainly including exposure, etching, ion implantation, thin film deposition and chemical mechanical polishing. In actual production and manufacturing, there are as many as six hundred to thousands of steps. There are many types of wafer defects, with different shapes and sizes. At present, the traditional computer vision detection method is not effective for wafer defect detection, especially for small-scale wafer defects, the detection accuracy is poor. Summary of the invention

[0004] The present application provides a wafer inspection method, device, equipment and storage medium to improve the detection accuracy of wafer defects of different scales.

[0005] In a first aspect, an embodiment of the present application provides a wafer detection method, comprising:

[0006] Receive the original wafer image to be inspected;

[0007] Performing image segmentation on the original wafer image to obtain a plurality of first images, wherein the plurality of first images partially overlap;

[0008] Scaling the original wafer image to obtain a second image;

[0009] Scaling the plurality of first pictures to obtain a plurality of third pictures;

[0010] Inputting the second image and the plurality of the third images into a wafer inspection model in sequence, and obtaining a first inspection result corresponding to the second image and a second inspection result corresponding to each of the third images;

[0011] An overall inspection result of the original wafer image is determined according to the first inspection result and a plurality of the second inspection results.

[0012] In one embodiment of the present application, the step of segmenting the original wafer image to obtain a plurality of first images includes:

[0013] The original wafer image is segmented using a preset sliding window to obtain a plurality of first images.

[0014] In one embodiment of the present application, the size of the original wafer image is N×N, the size of the sliding window is N / n×N / n, and the original wafer image is segmented using a preset sliding window to obtain multiple first images, including:

[0015] The sliding window is moved in a first direction and a second direction with a step size of N / 2n respectively to obtain (2n-1)×(2n-1) first pictures, wherein the first direction is perpendicular to the second direction, and n is a positive integer greater than or equal to 2.

[0016] In one embodiment of the present application, the first detection result includes a first defect position where a wafer defect exists in the second image, and the second detection result includes a second defect position where a wafer defect exists in each of the third images;

[0017] Determining the total inspection result of the original wafer image according to the first inspection result and the plurality of the second inspection results includes:

[0018] Mapping the first defect position in the first detection result and the second defect position in each of the second detection results to the coordinate system of the original wafer image to obtain a plurality of third defect positions;

[0019] According to the plurality of third defect positions, total defect positions of wafer defects in the original wafer image are determined.

[0020] In one embodiment of the present application, the wafer inspection model is based on a deep neural network model and is obtained through training with training samples. The process of obtaining the training samples includes:

[0021] Obtaining a wafer image sample and a labeling result corresponding to the wafer image sample, wherein the labeling result includes a defect position of a wafer defect in the wafer image sample;

[0022] Performing image segmentation on the wafer image sample to obtain a plurality of first segmented image samples;

[0023] According to the defect position in the wafer image sample, selecting a second segmented image sample having a wafer defect from the plurality of first segmented image samples;

[0024] The wafer image sample and the second segmented image sample are used as training samples of the wafer detection model.

[0025] In one embodiment of the present application, the step of segmenting the wafer image sample to obtain a plurality of first segmented image samples includes:

[0026] The wafer image sample is segmented using a preset sliding window to obtain a plurality of first segmented image samples.

[0027] In one embodiment of the present application, the size of the wafer image sample is N×N, the size of the sliding window is N / n×N / n, and the wafer image sample is segmented using a preset sliding window to obtain a plurality of first segmented image samples, including:

[0028] The sliding window is moved in a first direction and a second direction with a step size of N / 2n respectively to obtain (2n-1)×(2n-1) samples of the first segmented image, where the first direction is perpendicular to the second direction.

[0029] In one embodiment of the present application, if the wafer image sample or the second segmented image sample does not meet the input size requirement of the wafer detection model, the method further includes:

[0030] Scaling the wafer image sample, and using the scaled wafer image sample as a training sample for the wafer detection model; or

[0031] The second segmented image sample is scaled, and the scaled second segmented image sample is used as a training sample for the wafer detection model.

[0032] In a second aspect, an embodiment of the present application provides a wafer detection device, including:

[0033] A receiving module, used for receiving the original wafer image to be inspected;

[0034] A processing module, configured to segment the original wafer image to obtain a plurality of first images, wherein the plurality of first images partially overlap;

[0035] Scaling the original wafer image to obtain a second image;

[0036] Scaling the plurality of first pictures to obtain a plurality of third pictures;

[0037] Inputting the second image and the plurality of the third images into a wafer inspection model in sequence, and obtaining a first inspection result corresponding to the second image and a second inspection result corresponding to each of the third images;

[0038] An overall inspection result of the original wafer image is determined according to the first inspection result and a plurality of the second inspection results.

[0039] In one embodiment of the present application, the processing module is specifically used to:

[0040] The original wafer image is segmented using a preset sliding window to obtain a plurality of first images.

[0041] In one embodiment of the present application, the size of the original wafer image is N×N, the size of the sliding window is N / n×N / n, and the processing module is specifically used to:

[0042] The sliding window is moved in a first direction and a second direction with a step size of N / 2n respectively to obtain (2n-1)×(2n-1) first pictures, wherein the first direction is perpendicular to the second direction, and n is a positive integer greater than or equal to 2.

[0043] In one embodiment of the present application, the first detection result includes a first defect position where a wafer defect exists in the second image, and the second detection result includes a second defect position where a wafer defect exists in each of the third images; the processing module is specifically used to:

[0044] Mapping the first defect position in the first detection result and the second defect position in each of the second detection results to the coordinate system of the original wafer image to obtain a plurality of third defect positions;

[0045] According to the plurality of third defect positions, total defect positions of wafer defects in the original wafer image are determined.

[0046] In one embodiment of the present application, the apparatus further includes: an acquisition module;

[0047] The acquisition module is used to acquire wafer image samples and annotation results corresponding to the wafer image samples, wherein the annotation results include defect locations of wafer defects in the wafer image samples;

[0048] The processing module is further used to perform image segmentation on the wafer image sample to obtain a plurality of first segmented image samples;

[0049] According to the defect position in the wafer image sample, selecting a second segmented image sample having a wafer defect from the plurality of first segmented image samples;

[0050] The wafer image sample and the second segmented image sample are used as training samples of the wafer detection model.

[0051] In one embodiment of the present application, the processing module is specifically used to: use a preset sliding window to perform image segmentation on the wafer image sample to obtain multiple first segmented image samples.

[0052] In one embodiment of the present application, the size of the wafer image sample is N×N, the size of the sliding window is N / n×N / n, and the processing module is specifically used to:

[0053] The sliding window is moved in a first direction and a second direction with a step size of N / 2n respectively to obtain (2n-1)×(2n-1) samples of the first segmented image, where the first direction is perpendicular to the second direction.

[0054] In one embodiment of the present application, if the wafer image sample or the second segmented image sample does not meet the input size requirement of the wafer detection model, the processing module is further used to:

[0055] Scaling the wafer image sample, and using the scaled wafer image sample as a training sample for the wafer detection model; or

[0056] The second segmented image sample is scaled, and the scaled second segmented image sample is used as a training sample for the wafer detection model.

[0057] In a third aspect, an embodiment of the present application provides a wafer inspection device, including:

[0058] at least one processor; and

[0059] a memory communicatively connected to the at least one processor; wherein,

[0060] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the wafer inspection device to perform any one of the methods according to the first aspect.

[0061] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer execution instructions, and when the computer execution instructions are executed by a processor, the processor is enabled to execute any one of the methods described in the first aspect.

[0062] In a fifth aspect, an embodiment of the present application provides a computer program product, including a computer program, wherein the computer program is executed by a processor to implement a method as described in any one of the first aspects.

[0063] The embodiments of the present application provide a wafer detection method, device, equipment and storage medium, wherein the detection method includes: receiving the original wafer image to be detected, segmenting the original wafer image to obtain multiple first images; scaling the original wafer image and the multiple first images to obtain the second image and multiple third images respectively, and the second image and the third image both meet the size requirements of the wafer detection model for the input image; inputting the second image and the multiple third images into the wafer detection model in sequence to obtain the first detection result corresponding to the second image, and the second detection result corresponding to each third image; and then determining the total detection result of the original wafer image based on the first detection result and the multiple second detection results. The above detection scheme can avoid the loss of defect information caused by image compression, and greatly improves the detection accuracy of small-size defects while ensuring the detection accuracy of large-size defects. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0065] Figure 1 A schematic diagram of the architecture of a wafer inspection system provided in an embodiment of the present application;

[0066] Figure 2 Schematic diagram of the process of the wafer detection method provided in the embodiment of the present application Figure 1 ;

[0067] Figure 3 Schematic diagram of the process of the wafer detection method provided in the embodiment of the present application Figure 2 ;

[0068] Figure 4 Schematic diagram of segmenting the original wafer image provided in the embodiment of the present application Figure 1 ;

[0069] Figure 5 Schematic diagram of segmenting the original wafer image provided in the embodiment of the present application Figure 2 ;

[0070] Figure 6 Process of wafer inspection model training process provided in the embodiment of the present application Figure 1 ;

[0071] Figure 7 Process of wafer inspection model training process provided in the embodiment of the present application Figure 2 ;

[0072] Figure 8 A schematic diagram of the structure of a wafer inspection device provided in an embodiment of the present application;

[0073] Fig. 9 A hardware schematic diagram of a wafer inspection device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0074] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0075] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein, for example.

[0076] In addition, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that includes a series of steps or elements is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements not explicitly listed or inherent to such process, method, product, or apparatus.

[0077] The technical solution provided in the embodiments of the present application relates to the field of semiconductor wafer production, and in particular to the field of defect detection in the wafer production process.

[0078] The chip (i.e. integrated circuit) industry is a strategic, basic and leading industry for the national economy and social development, and plays a key role in several major fields such as computers, consumer electronics, network communications, and automotive electronics. The chip production and manufacturing process is very complicated. Among them, the surface defects of wafers, which are the main material for manufacturing chips, are the main obstacle affecting product yield. By detecting surface defects on wafers, not only can defective grains be found, but also faults in the process can be judged based on the distribution pattern of defective grains, so that engineers can make process improvements.

[0079] At present, wafer defect detection is mainly divided into two categories: one is to detect the electrical properties of the grains through probe testing, and the other is to detect defects on the surface of the wafer through manual visual inspection. Both methods require experienced engineers to analyze and judge, which is manpower-consuming, labor-intensive and prone to errors. With the continuous increase in factory production capacity, the efficiency of manual detection is low.

[0080] With the continuous development of detection technology, detection methods based on image recognition have emerged, which can improve the efficiency and accuracy of wafer detection to a certain extent. This detection method mainly includes the following steps: first, feature extraction of wafer images is performed, and then the extracted features are input into the machine learning model for judgment, and the wafer defects in the wafer images are classified and identified. However, the above detection method has poor effect on wafer defect detection, low accuracy and high false alarm rate.

[0081] Subsequently, deep learning-based detection methods emerged. As the hottest machine learning method at present, deep learning requires a large amount of training data. Compared with the above-mentioned image recognition detection method, it can further improve the accuracy of wafer detection and reduce the false alarm rate. However, there are many types of wafer defects, including large scratch defects and small particle defects. For small defects that appear in wafer images, such as within 10×10 pixels, when the input image size requirements of the deep learning model are met, small defects may not be recognized due to image compression, resulting in the loss of defect information.

[0082] In response to the above problems, an embodiment of the present application proposes a wafer defect detection solution based on a deep neural network model. In addition to compressing the original wafer image and inputting it into the wafer detection model, considering the small-size wafer defects, the design is to segment the original wafer image, scale the segmented image to the model input requirements, and also input the scaled segmented image into the wafer detection model. The two types of wafer images are combined to determine whether there are wafer defects in the original wafer image.

[0083] Before introducing the wafer inspection method provided in the embodiment of the present application, a brief introduction to the system architecture of the method is first given.

[0084] For example, Figure 1 A schematic diagram of the architecture of a wafer inspection system provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the wafer inspection system provided in this embodiment includes: multiple image acquisition devices, a storage server, and at least one resource management node ( Figure 1, a resource management node is shown, and multiple working nodes. Each image acquisition device is connected to a storage server, the storage server is connected to a resource management node, and the resource management server is connected to multiple working nodes respectively. Each working node includes multiple graphics processing units (GPUs), and the GPUs are used to actually perform wafer inspection tasks.

[0085] The image acquisition device of this embodiment is used to acquire images of each wafer on the production line, and the image acquisition device stores the acquired wafer images on a storage server. As an example, the image acquisition device can be set on a detection machine on the production line.

[0086] The storage server of this embodiment is used to store wafer images from different image acquisition devices, and trigger the GPU cluster to perform intelligent defect detection on the wafer images. Among them, the GPU cluster includes a resource management node (RMN) and a work node (WN). The resource management node is responsible for the scheduling of wafer detection tasks, and the work node is responsible for the execution of wafer detection tasks.

[0087] In one embodiment of the present application, the storage server sends a wafer inspection task to the resource management node. Through a two-level scheduling algorithm, the wafer inspection task is sent to the GPU that actually executes the task. Specifically, the resource management node assigns the wafer inspection task to the working node, and the working node then assigns the wafer inspection task to the GPU.

[0088] In one embodiment of the present application, the resource management node may use a dynamic weight-based polling algorithm to assign wafer inspection tasks to working nodes, and periodically check the health status of each working node connected to the resource management node.

[0089] As an example, Figure 1 The wafer inspection model is pre-set in the GPU shown in the figure, and the model can be trained based on any deep learning model. Using the wafer inspection model to detect defects in wafer images requires a lot of computing resources. By performing hardware acceleration on the GPU, the performance can be improved by more than 10 times compared to the central processing unit (CPU), meeting the real-time requirements of wafer inspection.

[0090] The technical solution of the present application is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0091] For example, Figure 2Schematic diagram of the process of the wafer detection method provided in the embodiment of the present application Figure 1 ,like Figure 2 As shown, the wafer detection method provided in this embodiment can be applied to Figure 1 Any work node shown in the figure consists of two parts: CPU and GPU. The execution process of the work node will run on two hardware devices, CPU and GPU. Among them, the CPU part is responsible for preprocessing the original wafer image, for example Figure 2 The segmented images in the image can be understood as segmenting the original wafer image into multiple small images of the same size. The GPU is responsible for the defect detection task of the wafer image in the wafer inspection task. Before executing the defect detection task, the GPU first schedules the execution file related to the defect detection task from the CPU. The execution file includes the model parameters of the wafer inspection model, etc. Based on the execution file, the original wafer image and the segmented wafer image are inferred to determine whether the original wafer image and the segmented wafer image have wafer defects.

[0092] It should be noted that the GPU uses the wafer inspection model to infer the segmented wafer image. If it is determined that there are wafer defects in the segmented wafer image, the defect coordinates can be mapped to the coordinate system of the original wafer image, and repeated defects can be merged to determine the defect detection results of the original wafer image. Finally, the CPU is responsible for returning the defect detection results of the GPU, thus ending the process.

[0093] Optionally, in some embodiments, the above preprocessing also includes at least one of rotation, cropping, scaling, and numerical normalization of the original wafer image. Among them, data normalization refers to normalizing the RGB value and position information of each pixel of the wafer image to between [0,1]. The advantage of normalizing to [0,1] is that data values ​​of different dimensions (RGB values, positions) can be compared by the same dimension, so that the contribution value of each feature to the result is the same. The preprocessed wafer image meets the requirements of the wafer detection model for the input image.

[0094] From the description of the above embodiment, it can be seen that in the reasoning stage of the wafer inspection model, the original wafer image is first segmented, and then the original wafer image and the segmented image are reasoned one by one. If a wafer defect is detected in the segmented image, the coordinate system of the defect is mapped to the coordinate system of the original image. Since there are overlapping parts in the segmented images, repeated defects need to be merged. The above reasoning processes are all executed on the GPU to improve the processing speed of model reasoning.

[0095] exist Figure 2 Based on the embodiment shown, the model input and model reasoning process of the wafer inspection model are described in detail below through a specific embodiment. Figure 3Schematic diagram of the process of the wafer detection method provided in the embodiment of the present application Figure 2 ,like Figure 3 As shown, the wafer detection method provided in this embodiment includes the following steps:

[0096] Step 101: Receive an original wafer image to be inspected.

[0097] Step 102: segment the original wafer image to obtain multiple first images.

[0098] There is partial overlap between the multiple first images.

[0099] In one embodiment of the present application, a preset sliding window may be used to segment the original wafer image to obtain multiple first images. Exemplarily, a high-resolution original wafer image (N×N) is segmented to obtain multiple low-resolution first images (N / n×N / n).

[0100] As an example, the size of the original wafer image is N×N, the size of the sliding window is N / n×N / n, and the original wafer image is segmented using a preset sliding window to obtain multiple first images, including: moving the sliding window in a first direction and a second direction with a step size of N / 2n, respectively, to obtain (2n-1)×(2n-1) first images. The first direction and the second direction are perpendicular to each other. N represents the number of pixels. For example, the size of an original wafer image is 2048×2048, and n is a positive integer greater than or equal to 2.

[0101] For example, Figure 4 Schematic diagram of segmenting the original wafer image provided in the embodiment of the present application Figure 1 .like Figure 4 As shown, for the high-resolution original wafer image (N×N) image segmentation, if N / n is used as the step size, taking n as 2 as an example, 4 low-resolution first images (N / 2×N / 2) can be obtained, namely, image 1 to image 4.

[0102] For example, Figure 5 Schematic diagram of segmenting the original wafer image provided in the embodiment of the present application Figure 2 .like Figure 5 As shown, for the high-resolution original wafer image (N×N), if N / 2n is used as the step size, and n is 2 as an example, (2n-1)×(2n-1) images, i.e., 9 low-resolution first images, are obtained, namely, images 1 to 9. Specifically, in the first direction, for example Figure 5 The Y direction shown, and the second direction, such as Figure 5In the X direction shown, the sliding window is moved (N / 2×N / 2) with a step length of N / 4 to obtain pictures 1 to 9 in sequence. The X direction is perpendicular to the Y direction. Through the picture segmentation method of this embodiment, multiple first pictures are obtained, and there is partial overlap between adjacent first pictures, so that the defect information that may exist in the original wafer picture can be completely retained.

[0103] Step 103: scaling the original wafer image to obtain a second image.

[0104] Step 104: scaling the multiple first images to obtain multiple third images.

[0105] The second image in step 103 and the third image in step 104 have the same image size, and both meet the size requirement of the wafer inspection model for the input image.

[0106] It should be noted that the execution order of step 103 and step 104 in this embodiment is only an example, and the image scaling can also be performed simultaneously, or step 104 can be performed first and then step 103.

[0107] It should be noted that, usually, the size of the original wafer image is larger than the input image size preset by the wafer detection model. Therefore, image scaling of the original wafer image generally refers to image compression of the original wafer image. The first image is obtained by image segmentation of the original wafer image. Therefore, the size of the first image is smaller than the original wafer image. If the size of the first image is smaller than the input image size preset by the wafer detection model, the first image is enlarged. If the size of the first image is larger than the input image size preset by the wafer detection model, the first image is compressed.

[0108] Step 105: input the second image and multiple third images into the wafer inspection model in sequence to obtain a first inspection result corresponding to the second image and a second inspection result corresponding to each third image.

[0109] In this embodiment, the first detection result includes a first defect position where a wafer defect exists in the second image, and the second detection result includes a second defect position where a wafer defect exists in each third image. The defect position indicates an area of ​​the wafer defect, which may be a rectangular area, and accordingly, the rectangular area may be represented by diagonal vertex coordinates or four vertex coordinates.

[0110] Optionally, in some embodiments, the detection results output by the wafer detection model also include: a label for indicating whether there are wafer defects in the input image and a defect category.

[0111] For example, the label can be a label value, for example, 0 indicates that there is no wafer defect in the input image, and 1 indicates that there is a wafer defect in the input image. The defect category can be indicated by the ID of the defect category. For example, the wafer defects include scratch defects, particle defects, poor coating, poor edge coverage and other defects.

[0112] Optionally, in some embodiments, the detection result also includes a confidence level (which can be understood as a probability value) corresponding to the defect category.

[0113] Step 106: Determine the total detection result of the original wafer image according to the first detection result and the plurality of second detection results.

[0114] In one embodiment of the present application, determining the total inspection result of the original wafer image according to the first inspection result and the plurality of second inspection results includes:

[0115] The first defect position in the first detection result and the second defect position in each second detection result are mapped to the coordinate system of the original wafer image to obtain multiple third defect positions; based on the multiple third defect positions, the total defect position of the wafer defects in the original wafer image is determined.

[0116] Since the first image is obtained by segmenting the original wafer image, and the third image is obtained by scaling the first image, the defect position on the third image can be mapped to the first image, and then to the original wafer image. Since the second image is obtained by scaling the original wafer image, the defect position on the second image can be mapped to the original wafer image. By mapping the coordinates of the defect position, the defect detection results of the second image and each third image are merged, and the repeated defect positions are eliminated, so as to obtain the total defect position of the wafer defects in the original wafer image.

[0117] It should be noted that compared with the second image obtained by directly scaling the original wafer image, the third image has a low resolution. The low-resolution image can completely retain the defect information that may exist in the original wafer image. In other words, the third image magnifies the small-size defects that may exist in the original wafer image, avoiding the loss of defect information caused by image compression.

[0118] For example, the resolution of the original wafer image obtained by the wafer inspection system (WIS) is 2048×2048 pixels, and the optimal input of the wafer inspection model is a 416×416 pixel image. The smallest defect that can be identified is 5×5 pixels. For small-sized defects (within 10×10 pixels) that appear in the original wafer image, the compressed small-sized defects cannot be identified (the defects are compressed to within 2×2 pixels). In this regard, consider segmenting the original wafer image to obtain multiple first images with a resolution of 512×512 pixels, and then compress the first image to a third image with a resolution of 416×416 pixels. In this way, small-sized defects in the third image will not be undetectable due to excessive compression ratio.

[0119] The wafer detection method provided in this embodiment receives the original wafer image to be detected, performs image segmentation on the original wafer image, and obtains multiple first images; performs image scaling on the original wafer image and the multiple first images, respectively obtains the second image and multiple third images, and both the second image and the third image meet the size requirements of the wafer detection model for the input image; the second image and the multiple third images are sequentially input into the wafer detection model to obtain the first detection result corresponding to the second image, and the second detection result corresponding to each third image; and then determines the total detection result of the original wafer image based on the first detection result and the multiple second detection results. The above detection scheme can avoid the loss of defect information caused by image compression, and greatly improves the detection accuracy of small-size defects while ensuring the detection accuracy of large-size defects.

[0120] It can be seen from the above embodiments that each GPU of the working node is pre-set with a wafer detection model. Figure 6 , 7 The training process of the wafer inspection model is explained.

[0121] For example, Figure 6 Process of wafer inspection model training process provided in the embodiment of the present application Figure 1 ,like Figure 6 As shown, before training the wafer inspection model, a certain number of training samples need to be created first. Specifically, the creation of training samples mainly includes: obtaining the annotated original wafer image, segmenting the original wafer image, mapping the annotation information (i.e. mapping the defect position coordinates), and removing the defect-free segmented images. The difference from the existing scheme is that both the original wafer image and the segmented image are put into the training sample set. The annotation information can be mapped to the segmented image based on the annotation information in the original wafer image. In some embodiments, in order to minimize the number of images in the training sample set, if there is no wafer defect in the segmented image, the image will be eliminated and will not enter the model training.

[0122] Based on the created training sample set, the wafer inspection model is trained to determine whether the model accuracy meets the preset requirements. If it does not meet the preset requirements, the model training continues; if it meets the preset requirements, the model training ends and the trained model is deployed on the GPU. Specifically, the model accuracy includes Accuracy, Precision, and Recall. These three parameters must be greater than or equal to the preset values, such as 90%, to determine that the model accuracy meets the preset requirements. The above three parameters are all controlled by the algorithm.

[0123] In one possible implementation, the creation of the training sample set can be performed on the CPU, the training and verification of the model can be performed on the GPU, and the trained wafer inspection model can be deployed on the CPU, such as Figure 6 shown.

[0124] It should be noted that the trained wafer inspection model is deployed on the CPU. In order to improve the wafer inspection speed, the GPU can perform wafer inspection in the actual application process. Specifically, the GPU calls the execution file from the CPU, that is, the relevant files of the wafer inspection model deployed on the CPU, and performs wafer inspection based on the called execution file.

[0125] For example, Figure 7 Process of wafer inspection model training process provided in the embodiment of the present application Figure 2 ,like Figure 7 As shown, the training method of the wafer inspection model includes the following steps:

[0126] Step 201: Establish an initial wafer inspection model.

[0127] Step 202: Obtain training samples and annotation results of the training samples.

[0128] Step 203: Use the training samples as input of the wafer detection model, use the annotation results of the training samples as output of the wafer detection model, train the initial wafer detection model, and obtain the wafer detection model.

[0129] In this embodiment, the process of obtaining training samples includes:

[0130] Step 2021: Obtain wafer image samples and annotation results corresponding to the wafer image samples, where the annotation results include defect locations of wafer defects in the wafer image samples.

[0131] Optionally, in some embodiments, the annotation results corresponding to the wafer image samples also include the ID of the defect category. In this embodiment, the wafer image samples include wafer images of different wafer defect categories, different wafer defect locations, and different environmental conditions (such as lighting conditions, temperature environment, humidity environment, etc.).

[0132] Step 2022: perform image segmentation on the wafer image sample to obtain a plurality of first segmented image samples.

[0133] Specifically, a preset sliding window may be used to perform image segmentation on the wafer image sample to obtain a plurality of first segmented image samples.

[0134] As an example, the size of the wafer image sample is N×N, the size of the sliding window is N / n×N / n, and the sliding window is moved with a step size of N / 2n in the first direction and the second direction to obtain (2n-1)×(2n-1) first segmented image samples, such as Figure 5 As shown, the first direction is the Y direction, the second direction is the X direction, and the first direction and the second direction are perpendicular to each other.

[0135] Step 2023: Select a second segmented image sample having a wafer defect from the plurality of first segmented image samples according to the defect position in the wafer image sample.

[0136] Step 2024: Use the wafer image sample and the second segmented image sample as training samples for the wafer detection model.

[0137] In this embodiment, the acquired training samples should include image samples of different wafer defect categories and image samples of wafer defects of different sizes.

[0138] Optionally, in some embodiments, if the wafer image sample or the second segmented image sample does not meet the input size requirement of the wafer detection model, the wafer image sample or the second segmented image sample needs to be processed as follows:

[0139] Scaling the wafer image sample, and using the scaled wafer image sample as a training sample for the wafer detection model. Or

[0140] The second segmented image sample is scaled, and the scaled second segmented image sample is used as a training sample of the wafer detection model.

[0141] It should be noted that, usually, the size of the wafer image sample is larger than the input image size preset by the wafer detection model. Therefore, image scaling of the wafer image sample generally refers to image compression of the wafer image sample. The second segmented image sample is obtained by segmenting the wafer image sample. Therefore, the size of the second segmented image sample is smaller than the wafer image sample. If the size of the second segmented image sample is smaller than the input image size preset by the wafer detection model, the second segmented image sample is enlarged. If the size of the second segmented image sample is larger than the input image size preset by the wafer detection model, the second segmented image sample is compressed.

[0142] The wafer inspection model training method provided in this embodiment takes into account small-sized wafer defects and uses original wafer image samples and segmented wafer image samples as image samples for model training. The trained wafer inspection model can accurately identify wafer defects of different scales and types, greatly improving the detection accuracy of the inspection system for wafer defects of different scales.

[0143] The embodiment of the present application can divide the functional modules of the wafer detection device according to the above method embodiment. For example, each functional module can be divided corresponding to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation. The following is an example of dividing each functional module corresponding to each function.

[0144] For example, Figure 8 This is a schematic diagram of the structure of a wafer inspection device provided in an embodiment of the present application. Figure 8 As shown, the wafer inspection device 300 of this embodiment includes:

[0145] The receiving module 301 is used to receive the original wafer image to be detected;

[0146] A processing module 302 is used to segment the original wafer image to obtain a plurality of first images, wherein the plurality of first images partially overlap;

[0147] Scaling the original wafer image to obtain a second image;

[0148] Scaling the plurality of first pictures to obtain a plurality of third pictures;

[0149] Inputting the second image and the plurality of the third images into a wafer inspection model in sequence, and obtaining a first inspection result corresponding to the second image and a second inspection result corresponding to each of the third images;

[0150] An overall inspection result of the original wafer image is determined according to the first inspection result and a plurality of the second inspection results.

[0151] In one embodiment of the present application, the processing module 302 is specifically configured to segment the original wafer image using a preset sliding window to obtain a plurality of first images.

[0152] In one embodiment of the present application, the size of the original wafer image is N×N, the size of the sliding window is N / n×N / n, and the processing module is specifically used to:

[0153] The sliding window is moved in a first direction and a second direction with a step size of N / 2n respectively to obtain (2n-1)×(2n-1) first pictures, wherein the first direction is perpendicular to the second direction, and n is a positive integer greater than or equal to 2.

[0154] In one embodiment of the present application, the first detection result includes a first defect position where a wafer defect exists in the second image, and the second detection result includes a second defect position where a wafer defect exists in each of the third images; the processing module 302 is specifically used to:

[0155] Mapping the first defect position in the first detection result and the second defect position in each of the second detection results to the coordinate system of the original wafer image to obtain a plurality of third defect positions;

[0156] According to the plurality of third defect positions, total defect positions of wafer defects in the original wafer image are determined.

[0157] In one embodiment of the present application, the apparatus further includes: an acquisition module 303;

[0158] The acquisition module 303 is used to acquire wafer image samples and annotation results corresponding to the wafer image samples, wherein the annotation results include defect locations of wafer defects in the wafer image samples;

[0159] The processing module 302 is further used to perform image segmentation on the wafer image sample to obtain a plurality of first segmented image samples;

[0160] According to the defect position in the wafer image sample, selecting a second segmented image sample having a wafer defect from the plurality of first segmented image samples;

[0161] The wafer image sample and the second segmented image sample are used as training samples of the wafer detection model.

[0162] In one embodiment of the present application, the processing module 302 is specifically used to: use a preset sliding window to perform image segmentation on the wafer image sample to obtain a plurality of first segmented image samples.

[0163] In one embodiment of the present application, the size of the wafer image sample is N×N, the size of the sliding window is N / n×N / n, and the processing module 302 is specifically used to:

[0164] The sliding window is moved in a first direction and a second direction with a step size of N / 2n respectively to obtain (2n-1)×(2n-1) samples of the first segmented image, where the first direction is perpendicular to the second direction.

[0165] In one embodiment of the present application, if the wafer image sample or the second segmented image sample does not meet the input size requirement of the wafer detection model, the processing module 302 is further configured to:

[0166] Scaling the wafer image sample, and using the scaled wafer image sample as a training sample for the wafer detection model; or

[0167] The second segmented image sample is scaled, and the scaled second segmented image sample is used as a training sample for the wafer detection model.

[0168] The wafer inspection device provided in the embodiment of the present application is used to execute each step of the resource management node in any of the aforementioned method embodiments. Its implementation principle and technical effects are similar and will not be repeated here.

[0169] For example, Fig. 9 A hardware schematic diagram of a wafer inspection device provided in an embodiment of the present application. Fig. 9 As shown, the wafer inspection device 400 of this embodiment includes:

[0170] At least one processor 401 ( Fig. 9 Only one processor is shown); and

[0171] A memory 402 is communicatively connected to the at least one processor; wherein,

[0172] The memory 402 stores instructions that can be executed by the at least one processor 401. The instructions are executed by the at least one processor 401 to enable the wafer inspection device 400 to execute each step of the resource management node in any of the aforementioned method embodiments.

[0173] Optionally, the memory 402 may be independent or integrated with the processor 401 .

[0174] When the memory 402 is a device independent of the processor 401 , the wafer inspection device 400 further includes a bus 403 for connecting the memory 402 and the processor 401 .

[0175] The present application also provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the technical solution of any of the aforementioned method embodiments.

[0176] The present application also provides a computer program product, including a computer program, wherein the computer program is executed by a processor to implement the technical solution of any of the aforementioned method embodiments.

[0177] It should be understood that the processor mentioned in the embodiments of the present application may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

[0178] It should also be understood that the memory mentioned in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus random access memory (Direct Rambus RAM, DR RAM).

[0179] It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, the memory (storage module) is integrated in the processor.

[0180] It should be noted that the memory described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0181] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0182] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A wafer detection method, characterized in that: include: Receive the original wafer image to be inspected; Performing image segmentation on the original wafer image to obtain a plurality of first images, wherein the plurality of first images partially overlap; Scaling the original wafer image to obtain a second image; Scaling the plurality of first pictures to obtain a plurality of third pictures; Inputting the second image and the plurality of the third images into a wafer inspection model in sequence, and obtaining a first inspection result corresponding to the second image and a second inspection result corresponding to each of the third images; The first detection result includes a first defect position where a wafer defect exists in the second image, and the second detection result includes a second defect position where a wafer defect exists in each of the third images; Determining an overall inspection result of the original wafer image according to the first inspection result and the plurality of the second inspection results includes: Mapping the first defect position in the first detection result and the second defect position in each of the second detection results to the coordinate system of the original wafer image to obtain a plurality of third defect positions; According to the plurality of third defect positions, total defect positions of wafer defects in the original wafer image are determined.

2. The method according to claim 1, characterized in that The step of segmenting the original wafer image to obtain a plurality of first images includes: The original wafer image is segmented using a preset sliding window to obtain a plurality of first images.

3. The method according to claim 2, characterized in that The size of the original wafer image is N×N, the size of the sliding window is N / n×N / n, and the original wafer image is segmented using a preset sliding window to obtain a plurality of first images, including: The sliding window is moved in a first direction and a second direction with a step size of N / 2n respectively to obtain (2n-1)×(2n-1) first pictures, wherein the first direction is perpendicular to the second direction and n is a positive integer greater than or equal to 2.

4. The method according to any one of claims 1 to 3, characterized in that The wafer detection model is based on a deep neural network model and is obtained through training with training samples. The process of obtaining the training samples includes: Obtaining a wafer image sample and a labeling result corresponding to the wafer image sample, wherein the labeling result includes a defect position of a wafer defect in the wafer image sample; Performing image segmentation on the wafer image sample to obtain a plurality of first segmented image samples; According to the defect position in the wafer image sample, selecting a second segmented image sample having a wafer defect from the plurality of first segmented image samples; The wafer image sample and the second segmented image sample are used as training samples of the wafer detection model.

5. The method according to claim 4, characterized in that The step of segmenting the wafer image sample to obtain a plurality of first segmented image samples includes: The wafer image sample is segmented using a preset sliding window to obtain a plurality of first segmented image samples.

6. The method according to claim 5, characterized in that The size of the wafer image sample is N×N, the size of the sliding window is N / n×N / n, and the wafer image sample is segmented using a preset sliding window to obtain a plurality of first segmented image samples, including: The sliding window is moved in a first direction and a second direction with a step length of N / 2n respectively to obtain (2n-1)×(2n-1) samples of the first segmented image, wherein the first direction is perpendicular to the second direction.

7. The method according to claim 4, characterized in that If the wafer image sample or the second segmented image sample does not meet the input size requirement of the wafer detection model, the method further includes: Scaling the wafer image sample, and using the scaled wafer image sample as a training sample for the wafer detection model; or The second segmented image sample is scaled, and the scaled second segmented image sample is used as a training sample for the wafer detection model.

8. A wafer inspection device, characterized in that: include: A receiving module, used for receiving the original wafer image to be inspected; A processing module, configured to segment the original wafer image to obtain a plurality of first images, wherein the plurality of first images partially overlap; Scaling the original wafer image to obtain a second image; Scaling the plurality of first pictures to obtain a plurality of third pictures; Inputting the second image and the plurality of the third images into a wafer inspection model in sequence, and obtaining a first inspection result corresponding to the second image and a second inspection result corresponding to each of the third images; The first detection result includes a first defect position where a wafer defect exists in the second image, and the second detection result includes a second defect position where a wafer defect exists in each of the third images; the processing module is specifically used to: Mapping the first defect position in the first detection result and the second defect position in each of the second detection results to the coordinate system of the original wafer image to obtain a plurality of third defect positions; According to the plurality of third defect positions, total defect positions of wafer defects in the original wafer image are determined.

9. The device according to claim 8, characterized in that The processing module is specifically used to: use a preset sliding window to segment the original wafer image to obtain multiple first images.

10. The device according to claim 9, characterized in that The size of the original wafer image is N×N, the size of the sliding window is N / n×N / n, and the processing module is specifically used for: The sliding window is moved in a first direction and a second direction with a step size of N / 2n respectively to obtain (2n-1)×(2n-1) first pictures, wherein the first direction is perpendicular to the second direction and n is a positive integer greater than or equal to 2.

11. The device according to any one of claims 8 to 10, characterized in that The device also includes: an acquisition module; The acquisition module is used to acquire wafer image samples and annotation results corresponding to the wafer image samples, wherein the annotation results include defect locations of wafer defects in the wafer image samples; The processing module is further used to perform image segmentation on the wafer image sample to obtain a plurality of first segmented image samples; According to the defect position in the wafer image sample, selecting a second segmented image sample having a wafer defect from the plurality of first segmented image samples; The wafer image sample and the second segmented image sample are used as training samples of the wafer detection model.

12. The device according to claim 11, characterized in that The processing module is specifically used to: use a preset sliding window to perform image segmentation on the wafer image sample to obtain multiple first segmented image samples.

13. The device according to claim 12, characterized in that The size of the wafer image sample is N×N, the size of the sliding window is N / n×N / n, and the processing module is specifically used for: The sliding window is moved in a first direction and a second direction with a step length of N / 2n respectively to obtain (2n-1)×(2n-1) samples of the first segmented image, wherein the first direction is perpendicular to the second direction.

14. The device according to claim 11, characterized in that If the wafer image sample or the second segmented image sample does not meet the input size requirement of the wafer detection model, the processing module is further used to: Scaling the wafer image sample, and using the scaled wafer image sample as a training sample for the wafer detection model; or The second segmented image sample is scaled, and the scaled second segmented image sample is used as a training sample for the wafer detection model.

15. A wafer inspection device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the wafer inspection device to perform the method according to any one of claims 1 to 7.

16. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the processor is enabled to execute the method according to any one of claims 1 to 7.

17. A computer program product, characterized in that The method comprises a computer program which is executed by a processor to implement the method according to any one of claims 1 to 7.

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