Method for Automatically Selecting Equalizer Gains

Abstract

The present invention discloses a method for automatically selecting an equalizer gear, which is applied to a display device. The display device includes a display panel, a plurality of source driver circuits and a timing control circuit. The plurality of source driver circuits respectively include a plurality of equalizers. The method includes the following steps: coupling the timing control circuit to the plurality of source driver circuits and coupling the plurality of source driver circuits to the display panel; and communicating the training results of the plurality of equalizers to each other between the timing control circuit and the plurality of source driver circuits through at least one bidirectional control signal to achieve synchronization of display data transmission.

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly to a method for automatically selecting an equalizer stage applied to a display device. Background Art

[0002] Generally, as Figure 1 shown, the display device 1 includes a display panel PL, source driver circuits SD1 to SDN, and a timing control circuit TCON. The timing control circuit TCON is coupled to the source driver circuits SD1 to SDN through traces respectively. The source driver circuits SD1 to SDN are respectively coupled to different display regions of the display panel PL.

[0003] However, as the size of the display panel PL increases and its resolution improves, due to the position differences between the source driver circuits SD1 to SDN, the lengths of the traces for coupling the timing control circuit TCON to the source driver circuits SD1 to SDN are different, and the resulting channel loss will become non-negligible. In particular, when the timing control circuit TCON outputs timing control signals to the source driver circuits SD1 to SDN, it is very likely that the source driver circuits SD1 to SDN will receive incorrect signals due to channel loss, which urgently needs to be improved. Summary of the Invention

[0004] In view of this, the present invention provides a method for automatically selecting an equalizer stage applied to a display device to effectively solve the above problems encountered in the prior art.

[0005] According to a specific embodiment of the present invention, a method for automatically selecting an equalizer stage is provided. In this embodiment, the method for automatically selecting an equalizer stage is applied to a display device. The display device includes a display panel, a plurality of source driver circuits, and a timing control circuit. The plurality of source driver circuits respectively include a plurality of equalizers. The method includes the following steps: coupling the timing control circuit to the plurality of source driver circuits and coupling the plurality of source driver circuits to the display panel; and communicating the training results of the plurality of equalizers between the timing control circuit and the plurality of source driver circuits through at least one bidirectional control signal to achieve synchronization of display data transmission.

[0006] In one embodiment, the iSP transmission mode is adopted for point-to-point data transmission between the timing control circuit and the plurality of source driver circuits.

[0007] In one embodiment, the timing control circuit transmits a training pattern with a specific frequency to the plurality of source driver circuits.

[0008] In one embodiment, when the plurality of source driver circuits respectively receive a training pattern with a specific frequency, the plurality of source driver circuits synchronize to the specific frequency and train the plurality of equalizers.

[0009] In one embodiment, when the plurality of source driver circuits respectively complete the training of the plurality of equalizers, the plurality of source driver circuits respectively transmit the training results of the plurality of equalizers to the timing control circuit through a plurality of equalizer feedback signals.

[0010] In one embodiment, when the timing control circuit receives the plurality of equalizer feedback signals and determines that the training results of the plurality of equalizers are correct, the timing control circuit will start to transmit display data to the plurality of source driver circuits.

[0011] In one embodiment, the at least one bidirectional control signal includes a lock signal, which includes a training pattern with a specific frequency.

[0012] In one embodiment, the at least one bidirectional control signal includes an equalizer feedback signal, which includes the training results of the equalizers.

[0013] In one embodiment, the timing control circuit includes a transmission end control unit, a clock generation unit, a parallel-to-serial conversion unit, a pre-emphasis unit, and a transmission end driving unit. The transmission end control unit is used to control the data transmission process within the timing control circuit. The clock generation unit is coupled to the control unit and is used to generate a clock signal with a specific frequency. The parallel-to-serial conversion unit is coupled to the control unit and the clock generation unit and is used to convert parallel data into serial data according to the clock signal. The pre-emphasis unit is coupled to the control unit and is used to generate a pre-emphasis setting. The transmission end driving unit is coupled to the parallel-to-serial conversion unit and the pre-emphasis unit and is used to output the processed serial data through a transmission end pin according to the pre-emphasis setting.

[0014] In one embodiment, each source driver circuit respectively includes an equalizer, a clock data recovery (CDR) unit, a serial-to-parallel conversion unit, and a receiving end control unit. The equalizer receives serial data through a receiving end pin. The clock data recovery unit is coupled to the equalizer and is used to obtain a clock signal from the serial data. The serial-to-parallel conversion unit is coupled to the equalizer and the clock data recovery unit and is used to convert the serial data into parallel data according to the clock signal. The receiving end control unit is coupled to the serial-to-parallel conversion unit and is used to control the data transmission process within the source driver circuit.

[0015] In one embodiment, communication between the transmission end control unit and the receiving end control unit is carried out through the at least one bidirectional control signal, and the control direction of the at least one bidirectional control signal is determined according to different mode settings.

[0016] In one embodiment, the at least one bidirectional transmission control signal includes a lock signal, which includes a training pattern having a specific frequency.

[0017] In one embodiment, the at least one bidirectional transmission control signal includes an equalizer feedback signal, which includes the training result of the equalizer.

[0018] In one embodiment, the plurality of source driver circuits can be set simultaneously or set serially in succession.

[0019] In one embodiment, the at least one bidirectional control signal includes a lock signal and an equalizer feedback signal.

[0020] In one embodiment, when both the lock signal and the equalizer feedback signal are at a low level, the plurality of source driver circuits perform clock synchronization training to synchronize with the timing control circuit.

[0021] In one embodiment, when the lock signal changes from a low level to a high level and the equalizer feedback signal remains at a low level, the plurality of source driver circuits perform training of the plurality of equalizers.

[0022] In one embodiment, when the equalizer feedback signal changes from a low level to a high level and the lock signal remains at a high level, the plurality of source driver circuits transmit the training results of the plurality of equalizers to the timing control circuit through the equalizer feedback signal.

[0023] In one embodiment, when the timing control circuit receives the training results of the plurality of equalizers, the timing control circuit determines whether the training results of the plurality of equalizers are correct.

[0024] In one embodiment, if the above determination result is yes, the timing control circuit changes the lock signal from a high level to a low level and maintains the equalizer feedback signal at a high level to start transmitting display data to the plurality of source driver circuits; if the above determination result is no, the timing control circuit changes both the lock signal and the equalizer feedback signal to a low level, causing the plurality of source driver circuits to re-perform clock synchronization training.

[0025] Compared with the prior art, the present invention proposes a method for automatically selecting an equalizer gear applied to a display device, which uses at least one bidirectional control signal (such as a lock signal Lock and an equalizer feedback signal EQFB) to control the state setting of an equalizer (EQ) in a source driver, so as to improve the stability of selecting the equalizer gear, and thus can effectively avoid the phenomenon of reception errors caused by channel loss due to the inconsistent wiring lengths of the timing controller coupled to each source driver.

[0026] The advantages and spirit of the present invention can be further understood through the following detailed description of the invention and the drawings. Description of the Drawings

[0027] Figure 1 It is a schematic diagram showing that the different positions of the source driver circuits in the prior art result in different lengths of the traces connecting the timing control circuit to each source driver circuit.

[0028] Figure 2 It is a schematic diagram of the architecture of the present invention in which the timing control circuit as the transmitting end and the source driver circuit as the receiving end adopt a point-to-point iSP transmission method.

[0029] Figure 3 It is a timing diagram of the present invention entering the normal display mode after completing the training mode and the feedback mode through the bidirectional control signals (lock signal and equalizer feedback signal).

[0030] Figure 4 It is a flowchart of the method for automatically selecting the equalizer gear in a preferred specific embodiment of the present invention.

[0031] Figure 5 It is a functional block diagram of the timing control circuit as the transmitting end and the source driver circuit as the receiving end in an embodiment.

[0032] Figure 6 It is a timing diagram for achieving automatic selection of the equalizer gear through the bidirectional control signals (lock signal and equalizer feedback signal).

[0033] Description of the Main Component Symbols

[0034] 1... Display device

[0035] PL... Display panel

[0036] SD1~SDN... Source driver circuit

[0037] TCON... Timing control circuit

[0038] TX1~TXK... Transmitter

[0039] LD... Lock signal detector

[0040] ED... Equalizer feedback signal detector

[0041] SD1~SDK... Source driver circuit

[0042] DVDD... Operating voltage

[0043] R... Resistor

[0044] GND... Ground terminal

[0045] RX1 to RXK... Receiver

[0046] M11 to M12... Switch

[0047] MK1 to MK2... Switch

[0048] LOCK... Locking Signal

[0049] EQFB... Equalizer Feedback Signal

[0050] ... Inverted Locking Signal

[0051] ...... Inverted Equalizer Feedback Signal

[0052] MODE1... Training Mode

[0053] MODE2... Feedback Mode

[0054] MODE3... Normal Display Mode

[0055] TP... Training Pattern

[0056] DD... Display Data

[0057] t1 to t2.. Time

[0058] 30... Timing Control Circuit

[0059] 32... Source Driver Circuit

[0060] 300... Transmitter Control Unit

[0061] 301... Clock Generation Unit

[0062] 302... Parallel-to-Serial Unit

[0063] 303... Pre-emphasis Unit

[0064] 304... Transmitter Driver Unit

[0065] 320... Equalizer

[0066] 321... Clock and Data Recovery (CDR) Unit

[0067] 322... Serial-to-Parallel Unit

[0068] 323... Receiver Control Unit

[0069] CLK... Clock Signal

[0070] PDT... Parallel Data

[0071] SDT... Serial data

[0072] PES... Pre - enhancement setting

[0073] TXPN... Transmitting - end pin

[0074] CH... Channel

[0075] RXPN... Receiving - end pin

[0076] TP1... Training pattern

[0077] TP2... Training pattern

[0078] SET... Setting signal

[0079] EQ1~EQK... Equalizer training result

[0080] S10~S12... Steps Detailed implementation manners

[0081] Now, reference will be made in detail to the exemplary embodiments of the present invention, and examples of the exemplary embodiments will be described in the accompanying drawings. Elements / components with the same or similar reference numerals in the drawings and embodiments are used to represent the same or similar parts.

[0082] According to a specific embodiment of the present invention, a method for automatically selecting an equalizer gear is provided. In this embodiment, the method for automatically selecting an equalizer gear is applied to a display device, and the type of the display device is not particularly limited. The display device includes a display panel, a plurality of source driver circuits, and a timing control circuit. The plurality of source driver circuits are respectively coupled to different display areas of the display panel. The plurality of source driver circuits respectively include a plurality of equalizers. The plurality of source driver circuits can be set simultaneously or set serially in succession.

[0083] As Figure 2 shown, Figure 2 is a schematic diagram of the architecture of the point - to - point iSP transmission mode between the timing control circuit as the transmitting end and the plurality of source driver circuits as the receiving end of the present invention.

[0084] As Figure 2 shown, the timing control circuit TCON as the transmitting end (TX) includes transmitters TX1~TXK, a lock signal detector LD, and an equalizer feedback signal detector ED, where K is a positive integer. The transmitters TX1~TXK are respectively coupled to the plurality of source driver circuits SD1~SDK as the receiving end (RX). The lock signal detector LD is coupled to the wire for transmitting the lock signal LOCK. The equalizer feedback signal detector ED is coupled to the wire for transmitting the equalizer feedback signal EQFB.

[0085] For the source driving circuit SD1 among the plurality of source driving circuits SD1-SDK, the source driving circuit SD1 includes a receiver RX1 and switches M11-M12. The receiver RX1 is coupled to the transmitter TX1 and receives the signal transmitted by the transmitter TX1. The switch M11 is coupled to the wire for transmitting the locking signal LOCK and its gate is controlled by the inverted locking signal The switch M12 is coupled to the conductor for transmitting the equalizer feedback signal EQFB and its gate is controlled by the inverted equalizer feedback signal

[0086] For the source driving circuit SDK among the plurality of source driving circuits SD1-SDK, the source driving circuit SDK includes a receiver RXK and switches MK1-MK2. The receiver RXK is coupled to the transmitter TXK and receives the signal transmitted by the transmitter TXK. The switch MK1 is coupled to the wire for transmitting the locking signal LOCK and its gate is controlled by the inverted locking signal The switch MK2 is coupled to the conductor for transmitting the equalizer feedback signal EQFB and its gate is controlled by the inverted equalizer feedback signal The rest can be inferred similarly and will not be elaborated here.

[0087] Figure 3 This is a timing diagram of the present invention entering a normal display mode after completing a training mode and a feedback mode through a bidirectional control signal (a locking signal and an equalizer feedback signal).

[0088] like Figure 3 As shown, the period before time t2 is the training mode MODE1 and the feedback mode MODE2. Figure 2 The timing control circuit TCON and the source driving circuits SD1-SDK in the circuit respectively perform clock training, automatic equalizer training (AEQ training) and feedback (Feedback) of the equalizer training results through the bidirectional control signals of the locking signal LOCK and the equalizer feedback signal EQFB. During this period, the transmitters TX1-TXK can respectively transmit the training pattern TP with a specific frequency to the corresponding receivers RX1-RXK, but not limited thereto.

[0089] When the timing control circuit TCON confirms that the equalizer training results of the source driving circuits SD1-SDK are correct at time t2, it starts to enter the normal display mode MODE3. At this time, the transmitters TX1-TXK in the timing control circuit TCON start to transmit the display data DD to the corresponding receivers RX1-RXK of the source driving circuits SD1-SDK, respectively, for the display panel to display.

[0090] Next, Figure 4 This is a flowchart of the method for automatically selecting the equalizer stage in this embodiment. As Figure 4 shown, the method for automatically selecting the equalizer stage in this embodiment includes the following steps:

[0091] Step S10: Couple the timing control circuit to the plurality of source driver circuits and couple the plurality of source driver circuits to the display panel; and

[0092] Step S12: Communicate the training results of the plurality of equalizers between the timing control circuit and the plurality of source driver circuits through at least one bidirectional control signal to achieve synchronization of display data transmission.

[0093] In practical applications, a point-to-point data transmission such as the iSP transmission method can be adopted between the timing control circuit and the plurality of source driver circuits, but it is not limited thereto.

[0094] Regarding the training of the plurality of equalizers of the plurality of source driver circuits, an example is as follows:

[0095] First, the timing control circuit can transmit a training pattern with a specific frequency to the plurality of source driver circuits through, for example, a lock signal LOCK. When the plurality of source driver circuits respectively receive the training pattern with a specific frequency, the plurality of source driver circuits will synchronize to the specific frequency and train the plurality of equalizers.

[0096] When the plurality of source driver circuits respectively complete the training of the plurality of equalizers, the plurality of source driver circuits respectively transmit the training results of the plurality of equalizers to the timing control circuit through a plurality of equalizer feedback signals. When the timing control circuit receives the plurality of equalizer feedback signals and determines that the training results of the plurality of equalizers are correct, the timing control circuit will start to transmit display data to the plurality of source driver circuits. In other words, if the timing control circuit determines that the training results of the plurality of equalizers are incorrect, the timing control circuit will not transmit display data to the plurality of source driver circuits.

[0097] In practical applications, the at least one bidirectional control signal described in step S12 may include a lock signal and an equalizer feedback signal, but it is not limited thereto. Among them, the lock signal may include a training pattern with a specific frequency and the equalizer feedback signal may include the training results of the equalizers, but it is not limited thereto.

[0098] Figure 5 This is a functional block diagram of a timing control circuit as a transmitter (TX) and a source driver circuit as a receiver (RX) in an embodiment.

[0099] As shown Figure 5 in FIG. Figure 5 , the timing control circuit 30 as a transmission end (TX) may include a transmission end control unit 300, a clock generation unit 301, a parallel-to-serial conversion unit 302, a pre-emphasis unit 303, and a transmission end driving unit 304, but is not limited thereto.

[0100] In this embodiment, the transmission end control unit 300 is used to control the data transmission process within the timing control circuit 30. The clock generation unit 301 is coupled to the transmission end control unit 300 and is used to generate a clock signal CLK with a specific frequency. The parallel-to-serial conversion unit 302 is coupled to the transmission end control unit 300 and the clock generation unit 301 and is used to convert parallel data PDT into serial data SDT according to the clock signal CLK. The pre-emphasis unit 303 is coupled to the transmission end control unit 300 and is used to generate a pre-emphasis setting PES. The transmission end driving unit 304 is coupled to the parallel-to-serial conversion unit 302 and the pre-emphasis unit 303 and is used to process the serial data SDT according to the pre-emphasis setting PES and output it to the channel CH through the transmission end pin TXPN.

[0101] In this embodiment, the source driver circuit 32 as a receiving end (RX) may include an equalizer 320, a clock data recovery (CDR) unit 321, a serial-to-parallel conversion unit 322, and a receiving end control unit 323. The equalizer 320 receives the serial data SDT from the channel CH through the receiving end pin RXPN. The clock data recovery unit 321 is coupled to the equalizer 320 and is used to obtain the clock signal CLK from the serial data SDT. The serial-to-parallel conversion unit 322 is coupled to the equalizer 320 and the clock data recovery unit 321 and is used to convert the serial data SDT into parallel data PDT according to the clock signal CLK. The receiving end control unit 323 is coupled to the serial-to-parallel conversion unit 322 and is used to control the data transmission process within the source driver circuit 32.

[0102] It should be noted that the transmission end control unit 300 in the timing control circuit 30 as the transmission end (TX) and the receiving end control unit 323 in the source driver circuit 32 as the receiving end (RX) can communicate through at least one bidirectional control signal (such as a lock signal LOCK and an equalizer feedback signal EQFB, but not limited thereto), and the at least one bidirectional control signal (such as the lock signal LOCK and the equalizer feedback signal EQFB) can determine its control direction according to different mode settings. In fact, the multiple source driver circuits of the display device can be set simultaneously or serially set continuously, without specific limitations.

[0103] Next, Figure 6It is a timing diagram for automatically selecting the equalizer gear through bidirectional control signals (lock signal LOCK and equalizer feedback signal EQFB).

[0104] As Figure 6 shown, before time t1 belongs to training mode MODE1; between time t1 and t2 belongs to the feedback mode MODE2 stage, and after time t2 belongs to the normal display mode MODE3.

[0105] In the training mode MODE1, the transmitter TX1 of the timing control circuit TCON can transmit training patterns (Training pattern) TP1 - TP2 with specific frequencies to the receiver RX1 of the source driver circuit SD1 through the lock signal LOCK. Similarly, the transmitter TXK of the timing control circuit TCON can transmit training patterns TP1 - TP2 with specific frequencies to the receiver RXK of the source driver circuit SDK through the lock signal LOCK. The rest can be inferred by analogy. Among them, the training pattern TP1 can be used for clock synchronization training and the training pattern TP2 can be used for equalizer synchronization training, but not limited to this.

[0106] As Figure 6 shown, in the training mode MODE1, when both the lock signal LOCK and the equalizer feedback signal EQFB are at low level, the source driver circuits SD1 - SDK will perform clock synchronization training according to the training pattern TP1 to synchronize with the timing control circuit TCON. When the lock signal LOCK changes from low level to high level and the equalizer feedback signal EQFB still remains at low level, the source driver circuits SD1 - SDK will perform the synchronization training of their equalizers.

[0107] At time t1, the equalizer feedback signal EQFB changes from low level to high level and starts to enter the feedback mode MODE2. In the feedback mode MODE2, when the equalizer feedback signal EQFB changes from low level to high level and the lock signal LOCK still remains at high level, the source driver circuits SD1 - SDK will respectively transmit their respective equalizer training results EQ1 - EQK to the timing control circuit TCON through the equalizer feedback signal EQFB.

[0108] When the timing control circuit TCON receives the equalizer training results EQ1 - EQK respectively, the timing control circuit TCON will judge whether the equalizer training results EQ1 - EQK are correct.

[0109] If the above judgment result is yes, it means that the source driver circuits SD1 to SDK have all completed their equalizer synchronization training. Then, the timing control circuit TCON will change the lock signal LOCK from a high level to a low level and maintain the equalizer feedback signal EQFB at a high level to enter the normal display mode MODE3 at time t2. At this time, the transmitters TX1 to TXK will start to transmit the display data DD to the source driver circuits SD1 to SDK respectively.

[0110] If the above judgment result is no, it means that the source driver circuits SD1 to SDK have not completed their equalizer clock synchronization training. Then, the timing control circuit TCON will change both the lock signal LOCK and the equalizer feedback signal EQFB to a low level to enter the training mode MODE1 again, causing the source driver circuits SD1 to SDK to re-perform their equalizer synchronization training.

[0111] It should be noted that, regarding the operation of the lock signal LOCK, as Figure 6 shown, in the training mode MODE1 and the feedback mode MODE2, the lock signal LOCK is transmitted from the timing control circuit TCON to the source driver circuits SD1 to SDK, that is, the lock signal LOCK is controlled by the timing control circuit TCON; in the normal display mode MODE3, the lock signal LOCK is transmitted from the source driver circuits SD1 to SDK to the timing control circuit TCON, that is, the lock signal LOCK is controlled by the source driver circuits SD1 to SDK.

[0112] In addition, regarding the operation of the equalizer feedback signal EQFB, as Figure 6 shown, in the training mode MODE1, the equalizer feedback signal EQFB is transmitted from the timing control circuit TCON to the source driver circuits SD1 to SDK, that is, the equalizer feedback signal EQFB is controlled by the timing control circuit TCON, and its EQ value steps from 0 to K in sequence; in the feedback mode MODE2 and the normal display mode MODE3, the equalizer feedback signal EQFB is transmitted from the source driver circuits SD1 to SDK to the timing control circuit TCON, that is, the equalizer feedback signal EQFB is controlled by the source driver circuits SD1 to SDK, and its EQ value is the optimal value Mi selected from 0 to K and i = 1 to K.

[0113] It should be noted that the source driver circuits SD1 to SDK in this embodiment can inform the timing control circuit TCON of the equalizer gear selection after training their equalizers through the equalizer feedback signal EQFB, so that the timing control circuit TCON can judge whether it is necessary to adjust Figure 5 the pre-emphasis setting PES provided by the pre-emphasis unit 303 in

[0114] Compared with the prior art, the present invention proposes a method for automatically selecting an equalizer gear applied to a display device, which uses at least one bidirectional control signal (such as a lock signal LOCK and an equalizer feedback signal EQFB) to control the state setting of an equalizer (EQ) in a source driver, so as to improve the stability of selecting the equalizer gear, and thus can effectively avoid the phenomenon of receiving errors caused by channel loss due to the different lengths of the traces connecting the timing controller to each source driver.

Claims

1. A method for automatically selecting an equalizer gear, which is applied to a display device, characterized in that, the display device includes a display panel, a plurality of source driver circuits and a timing control circuit, the plurality of source driver circuits respectively include a plurality of equalizers, and the method includes the following steps: Couple the timing control circuit to the plurality of source driver circuits and couple the plurality of source driver circuits to the display panel; And The training results of the plurality of equalizers are communicated between the timing control circuit and the plurality of source driver circuits through at least one bidirectional control signal to achieve synchronization of display data transmission; Wherein, the at least one bidirectional control signal includes a lock signal and a plurality of equalizer feedback signals, the timing control circuit transmits a training pattern with a specific frequency to the plurality of source driver circuits through the lock signal, when the plurality of source driver circuits respectively receive the training pattern with the specific frequency, the plurality of source driver circuits synchronize to the specific frequency and train the plurality of equalizers, when the plurality of source driver circuits respectively complete the training of the plurality of equalizers, the plurality of source driver circuits respectively transmit the training results of the plurality of equalizers to the timing control circuit through the plurality of equalizer feedback signals, when the timing control circuit receives the plurality of equalizer feedback signals and determines that the training results of the plurality of equalizers are correct, the timing control circuit will start to transmit display data to the plurality of source driver circuits, and the training results of the plurality of equalizers include the equalizer gear selection after the plurality of source driver circuits train the plurality of equalizers.

2. The method for automatically selecting an equalizer gear according to claim 1, characterized in that, Point-to-point data transmission is carried out between the timing control circuit and the plurality of source driver circuits by using the iSP transmission method.

3. The method for automatically selecting an equalizer gear according to claim 1, characterized in that, The timing control circuit includes: A transmission end control unit for controlling the data transmission process in the timing control circuit; A clock generation unit, coupled to the control unit, for generating a clock signal with the specific frequency; a parallel-to-serial conversion unit, coupled to the control unit and the clock generation unit, for converting parallel data into serial data according to the clock signal; A pre-emphasis unit, coupled to the control unit, for generating a pre-emphasis setting; and A transmission end driver unit, coupled to the parallel-to-serial conversion unit and the pre-emphasis unit, for processing the serial data according to the pre-emphasis setting and outputting it through a transmission end pin.

4. The method for automatically selecting an equalizer gear according to claim 3, characterized in that, Each source driver circuit respectively includes: The equalizer, which receives the serial data through a receiving end pin; A clock data recovery unit, coupled to the equalizer, for obtaining the clock signal from the serial data; A serial-to-parallel conversion unit, coupled to the equalizer and the clock data recovery unit, for converting the serial data into the parallel data according to the clock signal; and A receiving end control unit, coupled to the serial-to-parallel conversion unit, for controlling the data transmission process in the source driver circuit.

5. The method for automatically selecting an equalizer stage as claimed in claim 4, characterized in that, communication between the transmitter control unit and the receiver control unit is carried out through the at least one bidirectional control signal, and the control direction of the at least one bidirectional control signal is determined according to different mode settings.

6. The method for automatically selecting an equalizer stage as claimed in claim 1, characterized in that, the plurality of source driver circuits can be set simultaneously or set serially in succession.

7. The method for automatically selecting an equalizer stage as claimed in claim 1, characterized in that, when the lock signal and the plurality of equalizer feedback signals are both at a low level, the plurality of source driver circuits perform clock synchronization training to synchronize with the timing control circuit.

8. The method for automatically selecting an equalizer stage as claimed in claim 7, characterized in that, when the lock signal changes from a low level to a high level and the plurality of equalizer feedback signals still remain at a low level, the plurality of source driver circuits perform training of the plurality of equalizers.

9. The method for automatically selecting an equalizer stage as claimed in claim 8, characterized in that, when the plurality of equalizer feedback signals change from a low level to a high level and the lock signal still remains at a high level, the plurality of source driver circuits transmit the training results of the plurality of equalizers to the timing control circuit through the equalizer feedback signals.

10. The method for automatically selecting an equalizer stage as claimed in claim 9, characterized in that, when the timing control circuit receives the training results of the plurality of equalizers, the timing control circuit determines whether the training results of the plurality of equalizers are correct.

11. The method for automatically selecting an equalizer stage as claimed in claim 10, characterized in that, if the determination result of the timing control circuit is yes, the timing control circuit changes the lock signal from a high level to a low level and maintains the equalizer feedback signal at a high level to start transmitting display data to the plurality of source driver circuits; if the determination result of the timing control circuit is no, the timing control circuit changes both the lock signal and the equalizer feedback signal to a low level, causing the plurality of source driver circuits to perform clock synchronization training again.

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