Memory device for in-memory operation and data weight state determination method

Abstract

A memory device for in-memory operation includes a plurality of data lanes, a memory cell array, a maximum accumulation weight generation array, a minimum accumulation weight generation array, a reference value generator, and a comparator. The data lanes have an open number according to a data input. The memory cell array generates an accumulation data weight value according to the data lane open number, a first resistance value, and a second resistance value. The maximum accumulation weight generation array generates a maximum accumulation weight value according to the data lane open number and the first resistance value. The minimum accumulation weight generation array generates a minimum accumulation weight value according to the data lane open number and the second resistance value. The reference value generator generates a reference value according to the maximum accumulation weight value and the minimum accumulation weight value. The comparator compares the accumulation data weight value and the reference value to generate a data weight state.

Description

TECHNICAL FIELD

[0001] The present application relates to a memory device, and more particularly, to a memory device for in-memory operation. BACKGROUND

[0002] Resistive random-access memory (ReRAM) can store different data by different resistance states of a plurality of storage elements, and the resistance state of the storage element can be obtained by a reference current or voltage to identify the data stored in the memory. Currently, the reference current or voltage is usually set as a fixed value or selected from a plurality of fixed values.

[0003] However, when the number of input data channels changes, the reference current or voltage also changes. The data judgment architecture using a fixed value as the reference current or voltage will limit the memory device to operate only in a fixed number of data channels. Therefore, for the memory device with the requirement of input data channel variation, especially for the memory device for in-memory operation, the operation mode will be limited. SUMMARY

[0004] In view of the above, the present application provides a memory device for in-memory operation and a data weight state judgment method.

[0005] According to an embodiment of the present application, a memory device for in-memory operation includes a plurality of data channels, a storage cell array, a maximum accumulated weight generation array, a minimum accumulated weight generation array, a reference value generator, and a comparator. The data channels have an open number according to data input. The storage cell array is connected to the data channels and is used to generate an accumulated data weight value according to the open number of the data channels, a first resistance value, and a second resistance value, wherein the first resistance value is smaller than the second resistance value. The maximum accumulated weight generation array is connected to the data channels and is used to generate a maximum accumulated weight value according to the open number of the data channels and the first resistance value. The minimum accumulated weight generation array is connected to the data channels and is used to generate a minimum accumulated weight value according to the open number of the data channels and the second resistance value. The reference value generator is connected to the maximum accumulated weight generation array and the minimum accumulated weight generation array and is used to generate at least one reference value according to the maximum accumulated weight value and the minimum accumulated weight value. The comparator is connected to the storage cell array and the reference value generator and is used to compare the accumulated data weight value with the at least one reference value to generate and output a data weight state.

[0006] The data weight state determination method for in-memory operation according to an embodiment of the present application is suitable for a memory device including a plurality of data channels and a memory cell array. The data weight state determination method includes: generating a maximum accumulated weight value according to the number of opened data channels and a first resistance value; generating a minimum accumulated weight value according to the number of opened data channels and a second resistance value; generating at least one reference value according to the maximum accumulated weight value and the minimum accumulated weight value; and comparing the accumulated data weight of the memory cell array with the at least one reference value to generate and output a data weight state; wherein the first resistance value is smaller than the second resistance value.

[0007] Through the above structure, the memory device and the data weight state determination method for in-memory operation according to the present application can operate in various data channel opening numbers without being limited by fixed operation modes by generating upper and lower reference values according to the number of opened data channels and then generating reference values, and have high adaptability.

[0008] The present application is described in detail below with reference to the accompanying drawings and specific embodiments, but is not limited to the embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 A functional block diagram of a memory device according to an embodiment of the present application.

[0010] Figure 2 A relationship diagram of a maximum accumulated weight value, a minimum accumulated weight value, and a number of opened data channels according to an embodiment of the present application.

[0011] Figure 3 A circuit schematic diagram of a memory device according to an embodiment of the present application.

[0012] Figure 4 A circuit schematic diagram of a reference value generator of a memory device according to an embodiment of the present application.

[0013] Figure 5A A reference value distribution diagram of a memory device according to an embodiment of the present application.

[0014] Figure 5B A reference value distribution diagram of a memory device according to another embodiment of the present application.

[0015] Figure 6 A partial circuit schematic diagram of a memory device according to an embodiment of the present application.

[0016] Figure 7 A functional block diagram of a memory device according to another embodiment of the present application.

[0017] Figure 8A circuit diagram of a relative position amplifier of a memory device according to an embodiment of the present application.

[0018] Figure 9 A circuit diagram of a current-voltage conversion circuit of a memory device according to an embodiment of the present application.

[0019] Figure 10 A flowchart of a data weight state judging method according to an embodiment of the present application.

[0020] In the drawings:

[0021] 1, 1' memory device

[0022] 11 data path

[0023] 12 memory cell array

[0024] 13 maximum cumulative weight generation array

[0025] 14 minimum cumulative weight generation array

[0026] 15 reference value generator

[0027] 16 comparator

[0028] 17 relative position amplifier

[0029] 111 input terminal

[0030] 121a, 121b memory cell

[0031] 131 first resistance unit

[0032] 141 second resistance unit

[0033] 122a, 122b, 132, 142 sense amplifier

[0034] 123 switching circuit

[0035] 161a, 161b, 161c comparison element

[0036] 162 output terminal

[0037] 171a, 171b, 171c input terminal

[0038] 172a, 172b, 172c output terminal

[0039] 173a, 173b, 173c current-voltage conversion circuit

[0040] R1-R4 resistance string

[0041] M1-M8 transistors

[0042] Data<0>, Data<1>...Data <m>Data voltage

[0043] WS data weight state

[0044] ∑Wtop maximum accumulated weight

[0045] ∑Wbottom minimum accumulated weight

[0046] Vtop maximum accumulated weight value

[0047] Vbottom minimum accumulated weight value

[0048] Vweight accumulated data weight value

[0049] VDD operating voltage

[0050] Vclamp clamp voltage

[0051] I1, I2, I3, Iweight current

[0052] Ref0, Ref1, Ref2 reference value

[0053] 112, 102, 012, 002 data weight state

[0054] WS1 ~ WS4 data weight state

[0055] S1 ~ S4 step DETAILED DESCRIPTION

[0056] The detailed features and advantages of the present application are described in detail in the embodiments below, which are sufficient for anyone skilled in the art to understand the technical content of the present application and to implement it, and anyone skilled in the art can easily understand the purposes and advantages related to the present application according to the content disclosed in the specification, claims and drawings. The following examples further illustrate the concepts of the present application, but do not limit the scope of the present application in any way.

[0057] The structural principles and working principles of the present application will be described in detail below in conjunction with the accompanying drawings:

[0058] Please refer to Figure 1 , Figure 1 is a memory device 1 for in-memory operation according to an embodiment of the present application. As shown in Figure 1 As shown, the memory device 1 includes a plurality of data channels 11, a memory cell array 12, a maximum accumulation weight generation array 13, a minimum accumulation weight generation array 14, a reference value generator 15, and a comparator 16. Among them, the data channels 11 are electrically connected to the memory cell array 12, the maximum accumulation weight generation array 13, and the minimum accumulation weight generation array 14, the reference value generator 15 is electrically connected to the maximum accumulation weight generation array 13 and the minimum accumulation weight generation array 14, and the comparator 16 is electrically connected to the memory cell array 12 and the reference value generator 15.

[0059] The data channels 11 are used to receive data inputs, and have an open number according to the data inputs. Further, the data inputs can include data voltages Data<0>, Data<1>, …, Data <m>wherein the number of data voltages belonging to the high potential is the number of the opened data channels 11.

[0060] The memory cell array 12 can be a Memristor type memory, such as a ReRAM (Resistive random-access memory), a Magnetoresistive Memory, or the like, or can be implemented by a transistor's on-resistance. The memory cell array 12 includes a plurality of memory cells connected to the data channels 11, respectively, and each memory cell has a first resistance value or a second resistance value, wherein the first resistance value is smaller than the second resistance value. Further, the memory cell having the first resistance value is in a low resistance state and stores a weight 1, and the memory cell having the second resistance value is in a high resistance state and stores a weight 0. The memory cell array 12 can generate an accumulated data weight value according to the number of the opened data channels 11, the first resistance value, and the second resistance value. Further, the memory cell array 12 can include the same number of memory cells as the data channels 11, and be connected to the data channels 11 one-to-one, and when the data channels 11 are opened, the corresponding memory cells provide the stored weights (i.e., the first resistance value or the second resistance value). The memory cell array 12 can accumulate the weights provided by the memory cells corresponding to the opened data channels 11 and generate an electrical parameter (a current value or a voltage value) corresponding to the accumulated weights as the accumulated data weight value.

[0061] The maximum accumulated weight generation array 13 is configured to generate a maximum accumulated weight value according to the number of the opened data channels 11 and the first resistance value. As described above, the first resistance value corresponds to the weight 1, and the operation performed by the maximum accumulated weight generation array 13 can be regarded as accumulating the weight 1 of the number of the opened data channels 11, and generating an electrical parameter (a current value or a voltage value) corresponding to the accumulated weights as the maximum accumulated weight value. The minimum accumulated weight generation array 14 is configured to generate a minimum accumulated weight value according to the number of the opened data channels 11 and the second resistance value. As described above, the second resistance value corresponds to the weight 0, and the operation performed by the minimum accumulated weight generation array 14 can be regarded as accumulating the weight 0 of the number of the opened data channels 11, and generating an electrical parameter (a current value or a voltage value) corresponding to the accumulated weights as the minimum accumulated weight value.

[0062] The reference value generator 15 is configured to generate at least one reference value according to the maximum accumulated weight value and the minimum accumulated weight value. Further, the reference value generator 15 can generate at least one reference value between the maximum accumulated weight and the minimum accumulated weight. In particular, the number of the reference values can depend on the number of the opened data channels 11, for example, the number of the opened data channels 11 minus one.

[0063] The comparator 16 is used to compare the accumulated data weight value generated by the memory cell array 12 and the reference value generated by the reference value generator 15 to generate and output the data weight state WS. Further, when the number of reference values is one, the comparator 16 can determine whether the accumulated data weight value is greater than or less than the reference value and take the determination result as the data weight state WS, and when the number of reference values is multiple, the comparator 16 can compare the accumulated data weight value with the multiple reference values respectively to generate multiple comparison results, and the multiple comparison results constitute the data weight state WS.

[0064] Through the operation of the elements in the memory device 1, the memory device 1 can adjust the upper and lower reference values for generating the reference value according to the change of the number of open data lanes 11, thereby generating appropriate reference values. As illustrated in the accompanying drawings, please refer to Figure 2 Figure 2 The figure shows the relationship between the maximum accumulated weight value, the minimum accumulated weight value and the number of open data lanes according to an embodiment of the present application. As shown in Figure 2 For the variable resistance memory, as the number of open data lanes increases, the maximum accumulated weight ∑Wtop that each row of memory cells can have will increase, and the current value (accumulated weight current value) corresponding to the maximum accumulated weight ∑Wtop will also increase, while the minimum accumulated weight ∑Wbottom that each row of memory cells can have remains 0, but the accumulated weight current value corresponding to the minimum accumulated weight ∑Wbottom will increase.

[0065] Therefore, the fixed reference value is only suitable for the operation architecture with fixed number of open data lanes. In contrast, the memory device 1 of the present application can obtain the maximum accumulated weight value (such as the accumulated weight current value corresponding to the maximum accumulated weight ∑Wtop described above) and the minimum accumulated weight value (such as the accumulated weight current value corresponding to the minimum accumulated weight ∑Wbottom described above) as the upper and lower reference values for generating the reference value, so it can operate in various numbers of open data lanes and has high adaptability.

[0066] Further to illustrate the circuit architecture of the memory cell array 12, the maximum accumulated weight generation array 13 and the minimum accumulated weight generation array 14 of the memory device 1, please refer to Figure 3 Figure 3 The figure shows the circuit schematic diagram of the memory device according to an embodiment of the present application. As shown in Figure 3 ​​As shown, each of the data lanes 11 of the memory device 1 has an input end 111 for receiving a data input. The memory cell array 12 can include a plurality of memory cells 121a and 121b, a plurality of sense amplifiers (SAs) 122a and 122b, and a switching circuit 123. The memory cells 121a and 121b are arranged in two rows and connected to the sense amplifiers 122a and 122b, respectively, and the sense amplifiers 122a and 122b are connected to the switching circuit 123.

[0067] The memory cells 121a in the first column are connected to the data lanes 11 and configured to provide a shunt resistance according to the number of the data lanes 11 being turned on. Further, the memory cells 121a can be in a one transistor-one resistor (1T1R) structure. When a high potential signal is received by the data lanes 11 (i.e., turned on), the transistor of the memory cell 121a is enabled to allow current to flow through the resistor. The resistors in the memory cells 121a corresponding to the data lanes 11 being turned on are connected in parallel to form a shunt resistance. The sense amplifier 122a is configured to generate a first weight value according to the shunt resistance provided by the memory cells 121a in the first column. Further, the sense amplifier 122a can generate an electrical parameter (current value or voltage value) corresponding to the shunt resistance provided by the memory cells 121a in the first row as the first weight value. Similarly, the memory cells 121b in the second column are connected to the data lanes 11 and configured to provide a shunt resistance according to the number of the data lanes 11 being turned on, and the sense amplifier 122b is configured to generate a second weight value according to the shunt resistance.

[0068] The switching circuit 123 is configured to switch to obtain one of the first weight value and the second weight value as an accumulated data weight value. Further, the switching circuit 123 can include a plurality of switch elements connected between the sense amplifier 122a and the comparator 16 and between the sense amplifier 122b and the comparator 16, respectively. The switch elements can be controlled by a signal or manually to turn on the circuit between the sense amplifier 122a and the comparator 16 or the circuit between the sense amplifier 122b and the comparator 16.

[0069] Figure 3 Exemplarily, the storage cell array 12 includes two columns of storage cells and two sense amplifiers 122a and 122b, while in other embodiments, the storage cell array can include one or more than two columns of storage cells and a corresponding number of sense amplifiers. In embodiments with more than two columns of storage cells, the switching circuit can be switched to connect the comparator with the circuit of one column of storage cells to obtain the accumulated data weight value. In embodiments with one column of storage cells, the storage cell array can not be provided with the switching circuit, and the storage cells provide a shunt resistance according to the number of opened data channels, and the sense amplifier generates the accumulated data weight value according to the shunt resistance.

[0070] In Figure 3 In the embodiment, the maximum accumulated weight generation array 13 includes a plurality of first resistance units 131 and a sense amplifier 132, wherein the plurality of first resistance units 131 are connected in series with each other and connected to the sense amplifier 132. The plurality of first resistance units 131 each have a first resistance value and are respectively connected to the data channels 11, and are used to provide a shunt resistance according to the number of opened data channels 11. Further, the first resistance unit 131 can be a structure of one transistor and one resistance (1T1R), wherein the resistance has the first resistance value. As mentioned above, the first resistance value indicates a low resistance state, and the resistance with the first resistance value is referred to as a low resistance state resistance in the following. When the data channel 11 receives a high potential signal (i.e., is opened), the transistor of the first resistance unit 131 is enabled to make current flow through the low resistance state resistance. The low resistance state resistances in the first resistance units 131 corresponding to the opened data channels 11 are connected in parallel to form a shunt resistance. That is, the shunt resistance provided by the plurality of first resistance units 131 is formed by the low resistance state resistances in parallel with the number of opened data channels 11. The sense amplifier 132 is used to generate a maximum accumulated weight value according to the shunt resistance provided by the plurality of first resistance units 131. Further, the sense amplifier 132 can generate an electrical parameter (current value or voltage value) corresponding to the shunt resistance provided by the plurality of first resistance units 131 as the maximum accumulated weight value.

[0071] The minimum accumulation weight generating array 14 includes a plurality of second resistance units 141 and a sensing amplifier 142. The plurality of second resistance units 141 are connected in series with each other and connected to the sensing amplifier 142. Each of the plurality of second resistance units 141 has a second resistance value and is connected to the data channel 11, respectively, and is used to provide a shunt resistance according to the number of the data channels 11 being turned on. Further, the second resistance unit 141 can be a structure of one transistor and one resistance (1T1R), in which the resistance has the second resistance value. As mentioned above, the second resistance value indicates a high resistance state, and the resistance having the second resistance value is referred to as a high resistance state resistance in the following. When the data channel 11 receives a high potential signal (i.e., is turned on), the transistor of the second resistance unit 141 is enabled to make current flow through the high resistance state resistance. The high resistance state resistances in the second resistance units 141 corresponding to the data channels 11 being turned on are connected in parallel to form a shunt resistance. That is, the shunt resistance provided by the plurality of second resistance units 141 is formed by the high resistance state resistances corresponding to the number of the data channels being turned on connected in parallel. The sensing amplifier 142 is used to generate a minimum accumulation weight value according to the shunt resistance provided by the plurality of second resistance units 141. Further, the sensing amplifier 142 can generate an electrical parameter (a current value or a voltage value) corresponding to the shunt resistance provided by the plurality of second resistance units 141 as the minimum accumulation weight value.

[0072] The reference value generator 15 is connected to the maximum accumulation weight generating array 13 and the minimum accumulation weight generating array 14, and can generate at least one reference value according to the maximum accumulation weight value and the minimum accumulation weight value. The comparator 16 is connected to the storage unit array 12 and the reference value generator 15, and can compare the accumulation data weight value obtained from the storage unit array 12 with the at least one reference value to generate a data weight state, and output the data weight state through the output terminal 162.

[0073] Further, the circuit architecture of the reference value generator 15 is described with reference to Figure 4 , Figure 4 is a circuit schematic diagram of a reference value generator of a memory device according to an embodiment of the present application. As shown in Figure 4 As shown, the reference value generator 15 can include a plurality of resistance strings R1-R4 connected in series, and the two ends of the resistance strings R1-R4 can receive the maximum accumulated weight value Vtop and the minimum accumulated weight value Vbottom, respectively, i.e., connected to the maximum accumulated weight generating array 13 and the minimum accumulated weight generating array 14, respectively. Each two resistors in the resistance strings R1-R4 has a reference value output terminal for providing a reference value, i.e., the voltage value of the reference value output terminal. Taking the resistance strings R1-R4 including four resistors as an example, the resistance strings R1-R4 has three reference value output terminals for outputting three reference values Ref2, Refl and Ref0, respectively, and the three reference values Ref2, Refl and Ref0 can be used to distinguish four data weight states, such as 112, 102, 012 and 002.

[0074] It is particularly noted that, Figure 4 the four resistors and the three reference values generated thereby are only shown by way of example, and are not intended to limit the number of resistors included in the reference value generator 15 and the number of reference values generated thereby. In addition, Figure 4 the circuit architecture shown is applicable to the implementation in which the maximum accumulated weight value and the minimum accumulated weight value are voltage values, and for the implementation in which the maximum accumulated weight value and the minimum accumulated weight value are current values, the reference value generator 15 can further include a current-voltage conversion circuit connected between the maximum accumulated weight generating array 13 and the resistance strings, and connected between the minimum accumulated weight generating array 14 and the resistance strings, and used to convert the maximum accumulated weight value and the minimum accumulated weight value into voltage values.

[0075] Please refer to Figure 4 , Figure 5A and Figure 5B , wherein Figure 5A is a reference value distribution diagram generated by a memory device according to an embodiment of the present application, Figure 5B is a reference value distribution diagram generated by a memory device according to another embodiment of the present application. In Figure 5A the embodiment, each resistor in the resistance strings R1-R4 has the same resistance value, and thus, as shown in Figure 5A the reference values Ref2, Refl and Ref0 are evenly distributed between the maximum accumulated weight value Vtop and the minimum accumulated weight value Vbottom, i.e., the judgment intervals of the four data weight states 112, 102, 012 and 002 distinguished by the reference values Ref2, Refl and Ref0 are equal. In Figure 5B the embodiment, the number of resistors in the resistance strings R1-R4 is a multiple of 2, and the resistance values of the resistors in the resistance strings R1-R4 decrease from the two ends of the resistance strings R1-R4 to the center. For example, the resistance values of the resistors R1 and R4 are 10 times the resistance values of the resistors R2 and R3. In this way, as shown in Figure 5B As shown, the determination interval sizes of the data weight states 112, 102, 012 and 002 can be normally distributed, which is particularly suitable for artificial intelligence (AI) operations. Figure 5A and Figure 5B Two reference value distribution settings are exemplarily presented, but the present application is not limited thereto.

[0076] Further illustrating the circuit architecture of the comparator 16, please refer to Figure 6 A partial circuit schematic diagram of a memory device according to an embodiment of the present application is shown. As shown, Figure 6 The comparator 16 includes a plurality of comparison elements 161a, 161b and 161c. The number of comparison elements 161a, 161b and 161c used by the comparator 16 when performing comparison operations corresponds to the number of reference values Ref2, Ref1 and Ref0. The comparison elements 161a, 161b and 161c can compare the size of the accumulated data weight value with each reference value Ref2, Ref1 and Ref0, and can output the comparison results in digital or analog form. Taking the digital form as an example, when the accumulated data weight value is greater than the reference value Ref2, the comparison element 161a can output 1, and when the accumulated data weight value is less than the reference value Ref2, the comparison element 161a can output 0. The comparison elements 161b and 161c also have the same comparison mechanism.

[0077] The comparison results output by each of the comparison elements 161a, 161b and 161c can constitute the data weight states WS1, WS2, WS3 or WS4. Figure 6 Four data weight states WS1-WS4 corresponding to three reference values Ref2, Ref1 and Ref0 are exemplarily shown, wherein the data weight state WS1 indicates 002, the data weight state WS2 indicates 012, the data weight state WS3 indicates 102, and the data weight state WS4 indicates 112. It is particularly noted that, Figure 6 Only three reference values and four data weight states distinguished thereby are exemplarily shown, which is not intended to limit the number of reference values generated by the reference value generator 15 and the number of data weight states distinguished thereby.

[0078] Please refer to Figure 7 , Figure 7 A functional block diagram of a memory device according to another embodiment of the present application is shown. As shown, Figure 7 As shown, the memory device 1' further comprises a relative position amplifier 17 in addition to the data path 11, the memory cell array 12, the maximum accumulated weight generation array 13, the minimum accumulated weight generation array 14, the reference value generator 15 and the comparator 16 as described in the previous embodiments. The operation of the data path 11, the memory cell array 12, the maximum accumulated weight generation array 13, the minimum accumulated weight generation array 14, the reference value generator 15 and the comparator 16 is as described in the previous embodiments and will not be repeated here.

[0079] The relative position amplifier 17 has three input terminals 171a-171c connected to the memory cell array 12, the maximum accumulated weight generation array 13 and the minimum accumulated weight generation array 14 respectively. The relative position amplifier 17 is configured to amplify the voltage difference between the accumulated data weight value, the maximum accumulated weight value and the minimum accumulated weight value, and output the amplified maximum accumulated weight value and the amplified minimum accumulated weight value to the reference value generator 15 through two output terminals 172a-172b connected to the reference value generator 15 for generating one or more reference values, and output the amplified accumulated data weight value to the comparator 16 through an output terminal 172c connected to the comparator 16 for determining the data weight state WS.

[0080] Further description of the circuit architecture of the relative position amplifier 17 will be given with reference to Figure 8 and Figure 9 wherein Figure 8 is a circuit schematic diagram of the relative position amplifier of the memory device according to an embodiment of the present application, Figure 9 is a circuit schematic diagram of the current-voltage conversion circuit of the memory device according to an embodiment of the present application.

[0081] As shown in Figure 8 , the relative position amplifier 17 has three input terminals 171a-171c and three output terminals 172a-172c, and comprises three current-voltage conversion circuits 173a-173c and a plurality of transistors M1-M6. The input terminals 171a-171c are connected to the memory cell array 12, the maximum accumulated weight generation array 13 and the minimum accumulated weight generation array 14 respectively to receive the accumulated data weight value, the maximum accumulated weight value and the minimum accumulated weight value respectively. The current-voltage conversion circuits 173a-173c are connected to the input terminals 171a-171c respectively to convert the accumulated data weight value, the maximum accumulated weight value and the minimum accumulated weight value into voltage values respectively. As shown in Figure 9 As shown, the current-voltage conversion circuit 173a can include transistors M7 and M8, wherein the source of the transistor M7 is connected to the input terminal 171a for receiving the current Iweight generated by the memory cell array 12, the gate of the transistor M7 is for receiving the clamping voltage Vclamp, the drain of the transistor M7 is connected to the drain of the transistor M8, the source of the transistor M8 is for receiving the operating voltage VDD, and the gate of the transistor M8 provides a voltage value corresponding to the current Iweight as the converted accumulated data weight value Vweight. The gate of the transistor M8 is connected to the gate of the transistor Ml for providing the converted accumulated data weight value to the amplification circuit composed of the transistors Ml ~ M6 for amplification processing. Figure 8 The composition and operation mechanism of the current-voltage conversion circuits 173b and 173c are the same as those of the current-voltage conversion circuit 173a, and thus are not described herein.

[0082] In particular, the relative position amplifier 17 provided with the current-voltage conversion circuits 173a ~ 173c is applicable to the implementation in which the maximum accumulated weight value and the minimum accumulated weight value are current values, and for the implementation in which the maximum accumulated weight value and the minimum accumulated weight value are voltage values, the relative position amplifier 17 does not need to be provided with the current-voltage conversion circuits 173a ~ 173c.

[0083] In the implementation in which the maximum accumulated weight value and the minimum accumulated weight value are current values, the relative position amplifier 17 can include a first differential amplifier composed of the transistors Ml, M3, M4 and M6 for amplifying the voltage difference between the accumulated data weight value and the minimum accumulated weight value by a certain amplification factor. Figure 8 In particular, the relative position amplifier 17 provided with the current-voltage conversion circuits 173a ~ 173c is applicable to the implementation in which the maximum accumulated weight value and the minimum accumulated weight value are current values, and for the implementation in which the maximum accumulated weight value and the minimum accumulated weight value are voltage values, the relative position amplifier 17 does not need to be provided with the current-voltage conversion circuits 173a ~ 173c.

[0084] In particular, the relative position amplifier 17 provided with the current-voltage conversion circuits 173a ~ 173c is applicable to the implementation in which the maximum accumulated weight value and the minimum accumulated weight value are current values, and for the implementation in which the maximum accumulated weight value and the minimum accumulated weight value are voltage values, the relative position amplifier 17 does not need to be provided with the current-voltage conversion circuits 173a ~ 173c.

[0085] The values ​​of currents I1, I2, and I3 are expressed using formulas:

[0086] I1=A*(I weight -I bottom );

[0087] I2=A*(I top -I bottom );

[0088] I3 = I bottom ;

[0089] Among them, I weight I represents the current value corresponding to the accumulated data weight value. bottom I represents the current value corresponding to the minimum accumulated weight value. top This represents the current value corresponding to the maximum accumulated weight value, and A represents the specific amplification factor used.

[0090] Output terminals 172a to 172c are connected to the drains of transistors M1, M2, and M3, respectively, to obtain the amplified accumulated data weight value, the maximum accumulated weight value, and the minimum accumulated weight value. Output terminal 172a is connected to comparator 16 to provide the amplified accumulated data weight value to comparator 16, while output terminals 172b and 172c are connected to reference value generator 15 to provide the amplified maximum and minimum accumulated weight values ​​to reference value generator 15. The above exemplarily describes an implementation where the amplification process is performed based on the minimum accumulated weight value. In other implementations, the relative position amplifier 17 may also perform amplification based on either the maximum accumulated weight value or the accumulated data weight value.

[0091] This invention also provides a method for determining the data weight state for in-memory operations. Please refer to [link / reference]. Figure 10 , Figure 10 This is a flowchart illustrating a data weight state determination method according to an embodiment of the present invention. Figure 10 As shown, the data weight state determination method includes steps S1: generating a maximum accumulated weight value based on the number of data channels open and a first resistance value; step S2: generating a minimum accumulated weight value based on the number of data channels open and a second resistance value; step S3: generating at least one reference value based on the maximum and minimum accumulated weight values; and step S4: comparing the accumulated data weight value of the storage cell array with the at least one reference value to generate and output the data weight state. The above data weight state determination method is applicable to memory devices containing multiple data channels and a storage cell array, such as memory device 1 or 1' described in the preceding embodiments. Furthermore, step S1 can be performed by... Figure 1 The memory device 1 shown or Figure 7 The maximum accumulation weight generation array 13 of the memory device 1' shown can perform step S2, step S3 can be performed by the reference value generator 15, and step S4 can be performed by the comparator 16. The detailed operations of steps S1-S4 are as described above for the operations of the respective elements, and will not be described again here.

[0092] Through the above structure, the memory device for in-memory operation and the data weight state judgment method disclosed by the present application can operate in various data channel opening numbers without being limited by a fixed operation mode by generating upper and lower reference values following the number of data channels opened and then generating reference values, and have high adaptability.

[0093] Of course, the present application can also have other various embodiments, and those skilled in the art can make various corresponding changes and modifications according to the present application without departing from the spirit and essence of the present application. However, these corresponding changes and modifications should all belong to the protection scope of the claims attached to the present application.< / m> < / m>

Claims

1. A memory device for in-memory operations, the memory device comprising: The application relates to a data weight state generator, comprising: a plurality of data channels having an open number according to data input; a storage unit array connected to the plurality of data channels, used for generating an accumulated data weight value according to the open number, a first resistance value and a second resistance value; a maximum accumulated weight generating array connected to the plurality of data channels, and used for generating a maximum accumulated weight value according to the open number and the first resistance value; a minimum accumulated weight generating array connected to the plurality of data channels, and used for generating a minimum accumulated weight value according to the open number and the second resistance value; a reference value generator connected to the maximum accumulated weight generating array and the minimum accumulated weight generating array, and used for generating at least one reference value according to the maximum accumulated weight value and the minimum accumulated weight value; and a comparator connected to the storage unit array and the reference value generator, and used for comparing the accumulated data weight value with the at least one reference value to generate and output a data weight state. The first resistance value is smaller than the second resistance value. The maximum accumulated weight generating array comprises:

2. The memory device of claim 1, wherein, a plurality of first resistance units each having the first resistance value and connected to the plurality of data channels respectively, and used for providing a first shunt resistance according to the open number of the plurality of data channels; and a first sense amplifier connected to the plurality of first resistance units, and used for generating the maximum accumulated weight value according to the first shunt resistance. The minimum accumulated weight generating array comprises: a plurality of second resistance units each having the second resistance value and connected to the plurality of data channels respectively, and used for providing a second shunt resistance according to the open number of the plurality of data channels; and a second sense amplifier connected to the plurality of second resistance units, and used for generating the minimum accumulated weight value according to the second shunt resistance. Further comprising: a relative position amplifier having three input ends connected to the storage unit array, the maximum accumulated weight generating array and the minimum accumulated weight generating array respectively, used for amplifying a plurality of voltage differences between the accumulated data weight value, the maximum accumulated weight value and the minimum accumulated weight value, outputting the amplified maximum accumulated weight value and the minimum accumulated weight value to the reference value generator through two output ends connected to the reference value generator, and outputting the amplified accumulated data weight value to the comparator through an output end connected to the comparator. The relative position amplifier comprises:

3. The memory device of claim 1, wherein, a first differential amplifier used for amplifying a voltage difference between the accumulated data weight value and the minimum accumulated weight value by a specific multiple; and 4. The memory device of claim 3, wherein, a second differential amplifier used for amplifying a voltage difference between the maximum accumulated weight value and the minimum accumulated weight value by the specific multiple. The reference value generator comprises: a resistance string having two ends connected to the maximum accumulated weight generating array and the minimum accumulated weight generating array respectively, each two resistances in the resistance string having a reference value output end, and the reference value output end being used for providing the at least one reference value. The plurality of resistances in the resistance string have the same resistance value.

5. The memory device of claim 1, wherein, The resistance string has a resistance number being a multiple of 2, and the resistance value of the plurality of resistances in the resistance string decreases from the two ends of the resistance string to the center. The at least one reference value has a plurality of numbers, and the comparator comprises:

6. The memory device of claim 5, wherein, ​ 7. The memory device of claim 5, wherein, ​ 8. The memory device of claim 1, wherein, ​ a plurality of comparison elements respectively comparing the accumulated data weight value with the at least one reference value to generate a plurality of comparison results, wherein the plurality of comparison results constitute the data weight state.

9. The memory device of claim 1, wherein, The memory cell array includes: a plurality of first memory cells respectively connected to the plurality of data channels for providing a third shunt resistance according to the number of the plurality of data channels being turned on, and each of the plurality of first memory cells has the first resistance value or the second resistance value; a plurality of second memory cells respectively connected to the plurality of data channels for providing a fourth shunt resistance according to the number of the plurality of data channels being turned on, and each of the plurality of second memory cells has the first resistance value or the second resistance value; a third sense amplifier connected to the plurality of first memory cells and for generating a first weight value according to the third shunt resistance; a fourth sense amplifier connected to the plurality of second memory cells and for generating a second weight value according to the fourth shunt resistance; a switching circuit connected to the third sense amplifier and the fourth sense amplifier and for switching to output one of the first weight value and the second weight value as the accumulated data weight value to the comparator through an output terminal. The memory device suitable for including a plurality of data channels and a memory cell array, and includes:

10. A method for determining a data weight state for in-memory operations, the method comprising: determining a data weight state for a memory cell based on a number of times a read operation is performed on the memory cell. generating a maximum accumulated weight value according to the number of the plurality of data channels being turned on and a first resistance value; generating a minimum accumulated weight value according to the number of the plurality of data channels being turned on and a second resistance value; generating at least one reference value according to the maximum accumulated weight value and the minimum accumulated weight value; and comparing an accumulated data weight value of the memory cell array with the at least one reference value to generate and output a data weight state; wherein the first resistance value is smaller than the second resistance value. ​

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