Non-volatile memory with memory array between circuits

Abstract

The present disclosure is entitled "Non-volatile memory with memory array between circuits." An integrated memory assembly is provided that includes a memory die and a control die bonded to the memory die. The memory die includes a three-dimensional non-volatile memory structure and a first plurality of sense amplifiers. The first plurality of sense amplifiers is connected to the memory structure and positioned on a substrate of the memory die and between the memory structure and the substrate such that the memory structure is directly above the first plurality of sense amplifiers. The control die includes a second plurality of sense amplifiers connected to the memory structure. The first plurality of sense amplifiers and the second plurality of sense amplifiers are configured to perform memory operations concurrently.

Description

BACKGROUND

[0001] Semiconductor memory is widely used in various electronic devices such as cellular phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid state drives, non-mobile computing devices, and other devices. Semiconductor memory can include non-volatile memory or volatile memory. Non-volatile memory allows storage and retention of information even when not connected to a power source (e.g., a battery). One example of non-volatile memory is flash memory (e.g., NAND-type flash memory and NOR-type flash memory).

[0002] A user of a memory system including non-volatile memory can write data to the non-volatile memory and subsequently read the data. For example, a digital camera can take a photograph and store the photograph in the non-volatile memory. Subsequently, a user of the digital camera can view the photograph by causing the digital camera to read the photograph from the non-volatile memory. Performance of the memory system is important to the user. That is, the user generally does not want to wait for the memory system to write to or read from the non-volatile memory. For example, a user of a digital camera having non-volatile memory does not want to wait for a first photograph to be stored before taking other photographs. Thus, a high performance memory system utilizing non-volatile memory is desirable. BRIEF DESCRIPTION OF DRAWINGS

[0003] Like-numbered elements refer to common parts throughout the several views.

[0004] Figure 1 is a block diagram depicting one embodiment of a memory system.

[0005] Figure 2 is a block diagram of one embodiment of an integrated memory component.

[0006] Figure 3 is a block diagram of one embodiment of read / write circuitry and ECC circuitry of an integrated memory component.

[0007] Figure 4 is a block diagram depicting one embodiment of a sense block.

[0008] Figure 5 is a block diagram of a memory structure including four planes.

[0009] Figure 6 depicts a top view of a portion of a block of memory cells.

[0010] Figure 7 depicts a cross-sectional view of a portion of a block of memory cells.

[0011] Figure 8 is a cross-sectional view of a vertical column of memory cells.

[0012] Figure 9 is a cross-sectional view of one embodiment of a portion of two blocks of memory cells.

[0013] Figure 10 is a schematic diagram of a plurality of NAND strings showing a plurality of sub-blocks.

[0014] Figure 11 is a cross-sectional view of one embodiment of a portion of two blocks of memory cells.

[0015] Figure 12 is a cross-sectional view of one embodiment of a portion of two blocks of memory cells.

[0016] Figure 12A and Figure 12B is a table depicting bias voltages for top and bottom select lines.

[0017] Figure 13 is a block diagram of one embodiment of an integrated memory component.

[0018] Figure 14 is a block diagram of one embodiment of an integrated memory component.

[0019] Figure 15 depicts one embodiment of a plan view of a control die.

[0020] Figure 16 depicts one embodiment of a plan view of a memory die.

[0021] Figure 17 depicts one embodiment of a plan view of a control die.

[0022] Figure 18 depicts one embodiment of a plan view of a memory die.

[0023] Figure 19 depicts one embodiment of a side view of an integrated memory component.

[0024] Figure 20 is a block diagram of a memory structure including four planes.

[0025] Figure 21 is a block diagram of a memory structure including four planes.

[0026] Figure 22 depicts a top view of a portion of a block of memory cells.

[0027] Figure 23 depicts a top view of a portion of a block of memory cells.

[0028] Figure 24 is a flow diagram that describes one embodiment of a process for performing a memory operation.

[0029] Figure 25 is a flow diagram that describes one embodiment of a process for performing a write operation.

[0030] Figure 26 depicts a threshold voltage distribution.

[0031] Figure 27 is a table that describes one example of assigning data values to data states.

[0032] Figure 28 is a flow diagram that describes one embodiment of a process for programming non-volatile memory.

[0033] Figure 29 is a flow diagram that describes one embodiment of a process for reading non-volatile memory.

[0034] Figure 30 is a block diagram of one embodiment of an integrated memory component. DETAILED DESCRIPTION

[0035] Performance of a memory system is improved by increasing parallelism during memory operations (e.g., writes and reads). Some memory systems can include control circuitry (e.g., including sense amplifiers) on the same die as a memory array, for example, underneath the memory array. Other memory systems can include control circuitry (e.g., including sense amplifiers) on a different die than a memory array. In each case, the amount of parallelism (e.g., the amount of data that can be written or read at the same time) depends on the number of sense amplifiers. By including control circuitry (e.g., including sense amplifiers) on the same die as a memory array and on a different die than the memory array, the number of sense amplifiers can be increased. The increase in the number of sense amplifiers improves the amount of parallelism, which results in improved performance of the memory system. Additionally, the increase in the amount of parallelism can result in more efficient use of power and additional functionality.

[0036] One embodiment of a memory system presented herein includes an integrated memory component that includes a memory die and a control die bonded (or otherwise connected) to the memory die. The memory die includes a three-dimensional non-volatile memory structure and a first control circuit. The three-dimensional non-volatile memory structure (e.g., a memory array) includes a plurality of non-volatile memory cells. The first control circuit is positioned on a substrate of the memory die. The non-volatile memory cells are positioned directly above (e.g., on top of, but separated by one or more layers of non-conductive material such as a dielectric) the first control circuit. The first control circuit is connected to the memory cells of the three-dimensional non-volatile memory structure. The control die includes a second control circuit that is connected to the memory cells of the three-dimensional non-volatile memory structure. The first control circuit is configured to perform memory operations on a first subset of the non-volatile memory cells while the second control circuit is configured to perform memory operations on a second subset of the non-volatile memory cells simultaneously.

[0037] For example, in one embodiment, the first control circuit includes a first plurality of sense amplifiers connected to a first sub-block of the non-volatile memory cells and the second control circuit includes a second plurality of sense amplifiers connected to a second sub-block of the non-volatile memory cells. The first plurality of sense amplifiers and the second plurality of sense amplifiers are configured to perform memory operations on the first sub-block and the second sub-block simultaneously, where the first sub-block and the second sub-block are part of the same block of memory cells.

[0038] Figure 1 is a block diagram of one embodiment of a memory system 100 implementing the techniques described herein. In one embodiment, the memory system 100 is a solid state drive (“SSD”). The memory system 100 can also be a memory card, a USB drive, an embedded memory, a solid state drive, or other type of memory system. The techniques of the present invention are not limited to any one type of memory system. The memory system 100 is connected to a host 102’, which can be a computer, a server, an electronic device (e.g., a smartphone, a tablet, or other mobile device), an appliance, or another apparatus that uses memory and has data processing capabilities. In some embodiments, the host 102’ is separate from but connected to the memory system 100. In other embodiments, the memory system 100 is embedded within the host 102’.

[0039] Figure 1The components of the memory system 100 depicted are electronic circuits. The memory system 100 includes a memory controller 120 connected to one or more integrated memory components 130 and a local high-speed volatile memory 140 (e.g., DRAM). The one or more integrated memory components 130 each include a plurality of non-volatile memory cells. More information about the structure of each integrated memory component 130 is provided below. The controller 120 uses the local high-speed volatile memory 140 to perform certain functions. For example, the local high-speed volatile memory 140 stores logical-to-physical address translations in a table (“L2P table”).

[0040] The memory controller 120 includes a host interface 152 connected to and in communication with the host 102’. In one embodiment, the host interface 152 provides a PCIe interface. Other interfaces can also be used, such as SCSI, SATA, etc. The host interface 152 is also connected to a network-on-chip (NOC) 154. A NOC is a communication subsystem on an integrated circuit. A NOC can span synchronous and asynchronous clock domains, or use non- clocked, asynchronous logic. NOC technology applies network theory and methods to on-chip communication and results in significant improvements over conventional bus and crossbar interconnects. A NOC improves the scalability of a system-on-chip (SoC) and power efficiency of complex SoCs compared to other designs. The wires and links of a NOC are shared by many signals. Because all links in a NOC can run simultaneously on different data packets, a high degree of parallelism is achieved. Thus, as the complexity of integrated subsystems continues to grow, a NOC provides enhanced performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal lines, shared buses, or segmented buses with bridges). In other embodiments, the NOC 154 can be replaced by a bus. A processor 156, an ECC engine 158, a memory interface 160, and a DRAM controller 164 are connected to and in communication with the NOC 154. The DRAM controller 164 is used to operate and communicate with the local high-speed volatile memory 140 (e.g., DRAM). In other embodiments, the local high-speed volatile memory 140 can be SRAM or another type of volatile memory.

[0041] The ECC engine 158 performs error correction services. For example, the ECC engine 158 performs data encoding and decoding according to the implemented ECC technology. In one embodiment, the ECC engine 158 is an electronic circuit programmed by software. For example, the ECC engine 158 can be a programmable processor. In other embodiments, the ECC engine 158 is a custom, dedicated hardware circuit without any software. In another embodiment, the functions of the ECC engine 158 are implemented by the programmed processor 156.

[0042] The processor 156 performs various operations, such as programming, erasing, reading, and memory management processes. In one embodiment, the processor 156 is programmed by firmware. In other embodiments, the processor 156 is a custom, dedicated hardware circuit without any software. The processor 156 also implements a translation module, either as a software / firmware process or as a dedicated hardware circuit. In many systems, non-volatile memory is addressed inward to the storage system using physical addresses associated with one or more memory dies. However, a host system will address various memory locations using logical addresses. This enables the host to allocate data to consecutive logical addresses while the storage system is free to store the data wherever it wants among the locations of one or more memory dies. To enable this system, a controller (e.g., the translation module) performs address translations between the logical addresses used by the host and the physical addresses used by the memory dies. One example implementation is to maintain a table that identifies the current translations between logical addresses and physical addresses (i.e., the L2P table described above). An entry in the L2P table can include a logical address and an identification of the corresponding physical address. While the logical address to physical address tables (or L2P tables) include the word “table,” they need not be tables in the literal sense. Rather, the logical address to physical address tables (or L2P tables) can be any type of data structure. In some examples, the memory space of the storage system is so large that the local memory 140 cannot hold all of the L2P tables. In this case, the entire set of L2P tables is stored in the memory dies, and a subset of the L2P tables is cached (L2P cache) in the local, high-speed volatile memory 140.

[0043] The memory interface 160 communicates with one or more integrated memory components 130. In one embodiment, the memory interface 160 provides a switched mode interface. Other interfaces can also be used. In some example implementations, the memory interface 160 (or another portion of the controller 120) implements a scheduler and buffers for transmitting data to and receiving data from one or more memory dies.

[0044] Figure 2is a functional block diagram of one embodiment of an integrated memory component 130. In one embodiment, the integrated memory component 130 includes two semiconductor dies (or more simply, “dies”): a memory die 302 and a control die 304. In some embodiments, the memory die 302 and the control die 304 are directly connected or bonded together, as described in more detail below. For purposes of this document, the phrases “directly connected” and “directly bonded” mean that the memory die is connected / bonded to the control die without another die between the memory die and the control die. In this document, the term “memory die,” “memory semiconductor die,” and the like refer to a semiconductor die that includes non-volatile memory cells for storing data. In this document, the term “control die,” “control semiconductor die,” and the like refer to a semiconductor die that includes control circuitry for performing memory operations on the non-volatile memory cells on the memory die.

[0045] The memory die 302 includes a memory structure 326. The memory structure 326 includes non-volatile memory cells. In one embodiment, the memory structure 326 includes a monolithic three-dimensional memory array of non-volatile memory cells with multiple levels of memory cells formed above a single substrate such as a wafer. The memory structure can include any type of non-volatile memory formed monolithically in one or more physical layers of an array of memory cells with active regions disposed above a silicon (or other type) substrate. In one example, the non-volatile memory cells of the memory structure 326 include vertical NAND strings with charge-trapping material, such as described, for example, in U.S. Patent 9,721,662, which is incorporated by reference herein in its entirety. The NAND strings include memory cells connected by channels.

[0046] In another embodiment, the memory structure 326 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells with floating gates, such as described, for example, in U.S. Patent 9,082,502, which is incorporated by reference herein in its entirety. Other types of memory cells (e.g., NOR type flash memory) can also be used.

[0047] The exact type of memory array architecture or memory cell included in the non-volatile memory structure 326 is not limited to the examples described above. Many different types of memory array architecture or memory cell technology can be used to form the memory structure 326. The implementation of the claimed new embodiments presented herein does not require a particular non-volatile memory technology. Other examples of suitable technologies for the memory cells of the memory structure 326 include ferroelectric memory (FeRAM or FeFET), ReRAM memory, magnetoresistive memory (e.g., MRAM, spin-transfer torque MRAM, spin-orbit torque MRAM), phase change memory (e.g., PCM), etc. Examples of suitable technologies for the architecture of the memory structure 326 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, etc.

[0048] One of ordinary skill in the art will recognize that the technology described herein is not limited to a single particular memory structure, but encompasses many related memory structures within the spirit and scope of the technology described herein and as understood by one of ordinary skill in the art.

[0049] For the purposes of this document, control circuitry is circuitry used to control or manage non-volatile memory. In one embodiment, the memory die 302 includes control circuitry positioned on a silicon substrate of the memory die 302, and the non-volatile memory structure 326 is positioned directly above the control circuitry on the silicon substrate of the memory die 302. Thus, the control circuitry on the silicon substrate of the memory die 302 is referred to as being below the memory array. In one embodiment, the control circuitry on the silicon substrate of the memory die 302 includes read / write circuits 340 and control circuitry 342, both of which are described in greater detail below.

[0050] The control die 304 includes control circuitry 310 positioned on a silicon substrate of the control die 304. In one embodiment, the control circuitry 310 is an example of control circuitry for the memory structure 326. The control circuitry 310 includes a set of circuits that perform memory operations (e.g., program, read, erase, etc.) on the memory structure 326. In some embodiments, “write” refers to program. In some embodiments, “write” also refers to erase. Some embodiments utilize the concept of write without reference to program and erase.

[0051] The control circuit 310 includes a state machine 312, an on-chip address decoder 314, a power control circuit 316, a memory array 318, read / write circuits 328, an ECC engine 330, a memory controller interface 332, and a memory die interface 340. The state machine 312 is a circuit that controls operation of the operations performed by the control die 304. In some embodiments, the state machine 312 is implemented by or replaced with a microprocessor, microcontroller, and / or RISC processor. The memory array 318 can be a volatile memory used to store software for programming a processor (e.g., a RISC processor used to implement or replace the state machine 312) and for storing data (e.g., data and operational parameters for the decoding and encoding processes). In one embodiment, the memory array 318 is implemented with SRAM or DRAM.

[0052] The on-chip address decoder 314 provides an address interface between the addresses used by the host 120 or the memory controller 120 and the hardware addresses used by the row and column decoders (not explicitly shown in Figure 2 The power control circuit 316 controls the power and voltages provided to the word lines, bit lines, and select lines during memory operations. In one embodiment, the power control circuit 316 includes voltage circuits. The power control circuit 316 can include charge pumps, high voltage pumps, or other voltage sources for generating voltages. The power control circuit 316 is controlled by the state machine 312.

[0053] The read / write circuits 328 include sense blocks, which can contain sense amplifiers. The sense amplifiers include bit line drivers. The read / write circuits 328 are controlled by the state machine 312. Each memory structure 326 can be addressed by a word line through a row decoder (not shown in Figure 2 and by a bit line through a column decoder (not shown in Figure 2

[0054] The error correction code (ECC) engine 330 is a circuit configured to decode and correct codewords. In this document, the ECC engine 330 can be referred to as an on-die ECC engine. In one embodiment, the on-die ECC engine 330 is configured to encode data bits from the memory controller 120 into codewords containing the data bits and parity bits. The control circuit stores the codewords in the memory structure 326. In one embodiment, the on-die ECC engine 330 is also configured to decode codewords read from the memory structure 326. In some embodiments, if the on-die ECC engine 330 successfully decodes a codeword, the control die 304 only sends the data bits back to the memory controller 120. In some embodiments, if the on-die ECC engine 330 does not successfully decode a codeword, the ECC engine of the memory controller can be used to decode the codeword.

[0055] ​In one embodiment, all or a subset of the circuitry of the control circuit 310 (individually or collectively) can be considered a control circuit. The control circuit can include only hardware (e.g., circuitry) or a combination of hardware and software, including firmware. For example, a controller programmed by firmware is one example of a control circuit. The control circuit can include a processor, a PGA (programmable gate array), an FPGA (field programmable gate array), an ASIC (application specific integrated circuit), a microcontroller, an integrated circuit, or other types of circuitry.

[0056] The memory interface 340 is an electrical interface between the control die 304 and the memory die 302 employing the vias 344. The vias 344 are pathways between one or more components in the control circuit 310 and components on the memory die 302 (e.g., the memory structure 326, the read / write circuit 340, and the control circuit 342). A portion of each via resides in the memory die 302 and a portion of each via resides in the control die 304. The term “via” can be used for a portion of a via 344 that is entirely within one of the dies. Thus, it can be said that the memory die 302 has a first plurality of vias and the control die 304 has a second plurality of vias such that the first plurality of vias directly connect to the second plurality of vias (e.g., without intervening vias). In one embodiment, the control die 304 and the memory die 302 are configured to transmit signals over pairs of vias of the first plurality of vias and the second plurality of vias. In some embodiments, the memory die 302 and the control die 304 are bonded to or otherwise attached to each other to facilitate the transfer of signals over the pairs of vias.

[0057] A via can be used to provide or receive a signal (e.g., a voltage, a current). A via includes an electrically conductive path. A via can include one or more of a bond pad, a metal interconnect, a via, a transistor, an electrically conductive material, and other materials that can transmit or carry an electrical signal. In one embodiment, the vias 344 allow the control circuit 310 to provide voltages to word lines, select lines, and bit lines on the memory die 302. The vias 344 can be used to receive signals from, for example, bit lines. In one embodiment, there are approximately 100,000 vias 344. However, there can be more or fewer than 100,000 vias. Having such a large number of vias 344 allows a very large amount of data or other signals to be transferred in parallel.

[0058] The memory controller interface is an electrical interface for communicating with the memory controller 120. For example, the memory controller interface can implement a switched mode interface that connects to the memory controller 120. The memory interface 340 is significantly wider than the memory controller interface because the memory interface 340 has significantly more signals than the memory controller interface. Thus, the memory interface 340 can send more data in parallel compared to the memory controller interface. In some examples, the memory interface 340 is 4, 10, 20, or 50 times wider than the memory controller interface.

[0059] For generality, the communication channel 336 is depicted as connecting to the integrated memory component 130. The communication channel 336 can connect to either or both of the dies 302 and / or 304. In one embodiment, the communication channel 336 connects the memory controller 120 directly to the control die 304. In one embodiment, the communication channel 336 connects the memory controller 120 directly to the memory die 302. If the communication channel 336 connects the memory controller 120 directly to the memory die 302, then the pass-through 344 can be used to allow communication between the memory controller 120 and the control circuit 310.

[0060] Although Figure 2 One control die 304 and one memory die 302 in the integrated memory component 130 are depicted, there can be more than one control die 304 and more than one memory die 302 in the integrated memory component 130.

[0061] Figure 3 is a block diagram of one embodiment of the read / write circuit 328 and the ECC engine 330 of the control die 304. The read / write circuit 328 has a sense amplifier 350 and a latch 352. The latch 352 can include a data latch 354a and a parity latch 354b. In one embodiment, the data latch 354a stores the data bits of a codeword, and the parity latch stores the parity bits of the codeword. It is not required that there be specific latches for data bits and for parity bits. Figure 3 Four sets of data latches 354(1), 354(2), 354(3), 354(4) are depicted. Each set can be used to store codewords for a different page. In embodiments where each memory cell stores four bits, four pages are stored in a set of memory cells. These four pages can be referred to as a lower page (LP), a lower middle page (LMP), an upper middle page (UMP), and an upper page (UP). In embodiments where each memory cell stores three bits, three pages are stored in a set of memory cells, and these four pages can be referred to as a lower page (LP), a middle page (MP), and an upper page (UP).

[0062] The on-die ECC engine 330 can encode data bits received from the memory controller 120. In one embodiment, the on-die ECC engine 330 forms codewords, each containing data bits and parity bits. In one embodiment, the memory controller 120 provides these codewords to the control die 304. The control circuit 310 stores these codewords into non-volatile memory cells in the memory structure 326. When the memory controller 120 requests to read data, the control circuit 310 reads the codewords from the memory structure 326. The on-die ECC engine 330 can also decode and correct errors for the codewords read from the memory structure 326. In some embodiments, the on-die ECC engine 330 computes parity bits for each data unit (e.g., page) stored. The parity bits (also referred to as error correction code or error correction information) can be stored with the data unit (e.g., page). The combination of a data unit and its associated parity bits is referred to as a codeword. In one embodiment, the parity bits are stored away from the data unit (e.g., page).

[0063] In one embodiment, when a codeword is successfully decoded, the control die 304 sends only the data bits, but not the parity bits, to the memory controller 120. Thus, bandwidth on the communication lines between the memory controller 120 and the integrated memory component 130 is saved. In addition, a significant amount of power can be saved. For example, the interface between the control die and the controller can be a high-speed interface.

[0064] The on-die ECC engine 330 includes a syndrome computation logic 356, an encoder 358, and a decoder 394. The encoder 358 is configured to encode data using an ECC scheme, such as a low-density parity-check (LDPC) encoder, a Reed-Solomon encoder, a Bose-Chaudhuri-Hocquenghem (BCH) encoder, a Turbo code encoder, an encoder configured to encode one or more other ECC encoding schemes, or any combination thereof. The encoder 358 can form a codeword containing data bits 360 and parity bits 362. The data bits can be provided by the memory controller 120.

[0065] Based on the bits in the latches 352, the sense amplifier 350 can control the bit line voltage in the memory structure 326 when a non-volatile memory cell is being programmed / written. In this way, a codeword can be programmed into a non-volatile memory cell in the memory structure 326. It should be appreciated that other voltages can also be applied to the memory structure 326, such as a program voltage applied to a memory cell selected for programming, which is implemented by the control die 304 applying program and boost voltages to various word lines of the memory structure 326 through voltage generators on the control die 304.

[0066] The decoder 364 is configured to decode codewords stored in the memory die 302. In one embodiment, the sense amplifier 350 senses a bit line in the memory structure 326 in order to read a codeword. The sense amplifier 350 can store the read codeword into a latch 352. The decoder 364 is capable of detecting and correcting errors in the codeword. In one embodiment, the decoder 364 is a relatively lower power decoder compared to the decoder on the memory controller 120. In one embodiment, the decoder on the memory controller 120 is capable of correcting more bit errors in a codeword compared to the bit errors that can be corrected by the decoder 364. Thus, the decoder 364 can trade off between power and error correction capability. For example, the decoder 364 can be very efficient in terms of power consumption, but at the cost of possibly not being able to correct a large number of errors in a codeword.

[0067] In some embodiments, the decoder 364 is based on a sparse bipartite graph with bit (or variable) nodes and check nodes. The decoder 364 can pass messages between the bit nodes and the check nodes. The messages are passed between the bit nodes and the check nodes by performing message passing computations. The message passing computations can be based on belief propagation.

[0068] The syndrome computation logic 356 (e.g., circuitry and / or software) is capable of determining a syndrome weight of a codeword. The syndrome weight refers to the number of parity check equations that are not satisfied. The initial syndrome weight of a codeword can be associated with a bit error rate (BER) of the codeword. Thus, the control die 304 can estimate the BER of a codeword based on the initial syndrome weight. In one embodiment, the syndrome logic is implemented in hardware. The syndrome weight can be determined without fully decoding the codeword. Thus, the initial syndrome weight can be computed in less time and less power than decoding the codeword. In some embodiments, the control die 304 makes management decisions based on the estimated BER. For example, the control die 304 can determine which technique should be employed to decode a codeword, which read reference voltage should be employed to read a memory cell, etc. based on the estimated BER.

[0069] Figure 4 is a block diagram depicting one embodiment of a sense block 370 that is part of the read / write circuitry 328. A single sense block 450 is divided into one or more core portions, referred to as sense circuits or sense amplifiers 350(1) - 350(4), and a common portion, referred to as management circuitry 371. In one embodiment, there will be a separate sense circuit for each bit line / NAND string and common management circuitry 371 for a group of multiple (e.g., four or eight) sense circuits. Each sense circuit in a group of sense circuits communicates with the associated management circuitry via a data bus 372. Thus, there is one or more management circuits in communication with a group of sense circuits of storage elements (memory cells).

[0070] As one example, sense amplifier 350(1) includes a sense circuit 373 that senses by determining whether the conduction current in the connected bit line is above or below a predetermined threshold level. The sensing can occur in a read or verify operation. The sense circuit also supplies the bit line voltage during the application of a program voltage in a program operation (e.g., a write operation).

[0071] Sense circuit 373 can include a Vbl selector 374, a sense node 375, a comparison circuit 376, and a trip latch 377. Vbl selector 374 can pass either a program enable voltage (e.g., V_pgm_enable) or a program inhibit voltage (e.g., Vbl_inh) to the bit line connected to the memory cell during the application of a program voltage. Vbl selector 374 can also be used during a sense operation. In this document, a "program enable voltage" is defined as a voltage applied to a bit line coupled to a memory cell that enables programming of the memory cell while a program voltage (e.g., Vpgm) is also applied to the memory cell. In certain embodiments, the program enable voltage is applied to the bit line coupled to the memory cell while the program voltage is applied to the control gate of the memory cell. In this document, a "program inhibit voltage" is defined as a voltage applied to a bit line coupled to a memory cell to inhibit programming of the memory cell while a program voltage (e.g., Vpgm) is also applied to the memory cell (e.g., to the control gate of the memory cell). Note that a pass voltage (e.g., Vpass) can be applied to unselected word lines along with the program inhibit voltage applied to the bit line. The bit line is part of the memory structure 326 on the memory die 302.

[0072] A program inhibit voltage is applied to bit lines coupled to memory cells that are not to be programmed and / or to bit lines having memory cells that have reached their respective target threshold voltages through execution of a program process. These bit lines can be referred to as "unselected bit lines." A program inhibit voltage is not applied to bit lines having memory cells that are to be programmed ("selected bit lines"). In one embodiment, when a program inhibit voltage is applied to an unselected bit line, the bit line is cut off from the NAND channel. Thus, in one embodiment, the program inhibit voltage is not passed to the NAND channel. A pass voltage is applied to unselected word lines to raise the potential of the NAND channel, which inhibits programming of memory cells that receive a program voltage at their control gates.

[0073] By setting the control gate voltage of the transistor 380 high enough (e.g., higher than Vbl delivered from the Vbl selector), the transistor (e.g., nMOS) can be configured to pass through the gate of Vbl from the Vbl selector 374. For example, the selector 379 can deliver a supply voltage Vdd (e.g., 3-4V) to the control gate of the transistor 380.

[0074] The sense amplifier 350(1) is configured to control the timing of when a voltage is applied to the bit line. During a sensing operation, such as a read and verify operation, the transistor 380 sets the bit line voltage based on the voltage delivered by the selector 379. The bit line voltage is approximately equal to the control gate voltage of the transistor minus its Vt (e.g., 3V). For example, if the selector 379 delivered Vbl + Vt, then the bit line voltage would be Vbl. This assumes the source line is 0V. The transistor 380 clamps the bit line voltage according to the control gate voltage and acts as a source follower rather than a pass gate. The Vbl selector 374 can deliver a relatively high voltage, such as Vdd, which is higher than the control gate voltage on the transistor 380 to provide a source follower mode. Thus, during sensing, the transistor 380 charges the bit line.

[0075] In one approach, the selector 379 of each sense amplifier can be controlled separately from the selectors of the other sense amplifiers to deliver Vbl or Vdd. The Vbl selector 462 of each sense amplifier can also be controlled separately from the Vbl selectors of the other sense amplifiers.

[0076] During sensing, the sense node 375 is charged to an initial voltage, such as Vsense init = 3V. The sense node is then connected to the bit line through the transistor 380, and the amount of decay of the sense node is used to determine whether the memory cell is in a conductive state or a non-conductive state. In one embodiment, the current flowing in the bit line discharges the sense node (e.g., sense capacitor). The length of time the sense node is allowed to decay can be referred to herein as the “accumulation time.” The comparison circuit 466 is used to compare the sense node voltage to a trip voltage at the time of sensing. If the sense node voltage decays below the trip voltage Vtrip, then the memory cell is in a conductive state and its Vt is equal to or lower than the voltage of the verify signal. If the sense node voltage does not decay below Vtrip, then the memory cell is in a non-conductive state and its Vt is higher than the voltage of the verify signal. The sense amplifier 350(1) includes a trip latch 468 that is set by the comparison circuit 466 based on whether the memory cell is in a conductive state or a non-conductive state. The data in the trip latch can be the bit that is read by the processor 381.

[0077] The management circuit 371 includes a processor 381, four sets of exemplary data latches 382, 383, 384, 385, and an I / O interface 387 coupled between the four sets of data latches and a data bus 332 (which can be connected to the memory controller 120). One set of data latches can be provided for each sense amplifier, e.g., including individual latches LDL, LMDL, UMDL, and UDL. In some cases, fewer or more data latches can be used. LDL stores bits for lower page data, LMDL stores bits for middle lower page data, UMDL stores bits for middle upper page data, and UDL stores bits for upper page data. This is in a memory device that is sixteen levels or four bits per memory cell. In one embodiment, each memory cell has eight levels or three bits, and thus each sense amplifier has only three latches (LDL, MDL, UDL).

[0078] The processor 381 performs computations in order to determine the data stored in the sensed memory cell and to store the determined data in the set of data latches. Each set of data latches 382-385 is used to store data bits determined by the processor 381 during a read operation and to store data bits imported from the data bus 332 during a program operation, which represent the write data to be programmed into the memory. The I / O interface provides an interface between the data latches 382-385 and the data bus 332.

[0079] The processor 381 can also be used to determine how much voltage to apply to the bit line based on the state of the latches.

[0080] During a read, the operation of the system is controlled by the state machine 312, which controls the different control gate voltages provided to the addressed memory cell (e.g., by applying the voltages from the power control circuit 316 to the word lines on the memory structure 326 via the passageway between the control die 304 and the memory die 302 described herein). As it steps through the various predefined control gate voltages corresponding to the various memory states supported by the memory, the sense circuit can trip at one of these voltages, and the corresponding output will be provided from the sense circuit to the processor via the data bus 454. At this point, the processor determines the resulting memory state by considering the trip event of the sense circuit and the information about the control gate voltage applied from the state machine via the input line 490. It then computes the binary encoding of the memory state, and stores the resulting data bits into the data latches 484-487.

[0081] Some implementations can include multiple processors 381. In one embodiment, each processor 381 will include an output line (not shown) such that each output line is wired or wired together. In some embodiments, the output line is inverted before being connected to the line or line. This configuration enables a quick determination of when the programming process is complete during a program verify test, as the receiving line or state machine can determine when all programmed bits have reached the desired level. For example, when each bit reaches its required level, the logical zero for that bit will be sent to the line or line (or data one is inverted). When all bits output data 0 (or data one is inverted), the state machine knows to terminate the programming process. Because (in one embodiment) each processor communicates with four sense amplifiers, the state machine needs to read the line or line four times, or add logic to the processor 381 to accumulate the results of the associated bit lines such that the state machine only needs to read the line or line once. Similarly, by properly selecting the logic levels, the global state machine can detect when the first bit changes its state and change the algorithm accordingly.

[0082] During a program or verify operation of the memory cells, data to be programmed (write data) is stored from the data bus 332 into the set of data latches 382-385, in the LDL, LMDL, UMDL, and UDL latches in implementations with four bits per memory cell.

[0083] Under the control of the state machine, the program operation applies a set of program voltage pulses to the control gate of the addressed memory cell. The magnitude of each voltage pulse can be stepped up by one step from the previous program pulse in a process known as incremental step pulse programming. Each program voltage is followed by a verify operation to determine whether the memory cell has been programmed to the desired memory state. In some cases, the processor 381 monitors the read-back memory state relative to the desired memory state. When the two are in agreement, the processor 381 sets the bit line to a program inhibit mode, such as by updating its latches. This inhibits the further programming of the memory cell coupled to the bit line even if additional program pulses are applied to its control gate.

[0084] Each set of data latches 382-385 can be implemented as a stack of data latches for each sense amplifier. In one embodiment, each sense amplifier 350 has three data latches. In some implementations, the data latches are implemented as shift registers so that the parallel data stored therein is converted to serial data for the data bus 332 and vice versa. All of the data latches corresponding to a read / write block of memory cells can be connected together to form a block shift register so that a block of data can be input or output by serial transfer. Specifically, the read / write circuit module set is adjusted so that its set of data latches will shift data in or out of the data bus in sequence as if they were part of a shift register for the entire read / write block.

[0085] Data latches identify when the associated memory cell reaches certain milestones of a program operation. For example, a latch can identify when the Vt of a memory cell is below a particular verify voltage. Data latches indicate whether the memory cell currently stores one or more bits from a page of data. For example, an LDL latch can be used to store lower page data. The LDL latch is flipped (e.g., from 0 to 1) when a lower page bit is stored in the associated memory cell. The LMDL, UMDL, or UDL latches are flipped when a middle lower, middle upper, or upper page bit is stored in the associated memory cell, respectively. This occurs when the associated memory cell completes programming.

[0086] In one embodiment, the memory structure 326 includes a plurality of non-volatile memory cells arranged as vertical NAND strings. For example, the memory structure can include a stack of alternating dielectric layers and conductive layers, with memory holes formed in the stack. The NAND strings are formed by filling the memory holes with material that includes charge-trapping material to form a vertical column of memory cells. Each memory cell can store one or more bits of data. More details are provided below in connection with Figure 4 to Figure 12 More details are provided of a three-dimensional monolithic memory array that includes the memory structure 326.

[0087] Figure 5 is a block diagram illustrating one example organization of the memory structure 326, which is divided into four planes P0, PI, P2, and P3. Each plane is then divided into M blocks. In one example, each plane has about 2000 blocks. However, different numbers of blocks and planes can also be used. In one embodiment, the blocks of memory cells are the erase unit. That is, all of the memory cells of one block are erased together. Thus, a block can also be referred to as an erase block. In other embodiments, the memory cells can be grouped into blocks for other reasons, in order to organize the memory structure 326 to enable signaling and selection circuitry. In some embodiments, a block represents a group of connected memory cells, as the memory cells of a block share a common set of word lines.

[0088] Figure 6 to Figure 9 An example three-dimensional (“3D”) NAND structure that can be used to implement the memory structure 326 is depicted. Figure 6 is a block diagram depicting a top view of a portion of one block from the memory structure 326. Figure 6 The portion of the depicted block corresponds to Figure 5 portion 401 in block 2 of Figure 6 As can be seen in Figure 6 The depicted block extends in the direction of 431. In one embodiment, the memory array has many layers; however, Figure 6 only the top layer is shown.

[0089] Figure 6 A plurality of circles representing vertical columns are depicted. Each of the vertical columns includes a plurality of select transistors (also referred to as select gates or select gates) and a plurality of memory cells. In one embodiment, each vertical column implements one NAND string. For example, Figure 6 Vertical columns 422, 432, 442, and 452 are depicted. Vertical column 422 implements NAND string 482. Vertical column 432 implements NAND string 484. Vertical column 442 implements NAND string 486. Vertical column 452 implements NAND string 488. More details of the vertical columns are provided below. As Figure 6 The depicted block extends in the direction of arrow 431, so the block includes more vertical columns than Figure 6 More vertical columns are depicted.

[0090] Figure 6 A set of bit lines 415, including bit lines 411, 412, 413, 414,..., 419, is also depicted. Figure 6 Twenty-four bit lines are shown, as only a portion of the block is depicted. It is contemplated that more than twenty-four bit lines are connected to the vertical columns of the block. Some of the circles representing the vertical columns have an "x" in them to indicate that they are connected to a bit line. For example, bit line 414 is connected to vertical columns 422 and 432. Figure 6 The depicted block includes a set of full slits 402 and 410 that are etched from the top of the vertical columns to the bottom of the vertical columns and filled with oxide. Partial slits 404, 406, and 408 are etched through the top of the layer to divide the select lines (as described below) in order to divide each layer of the block into four regions (420, 430, 440, 450), which are referred to as sub-blocks (discussed in more detail below). In one example embodiment, a bit line is connected to (at most) one vertical column in each of the sub-blocks 420, 430, 440, and 450. In this embodiment, each block has sixteen rows of active columns, and each bit line is connected to two rows in each block. In one embodiment, all two rows connected to a common bit line are connected to the same word line, but to different select lines; thus, the system uses source-side select lines and drain-side select lines to select one (or another subset) of the four to perform a memory operation on. Although Figure 6 Four rows of vertical columns are shown for each region, four regions and sixteen rows of vertical columns in one block, but these exact numbers are example embodiments. Other embodiments can include more or fewer regions per block, more or fewer rows of vertical columns per region, and more or fewer rows of vertical columns per block. Figure 6It is also shown that the vertical columns are staggered. In other embodiments, different staggering patterns can be used. In some embodiments, the vertical columns are not staggered.

[0091] Figure 7 A portion of one embodiment of a three-dimensional memory structure 326 is depicted, showing a cross-sectional view along line AA of Figure 6 . The cross-sectional view is through vertical columns 432, 434 and region / sub-block 430 (see Figure 6 ). Figure 7 The structure includes: four top side select layers TSGL0, TSGL1, TSGL2, and TSGL3; four bottom side select layers BSGL0, BSGL1, BSGL2, and BSGL3; six dummy word line layers DD0, DD1, DS0, DS1, WLDL, WLDU; and ninety-six data word line layers WLL0 through WLL95, which are used to connect to data memory cells. Other embodiments can implement more or less than four top side select layers, more or less than four bottom side select layers, more or less than six dummy word line layers, and more or less than ninety-six word line layers. Vertical columns 432, 434 are depicted as protruding through the top side select layers, the source side select layers, the dummy word line layers, and the word line layers. In one embodiment, each vertical column includes a vertical NAND string. For example, vertical column 432 includes NAND string 484. Directly below the vertical columns and the following layers is control circuitry (not shown in Figure 7 ), and directly below the control circuitry is a substrate (not shown). For the purposes of this document, the phrase “directly below” means below and not sideways. The NAND string of vertical column 432 has a source end at the bottom of the stack and a drain end at the top of the stack. Consistent with Figure 6 , Figure 6 Vertical column 432 is shown connected to bit line 414 via connector 417. Local interconnects are also depicted.

[0092] For ease of reference, top side select layers TSGL0, TSGL1, TSGL2, and TSGL3; bottom side select layers BSGL0, BSGL1, BSGL2, and BSGL3; dummy word line layers DD0, DD1, DS0, DS1, WLDL, and WLDU; and word line layers WLL0 through WLL95 are collectively referred to as conductive layers. In one embodiment, the conductive layers are made of a combination of TiN and tungsten. In other embodiments, other materials can be used to form the conductive layers, such as doped polysilicon, metals such as tungsten or metal silicides. In some embodiments, different conductive layers can be formed of different materials. Between the conductive layers are dielectric layers DL0 through DL111. For example, dielectric layer DL104 is above word line layer WLL94 and below word line layer WLL95. In one embodiment, the dielectric layers are made of SiO2. In other embodiments, other dielectric materials can be used to form the dielectric layers.

[0093] Non-volatile memory cells are formed along vertical columns that extend through the alternating conductive layers and dielectric layers in the stack. In one embodiment, the memory cells are arranged in NAND strings. Word line layers WLL0 through WLL95 are connected to memory cells (also referred to as data memory cells). Dummy word line layers DD0, DD1, DS0, DS1, WLDL, and WLDU are connected to dummy memory cells. Dummy memory cells do not store host data and are not eligible to store host data (data provided from a host, such as data from a host user), while data memory cells are eligible to store host data. In some embodiments, data memory cells and dummy memory cells can have the same structure. Dummy word lines are connected to dummy memory cells. Top side select layers TSGL0, TSGL1, TSGL2, and TSGL3 are used to electrically connect and disconnect NAND strings to bit lines or source lines (as described below). Bottom side select layers BSGL0, BSGL1, BSGL2, and BSGL3 are used to electrically connect and disconnect NAND strings to source lines or bit lines (as described below).

[0094] Figure 7 A junction region is also shown. In one embodiment, etching ninety-six word line layers intermixed with dielectric layers is expensive and / or challenging. To mitigate this burden, one embodiment includes laying down a first stack of forty-eight word line layers alternating with dielectric layers, laying down a junction region, and laying down a second stack of forty-eight word line layers alternating with dielectric layers. The junction region is positioned between the first stack and the second stack. The junction region is used to connect the first stack to the second stack. In one embodiment, the junction region is a conductive layer. In other embodiments, the junction region can be a dielectric layer. In some embodiments, the junction region can be a combination of a conductive layer and a dielectric layer. Figure 7In this context, the first stack is labeled "lower set of word lines," and the second stack is labeled "upper set of word lines." In one embodiment, the bonding region is made of the same material as the word line layers. In a set of exemplary embodiments, multiple word lines (control lines) include a first stack of alternating word line layers and dielectric layers, a second stack of alternating word line layers and dielectric layers, and a bonding region between the first and second stacks, as shown below. Figure 7 What is depicted.

[0095] Figure 8 A portion of the vertical column 432 (memory holes) is depicted. Figure 7 A cross-sectional view of the area indicated by the dashed line. In one embodiment, the vertical column is circular; however, other shapes may be used in other embodiments. In one embodiment, the vertical column 432 includes an inner core layer 470 made of a dielectric such as SiO2. Other materials may also be used. Surrounding the inner core 470 is a polysilicon channel 471. Materials other than polysilicon may also be used. Note that the channel 471 connects to the bit line and the source line. Surrounding the channel 471 is a tunneling dielectric 472. In one embodiment, the tunneling dielectric 472 has an ONO structure. Surrounding the tunneling dielectric 472 is a charge trapping layer 473, such as, for example, silicon nitride. Other memory materials and structures may also be used. The techniques described herein are not limited to any particular material or structure.

[0096] Figure 8 Dielectric layers DLL105, DLL104, DLL103, DLL102, and DLL101, and word line layers WLL95, WLL94, WLL93, WLL92, and WLL91 are depicted. Each word line layer includes a word line region 476 surrounded by an aluminum oxide layer 477, which is surrounded by a barrier oxide layer 478. In other embodiments, the barrier oxide layer may be a vertical layer parallel to and adjacent to the charge trapping layer 473. The physical interaction between the word line layers and the vertical column forms a memory cell. Thus, in one embodiment, the memory cell includes a channel 471, a tunneling dielectric 472, a charge trapping layer 473, a barrier oxide layer 478, an aluminum oxide layer 477, and a word line region 476. For example, word line layer WLL95 and a portion of vertical column 432 constitute memory cell MC1. Word line layer WLL94 and a portion of vertical column 432 constitute memory cell MC2. A portion of word line layer WLL93 and vertical column 432 constitutes memory cell MC3. A portion of word line layer WLL92 and vertical column 432 constitutes memory cell MC4. A portion of word line layer WLL91 and vertical column 432 constitutes memory cell MC5. In other architectures, memory cells may have different structures; however, a memory cell will still be a storage cell.

[0097] When a memory cell is programmed, electrons are stored in a portion of the charge trapping layer 473 associated with the memory cell. In response to an appropriate voltage on the word line region 476, these electrons are attracted from the channel 471 into the charge trapping layer 473 through the tunneling dielectric 472. The threshold voltage (Vth) of the memory cell increases in proportion to the amount of charge stored. In one embodiment, programming is accomplished by Fowler-Nordheim tunneling of electrons into the charge trapping layer. During an erase operation, electrons return to the channel or holes are injected into the charge trapping layer to recombine with the electrons. In one embodiment, erase is accomplished using hole injection into the charge trapping layer via a physical mechanism such as gate-induced drain leakage (GIDL).

[0098] As described above, the integrated memory component includes a first control circuit on the memory die (underneath the memory structure 326) and a second control circuit on the control die, such that the first control circuit is configured to perform a memory operation on a first subset of non-volatile memory cells (e.g., a first sub-block), while the second control circuit is configured to perform the same memory operation on a second subset of non-volatile memory cells (e.g., a second sub-block of the same block) at the same time. Figure 9 is a cross-sectional view of one embodiment of a portion of two blocks (block N and block N+1) of memory cells of the memory structure 326 that better explains how the various memory holes / NAND strings are connected to bit lines and source lines to enable the first control circuit to perform a memory operation on a first subset of non-volatile memory cells while the second control circuit performs the same memory operation on a second subset of non-volatile memory cells at the same time. In one embodiment, each block is divided into four sub-blocks SB0, SB1, SB2, and SB3. Sub-block SB0 corresponds to those vertical NAND strings controlled by TSGL0 and BSGL0, sub-block SB1 corresponds to those vertical NAND strings controlled by TSGL1 and BSGL1, sub-block SB2 corresponds to those vertical NAND strings controlled by TSGL2 and BSGL2, and sub-block SB3 corresponds to those vertical NAND strings controlled by TSGL3 and BSGL3. For illustrative purposes, and to make the drawing easier to read, Figure 9 two memory holes / NAND strings for each sub-block (SB0, SB1, SB2, SB3) of block N and block N+1 are shown; however, in most embodiments, each sub-block will include more than two memory holes / NAND strings.

[0099] The memory structure 326 includes bit lines above and below the memory structure 326. For example, bit line Top BLn and bit line Top BLn+1 are above the memory structure 326, while bit line Bottom BLn and bit line Bottom BLn+1 are below the memory structure 326. It is contemplated that there will be more than two bit lines above the memory structure 326 and more than two bit lines below the memory structure 326; however, Figure 9 Only two are shown to make the drawing easier to read. In one embodiment, the top bit lines are connected to the control circuitry (including sense amplifiers) of the control die 304 (CCAA), and the bottom bit lines are connected to the control circuitry (including sense amplifiers) of the memory die 302 (CCUA). In Figure 9 In the depicted implementation, the NAND strings of sub-blocks SB0 and SB1 are connected to bit lines above the memory structure, and thus to the sense amplifiers of the control die 304 (CCAA), while the NAND strings of sub-blocks SB2, SB3 are connected to bit lines below the memory structure, and thus to the sense amplifiers of the memory die 302 (CCUA). For example, NAND string a of sub-block SB0 is connected to Top BLn, NAND string b of sub-block SB0 is connected to Top BLn+1, NAND string c of sub-block SB1 is connected to Top BLn, NAND string d of sub-block SB1 is connected to Top BLn+1, NAND string e of sub-block SB2 is connected to Bottom BLn, NAND string f of sub-block SB2 is connected to Bottom BLn+1, NAND string g of sub-block SB3 is connected to Bottom BLn, NAND string h of sub-block SB3 is connected to Bottom BLn+1, NAND string i of sub-block SB0 is connected to Top BLn, NAND string j of sub-block SB0 is connected to Top BLn+1, NAND string k of sub-block SB1 is connected to Top BLn, NAND string 1 of sub-block SB1 is connected to Top BLn+1, NAND string m of sub-block SB2 is connected to Bottom BLn, NAND string n of sub-block SB2 is connected to Bottom BLn+1, NAND string o of sub-block SB3 is connected to Bottom BLn, and NAND string p of sub-block SB3 is connected to Bottom BLn+1.

[0100] Memory structure 326 includes a source line (Top_SL) above memory structure 326 and a source line (Bottom_SL) below memory structure 326. The source lines are shown as being divided into separate and independent non-contiguous segments. Each segment of source line Top_SL is connected together (e.g., shorted together or routed to a common connection). Each segment of source line Bottom_SL is connected together (e.g., shorted together or routed to a common connection). In one embodiment, both Top_SL and Bottom_SL are connected to the control circuitry of control die 304. In another embodiment, both Top_SL and Bottom_SL are connected to the control circuitry of memory die 302. In yet another embodiment, Top_SL is connected to the control circuitry of control die 304, and Bottom_SL is connected to the control circuitry of memory die 302.

[0101] exist Figure 9 In this arrangement, memory operations can be performed on the NAND strings (e.g., NAND strings a and b) of sub-block SB0 via a sense amplifier on control die 304 (CCAA), while simultaneously performing memory operations on the NAND strings (e.g., NAND strings e and f) of sub-block SB2 via a sense amplifier on memory die 302 (CCUA); similarly, memory operations can be performed on the NAND strings (e.g., NAND strings a and b) of sub-block SB0 via a sense amplifier on control die 304, while simultaneously performing memory operations on the NAND strings (e.g., NAND strings g and h) of sub-block SB3 via a sense amplifier on memory die 302. Memory operations can be performed; memory operations can be performed on the NAND strings (e.g., NAND strings c and d) of sub-block SB1 via a sense amplifier on control die 304, while memory operations can be performed on the NAND strings (e.g., NAND strings e and f) of sub-block SB2 via a sense amplifier on memory die 302; and memory operations can be performed on the NAND strings (e.g., NAND strings c and d) of sub-block SB1 via a sense amplifier on control die 304, while memory operations can be performed on the NAND strings (e.g., NAND strings g and h) of sub-block SB3 via a sense amplifier on memory die 302.

[0102] In one example, the memory system can write a first page of data (e.g., 16KB) to SB0 or SB1 via sense amplifiers on the control die 304, while simultaneously writing a second page of data to SB2 or SB3 via sense amplifiers on the memory die 302, doubling the parallelism level, which results in an improvement in speed / performance of the memory system. Similarly, the memory system can read a first page of data (e.g., 16KB) from SB0 or SB1 via sense amplifiers on the control die 304, while simultaneously reading a second page of data from SB2 or SB3 via sense amplifiers on the memory die 302, doubling the parallelism level, which results in an improvement in speed / performance of the memory system. Additionally, since all memory cells of the two sub-blocks that are undergoing a memory operation are connected to the same word line, the word line voltage (e.g., power) is being used more efficiently. That is, the same word line voltage will be used to write to or read from twice the number of memory cells. Existing memory systems cannot achieve this level of parallelism because there is not enough space on a single die for enough sense amplifiers.

[0103] For purposes of this document, the term “simultaneously” includes overlapping in time, even if they start or stop at different times. Note that Figure 9 Top BLn+1, Top BLn, Top SL, and CCAA are shown above the memory structure, while Bottom BLn, Bottom BLn+1, Bottom SL, and CCUA are below the memory structure. The terms above and below are taken with respect to the memory structure 326 and the substrate of the memory die 302, such that whatever is between the memory structure 326 and the substrate of the memory die 302 is considered to be below the memory structure, and whatever is on the opposite side of the memory structure from the substrate of the memory die 302 is considered to be above the memory structure, regardless of the orientation of the integrated memory assembly.

[0104] Figure 9 A top side select line Top SGL is shown, which represents top side select lines TSGL0, TSGL1, TSGL2, and TSGL3; thus, Figure 9 Top SGL is depicted as four unconnected metal lines (with the same shading). Figure 9 A bottom side select line Bottom SGL is also shown, which represents bottom side select lines BSGL0, BSGL1, BSGL2, and BSGL3; thus, Figure 9Bottom_SGL is depicted as four unconnected metal lines (with the same shading). For the NAND strings of sub-blocks SB0 and SB1 (e.g., a, b, c, d, i, j, k, 1), Top_SGL serves as the drain-side select line and Bottom_SGL serves as the source-side select line; thus, the select gates connected to Top_SGL are drain-side select gates and the select gates connected to Bottom_SGL are source-side select gates. For the NAND strings of sub-blocks SB2 and SB3 (e.g., e, f, g, h, m, n, o, p), Top_SGL serves as the source-side select line and Bottom_SGL serves as the drain-side select line; thus, the select gates connected to Top_SGL are source-side select gates and the select gates connected to Bottom_SGL are drain-side select gates. Thus, the same select line can be both a drain-side select line for some sub-blocks and a source-side select line for other sub-blocks.

[0105] Figure 10 is Figure 9 a circuit diagram of an embodiment of Figure 5 to Figure 8 the memory described. In particular, Figure 10 a portion of one block is shown, which includes NAND string a in sub-block SB0, NAND string c in sub-block SB1, NAND string e in sub-block SB2, NAND string g in sub-block SB0, top bit lines (411, 412, 413, 414, 419), bottom bit lines (423, 425, 427, 429), Bottom_SL, and Top_SL. Top bit line 411 and top bit line 412 correspond to bit line Top_BLn and bit line Top_BLn+1 of Figure 9 . Bottom bit line 423 and bottom bit line 425 correspond to bit line Bottom_BLn and bit line Bottom_BLn+1 of Figure 9 . To make Figure 10 easier to read, and for exemplary purposes, only one NAND string is depicted for each of sub-blocks SB0, SB1, SB2, SB3. Figure 10 physical word lines WLL0 through WLL95 are shown, which run through the entire block. Figure 10 the structure of Figure 5 corresponds to portion 401 in block 2 of Within this block, each bit line is connected to two NAND strings. Top-side select lines TSGL0, TSGL1, TSGL2, and TSGL3 and bottom-side select lines BSGL0, BSGL1, BSGL2, and BSGL3 are used to determine which NAND strings are connected to the associated bit line and source line.

[0106] Figure 11is a cross-sectional view of one embodiment of a portion of two blocks of memory cells. Figure 11 has a structure similar to Figure 9 , except that the source lines (Top_SL and Bottom_SL) are continuous rather than separated into individual non-continuous segments (as depicted in Figure 9 ). In the structure of Figure 11 , the source lines (Top_SL and Bottom_SL) would have been etched (e.g., holes etched through the source lines) to allow the bit line contacts (and the dielectric surrounding the bit line contacts) to pass through the source lines.

[0107] As described above, the NAND strings in one half of the sub-blocks of a block are connected to sense amplifiers above the memory structure (e.g., on the control die 304), and the NAND strings in the other half of the sub-blocks of a block are connected to sense amplifiers below the memory structure (e.g., on the memory die 302). In the embodiment of Figure 9 and Figure 11 , the NAND strings of SB0 and SB1 are connected to sense amplifiers above the memory structure (e.g., on the control die 304), and the NAND strings of SB2 and SB3 are connected to sense amplifiers below the memory structure (e.g., on the memory die 302). Figure 12 is a cross-sectional view of another embodiment of a portion of two blocks of memory cells, where the NAND strings of SB0 and SB2 are connected to sense amplifiers above the memory structure (e.g., on the control die 304), and the NAND strings of SB1 and SB3 are connected to sense amplifiers below the memory structure (e.g., on the memory die 302). Thus, in the embodiment of Figure 12 , the NAND strings of SB0 and SB2 are connected to bit lines above the memory structure (Top BLn and Top BLn+1) and to a source line below the memory structure (Bottom_SL), and the NAND strings of SB1 and SB3 are connected to bit lines below the memory structure (Bottom BLn and Bottom BLn+1) and to a source line above the memory structure (Top_SL). Thus, memory operations can be performed simultaneously on SB0 and SB1 or SB3. Similarly, memory operations can be performed simultaneously on SB2 and SB1 or SB3.

[0108] Figure 12A and Figure 12B includes a table identifying exemplary voltage biases to be applied to the top side select lines TSGL0, TSGL1, TSGL2, and TSGL3 (collectively, Top_SGL) and the bottom side select lines BSGL0, BSGL1, BSGL2, and BSGL3 (collectively, Bottom_SGL) in order to perform data writes and reads. Figure 12AThe table is applicable to Figure 9 to Figure 11 The implementation plan. Figure 12B The table is applicable to Figure 12 The implementation plan. For example, Figure 12A The third column teaches how to simultaneously program / write a NAND string (e.g., NAND string a) in SB0 and a NAND string (e.g., NAND string e) in SB2. The system applies VSGD to TSGL0, VSS to TSGL1, VSS to TSGL2, VSS to TSGL3, VSS to BSGL0, VSS to BSGL1, VSGD to BSGL2, and VSS to BSGL3. The voltage VSGD is approximately 2.5 volts. The voltage VSS is approximately 0 volts. The voltage VSG is approximately 7 volts. Other voltages may be used depending on the specific implementation. Note that in... Figure 12B In the table, even if a positive voltage is applied to Top_SGL and Bottom_SGL for the selected NAND string, the selected NAND string can be cut off from the top or bottom by using the appropriate threshold voltage of the transistor that serves as the selection gate.

[0109] Figure 13 This is a block diagram depicting further details of one embodiment of the integrated memory assembly, illustrating a control die 304 coupled to the memory die 302. The control die includes multiple sense amplifiers 350, multiple word line drivers 502(1)...502(n), and other circuitry that accumulates to form the control circuitry. Figure 13 (Not shown in the diagram). On the surface of the substrate of memory die 302 (and between the substrate and memory structure 326) are multiple sense amplifiers 350 and other control logic components that together form control circuitry. Memory die 302 includes at least one plane 530 composed of memory cells. Plane 530 is all or part of an exemplary embodiment of memory structure 326. Memory die 302 may have other planes. This plane is divided into M blocks.

[0110] Each sense amplifier 350 is connected to a bit line. Two representative bit lines (BL1 and BL2) are depicted for plane 530. There can be thousands or tens of thousands of such bit lines for each plane. Bit line BL1 is on the top of plane 530 and is connected to a sense amplifier 350 on control die 304. Bit line BL2 is below plane 530 and is connected to a sense amplifier 350 on memory die 302 (positioned on the substrate of memory die 302). The sense amplifier includes a bit line driver. Thus, the sense amplifier can provide a voltage to the bit line to which it is connected. The sense amplifier is also configured to sense a condition of the bit line. In one embodiment, the sense amplifier is configured to sense a current flowing in the bit line. In one embodiment, the sense amplifier is configured to sense a voltage on the bit line.

[0111] Control die 304 includes several word line drivers 502(1)-502(n). Word line drivers 560 are configured to provide a voltage to a word line. In this example, there are “n” word lines per memory cell block. In one embodiment, each time a memory array is operated, one of the blocks in plane 530 is selected. In one embodiment, if the memory operation is a program or read, one word line within the selected block is selected for the memory operation. In one embodiment, if the memory operation is an erase, all of the word lines within the selected block are selected for the erase. Word line drivers 502 (e.g., part of power control circuit 316) provide a voltage to the word lines in a first selected block (e.g., block 2) in memory die 302. Control die 304 can also include charge pumps, voltage generators, etc. that can be used to provide voltages to the word line drivers 502 and / or bit line drivers.

[0112] Memory die 302 has several bond pads 572a, 572b on a first major surface 586 of memory die 302. There can be “n” bond pads 572a to receive a voltage from the corresponding “n” word line drivers 502(1)-502(n). There can be one bond pad 572b for each bit line associated with plane 530. Reference number 572 will be used to refer to bond pads on major surface 586 in general.

[0113] The control die 304 has a number of bond pads 576a, 576b on a first major surface 588 of the control die 304. There can be "n" bond pads 576a to deliver voltage from the corresponding "n" word line drivers 502(1)-502(n) to the memory die 302. There can be one bond pad 576b for each bit line associated with the plane 530. Reference number 576 will be used to refer to bond pads on the major surface 588 in general. Note that there can be bond pad pairs 572a / 576a and 572b / 572b. In some embodiments, the bond pads 570 and / or 574 are flip chip bond pads (other types can also be employed).

[0114] In one embodiment, the pattern of the bond pads 572 matches the pattern of the bond pads 576. The bond pads 572 are bonded (e.g., flip chip bonded) to the bond pads 576. Thus, the bond pads 572, 576 electrically and physically couple the memory die 302 to the control die 304. In addition, the bond pads 572, 576 allow internal signal transfer between the memory die 302 and the control die 304. Thus, the memory die 302 and the control die 304 are bonded together with the bond pads. Although Figure 13 One control die 304 is depicted as bonded to one memory die 302, but in another embodiment, one control die 304 is bonded to multiple memory dies 302.

[0115] In this document, "internal signal transfer" refers to signal transfer between the control die 304 and the memory die 302. Internal signal transfer allows the circuitry on the control die 304 to control memory operations in the memory die 302 via the bond pads. Thus, the bond pads 572, 576 can be used for memory operation signal transfer. Memory operation signal transfer can include, but is not limited to, providing voltage, providing current, receiving voltage, receiving current, sensing voltage, and / or sensing current.

[0116] The bond pads 572, 576 can be formed from, for example, copper, aluminum, and alloys thereof. There can be a liner between the bond pads 572, 576 and the major surfaces (586, 588). The liner can be formed from, for example, a titanium / titanium nitride stack. The bond pads 572, 576 and the liner can be applied by vapor deposition and / or electroplating techniques. Together, the bond pads and the liner can have a thickness of 720 nm, but in other embodiments the thickness can be greater or less.

[0117] Metal interconnects and / or vias can be used to electrically connect various elements in the die to bond pads 572, 576. Several conductive paths that can be implemented with metal interconnects and / or vias are described. For example, sense amplifiers 350 can be electrically connected to bond pads 576b through a path. There can be thousands or millions of such sense amplifiers, paths, and bond pads. Note that BL is not necessarily directly connected to bond pad 572b. Word line drivers 560 can be electrically connected to bond pads 576a through paths 508. Note that paths 508 can include separate conductive paths for each word line driver 502(1)-502(n). Likewise, there can be a separate bond pad 576a for each word line driver 502(1)-502(n). Word lines in block 2 of memory die 302 can be electrically connected to bond pads 572a through paths 508.

[0118] Figure 14 is a block diagram depicting additional details of one embodiment of an integrated memory assembly including a memory die 302 directly bonded to a control die 304. This direct bonding configuration is similar to Figure 13 the embodiment depicted. Note that although gaps are depicted between adjacent pairs of dies, such gaps can be filled with epoxy or other resin or polymer.

[0119] Memory structure 326 on memory die 302 includes several word line layers (WL) separated by dielectric layers. The dielectric layers are represented by gaps between the word line layers. Thus, the word line layers and dielectric layers form a stack. There can be more word line layers than Figure 14 depicted. As with the example of Figure 13 There are several columns that extend through the stack. One column is designated with reference number 656 in the stack. A column contains memory cells. For example, each column can contain a NAND string. There are several bit lines (BL) above and below the stack.

[0120] Memory die 302 includes a substrate 640. On a top surface of substrate 640 are circuitry 642, circuitry 644, and a plurality of sense amplifiers 350 Figure 14Only one sense amplifier is depicted, but there are many more, which together form the control circuit. In some embodiments, the sense amplifiers 350 and / or other circuitry 642 / 644 comprise CMOS circuitry. The memory structure 326 is positioned directly above the circuitry 642, the circuitry 644, and the plurality of sense amplifiers 350. The memory structure 326 comprises bit lines 650 above the memory structure and bit lines 652 below the memory structure. Each sense amplifier 350 on the substrate 640 is connected to a bit line 652 below the stack. Each memory hole, such as memory hole 656, in the memory hole (NAND string) is connected to one of the bit lines 650 and 652, as described above.

[0121] The control die 304 comprises a substrate 602. On a top surface of the substrate 602 are control circuitry, which comprises a plurality of sense amplifiers 350 Figure 14 only one sense amplifier is depicted in the middle), circuitry 664, circuitry 666, circuitry 668, and a plurality of word line drivers 502 Figure 14 only one word line driver is depicted in the middle). In some embodiments, the sense amplifiers 350, the word line drivers 502, and / or other circuitry 664 / 666 / 668 comprise CMOS circuitry. The sense amplifiers 350 are connected to one of the bit lines 650 on the top of the memory structure 326 through conductive vias 624, TSVs 622, bond pads 576b, bond pads 572b, and conductive vias 630. The word line drivers 502 are connected to one of the word lines (WL) 632 through conductive vias 616, TSVs 618, bond pads 576a, bond pads 572a, and conductive vias 508.

[0122] There are external signal paths that allow the circuitry on the control die 304 to communicate with entities outside of the integrated memory assembly 130, such as the memory controller 120. Thus, the circuitry 668 on the control die 304 communicates with and provides an interface to the memory controller 120. Optionally, the circuitry 668 on the control die 304 can communicate with the host 120. The external signal paths comprise vias 670 and bond pads 672 in the control die 304.

[0123] Figure 15 One embodiment of a plan view 704 of the control die 304 is depicted, and Figure 16One embodiment of a plan view 702 of the memory die 302 is depicted. The plan view 704 shows one embodiment of the layout of some of the components of the control circuitry on the control die 304. For example, the plan view 704 shows the layout of eight modules labeled SA / DL corresponding to sense amplifiers and data latches. The plan view 704 also includes eight modules labeled HVP (high voltage pumps), input / output circuitry (I / O), row decoders (RD), and other logic components implementing various control functions (logic). In one embodiment, each component of the plan view 704 is a circuit positioned on the surface of the substrate of the control die 304. In other embodiments, the plan view 704 can arrange the depicted components in other locations, including other components, and / or include fewer than Figure 15 all of the components depicted.

[0124] The plan view 702 shows one embodiment of the layout of some of the components of the control circuitry on the memory die 302. For example, the plan view 702 shows the layout of eight modules labeled SA / DL corresponding to sense amplifiers and data latches. The remainder of the plan view 702 is used for logic components implementing various control functions (logic). In one embodiment, each component of the plan view 702 is a circuit positioned on the surface of the substrate of the memory die 302 and positioned below the memory structure 326 so that the components of the plan view 702 are between the substrate and the memory structure. In other embodiments, the plan view 702 can arrange the depicted components in other locations, including other components, and / or include fewer than Figure 16 all of the components depicted. In one embodiment, the logic components implementing various control functions (logic) can be used to implement some of the functions of the control die 304 depicted as Figure 2 part of the control die 304 in FIG. 6B.

[0125] Figure 17 Another embodiment of a plan view 714 of the control die 304 is depicted, and Figure 18 Another embodiment of a plan view 712 of the memory die 302 is depicted. The plan view 714 shows one embodiment of the layout of some of the components of the control circuitry on the control die 304. For example, the plan view 714 shows the layout of eight modules labeled SA / DL corresponding to sense amplifiers and data latches. The plan view 714 also includes logic components implementing various control functions (logic) and input / output circuitry (I / O). In one embodiment, each component of the plan view 714 is a circuit positioned on the surface of the substrate of the control die 304. In other embodiments, the plan view 704 can arrange the depicted components in other locations, including other components, and / or include fewer than Figure 17 all of the components depicted.

[0126] Plan view 712 illustrates another embodiment of the layout of some of the components of the control circuit on the memory die 302. For example, plan view 712 illustrates the layout of eight modules labeled SA / DL corresponding to sense amplifiers and data latches. Plan view 712 also includes eight modules labeled HVP (high voltage pumps), row decoders (RD), and other logic components that implement various control functions (logic). In one embodiment, each component of plan view 712 is a circuit positioned on the surface of the substrate of the memory die 302 and positioned underneath the memory structure 326 so as to place the components of plan view 712 between the substrate and the memory structure. In other embodiments, plan view 712 can arrange the depicted components in other locations, including other components, and / or include fewer than Figure 18 all of the depicted components.

[0127] In some embodiments, there can be more than one control die 304 and more than one memory die 302 in the integrated memory assembly 130. In some embodiments, the integrated memory assembly 130 includes a stack of multiple control dies 304 and multiple memory dies 302. Figure 19 A side view of one embodiment of the integrated memory assembly 130 is depicted stacked on a substrate 802. The integrated memory assembly 130 has three control dies 304 and three memory dies 302. Each control die 304 is directly bonded to one of the memory dies 302. Some of the bond pads 8730, 824 are depicted. There can be many more bond pads. The space between the bonded together dies 302, 304 is filled with a solid layer 848, which can be formed of an epoxy or other resin or polymer. The solid layer 848 protects the electrical connections between the dies 302, 304 and further secures the dies together. Various materials can be used as the solid layer 848, but in an embodiment, the material can be Hysol epoxy from Henkel Corporation.

[0128] The integrated memory assembly 130 can be stacked, for example, with a stepped offset so that the bond pads 804 at each level are not covered and are accessible from above. The wire bonds 806 connected to the bond pads 804 connect the control dies 304 to the substrate 802. Multiple such wire bonds can be formed across the width of each control die 304 (i.e., to the Figure 8

[0129] ​Through-silicon vias (TSVs) 812 can be used to route signals through the control die 304. Through-silicon vias (TSVs) 814 can be used to route signals through the memory die 302. The TSVs 812, 814 can be formed before, during, or after the integrated circuits in the semiconductor dies 302, 304 are formed. The TSVs can be formed by etching holes through a wafer. These holes can then be lined with a barrier to prevent diffusion of metals. The barrier layer, in turn, can be lined with a seed layer, and the seed layer can be plated with an electrical conductor, such as copper, although other suitable materials can be used, such as aluminum, tin, nickel, gold, doped polysilicon, and alloys or combinations thereof.

[0130] Solder balls 808 can optionally be attached to the contact pads 810 on the lower surface of the substrate 802. The solder balls 808 can be used to electrically and mechanically couple the integrated memory component 130 to a host device, such as a printed circuit board. In cases where the integrated memory component 130 is to be used as an LGA package, the solder balls 808 can be omitted. The solder balls 808 can form part of the interface between the integrated memory component 130 and the memory controller 120.

[0131] In Figure 19 In embodiments of the memory structure 900, the memory dies 302 and the control dies 304 are arranged in pairs. That is, each memory die 302 is joined to and communicates with a corresponding / matched / paired control die.

[0132] Figure 20 is a block diagram of a memory structure 900 that includes four planes 902, 904, 906, 908 and does not utilize the techniques presented herein. That is, the memory structure 900 is used in a memory system that does not include sense amplifiers on either the memory dies or the control dies. Thus, at a given time, only one sub-block per plane can be selected for a memory operation. Figure 20 The sub-blocks are shown shaded so that horizontal shading indicates unselected sub-blocks and cross-hatched shading indicates selected sub-blocks. Figure 20Four sub-blocks of the same block are shown for each plane 902, 904, 906, and 908. For example, sub-blocks 902-0, 902-1, 902-2, and 902-3 are depicted for the same block in plane 902. Of sub-blocks 902-0, 902-1, 902-2, and 902-3, only sub-block 902-3 is selected for a memory operation, while the other sub-blocks are unselected (e.g., idle) during the memory operation. Sub-blocks 904-0, 904-1, 904-2, and 904-3 are depicted for the same block in plane 904. Of sub-blocks 904-0, 904-1, 904-2, and 902-3, only sub-block 904-3 is selected for a memory operation, while the other sub-blocks are unselected (e.g., idle) during the memory operation. Sub-blocks 906-0, 906-1, 906-2, and 906-3 are depicted for the same block in plane 906. Of sub-blocks 906-0, 906-1, 906-2, and 906-3, only sub-block 906-3 is selected for a memory operation, while the other sub-blocks are unselected (e.g., idle) during the memory operation. Sub-blocks 908-0, 908-1, 908-2, and 908-3 are depicted for the same block in plane 908. Of sub-blocks 908-0, 908-1, 908-2, and 908-3, only sub-block 908-3 is selected for a memory operation, while the other sub-blocks are unselected (e.g., idle) during the memory operation.

[0133] Figure 21 is a block diagram of a memory structure 920 that includes four planes of memory cells 922, 924, 926, and 928 that utilize / benefit from the techniques presented herein. That is, memory structure 920 is used in a memory system that includes sense amplifiers on a memory die and a control die, as described above in connection with Figure 1 to Figure 19 Thus, each plane can select two sub-blocks (which is twice the system of Figure 20 for simultaneous execution of memory operations. Figure 21For each plane 922, 924, 926, and 928, four sub-blocks of the same block are shown. For example, sub-blocks 922-0, 922-1, 922-2, and 922-3 are depicted for the same block in plane 922. In sub-blocks 922-0, 922-1, 922-2, and 922-3, sub-blocks 922-1 and 922-3 are selected for simultaneous memory operations, while other sub-blocks are not selected during the memory operation (e.g., idle). Sub-blocks 924-0, 924-1, 924-2, and 924-3 are depicted for the same block in plane 924. In sub-blocks 924-0, 924-1, 924-2, and 922-3, sub-blocks 924-1 and 924-3 are selected for simultaneous memory operations, while other sub-blocks are not selected during the memory operation (e.g., idle). Sub-blocks 926-0, 926-1, 926-2, and 926-3 are depicted for the same block in plane 926. Among sub-blocks 926-0, 926-1, 926-2, and 926-3, sub-blocks 926-1 and 926-3 are selected for simultaneous memory operations, while other sub-blocks are not selected during the memory operation (e.g., idle). Sub-blocks 928-0, 928-1, 928-2, and 928-3 are depicted for the same block in plane 928. Among sub-blocks 928-0, 928-1, 928-2, and 928-3, sub-blocks 908-1 and 908-3 are selected for simultaneous memory operations, while other sub-blocks are not selected during the memory operation (e.g., idle). Therefore, it can be seen that the technique described herein provides twice the performance enhancement compared to memory cells that can be written to and / or read simultaneously. It should be noted that when two sub-blocks of the same block are selected for simultaneous writing or reading, the memory cells of the two selected sub-blocks connected to the same word line are written to and / or read simultaneously.

[0134] Figure 21 A memory system with four planes is shown to simultaneously write to and / or read memory cells in eight sub-blocks (two sub-blocks in each plane). Similarly, a memory system with eight planes can simultaneously write to and / or read memory cells in sixteen sub-blocks (two sub-blocks in each plane).

[0135] As mentioned above, Figure 6 Depicting according to Figure 9 The implementation is a top view of a portion of a block of memory structure 326 (sub-blocks SB0, SB1 are connected to the bit lines above memory structure 326, and sub-blocks SB2, SB3 are connected to the bit lines below memory structure 326). Figure 22 Depicting according to Figure 12the same portion of the same block from memory structure 326 (sub-blocks SBO, SB2 are connected to bit lines above memory structure 326 and sub-blocks SBl, SB3 are connected to bit lines below memory structure 326). In Figure 12 and Figure 22 In this embodiment of the same, partial slits 404 and 408 can be removed. Partial slit 404 is employed so that sub-block SBO and sub-block SBl can be selected separately. However, since SBO is connected to bit lines above memory structure 326 and SBl is connected to bit lines below memory structure 326, partial slit 404 is optional. Similarly, partial slit 408 is employed so that sub-block SB2 and sub-block SB3 can be selected separately. However, since SB2 is connected to bit lines above memory structure 326 and SB3 is connected to bit lines below memory structure 326, partial slit 408 is optional. Figure 23 depicts the same top view of the same portion of the same block as Figure 22 However, partial slits 404, 408 have been removed. Removal of partial slits 404 and 408 allows the block of memory cells to be smaller because Figure 23 width W23 is less than width W22 of Figure 22 This can result in a smaller die size, saving cost and space.

[0136] Figure 24 is a flowchart that describes one embodiment of a process to perform memory operations employing the structure described above in Figure 1 to Figure 23 Figure 24 ​In step 1002, a request to perform a memory operation (e.g., write or read) at the integrated memory component 130 is received. For example, the request is received at the control die 304. This request may originate from a memory controller, a host, or another integrated component. In step 1004, the integrated memory component 130 performs a memory operation on a first portion of a first block of non-volatile memory cells using a first plurality of sense amplifiers. For example, the memory operation is performed in step 1004 using control circuitry (including sense amplifiers) residing on the memory die 302. The control circuitry of the control die 304 may also (in some embodiments) be used to perform the memory operation. For example, the memory operation may be performed under the instruction of a state machine on the control die 304 using sense amplifiers of the memory die of a first sub-block of a selected block of memory cells connected to the memory die 302. In step 1006, the integrated memory component 130 simultaneously performs a memory operation on a second portion of the first block of non-volatile memory cells using a second plurality of sense amplifiers. For example, the memory operation is performed using control circuitry (including sense amplifiers) residing on the control die 304. In one implementation, steps 1004 and 1006 are performed simultaneously, as described above. Figure 24 The process can be used in conjunction with any of the above-described implementation schemes. The following is combined with... Figure 25 to Figure 29 Provided Figure 24 More details on the steps.

[0137] Figure 25 It is a flowchart describing one implementation of the process used to perform a write operation. Figure 25 The process is Figure 24 An exemplary implementation of the process. In Figure 25 In step 1102, the integrated memory component 130 receives a request to perform a write operation at the integrated memory component. For example, control die 304 may receive (from the memory controller) a write command, host data for the write command, and one or more write addresses in the memory structure where the host data is written. The host data is data received from the host. In one embodiment, the memory controller receives host data from the host and forwards it to the integrated memory component. In step 1104, control die 304 applies a programming voltage signal to the selected word lines of the memory structure 326. Additionally, the select lines (Top_SGL and Bottom_SGL) are as follows: Figure 12A or Figure 12BThe depicted bias (or another suitable bias scheme). In step 1106, the first plurality of sense amplifiers on the memory die 302 provide a program condition on the first plurality of bit lines while driving a program voltage on the selected word line. The first plurality of sense amplifiers on the memory die 302 are connected to the bit lines below the memory structure 326, as described above. In step 1108, the second plurality of sense amplifiers on the control die 304 are controlled to provide a program condition on the second plurality of bit lines while driving a program voltage on the selected word line. The second plurality of sense amplifiers on the control die 304 are connected to the bit lines above the memory structure 326, as described above. In one embodiment, the sense amplifiers provide a program condition by applying a small voltage or 0 volt voltage on the bit lines. As a result of steps 1102-1108, the host data is programmed into the memory structure 326. In one embodiment, steps 1106 and 1108 are performed simultaneously so that memory cells connected to a common word line but in two sub-blocks are written simultaneously.

[0138] At the end of a successful program process, the threshold voltages of the memory cells should be within one or more distributions of threshold voltages for programmed memory cells or within a distribution of threshold voltages for erased memory cells, as appropriate. Figure 26 is a plot of threshold voltage versus number of memory cells and illustrates exemplary threshold voltage distributions for the memory structure 326 when each memory cell stores three bits of data. However, other embodiments can use other data capacities per memory cell (e.g., such as one bit of data, two bits of data, four bits of data, or five bits of data per memory cell). Figure 26 illustrates eight threshold voltage distributions corresponding to eight data states. For data state N, the data state N has a higher threshold voltage than data state N-1 and a lower threshold voltage than data state N+1. The first threshold voltage distribution (data state) S0 represents an erased memory cell. The other seven threshold voltage distributions (data states) S1-S7 represent programmed memory cells and are thus also referred to as program states or program data states. In some embodiments, the data states S1-S7 can overlap, with the controller 122 relying on error correction to identify the correct data being stored.

[0139] Figure 26 illustrates seven read reference voltages Vrl, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7 used to read data from the memory cells. By testing (e.g., performing a sense operation) whether a given memory cell’s threshold voltage is above or below the seven read reference voltages, the system can determine the data state (i.e., S0, S1, S2, S3,...) in which the memory cell resides.

[0140] Figure 26Seven verify reference voltages Vvl, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7 (also referred to as verify target voltages) are also shown. When programming the memory cells to data state SI, the system will test whether the memory cells have a threshold voltage greater than or equal to Vvl. When programming the memory cells to data state S2, the system will test whether the memory cells have a threshold voltage greater than or equal to Vv2. When programming the memory cells to data state S3, the system will determine whether the memory cells have a threshold voltage greater than or equal to Vv3. When programming the memory cells to data state S4, the system will test whether the memory cells have a threshold voltage greater than or equal to Vv4. When programming the memory cells to data state S5, the system will test whether the memory cells have a threshold voltage greater than or equal to Vv5. When programming the memory cells to data state S6, the system will test whether the memory cells have a threshold voltage greater than or equal to Vv6. When programming the memory cells to data state S7, the system will test whether the memory cells have a threshold voltage greater than or equal to Vv7.

[0141] In one embodiment, referred to as full sequence programming, the memory cells can be programmed directly from the erased data state SO to any of the programmed data states SI through S7. For example, a group of memory cells to be programmed (e.g., memory cells in two sub-blocks of a plane and connected to the same word line) can first be erased so that all of the memory cells in the group are in the erased data state SO. Then, a programming process is used to program the memory cells directly to data states SI, S2, S3, S4, S5, S6, and / or S7. For example, while some memory cells are being programmed from data state SO to data state SI, other memory cells are being programmed from data state SO to data state S2 and / or from data state SO to data state S3, and so on. Figure 26 The arrows of FIG. 1 represent full sequence programming. In addition to full sequence programming, the techniques described herein can be used with other types of programming, including but not limited to multi-level programming / multi-phase programming.

[0142] Figure 26 Each threshold voltage distribution (data state) of FIG. 1 corresponds to a predetermined value of a set of data bits stored in the memory cell. The specific relationship between the data programmed into the memory cell and the threshold voltage level of the memory cell depends on the data encoding scheme employed by the memory cell. In one embodiment, a Gray code assignment is used to assign data values to threshold voltage ranges such that if the threshold voltage of the memory shifts erroneously to its adjacent physical state, only one bit will be affected.

[0143] Figure 27is a table describing one example of assigning data values to data states. In Figure 27 In the table of, S0 = 111 (erased state), S1 = 110, S2 = 100, S3 = 000, S4 = 010, S5 = 011, S6 = 001, and S7 = 101. Other encodings of data can also be used. The technology disclosed herein does not require a particular data encoding. In one embodiment, when a block is subjected to an erase operation, all memory cells are moved to data state S0, the erased state.

[0144] Generally, during verify operations and read operations, the selected word line is connected to a voltage (one example of a reference signal) whose level is specified for each read operation (see, e.g., read reference voltages Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7 of Figure 26 or verify operations (see, e.g., verify reference voltages Ev, Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7 of Figure 26 ) in order to determine whether the threshold voltage of the relevant memory cell has reached this level. After the word line voltage is applied, the conduction current of the memory cell is measured to determine whether the memory cell turns on (is conducted) in response to the voltage applied to the word line. If the conduction current is measured to be greater than a particular value, then it is assumed that the memory cell turns on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than a particular value, then it is assumed that the memory cell does not turn on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During a read or verify process, unselected memory cells are provided with one or more read-through voltages (also referred to as bypass voltages) at their control gates so that these memory cells will operate as pass gates (e.g., conduct current regardless of whether these memory cells are programmed or erased).

[0145] There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of a memory cell is measured as the rate at which the memory cell discharges or charges a dedicated capacitor in a sense amplifier. In another example, the conduction current of a selected memory cell allows (or does not allow) a NAND string including the memory cell to discharge to a corresponding bit line. The voltage on the bit line is measured after a certain time period to see whether it has discharged. Note that the technology described herein can be used with different methods for verify / read known in the art. Other read and verify techniques known in the art can also be used.

[0146] Figure 28This is a flowchart describing one embodiment of the process for programming memory structure 326. In one exemplary embodiment, as described above, under the instruction of state machine 312, the control die 302 is executed using sense amplifiers on the control die and the memory die. Figure 28 The process. Execution Figure 28 The process to achieve Figure 26 Full-sequence programming and other programming schemes including multilevel programming. When implementing multilevel programming, Figure 28 The process is used to implement any / every stage of a multi-level programming process. Figure 28 The process can be used to execute Figure 25 The process.

[0147] Typically, during programming operations (via the selected word line), the programming voltage applied to the control gate is a series of programming pulses (voltage pulses). Between the programming pulses is a set of verification pulses to perform verification. In many implementations, the amplitude of the programming pulses increases by a predetermined step size with each successive pulse. Figure 28 In step 1202, the programming voltage (Vpgm) is initialized to an initial amplitude (e.g., approximately 12V to 16V or another suitable level), and the programming counter PC maintained by state machine 312 is initialized to 1. In step 1204, a programming pulse of the programming signal Vpgm is applied to the selected word line (the word line selected for programming). In one embodiment, a group of memory cells to be programmed simultaneously are all connected to the same word line (the selected word line). Unselected word lines receive one or more boost voltages (e.g., approximately 7V to 11V) to perform boost schemes known in the art. The programming pulse applied to the selected word line is... Figure 25 An example of the programming voltage signal in step 1104. In one implementation, if the memory cell is to be programmed, the corresponding bit line is grounded (e.g., Figure 25 (Programming conditions in steps 1106 and 1108). On the other hand, if the memory cell should remain at its current threshold voltage, then the corresponding bit line is connected to Vdd to disable programming. In step 1204, programming pulses are simultaneously applied to all memory cells connected to the selected word line so that all memory cells connected to the selected word line are programmed simultaneously. That is, they are programmed at the same time or during the overlap time (both are considered simultaneous). In this way, unless they have been locked to prevent programming, all memory cells connected to the selected word line will have their threshold voltage change simultaneously.

[0148] In step 1206, the appropriate memory cells are verified with a set of appropriate verify reference voltages to perform one or more verify operations. In one embodiment, the verify process is performed by testing whether the threshold voltage of a memory cell selected for programming has reached an appropriate verify reference voltage. In step 1208, a determination is made as to whether all memory cells have reached their target threshold voltage (pass). If so, the programming process is complete and is successful because all selected memory cells are programmed and verified in their target state. In step 1210, a "pass" (or success) status is reported. If a determination is made in step 1208 that not all memory cells have reached their target threshold voltage (fail), the programming process proceeds to step 1212. In step 1212, the system counts the number of memory cells that have not reached their respective target threshold voltage distribution. That is, the system counts the number of memory cells for which the verify process has failed so far. The counting can be done by the state machine 312, the controller 120, or other logic. In one implementation, each sense block will store the status (pass / fail) of its respective memory cells. In one embodiment, there is a total count that reflects the total number of memory cells currently being programmed that have failed the last verify step. In another embodiment, a separate count is kept for each data state.

[0149] In step 1214, a determination is made as to whether the count from step 1212 is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by an error correction code (ECC) during a read process of a page of memory cells. If the number of failed cells is less than or equal to the predetermined limit, the programming process can stop and a "pass" status is reported in step 1210. In this case, enough memory cells are correctly programmed so that the remaining few memory cells that have not been completely programmed can be corrected using the ECC during the read process. In some embodiments, step 1212 will count the number of failed cells for each sector, each target data state, or other unit, and these counts are individually or collectively compared to one or more thresholds in step 1214.

[0150] In one embodiment, the predetermined limit can be less than the total number of bits that can be corrected by the ECC during the read process to account for future errors. When less than all of the memory cells of a page are programmed, or the count of only one data state (or less than all states) is compared, the predetermined limit can be a fraction (proportional or not) of the number of bits that the ECC can correct during the read process of the page of memory cells. In some embodiments, the limit is not predetermined. Rather, it varies based on the number of errors already counted for the page, the number of program-erase cycles performed, or other criteria.

[0151] If the number of failed memory cells is not less than the predetermined limit, the program process continues at step 1216 and the program counter PC is checked against a program limit value (PL). Examples of program limit values include 6, 20, and 30; however, other values can be used. If the program counter PC is not less than the program limit value PL, the program process is considered to have failed and a "fail" status is reported in step 1218. If the program counter PC is less than the program limit value PL, the process continues at step 1220 during which the program counter PC is incremented by 1 and the program voltage Vpgm is increased to the next magnitude. For example, the next pulse will have a magnitude that is one step (e.g., 0.1 volt to 0.8 volt step) greater than the previous pulse. After step 1220, the process loops back to step 1204 and another program pulse is applied to the selected word line in order to perform another iteration of the program process (steps 1204-1220). Figure 28

[0152] ​Because errors can occur when programming or reading, and errors can occur when storing data (e.g., due to electronic drift, data retention issues, or other phenomena), error correction is used in conjunction with data programming. Memory systems often use error-correcting codes (ECC) to protect data from corruption. Numerous ECC encoding schemes are well known in the art. These conventional error-correcting codes are particularly useful in mass storage memory including flash memory (and other non-volatile) memory because such encoding schemes can have a significant impact on manufacturing yield and device reliability, making devices with a small number of unprogrammable or defective cells usable. Of course, there is a tradeoff between yield savings and the cost of providing additional memory cells to store code bits (i.e., the encoding “rate”). Thus, some ECC codes are more suitable for flash memory devices than others. Generally, ECC codes for flash memory devices tend to have a higher encoding rate (i.e., a lower code bit / data bit ratio) than codes used in data communication applications, which can have an encoding rate as low as 1 / 2. Examples of well-known ECC codes that are often used in conjunction with flash memory storage include Reed-Solomon codes, other BCH codes, Hamming codes, and the like. Sometimes, error-correcting codes used in conjunction with flash memory storage are “systematic” in that the data portion of the final code word is not changed from the actual data being encoded, with code or parity bits being appended to the data bits to form the complete code word.

[0153] The particular parameters of a given error-correcting code include the type of code, the size of the block of actual data from which the code word is derived, and the total length of the code word after encoding. For example, a typical BCH code applied to a 512-byte (4096-bit) data sector can correct up to four error bits if at least 60 ECC or parity bits are used. Reed-Solomon codes are a subset of BCH codes and are also commonly used for error correction. For example, a typical Reed-Solomon code can correct up to four errors in a 512-byte data sector using about 72 ECC bits. In the case of flash memory, error correction encoding provides a significant improvement in manufacturing yield as well as reliability of flash memory over time.

[0154] In some embodiments, the controller 120 receives host data (also referred to as user data or data from an entity outside the memory system) to be stored in the non-volatile memory structure 326, also referred to as information bits. The information bits are represented by the matrix i = [1 0] (note that two bits are used for example purposes only, and many embodiments have codewords longer than two bits). An error correction encoding process, such as any of the processes mentioned above or below, is implemented by the ECC engine 158 of the controller 120, where parity bits are added to the information bits to provide data represented by the matrix or codeword v = [1 0 1 0], indicating that two parity bits have been appended to the data bits. Other techniques can be used that map input data to output data in a more complex manner. For example, low density parity check (LDPC) codes, also known as Gallager codes, can be used. More details on LDPC codes can be found in R. G. Gallager, “Low-density parity-check codes”, IRE Trans. Inform. Theory, vol. IT-8, pp. 21 28, Jan. 1962; and D. MacKay, Information Theory, Inference and Learning Algorithms, Cambridge University Press 2003, chapter 47. In implementations, such LDPC codes are typically applied (e.g., by the ECC engine 158) to multiple pages of data encoded across multiple storage elements, but they need not be applied across multiple pages. In some embodiments, the ECC process (encoding data and / or decoding data) can be performed by the ECC engine 330 on the control die 304. In some embodiments, the ECC process (encoding data and / or decoding data) can be performed by an ECC engine on the memory die 302 (e.g., the ECC engine is Figure 16 part of the logic depicted).

[0155] In one embodiment, program is used to raise the threshold voltage of the memory cell into one of the program data states S1-S7. Erase is used to lower the threshold voltage of the memory cell into the erase data state S0.

[0156] One technique to erase memory cells in some memory devices is to bias the p-well (or other type of) substrate to a high voltage to charge the NAND channel. When the NAND channel is at a high voltage, an erase enable voltage (e.g., a low voltage) is applied to the control gate of the memory cell to erase the non-volatile storage element (memory cell). This is referred to herein as p-well erase.

[0157] Another method to erase memory cells is to generate a gate induced drain leakage (GIDL) current to charge the NAND string channel. An erase enable voltage is applied to the control gate of the memory cell while the NAND string channel potential is maintained to erase the memory cell. This is referred to herein as GIDL erase. Both p-well erase and GIDL erase can be used to lower the threshold voltage (Vt) of the memory cell.

[0158] In one embodiment, the GIDL current is generated by inducing a drain-to-gate voltage at the select transistor (e.g., SGD and / or SGS). The transistor drain-to-gate voltage that generates the GIDL current is referred to herein as the GIDL voltage. The GIDL current can be generated when the select transistor drain voltage is significantly higher than the select transistor control gate voltage. The GIDL current is a result of carrier generation, i.e., electron-hole pair generation and / or trap assisted generation due to band-to-band tunneling. In one embodiment, the GIDL current can cause one type of carrier (e.g., holes) to predominantly move into the NAND channel, thereby raising the potential of the channel. The other type of carrier (e.g., electrons) is extracted from the channel by the electric field in the direction of the bit line or in the direction of the source line. During erase, the holes can tunnel from the channel to the charge storage region of the memory cell and recombine with the electrons therein to lower the threshold voltage of the memory cell.

[0159] The GIDL current can be generated at either end of the NAND string. A first GIDL voltage can be generated between two terminals of a select transistor (e.g., a drain side select transistor) connected to a bit line to generate a first GIDL current. A second GIDL voltage can be generated between two terminals of a select transistor (e.g., a source side select transistor) connected to a source line to generate a second GIDL current. Erase based on GIDL current at only one end of the NAND string is referred to as single-sided GIDL erase. Erase based on GIDL current at both ends of the NAND string is referred to as double-sided GIDL erase.

[0160] Figure 29 is a flow diagram that describes one embodiment of a process for performing a read operation. Figure 29 The process of Figure 24 is one example implementation of the process of Figure 29In step 1302, the integrated memory component 130 receives a request to perform a read operation, including receiving one or more read addresses. For example, the control die 302 can receive a read command and read addresses from a memory controller. In step 1304, the control die 304 applies one or more read reference voltages. For example, the word line drivers described above can be used by the control die 304 to drive any of the read reference voltages (e.g., Vrl, Vr2, Vr3, Vr4, Vr5, Vr6, and / or Vr7) on the selected word lines. Additionally, the select lines (Top_SGL and Bottom_SGL) are as described above in connection with Figure 12A or Figure 12B the biasing (or another suitable biasing scheme) depicted above. In step 1306, in response to the one or more read reference voltages on the selected word lines, a first plurality of sense amplifiers on the memory die sense conditions of a first plurality of memory cells (e.g., a first sub-block) via a first plurality of bit lines (e.g., bit lines under the memory structure). In step 1308, in response to the one or more read reference voltages on the selected word lines, a second plurality of sense amplifiers on the control die sense conditions of a second plurality of memory cells (e.g., a second sub-block of the same block as the first sub-block) via a second plurality of bit lines (e.g., bit lines under the memory structure). Steps 1306 and 1308 are performed simultaneously so that both sub-blocks of each plane are read simultaneously.

[0161] Figure 30 is a block diagram depicting more details of one embodiment of an integrated memory component implementing a three-die system. For example, Figure 30 depicts the control die 304 interfacing with the memory die 302 as described above in connection with Figure 13 and further depicts an additional control die 1400 (third die) interfacing (connected) with the memory die 302. In one embodiment, the control die 1400 has the same structure as the control die 304, including the control circuitry made up of the plurality of sense amplifiers 350. In some embodiments, the control die 1400 has the plurality of sense amplifiers 350 like the control die 304, but the control die 1400 does not include the word line drivers and other logic components that do not need to be replicated in the control die 1400 (as compared to the control die 304).

[0162] Each sense amplifier 350 is connected to one bit line. Three representative bit lines (BL1, BL2, and BL3) are depicted. The bit line BL3 can be positioned under or over the memory cells. For example, Figure 9 shows half of the bit lines connected to the sense amplifiers on the memory die 302 and half of the bit lines connected to the sense amplifiers on the control die 304, while in Figure 30In one embodiment, zero or more bit lines below the memory array can be connected to the sense amplifier of the control die 1400, and zero or more bit lines above the memory array can be connected to the sense amplifier of the control die 1400. Thus, the sense amplifier on memory die 302 is connected to a first group of memory cells in the block, the sense amplifier on control die 304 is connected to a second group of memory cells in the same block, and the sense amplifier on control die 1400 is connected to a third group of memory cells in the same block. In an exemplary embodiment, the sense amplifier on memory die 302 is connected to memory cells in a first sub-block of the block, the sense amplifier on control die 304 is connected to memory cells in a second sub-block of the same block, and the sense amplifier on control die 1400 is connected to memory cells in a third sub-block of the same block.

[0163] The memory die 302 also includes bonding pads 1402. The control die 1400 includes bonding pads 1404 connected to the bonding pads 1402. There may be "n" bonding pads 1402 and "n" bonding pads 1404 to transmit signals between the bit lines of the memory die 302 and the sense amplifier of the control die 1400.

[0164] exist Figure 13 In the implementation scheme, the control circuit of memory die 302 performs memory operations on a first subset of memory cells, while the control circuit of control die 304 performs memory operations on a second subset of memory cells. Figure 30 In one embodiment, the control circuitry of control die 1400 is configured to perform memory operations on a third subset of memory cells while the control circuitry of memory die 302 performs memory operations on a first subset of memory cells and the control circuitry of control die 304 performs memory operations on a second subset of memory cells. Other embodiments may include additional control dies (e.g., more than two control dies, wherein the sense amplifier is connected to a bit line on the memory die).

[0165] A memory has been described that includes control circuitry (e.g., including sense amplifiers) on the same die as the memory array and control circuitry (e.g., including sense amplifiers) on a different die from the memory array, so that the number of sense amplifiers (or equivalent circuitry) can be increased. Increasing the number of sense amplifiers improves parallelism, which in turn improves the performance of the memory system. Furthermore, the increased parallelism allows for more efficient utilization of power and additional functions.

[0166] One embodiment includes a non-volatile storage device including a first semiconductor die and a second semiconductor die. The first semiconductor die includes a substrate, a first control circuit positioned on the substrate, and non-volatile memory cells positioned directly above the first control circuit. The second semiconductor die includes a second control circuit on a substrate. The second semiconductor die also includes an interface for a memory controller and an interface for the first semiconductor die. The second semiconductor die is directly connected to the first semiconductor die. The first control circuit is configured to perform memory operations on a first subset of the non-volatile memory cells while the second control circuit is configured to perform memory operations on a second subset of the non-volatile memory cells simultaneously.

[0167] In one example embodiment, the non-volatile memory cells are organized into blocks of non-volatile memory cells; the first subset of non-volatile memory cells and the second subset of non-volatile memory cells are part of a first block and connected to a first word line; the first block is divided into a plurality of sub-blocks including a first sub-block and a second sub-block; the first subset of non-volatile memory cells is in the first sub-block; the second subset of non-volatile memory cells is in the second sub-block; the first control circuit includes a first set of sense amplifiers connected to the first subset of non-volatile memory cells in the first sub-block; and the second control circuit includes a second set of sense amplifiers connected to the second subset of non-volatile memory cells in the second sub-block.

[0168] One example embodiment also includes a third semiconductor die including a third control circuit, the third semiconductor die connected to the first semiconductor die, the third control circuit configured to perform memory operations on a third subset of the non-volatile memory cells simultaneously with the first control circuit performing memory operations on the first subset of the non-volatile memory cells and the second control circuit performing memory operations on the second subset of the non-volatile memory cells.

[0169] One embodiment includes a non-volatile storage device including a memory controller and an integrated memory component separate from the memory controller and in communication with the memory controller via a communication path. The integrated memory component includes a memory die and a control die bonded to the memory die. The memory die includes a three-dimensional non-volatile memory structure and a first plurality of sense amplifiers. The first plurality of sense amplifiers is connected to the memory structure and positioned on a substrate of the memory die and between the memory structure and the substrate such that the memory structure is directly above the first plurality of sense amplifiers. The control die has a first interface for communication with the memory controller and a second interface for communication with the memory die. The second interface is wider than the first interface. The control die includes a second plurality of sense amplifiers connected to the memory structure via the second interface. The first plurality of sense amplifiers and the second plurality of sense amplifiers are configured for simultaneous writing of data to the memory structure.

[0170] In one example implementation, the first plurality of sense amplifiers and the second plurality of sense amplifiers are configured for reading data from the memory structure such that the first plurality of sense amplifiers is used to read data from a first portion of the memory structure and the second plurality of sense amplifiers is used to simultaneously read data from a second portion of the memory structure.

[0171] One embodiment includes a method of operating a non-volatile storage device, the method including receiving a request to perform a memory operation at an integrated memory component, the integrated memory component including a memory die and a control die bonded to the memory die, the memory die including a three-dimensional non-volatile memory structure and a first plurality of sense amplifiers, the control die including a second plurality of sense amplifiers connected to the memory structure, the memory structure organized into blocks of non-volatile memory cells; and performing the memory operation on a first portion of a first block of non-volatile memory cells with the first plurality of sense amplifiers simultaneously with performing the memory operation on a second portion of the first block of non-volatile memory cells with the second plurality of sense amplifiers.

[0172] For the purposes of this document, reference to “an embodiment,” “one embodiment,” “some embodiments,” or “another embodiment” can be used to describe different embodiments or the same embodiment.

[0173] For the purposes of this document, a connection can be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, it can be directly connected to the other element or indirectly connected to the other element via an intervening element. When an element is referred to as being directly connected to another element, then there are no intervening elements between the element and the other element. Two devices are “in communication” if they are directly or indirectly connected such that they are able to communicate electronic signals between them.

[0174] For the purposes of this document, the term “based on” can be understood as “based at least in part on.”

[0175] For the purposes of this document, the use of the term “about” in conjunction with a numerical value or a range of values can be understood as “substantially around” or “substantially approximately”.

[0176] For the purposes of this document, the term “group” of objects can refer to a “set” of one or more objects.

[0177] The detailed description provided above is presented in terms of specific embodiments. The description provided is intended for the purposes of illustrating and describing the principles of the proposed technology and its practical application, thereby enabling others skilled in the art to best utilize it in various embodiments and with various modifications as are suited to the particular use contemplated. The scope of the technology is defined by the appended claims.

Claims

1. A non-volatile storage device, comprising: A first semiconductor die, the first semiconductor die including a substrate, a first control circuit positioned on the substrate, and a non-volatile memory cell positioned directly above the first control circuit; and A second semiconductor die, the second semiconductor die including a second control circuit, the second semiconductor die further including an interface for a memory controller and an interface for the first semiconductor die, the second semiconductor die being directly connected to the first semiconductor die, the first control circuit being configured to perform memory operations on a first subset of the non-volatile memory cells, and the second control circuit being configured to perform the memory operations on a second subset of the non-volatile memory cells.

2. The non-volatile storage device according to claim 1, wherein: The first control circuit is configured to perform the memory operation on a first subset of the non-volatile memory cells, while the second control circuit simultaneously performs the memory operation on a second subset of the non-volatile memory cells.

3. The non-volatile storage device according to claim 1, wherein: The first control circuit includes a first set of sensing amplifiers connected to the first subset of the non-volatile memory cells; The second control circuit includes a second set of sense amplifiers connected to the second subset of the non-volatile memory cells; and The first set of sense amplifiers is configured to perform the memory operation on a first subset of the non-volatile memory cells, while the second set of sense amplifiers is configured to perform the memory operation on a second subset of the non-volatile memory cells simultaneously.

4. The non-volatile storage device according to claim 3, wherein: The non-volatile memory cells are organized into blocks of non-volatile memory cells; The first subset of the non-volatile memory cells and the second subset of the non-volatile memory cells are part of the same block and connected to the same word line.

5. The non-volatile storage device according to claim 4, further comprising: The first plurality of bit lines are below the non-volatile memory cells and are connected to the first set of sense amplifiers and the first subset of the non-volatile memory cells. and The second plurality of bit lines, above the non-volatile memory cells, are connected to the second set of sense amplifiers and the second subset of the non-volatile memory cells.

6. The non-volatile memory device according to claim 5, wherein the first semiconductor die further comprises: A first source line is located above the non-volatile memory cell and is connected to the first subset of the non-volatile memory cell. and The second source line is located below the non-volatile memory cell and is connected to the second subset of the non-volatile memory cell.

7. The non-volatile storage device according to claim 6, wherein: The first source line is continuous on the same block.

8. The non-volatile storage device according to claim 6, wherein: The first source electrode line is divided into discontinuous segments.

9. The non-volatile storage device according to claim 1, wherein: The non-volatile memory cell is part of a vertical NAND string, each of the vertical NAND strings including a first select gate at a first end and a second select gate at a second end; The first select gate of the NAND string is connected by a first select line, which serves as the source-side select line for a first subset of the NAND string and the drain-side select line for a second subset of the NAND string. and The second select gate of the NAND string is connected via a second select line, which serves as the drain-side select line for the first subset of the NAND string and the source-side select line for the second subset of the NAND string.

10. The non-volatile storage device according to claim 1, wherein: The non-volatile memory cells are organized into blocks of non-volatile memory cells; The first subset of the non-volatile memory cells and the second subset of the non-volatile memory cells are part of a first block and connected to a first word line; The first block is divided into multiple sub-blocks, including a first sub-block and a second sub-block; The first subset of the non-volatile memory cells is in the first sub-block; The second subset of the non-volatile memory cells is in the second sub-block; The first control circuit includes a first set of sense amplifiers connected to a first subset of the non-volatile memory cells in the first sub-block; and The second control circuit includes a second set of sense amplifiers connected to the second subset of the non-volatile memory cells in the second sub-block.

11. The non-volatile storage device according to claim 10, wherein: A third subset of the non-volatile memory cells is connected to the first word line and is located in the third sub-block of the first block; The fourth subset of the non-volatile memory cells is connected to the first word line and is located in the fourth sub-block of the first block; The first control circuit is connected to the third subset of the non-volatile memory cells; The second control circuit is connected to the fourth subset of the non-volatile memory cells; The first control circuit is configured to perform the memory operation on the third subset of the non-volatile memory cells, while the second control circuit simultaneously performs the memory operation on the fourth subset of the non-volatile memory cells.

12. The non-volatile storage device according to claim 1, further comprising: A third semiconductor die, the third semiconductor die including a third control circuit, the third semiconductor die being connected to the first semiconductor die, the third control circuit being configured to: perform the memory operation on a third subset of the non-volatile memory cells while the first control circuit performs the memory operation on a first subset of the non-volatile memory cells and the second control circuit performs the memory operation on a second subset of the non-volatile memory cells.

13. A non-volatile storage device, comprising: Memory controller; and An integrated memory assembly, separate from and communicating with a memory controller via a communication path, includes a memory die and a control die bonded to the memory die. The memory die includes a three-dimensional non-volatile memory structure and a first plurality of sense amplifiers connected to the memory structure and positioned on a substrate of the memory die and between the memory structure and the substrate, such that the memory structure is directly above the first plurality of sense amplifiers. The control die has a first interface for communicating with the memory controller and a second interface for communicating with the memory die, the second interface being wider than the first interface. The control die includes a second plurality of sense amplifiers connected to the memory structure via the second interface. The first plurality of sense amplifiers and the second plurality of sense amplifiers are configured to write data to the memory structure.

14. The non-volatile storage device according to claim 13, wherein: The first plurality of sensing amplifiers and the second plurality of sensing amplifiers are configured to write data into the memory structure, such that the first plurality of sensing amplifiers are used to write data into a first portion of the memory structure, while the second plurality of sensing amplifiers are used to simultaneously write data into a second portion of the memory structure.

15. The non-volatile storage device according to claim 13, wherein: The first plurality of sensing amplifiers and the second plurality of sensing amplifiers are configured to read data from the memory structure, such that the first plurality of sensing amplifiers are used to read data from a first portion of the memory structure, while the second plurality of sensing amplifiers are used to simultaneously read data from a second portion of the memory structure.

16. The non-volatile storage device according to claim 13, wherein: The memory structure is organized into blocks of non-volatile memory cells; and The first plurality of sense amplifiers and the second plurality of sense amplifiers are configured to write data into the memory structure such that the first plurality of sense amplifiers are used to write data into memory cells in a first subset of memory cells of a block of memory cells, while the second plurality of sense amplifiers are used to simultaneously write data into a second subset of memory cells of the block of memory cells, the first subset of memory cells and the second subset of memory cells being connected to a selected word line.

17. A method of operating a non-volatile memory device, comprising: A request is received to perform a memory operation at an integrated memory assembly, the integrated memory assembly including a memory die and a control die coupled to the memory die, the memory die including a three-dimensional non-volatile memory structure and a first plurality of sense amplifiers, the control die including a second plurality of sense amplifiers connected to the memory structure, the memory structure being organized into blocks of non-volatile memory cells; as well as The memory operation is performed on a first portion of a first block of the non-volatile memory cell using the first plurality of sense amplifiers, while the memory operation is performed on a second portion of the first block of the non-volatile memory cell using the second plurality of sense amplifiers.

18. The method of claim 17, wherein: The first portion of the first block of the non-volatile memory cell includes a first plurality of memory cells connected to a selected word line, a first source line above the memory structure, and a first plurality of bit lines below the memory structure; The first plurality of bit lines are connected to the first plurality of sensing amplifiers; The second portion of the first block of the non-volatile memory cell includes a second plurality of memory cells connected to the selected word line, a second source line below the memory structure, and a second plurality of bit lines above the memory structure; and The second plurality of bit lines are connected to the second plurality of sensing amplifiers.

19. The method of claim 18, wherein: The step of performing the memory operation on the first portion of the first block of the non-volatile memory cells using the first plurality of sensing amplifiers includes: in response to a read reference voltage on the selected word line, the first plurality of sensing amplifiers on the memory die sense the status of the first plurality of memory cells via the first plurality of bit lines; and The method of performing the memory operation on the second portion of the first block of the non-volatile memory cell using the second plurality of sensing amplifiers includes: in response to the read reference voltage on the selected word line, the second plurality of sensing amplifiers on the control die sense the status of the second plurality of memory cells via the second plurality of bit lines.

20. The method of claim 18, wherein: The step of performing the memory operation on the first portion of the first block of the non-volatile memory cells using the first plurality of sense amplifiers includes: the first plurality of sense amplifiers on the memory die providing programming conditions on the first plurality of bit lines, while simultaneously driving a programming voltage on the selected word line; and The method of performing the memory operation on the second portion of the first block of the non-volatile memory cell using the second plurality of sense amplifiers includes: the second plurality of sense amplifiers on the control die providing programming conditions on the second plurality of bit lines while driving a programming voltage on the selected word line.

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