Memory devices and operating methods using plane-dependent ramp rate and timing control for program operation

Abstract

The present invention is entitled "Memory Device and Operation Method for Program Operation Using Plane-Related Ramp Rate and Timing Control". The present invention provides a memory device and operation method. The device includes memory cells connected to word lines and bit lines and arranged in a plurality of planes. The device also includes control circuitry coupled to the word lines and bit lines and configured to determine whether a program operation of the memory cell involves all of the plurality of planes. In response to the program operation of the memory cell not involving all of the plurality of planes, the control circuitry adjusts at least one of a bit line ramp rate applied to the bit line and a word line ramp rate applied to at least one word line voltage applied to the word line during the program operation based on an amount of the plurality of planes associated with the memory cell being programmed and verified in the program operation.

Description

Technical Field

[0001] This application relates to the operation of non-volatile memory devices. Background Technology

[0002] This section provides background information related to the technology associated with this disclosure, and is not necessarily prior art.

[0003] Charge-trapping materials can be used in memory devices to store charges representing data states. These materials can be arranged vertically in a three-dimensional (3D) stacked memory structure or horizontally in a two-dimensional (2D) memory structure. An example of a 3D memory structure is the Bit Cost Scalable (BiCS) architecture, which comprises a stack of alternating conductive and dielectric layers. Memory vias are formed in the stack, and NAND strings are then formed by filling these vias with a material including the charge-trapping layers. Straight NAND strings extend within a single memory via, while tubular or U-shaped NAND strings (P-BiCS) consist of a vertical column of a pair of memory cells extending within two memory vias and joined by a bottom back gate. The control gate for the memory cells is provided by the conductive layer.

[0004] However, operating such memory devices presents various challenges. For example, various voltages are applied to the bit lines and word lines at specific times during program operation. The rate at which these voltages are applied can affect the current consumption of the memory device and the speed of programming operations. Summary of the Invention

[0005] This section provides a general overview of the disclosure and is not a full disclosure of its entire scope or all its features and advantages.

[0006] The purpose of this disclosure is to provide a memory device and a method for operating the memory device that solves and overcomes the above-mentioned disadvantages.

[0007] Therefore, one aspect of this disclosure is to provide an apparatus comprising a plurality of memory cells connected to word lines and bit lines and arranged in a plurality of planes. The apparatus further includes control circuitry coupled to the word lines and bit lines and configured to determine whether program operation of the plurality of memory cells involves all of the plurality of planes. In response to program operation of the plurality of memory cells not involving all of the plurality of planes, the control circuitry is configured to adjust, during program operation of the plurality of memory cells, at least one of a bit line ramp rate of a bit line voltage applied to the bit lines and a word line ramp rate of at least one word line voltage applied to the word lines, based on an amount of the plurality of planes associated with the plurality of memory cells being programmed and verified during program operation.

[0008] According to another aspect of this disclosure, a controller is provided for communicating with a memory device including a plurality of memory cells connected to word lines and bit lines and arranged in a plurality of planes. The controller is configured to determine whether program operations on the plurality of memory cells involve all of the plurality of planes. In response that program operations on the plurality of memory cells do not involve all of the plurality of planes, the controller instructs the memory device during program operations on the plurality of memory cells to adjust at least one of a bit line ramp rate of a bit line voltage applied to the bit lines and a word line ramp rate of at least one word line voltage applied to the word lines, based on an amount of the plurality of planes associated with the plurality of memory cells being programmed and verified during the program operations.

[0009] According to an additional aspect of this disclosure, a method of operating a memory device is provided. The memory device includes a plurality of memory cells connected to word lines and bit lines and arranged in a plurality of planes. The method includes the step of determining whether program operation of the plurality of memory cells involves all of the plurality of planes. A next step of the method is, in response to the program operation of the plurality of memory cells not involving all of the plurality of planes, adjusting at least one of a bit line ramp rate of a bit line voltage applied to the bit lines and a word line ramp rate of at least one word line voltage applied to the word lines during program operation of the plurality of memory cells based on an amount of the plurality of planes associated with the plurality of memory cells being programmed and verified in the program operation.

[0010] Further applicable fields will become apparent from the description provided herein. The descriptions and specific examples in this invention are intended for illustrative purposes only and are not intended to limit the scope of the invention. Attached Figure Description

[0011] The accompanying drawings described herein are for illustrative purposes only, and not for all possible specific implementations, and are not intended to limit the scope of this disclosure.

[0012] Figure 1A A block diagram of an exemplary non-volatile memory system according to various aspects of this disclosure;

[0013] Figure 1B It is a block diagram of a storage module comprising multiple non-volatile memory systems according to various aspects of this disclosure;

[0014] Figure 1C A block diagram of a hierarchical storage system according to various aspects of this disclosure;

[0015] Figure 2A Based on all aspects of this disclosure Figure 1A A block diagram of exemplary components of a controller for a non-volatile memory system;

[0016] Figure 2BBased on all aspects of this disclosure Figure 1A A block diagram of exemplary components of a non-volatile memory die for a non-volatile memory system;

[0017] Figure 3 A block diagram of an example floating-gate transistor according to various aspects of this disclosure;

[0018] Figure 4 It is a graph of the drain-source current as a function of the control gate voltage drawn by the floating gate transistor, according to various aspects of this disclosure;

[0019] Figure 5A It is a block diagram of multiple memory cells organized into blocks according to various aspects of this disclosure;

[0020] Figure 5B It is a block diagram of multiple memory cells organized into blocks in different planes according to various aspects of this disclosure;

[0021] Figure 6 This is a circuit diagram of an example two-dimensional NAND flash memory array based on various aspects of this disclosure;

[0022] Figure 7 This is an example physical structure of a three-dimensional (3-D) NAND string according to various aspects of this disclosure;

[0023] Figure 8 This is an example physical structure of a U-shaped 3-D NAND string according to various aspects of this disclosure;

[0024] Figure 9 An example configuration of a block of 3-D NAND memory array according to various aspects of this disclosure is depicted;

[0025] Figure 10A It is a cross-sectional view along the bit line direction (along the y direction) of an example memory structure according to various aspects of this disclosure, wherein a straight vertical NAND string extends from a common source connection in or near the substrate to a global bit line extending above the physical level of the memory cell;

[0026] Figure 10B Based on all aspects of this disclosure Figure 10A Circuit diagram of a single optional NAND string group;

[0027] Figure 10C It is a circuit diagram of a single optional NAND string group in a cross section along the xz plane according to various aspects of this disclosure;

[0028] Figure 11A It is a graph of the threshold voltage distribution curve of a memory cell storing two bits of data according to various aspects of this disclosure;

[0029] Figure 11B It is a graph of the threshold voltage distribution curve of a memory cell storing three-bit data according to various aspects of this disclosure.

[0030] Figure 11C It is a graph of the threshold voltage distribution curve of the memory cell storing four-bit data according to various aspects of this disclosure.

[0031] Figure 12 For the purposes of this disclosure Figure 2B A block diagram of an example configuration of the sensing block;

[0032] Figure 13A A graph showing programming time versus bit line voltage ramp rate parameters according to various aspects of this disclosure is provided.

[0033] Figure 13B Peak current and bit line voltage ramp rate parameters according to various aspects of this disclosure are shown;

[0034] Figure 14A The graphs showing the peak current versus bit line voltage ramp rate parameters for a device having two planes with various timings according to aspects of this disclosure are shown.

[0035] Figure 14B A graph showing the current consumption of the device over a period of time for multiple values ​​of the bit line voltage ramp rate parameter during program operation, according to various aspects of this disclosure;

[0036] Figure 15A and Figure 15B An example default bit line voltage ramp rate lookup table and an example shift bit line voltage ramp rate lookup table are shown according to various aspects of this disclosure for adjusting the bit line voltage ramp rate parameter or bit line voltage applied to the bit line.

[0037] Figure 16 Example graphs of high-voltage power supply levels VDDSA, VHSA, and corresponding peak currents according to various aspects of this disclosure are shown.

[0038] Figure 17A and Figure 17B Examples of default voltage ramp lookup tables and example shift voltage ramp lookup tables are shown according to various aspects of this disclosure;

[0039] Figure 18A and Figure 18B Examples of default read voltage ramp rate lookup tables and examples of shift read voltage ramp rate lookup tables are shown according to various aspects of this disclosure;

[0040] Figure 19A and Figure 19BExamples of default lookup tables by voltage ramp change time periods and examples of shift lookup tables by voltage ramp change time periods are shown according to various aspects of this disclosure;

[0041] Figure 20A and Figure 20B Examples of default read voltage ramp change time period lookup tables and example shift read voltage ramp change time period lookup tables are shown according to various aspects of this disclosure;

[0042] Figure 21 The diagram illustrates how, according to various aspects of this disclosure, a graph of voltage versus time is referenced to determine the voltage ramp rate or read voltage; and

[0043] Figure 22 The steps of a method for operating a memory device according to various aspects of this disclosure are shown. Detailed Implementation

[0044] In the following description, details are set forth to provide an understanding of this disclosure. In some instances, certain circuits, structures, and techniques have not been described or shown in detail so as not to obscure this disclosure.

[0045] Generally, this disclosure relates to a type of nonvolatile memory device that is well-suited to many applications. The nonvolatile memory device and associated methods of operation of this disclosure will be described in conjunction with one or more exemplary embodiments. However, the specific exemplary embodiments disclosed are merely for the purpose of clearly describing the concepts, features, advantages, and objects of the invention to allow those skilled in the art to understand and practice this disclosure. Specifically, exemplary embodiments are provided so that this disclosure will be comprehensive and will fully convey the scope to those skilled in the art. Numerous specific details, such as examples of specific components, apparatus, and methods, are set forth to provide a thorough understanding of embodiments of this disclosure. It will be apparent to those skilled in the art that specific details are not required, exemplary embodiments may be embodied in many different forms, and none should be construed as limiting the scope of this disclosure. In some exemplary embodiments, well-known processes, well-known apparatus structures, and well-known techniques are not described in detail.

[0046] In some memory devices or apparatuses, memory cells are joined together, such as in NAND strings within a block or sub-block. Each NAND string comprises a plurality of memory cells connected in series between one or more drain-side SG transistors (SGD transistors) on the drain side of the NAND string connected to a bit line and one or more source-side SG transistors (SGS transistors) on the source side of the NAND string connected to a source line. Furthermore, the memory cells may be arranged with a common control gate line (e.g., a word line) serving as a control gate. A set of word lines extends from the source side of the block to the drain side of the block. Memory cells may be connected in other types of string connections and in other ways.

[0047] In a 3D memory architecture, memory cells can be arranged in a stacked vertical string, wherein the stack includes alternating conductive and dielectric layers. The conductive layers serve as word lines connecting to the memory cells. Memory cells may include data memory cells eligible to store user data, as well as dummy memory cells or non-data memory cells not eligible to store user data.

[0048] Each memory cell can be associated with a data state based on the data written in the program command. Based on the data state of that memory cell, the memory cell will remain in an erase state or be programmed into a programmed data state. For example, in a one-bit memory device or apparatus per cell, there are two data states: an erase state and a programmed state. In a two-bit memory device per cell, there are four data states, including an erase state and three higher data states, referred to as A, B, and C data states (see [link to documentation]). Figure 11A In a three-bit memory device, there are eight data states, including an erase state and seven higher data states, referred to as A, B, C, D, E, F, and G data states (see also...). Figure 11B In each 4-bit memory device, there are sixteen data states, including the erase state and fifteen higher data states (see [link to relevant documentation]). Figure 11C ).

[0049] The various stages of programming a memory device may require variable current, resulting in the total current consumed by the device during program operation. For example, during programming, various voltages are applied to the bit lines and word lines at specific times. The rate at which these voltages are applied can affect current consumption and the speed of the programming operation. However, the host or device using the memory device or apparatus may have current consumption limitations that restrict how the various voltages are applied to the bit lines and word lines.

[0050] Figure 1AThis is a block diagram illustrating a memory system 100. The memory system 100 may include a controller 102 and a memory that may be composed of one or more memory dies 104. As used herein, the term die refers to a set of memory cells formed on a single semiconductor substrate and the associated circuitry for managing the physical operations of these memory cells. The controller 102 may be connected to a host system and send sequences of commands for read, program, and erase operations to the non-memory dies 104.

[0051] The controller 102 (which may be a flash memory controller) may take the form of, for example, processing circuitry, a microprocessor or processor, and a computer-readable medium (e.g., software or firmware) storing computer-readable program code executable by the (micro)processor, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers. The controller 102 may be configured with hardware and / or firmware to perform the various functions described below and shown in the flowcharts. Additionally, some components shown as internal to the controller may also be stored externally, and other components may be used. Furthermore, the phrase "operationally communicating with..." may mean communicating directly or indirectly (wired or wirelessly) with one or more components, or communicating through one or more components, which may or may not be shown herein.

[0052] As used herein, controller 102 is a device that manages data stored in a memory die and communicates with a host, such as a computer or electronic device. In addition to the specific functions described herein, controller 102 may also have various other functions. For example, controller 102 may format memory die 104 to ensure its proper functioning, identify bad flash memory cells, and allocate spare cells to replace cells that fail in the future. Some portions of the spare cells may be used to maintain firmware to operate controller 102 and implement other features. In operation, when the host needs to read data from or write data to memory die 104, the host communicates with controller 102. If the host provides a logical address to which data is to be read / written, controller 102 may translate the logical address received from the host into a physical address in memory die 104. (Alternatively, the host may provide a physical address). Controller 102 may also perform various memory management functions, such as, but not limited to, wear leveling (allocating writes to specific memory blocks to avoid wear that would otherwise be repeatedly written to) and garbage collection (moving only valid data pages to a new block after a block is full, so that the entire block can be erased and reused).

[0053] The interface between the controller 102 and the non-volatile memory die 104 can be any suitable interface, such as a flash memory interface, including interfaces configured to switch modes 200, 400, 800, 1000, or higher. For some exemplary embodiments, the memory system 100 can be a card-based system, such as a Secure Digital (SD) or Micro Secure Digital (Micro SD) card. In another exemplary embodiment, the memory system 100 can be part of an embedded memory system.

[0054] exist Figure 1A In the illustrated embodiment, memory system 100 is shown as including a single channel between controller 102 and non-volatile memory die 104. However, the subject matter described herein is not limited to memory systems with a single memory channel. For example, in some memory systems, such as those embodying a NAND architecture, there may be 2, 4, 8, or more channels between controller 102 and memory die 104, depending on controller capabilities. In any embodiment described herein, even if a single channel is shown in the figures, there may be more than one single channel between the controller and memory die 104.

[0055] Figure 1B A storage module 200 comprising multiple non-volatile memory systems 100 is illustrated. Therefore, the storage module 200 may include a storage controller 202 connected to a host and a storage system 204 comprising multiple non-volatile memory systems 100. The interface between the storage controller 202 and the non-volatile memory systems 100 may be a bus interface, such as Serial Advanced Technology Attachment (SATA), Peripheral Component Interface Express (PCIe), Embedded Multimedia Card (eMMC), SD, or Universal Serial Bus (USB) interfaces, as examples. In one embodiment, the storage module 200 may be a solid-state drive (SSD), such as those found in portable computing devices (such as laptops and tablets) and mobile phones.

[0056] Figure 1C This is a block diagram illustrating a hierarchical storage system 210. The hierarchical storage system 210 may include multiple storage controllers 202, each controlling a corresponding storage system 204. A host system 212 may access the memory within the hierarchical storage system 210 via a bus interface. As an example, exemplary bus interfaces may include non-volatile memory express (NVMe), a Fibre Channel over Ethernet (FCoE) interface, an SD interface, a USB interface, a SATA interface, a PCIe interface, or an eMMC interface. In one embodiment, Figure 1CThe storage system 210 shown may be a rack-mountable, high-capacity storage system accessible by multiple host computers, such as one that would exist in a data center or other location requiring high-capacity storage.

[0057] Figure 2A This is a block diagram showing exemplary components of controller 102 in more detail. Controller 102 may include a front-end module 108 that interacts with a host, a back-end module 110 that interacts with a non-volatile memory die 104, and various other modules that perform various functions of the non-volatile memory system 100. Generally, modules may be hardware or a combination of hardware and software. For example, each module may include an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), circuits, digital logic circuits, analog circuits, discrete circuits, gates, or any other type of hardware, or a combination thereof. In addition or alternatively, each module may include memory hardware including instructions executable by a processor or processor circuitry to implement one or more of the features of the module. When any of the modules includes a portion of the memory comprising instructions executable by a processor, the module may or may not include a processor. In some examples, each module may consist only of a portion of the memory comprising instructions executable by a processor to implement the features of the corresponding module, and the module may not include any other hardware. Because each module includes at least some hardware, each module may be interchangeably referred to as a hardware module even when the included hardware includes software.

[0058] Controller 102 may include a buffer manager / bus controller module 114, which manages buffers in random access memory (RAM) 116 and controls internal bus arbitration for communication on the internal communication bus 117 of controller 102. Read-only memory (ROM) 118 may store and / or access system boot codes. Although Figure 2A The RAM 116 and ROM 118 are shown positioned separately from the controller 102, but in other embodiments, one or both of them may be located within the controller 102. In other embodiments, portions of the RAM 116 and ROM 118 may be located both inside and outside the controller 102. Furthermore, in some embodiments, the controller 102, RAM 116, and ROM 118 may be located on separate semiconductor dies.

[0059] Additionally, the front-end module 108 may include a host interface 120 and a physical layer interface (PHY) 122 that provide an electrical interface to the host or a next-level storage controller. The type of host interface 120 may be selected depending on the type of memory used. Examples of host interface 120 types may include, but are not limited to, SATA, SATA Express, SAS, Fibre Channel, USB, PCIe, and NVMe. Host interface 120 may generally facilitate the transmission of data, control signals, and timing signals.

[0060] Backend module 110 may include an error correction code (ECC) engine or module 124 that encodes data bytes received from the host and decodes and error-corrects data bytes read from non-volatile memory die 104. Backend module 110 may also include a command sequencer 126 that generates command sequences, such as programming, reading, and erasing command sequences, for transmission to non-volatile memory die 104. Additionally, backend module 110 may include a RAID (Redundant Array of Independent Drives) module 128 that manages the generation of RAID parity and the recovery of failed data. RAID parity can be used as an additional level of integrity protection for data written to non-volatile memory system 100. In some cases, RAID module 128 may be part of ECC engine 124. Memory interface 130 provides command sequences to non-volatile memory die 104 and receives status information from non-volatile memory die 104. Along with command sequences and status information, data to be programmed into and read from the non-volatile memory die 104 can be transmitted via memory interface 130. In one embodiment, memory interface 130 may be a dual data rate (DDR) interface and / or a switching mode 200, 400, 800, or higher interface. Control layer 132 controls the overall operation of back-end module 110.

[0061] Figure 2A Additional modules for the non-volatile memory system 100 shown may include a media management layer 138, which performs wear leveling, address management, and facilitates folding operations for the memory cells of the non-volatile memory die 104, as described in further detail below. The non-volatile memory system 100 may also include other discrete components 140, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that can interact with the controller 102. In alternative embodiments, one or more of the RAID module 128, the media management layer 138, and the buffer management / bus controller 114 may be optional components that may not be needed in the controller 102.

[0062] Figure 2BThis is a block diagram showing exemplary components of memory die 104 in more detail. Memory die 104 may include a memory cell structure 142 that includes a plurality of memory cells, or memory elements. Any suitable type of memory may be used for memory cell 142. As an example, the memory may be dynamic random access memory (“DRAM”) or static random access memory (“SRAM”), non-volatile memory such as resistive random access memory (“ReRAM”), electrically erasable programmable read-only memory (“EEPROM”), flash memory (which may also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), as well as other semiconductor elements capable of storing information. Each type of memory may have a different configuration. For example, a flash memory device may be configured in a NAND configuration or a NOR configuration.

[0063] The memory can be formed from any combination of passive and / or active elements. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity-switching storage elements such as antifuses, phase-change materials, etc., and optionally include guiding elements such as diodes. As a further non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements having charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0064] Multiple memory elements can be configured such that they are connected in series or that each element can be accessed individually. By way of non-limiting example, a flash memory device (NAND memory) in a NAND configuration typically includes memory elements connected in series. A NAND memory array can be configured such that the array consists of multiple strings of memory, where a string consists of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements can be configured such that each element can be accessed individually, for example, in a NOR memory array. NAND and NOR memory configurations are exemplary, and memory elements can be configured in other ways.

[0065] Semiconductor memory elements located within and / or above a substrate can be arranged in two or three dimensions, such as two-dimensional or three-dimensional memory structures.

[0066] In a two-dimensional memory structure, semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two-dimensional memory structure, the memory elements are arranged in a plane (e.g., in the xz plane) that extends substantially parallel to the main surface of the substrate supporting the memory elements. The substrate may be a wafer on which layers of the memory elements are formed, or it may be a carrier substrate attached to the memory elements after they have been formed. As a non-limiting example, the substrate may include a semiconductor, such as silicon.

[0067] Memory elements can be arranged in a single memory device level in an ordered array (such as in multiple rows and / or columns). However, memory elements can be arranged in unconventional or non-orthogonal configurations. Each memory element may have two or more electrodes or contact lines, such as bit lines and word lines.

[0068] A three-dimensional memory array is arranged such that the memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., x, y and z directions, where the z direction is substantially perpendicular and the x and y directions are substantially parallel to the main surface of the substrate).

[0069] As a non-limiting example, a three-dimensional memory structure can be vertically arranged as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate, i.e., in the z-direction), wherein each column has multiple memory elements. The columns can be arranged in a two-dimensional configuration, for example, in the xy-plane, resulting in a three-dimensional arrangement of the memory elements, where the elements are located on multiple vertically stacked memory planes. Other configurations of the three-dimensional memory elements can also constitute a three-dimensional memory array.

[0070] For some memory configurations, such as flash memory, the memory cells of the multiple memory cells 142 can be floating gate transistors (FGTs). Figure 3 A circuit schematic of an example FGT 300 is shown. The FGT 300 may include a source 302, a drain 304, a control gate 306, a floating gate 308, and a substrate 310. The floating gate 308 may be surrounded by an insulator or insulating material to help retain the charge within the floating gate 308. The presence or absence of charge within the floating gate 308 can cause a shift in the threshold voltage of the FGT, which is used to distinguish logic levels. For each given charge stored in the floating gate 308, a fixed control gate voltage V is applied relative to the control gate 306. CGThe corresponding drain-source conduction current ID. Additionally, the FGT 300 may have an associated range charge programmable onto its floating gate 308, which defines a corresponding threshold voltage window or a corresponding conduction current window. In this way, the threshold voltage of each FGT can indicate the data stored in the memory cell.

[0071] Figure 4 This shows the control gate voltage V applied to the control gate 306. CG The graph illustrates four curves 402, 404, 406, and 408 representing the drain-source current ID drawn by the FGT 300. Each curve 402-408 corresponds to one of four different charges or charge levels Q1, Q2, Q3, and Q4 that the floating gate 308 can selectively store at any given time. In other words, the four curves 402-408 represent four possible charge levels that can be programmed on the floating gate 308 of the FGT 300, each corresponding to one of four possible memory states. Figure 4 In the example illustration, the threshold voltage window of the FGT group ranges from 0.5 volts (V) to 3.5 V. Seven possible memory states “0”, “1”, “2”, “3”, “4”, “5”, and “6” are defined or extended across the threshold voltage window, and respectively represent an erase state and six programming states. The different states can be defined by dividing the threshold voltage window into six regions with 0.5 V intervals. The FGT 300 can be in one of these states depending on the charge stored in its floating gate 308, and its drain-source current ID is related to the reference current I. REF Intersecting. For example, FGT is programmed to store charge Q1 in memory state "1" because its curve 402 intersects with the control gate voltage V. CG The defined threshold voltage region is in the range of 0.5V to 1.0V, corresponding to the reference current I. REF Intersecting. The more memory states the FGT 300 can be programmed to store, the more finely segmented the region defining the threshold voltage window becomes. In some example configurations, the threshold voltage window can extend from -1.5V to 5V, providing a maximum width of 6.5V. If the FGT 300 can be programmed to any of sixteen possible states, each state can occupy a corresponding region spanning from 200 mV to 300 mV. The higher the resolution of the threshold voltage window (i.e., the more states the FGT300 can be programmed to), the higher the precision required for successful data reading and writing during programming and read operations. A further description of memory states and threshold voltages is provided below relative to programming, program verification, and read operations.

[0072] See Figure 5AThe memory cells 142 can be organized into N blocks, extending from the first block 1 to the Nth block N. See also Figure 5B For some example configurations, N blocks are organized into multiple planes. Figure 5B An exemplary configuration of organizing blocks into two planes is shown, including a first plane, Plane 0, and a second plane, Plane 1. Each plane is shown as comprising M blocks, extending from the first block, Block 1, to the Mth block, Block M. As shown, plane 0 includes even-numbered blocks 0, 2, 4, ..., etc., and plane 1 includes odd-numbered blocks 1, 3, 5, ..., etc. It should be understood that although only two planes are shown, the memory device may alternatively include a four-plane architecture (or more planes). For plane 0, the block address is defined as 4n; for plane 1, the block address is defined as 4n+1; for plane 2, the block address is defined as 4n+2; and for plane 3, the block address is defined as 4n+3. Data stored in different planes can be sensed simultaneously or independently.

[0073] For a configuration where memory cells are organized into a two-dimensional array, the memory cells can be configured as a matrix structure of rows and columns within each block. Memory cells are located at the intersections of rows and columns. Columns of memory cells are called strings, and memory cells within a string are electrically connected in series. Rows of memory cells are called pages. In the case of FGTs (Field-Gate Systems), the control gates of the FGTs within a page or row can be electrically connected together.

[0074] Additionally, each block includes word lines and bit lines connected to memory cells. Each page of a memory cell is coupled to a word line. In the case of a memory cell being an FGT, each word line may be coupled to the control gate of the FGT within a page. Furthermore, each memory cell string is coupled to a bit line. Moreover, a single string may span multiple word lines, and the number of memory cells in a string may be equal to the number of pages in the block.

[0075] Figure 6 This is a circuit diagram of at least a portion of an exemplary two-dimensional NAND flash memory array 600, which may represent at least a portion of a plurality of memory cells 142. For example, the memory array 600 may represent a single plane of a block on a memory die 104. The memory array 600 may include N blocks 6020 to 602 N-1 Each block 602 includes P strings of FGT604, where each string is coupled to P bit lines BL0 to BL604. P-1 The corresponding bit line in the [text missing]. Additionally, each box 602 includes M pages of FGT 604, each page coupled to M word lines WL0 to WL0. M-1The corresponding word line in the given block. Each i-th and j-th FGT(i,j) of a given block 602 is connected to the i-th word line WL of the given block. i And connected to the j-th bit line BL j .like Figure 6 As shown, bit lines BL0 to BL P-1 In blocks 6020 to 602 N-1 These bit lines can be shared between blocks, such as blocks within the same plane.

[0076] Within each block 602, each string is connected at one end to an associated drain-select gate transistor 606, and each string is coupled to its associated bit line BL via the associated drain-select gate transistor 606. Drain-select gate transistors 6060 to 606 P-1 The switch can be controlled using a drain-select gate bias line SGD, which provides a drain-select gate bias voltage V. SGD Selecting transistors 6060 to 606 by turning the drain on and off. P-1 Furthermore, within each block 602, each string is connected at its other end to an associated source-select gate transistor 608, and each string is coupled to a common source line SL via the associated source-select gate transistor 608. Source-select gate transistors 6080 to 608 P-1 The switch can be controlled using the source-select gate bias line SGS, which provides the source-select gate bias voltage V. SGS Source selection transistors 6080 to 608 are used to turn the source on and off. P-1 Additionally, although not shown, in some cases, it may also be used in conjunction with source-select gate transistors 6080 to 608. P-1 Adjacent memory arrays 600 use dummy word lines that do not contain user data. Dummy word lines can be used to shield edge word lines and FGT from certain edge effects.

[0077] An alternative arrangement to conventional two-dimensional (2-D) NAND arrays is a three-dimensional (3-D) array. Compared to 2-D NAND arrays formed along the flat surface of a semiconductor wafer, 3-D arrays extend upwards from the wafer surface and typically comprise stacks or columns of upward-extending memory cells. Various 3D arrangements are possible. In one arrangement, NAND strings are formed vertically, with one end (e.g., the source) at the wafer surface and the other end (e.g., the drain) at the top. In another arrangement, NAND strings are formed in a U-shape, allowing access to both ends of the NAND string at the top, thus facilitating connections between such strings.

[0078] Figure 7A first example of a NAND string 701 is shown, which extends in a vertical direction, i.e., in the z-direction perpendicular to the xy-plane of the substrate. Memory cells are formed, in which vertical bit lines (local bit lines) 703 pass through word lines (e.g., WL0, WL1, etc.). A charge-trapping layer between the local bit lines and the word lines stores charge that affects the threshold voltage of the transistors formed by the word lines (gates) coupled to the vertical bit lines (channels) they surround. Such memory cells can be formed by forming a stack of word lines and then etching memory holes in which the memory cells are to be formed. The memory holes are then lined with a charge-trapping layer and filled with a suitable local bit line / channel material (with a suitable dielectric layer for isolation).

[0079] Similar to two-dimensional (planar) NAND strings, selection gates 705 and 707 are located at either end of the string to allow the NAND string to be selectively connected to or isolated from external components 709 and 711. Such external components are typically conductive lines, such as common source lines or bit lines serving a large number of NAND strings. Vertical NAND strings can operate in a similar manner to planar NAND strings, and both single-cell (SLC) and multi-cell (MLC) operations are possible. Although Figure 7 An example of a NAND string with 32 serially connected cells (0-31) is shown, but the number of cells in a NAND string can be any suitable number. For clarity, not all cells are shown. It should be understood that additional cells are formed where word lines 3-29 (not shown) intersect with the local vertical bit lines.

[0080] Figure 8 A second example of a NAND string 815 extending in the vertical direction (z-direction) is shown. In this case, the NAND string 815 forms a U-shape and connects to external components (source line "SL" and bit line "BL") located at the top of the structure. The bottom of the NAND string 815 is a controllable gate (back gate "BG") connecting the two wings 816A and 816B of the NAND string 815. A total of 64 cells are formed where word lines WL0-WL63 intersect with the vertical local bit line 817 (but in other examples, a different number of cells may be provided). Select gates SGS and SGD are located at either end of the NAND string 815 to control the connection / isolation of the NAND string 815.

[0081] Vertical NAND strings can be arranged in various ways to form a 3D NAND array. Figure 9An example of multiple NAND strings connected to bit line BL0 in a block is shown. Specifically, block BLK0 and its sub-blocks SB0 to SB6 are shown. Example NAND strings 900n, 910n, 920n, 930n, 940n, 950n, and 960n are provided in SB0-SB6, respectively. In each sub-block, multiple NAND strings are provided. NAND string 900n includes a channel 900a, an SGS transistor 901, a source-side dummy memory cell 902 connected to the source-side dummy word line WLDS, data memory cells 903-913, a drain-side dummy memory cell 914 connected to the drain-side dummy word line WLDD, and SGD transistors 915-918. This arrangement is convenient but not required, and other configurations are also possible.

[0082] NAND string 910n includes channel 910a, SGS transistor 921, source-side dummy memory cell 922 connected to source-side dummy word line WLDS, data memory cells 923-933, drain-side dummy memory cell 934 connected to drain-side dummy word line WLDD, and SGD transistors 935-938.

[0083] NAND string 920n includes channel 920a, SGS transistor 941, source-side dummy memory cell 942 connected to source-side dummy word line WLDS, data memory cells 943-953, drain-side dummy memory cell 954 connected to drain-side dummy word line WLDD, and SGD transistors 955-958.

[0084] NAND string 930n includes channel 930a, SGS transistor 961, source-side dummy memory cell 962 connected to source-side dummy word line WLDS, data memory cells 963-973, drain-side dummy memory cell 974 connected to drain-side dummy word line WLDD, and SGD transistors 975-978.

[0085] NAND string 940n includes channel 940a, SGS transistor 981, source-side dummy memory cell 982 connected to source-side dummy word line WLDS, data memory cells 983-993, drain-side dummy memory cell 994 connected to drain-side dummy word line WLDD, and SGD transistors 995-998.

[0086] NAND string 950n includes channel 950a, SGS transistor 1001, source-side virtual memory cell 1002 connected to source-side virtual word line WLDS, data memory cells 1003-1013, drain-side virtual memory cell 1014 connected to drain-side virtual word line WLDD, and SGD transistors 1015-1018.

[0087] NAND string 960n includes channel 960a, SGS transistor 1021, source-side dummy memory cell 1022 connected to source-side dummy word line WLDS, data memory cells 1023-1033, drain-side dummy memory cell 1034 connected to drain-side dummy word line WLDD, and SGD transistors 1035-1038.

[0088] SGD transistors 918, 938, 958, 978, 998, 918, and 938 are the first topmost SGD transistors in SB0-SB6. SGD transistors 917, 937, 957, 977, 997, 1017, and 1037 are the second SGD transistors in SB0-SB6. SGD transistors 916, 936, 956, 976, 996, 1016, and 1036 are the third SGD transistors in SB0-SB6. Furthermore, SGD transistors 915, 935, 955, 975, 995, 915, and 935 are the fourth SGD transistors in SB0-SB6.

[0089] The source end of the NAND string is connected to the common source line SL, and the drain end of the NAND string is connected to the common bit line BL0.

[0090] SGD transistors can be connected in various ways within NAND strings, sub-blocks, and blocks. In this example, within each sub-block SB0-SB6, the control gates of SGD transistors 915-918, 935-938, 955-958, 975-978, 995-998, 1015-1018, and 1035-1038 are connected to each other via conductive paths 918a, 938a, 958a, 978a, 998a, 1018a, and 1038a, respectively. The control gates of SGD transistors in different sub-blocks are not connected to each other. Within each sub-block, the connected SGD transistors in the NAND string are driven using a common control gate voltage. This provides a simplified implementation, as one SGD driver is sufficient for each sub-block.

[0091] During the erase operation, GIDL is primarily generated in the first SGD transistor. For example, this method allows for the generation of different amounts of GIDL in different sub-blocks by applying different SGD control gate voltages in different sub-blocks, while a common bit line voltage is applied across all sub-blocks.

[0092] Figure 10AA memory structure is illustrated in a cross-section along the bit line direction (y-direction), where straight vertical NAND strings extend from a common source connection in or near the substrate to global bit lines (GBL0-GBL3) extending above the physical level of the memory cells. Word lines for a given physical level within the block are formed from sheets of conductive material. Memory via structures extend downward through these conductive material sheets to form memory cells, which are vertically connected in series (along the z-direction) via vertical bit lines (BL0-BL3) to form vertical NAND strings. Within a given block, there are multiple NAND strings connected to a given global bit line (e.g., GBL0 connected to multiple BL0s). The NAND strings are grouped into strings sharing a common select line. Thus, for example, a NAND string selected by the source select line SGS0 and the drain select line SGD0 can be considered as one group of NAND strings and can be designated as string 0, while a NAND string selected by the source select line SGS1 and the drain select line SGD1 can be considered as another group of NAND strings and can be designated as string 1, as shown. The box can consist of any suitable number of such individually selectable strings. It should be understood that... Figure 10A Only portions of GBL0 and GBL3 are shown, and these bit lines extend further in the y-direction and can be connected to additional NAND strings in the block and other blocks. Furthermore, the additional bit lines extend parallel to GBL0-GBL3 (e.g., along the x-axis, in...). Figure 10A (At different locations in front of or behind the cross-section).

[0093] Figure 10B schematically shown Figure 10AIndividual optional NAND string groups. It can be seen that each global bit line in the global bit lines (GBL0-GBL3) is connected to multiple individually optional NAND string groups in the portion of the block shown (e.g., GBL0 is connected to the vertical bit line BL0 of string 0, and also to the vertical bit line BL0 of string 1). In some cases, the word lines of all strings in the block are electrically connected; for example, WL0 in string 0 can be connected to WL0 of string 1, string 2, etc. Such word lines can be formed as a continuous sheet of conductive material extending through all the string groups in the block. Source lines can also be common to all strings in the block. For example, a portion of the substrate can be doped to form a continuous conductor beneath the block. Source select lines and drain select lines are not shared by different string groups, such that, for example, SGD0 and SGS0 can be biased to select string 0, without similarly biasing SGD1 and SGS1. Therefore, string 0 can be selected individually (connected to the global bit lines and the common source), while string 1 (and other string groups) remains isolated from the global bit lines and the common source. Accessing memory cells within a block during programming and read operations typically involves applying selection voltages to a pair of select lines (e.g., SGS0 and SGD0) while simultaneously providing unselected voltages to all other select lines in the block (e.g., SGS1 and SGD1). Appropriate voltages are then applied to the word lines of the block, allowing access to specific word lines within the selected string group (e.g., applying a read voltage to a specific word line while applying a read pass voltage to other word lines). Erase operations can be applied to the entire block (all string groups within the block) rather than specific string groups within the block.

[0094] Figure 10C The cross-section along the XZ plane is shown. Figures 10A to 10B The individual selectable NAND string group is String 0. It can be seen that each global bit line (GBL0-GBLm) is connected to a vertical NAND string (vertical bit line BL0-BLm) in String 0. String 0 can be selected by applying an appropriate voltage to the select lines SGD0 and SGS0. Other string groups are similarly connected to the global bit lines (GBL0-GBLm) at different locations along the Y direction and have different select lines that can receive unselected voltages when String 0 is selected.

[0095] Re-reference Figure 2B The memory die 104 may also include read / write circuitry 144, which includes multiple or p sensing blocks (also referred to as sensing modules or sensing circuits) 146. As described in further detail below, the sensing blocks 146 are configured to participate in reading or programming pages of memory cells in parallel.

[0096] The memory die 104 may also include a row address decoder 148 and a column address decoder 150. When data is read from or written to the memory cell 142, the row address decoder 148 can decode the row address and select a specific word line in the memory array 142. The column address decoder 150 can decode the column address to select a specific group of bit lines in the memory array 142 to be read / written by the circuitry 144.

[0097] In addition, the non-volatile memory die 104 may include peripheral circuitry 152. Peripheral circuitry 152 may include control logic circuitry 154, which may be implemented as a state machine providing on-chip control and status information for memory operations to the controller 102. Peripheral circuitry 152 may also include an on-chip address decoder 156, which provides an address interface between addressing used by the controller 102 and / or the host and hardware addressing used by row and column decoders 148, 150. Furthermore, peripheral circuitry 152 may also include volatile memory 158. An exemplary configuration of volatile memory 158 may include latches, but other configurations are also possible.

[0098] Furthermore, peripheral circuitry 152 may include power control circuitry 160 configured to generate and supply voltages to memory array 142, including voltages to word lines (including programming voltage pulses), erase voltages (including erase voltage pulses), and source-select gate bias voltage V to the source-select gate bias line SSG. SSG The drain-select gate bias voltage V to the drain-select gate bias line DSG DSG The unit source voltage V on the source line SL celsrc Other voltages that may be supplied to the memory array 142, the read / write circuitry 144 (including the sensing block 146), and / or other circuit components on the memory die 104. The various voltages provided by the power control circuitry 160 are described in more detail below. The power control circuitry 160 may include any of a variety of circuit topologies or configurations to provide voltages at appropriate levels to perform read, write, and erase operations, such as driver circuitry, charge pumps, reference voltage generators, and pulse generation circuitry, or combinations thereof. Other types of circuitry for generating voltages may be possible. Furthermore, the power control circuitry 160 may communicate with and / or be controlled by the control logic circuitry 154, the read / write circuitry 144, and / or the sensing block 146 to provide voltages at appropriate levels and at appropriate times to perform memory operations.

[0099] To program a target memory cell, specifically the FGT, the power control circuit 160 applies a programming voltage to the control gate of the memory cell and grounds the bit lines connected to the target memory cell, which in turn allows electrons to be injected into the floating gate from the channel. Conversely, the bit line voltage rises to VHSA to prevent electron injection into the floating gate, a phenomenon known as programming disable. A peak current (Icc) occurs during BL operation. The highest peak Icc occurs in the middle of the programming cycle, where almost an equal amount of the bit lines remain grounded, and the other half rises to VHSA. The voltage difference between the bit lines causes bit line-to-bit line coupling and significant peak Icc. During program operation, the bit lines connected to the target memory cell are called selected bit lines. Conversely, bit lines not connected to the target memory cell during program operation are called unselected bit lines. In this context, the state of a bit line can refer to whether it is selected or unselected. In other words, a bit line can be in one of two states: selected or unselected. When electrons accumulate in the floating gate, the floating gate becomes negatively charged, and the threshold voltage V of the memory cell... TH The power control circuit 160 applies a programming voltage V to the word line connected to the target memory cell. PGM So that the control gate of the target memory cell receives the programming voltage V PGM This allows the memory cells to be programmed. As previously mentioned, within a block, a memory cell in each NAND string shares the same word line. During program operation, the word line connected to the target memory cell is called the selected word line. Conversely, the word line not connected to the target memory cell during program operation is called the unselected word line.

[0100] Figures 11A to 11C This is a graph showing the threshold voltage distribution for different numbers of bits stored in a memory cell. It focuses on the threshold voltage V. TH Plot the threshold voltage distribution curve as a function of the number of memory cells. Figure 11A The threshold voltage distribution curves of a memory cell programmed to store two bits of data are shown. Figure 11B The threshold voltage distribution curves of a memory cell programmed to store three bits of data are shown, and Figure 11C The voltage distribution curves for a memory cell programmed to store four bits of data are shown. Similar threshold voltage distribution curves can be generated for memory cells programmed to store bits other than two, three, and four.

[0101] At a given point in time, each memory cell can be in one of several memory states (or data states). Memory states can include erase states and multiple programming states. Therefore, at a given point in time, each memory cell can be in an erase state or in one of several programming states. The number of programming states corresponds to the number of bits the memory cell is programmed to store. (Reference) Figure 11A For a memory cell programmed to store two bits, the memory cell can be in an erase state (Er) or one of three programming states (A, B, C). (See reference) Figure 11B For a memory cell programmed to store three bits, the memory cell can be in an erase state (Er) or one of seven programming states (A, B, C, D, E, F, G). (See reference) Figure 11C For a memory cell programmed to store four bits, the memory cell can be in the erase state Er or one of the fifteen programming states 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F. For example... Figures 11A to 11C As shown, each voltage distribution curve is associated with either the erase state or one of these programming states.

[0102] Furthermore, each threshold voltage distribution curve defines and / or is associated with different threshold voltage ranges, which in turn define, are assigned to, or are associated with different binary values ​​among a plurality of predetermined N-bit binary values. Therefore, determining which threshold voltage V... TH The lower memory cell allows determination of the data (i.e., the logical value of the bits) currently stored in the memory cell. The specific relationship between the data programmed into the memory cell and the threshold voltage level of the memory cell depends on the data encoding scheme used to program the memory cell. In one example, such as... Figure 11A and Figure 11B As shown, a Gray code scheme is used to assign data values ​​to threshold voltage distribution curves. According to this scheme, for a memory cell programmed with two bits of data, the data value "11" is assigned to the threshold voltage range associated with the erased state Er, the data value "01" is assigned to the threshold voltage range associated with the programmed state A, the data value "00" is assigned to the threshold voltage range associated with the programmed state B, and the data value "10" is assigned to the threshold voltage range associated with the programmed state C. A similar relationship between data values ​​and memory states can be established for memory cells programmed to store three, four, or other bits of data.

[0103] Before executing a program operation to program multiple or a group of target memory cells, all memory cells in the group that are to be programmed and / or selected for programming in the programming operation may be in an erase state. During the programming operation, the power control circuit 160 may apply a programming voltage to the selected word line and then to the control gate of the target memory cell as a series of programming voltage pulses. The target memory cells to be programmed are connected to the same selected word line. In many programming operations, the power control circuit 160 increases the magnitude of the programming pulse with each successive pulse in predetermined steps. Additionally, as described in further detail below, as part of a program loop or program operation, the power control circuit 160 may apply one or more verification pulses to the control gate of the target memory cell between programming pulses. Furthermore, during the programming operation, the power control circuit 160 may apply one or more boost voltages to unselected word lines.

[0104] Unless programming is disabled, the target memory cells connected to the selected word lines will simultaneously have their threshold voltages changing. When programming of one target memory cell is complete, it is disabled from further programming in subsequent program loops, while programming of the other target memory cells continues. Additionally, for some example programming operations, control logic 154 may maintain a counter that counts the programming pulses.

[0105] During a program operation to program a set of target memory cells, each target memory cell is assigned to one of a plurality of memory states based on the write data to be programmed into the target memory cells during the program operation. Based on the assigned memory state, a given target memory cell will remain in an erased state or be programmed into a programmed state different from the erased state. When control logic 154 receives a program command from controller 102 or otherwise determines to perform a program operation, the write data is stored in a latch included in read / write circuitry 144. During the programming operation, read / write circuitry 144 can read the write data to determine the corresponding memory state to which each of the target memory cells will be programmed.

[0106] As described in more detail below, and as Figures 11A to 11C As shown, each programming state corresponds to a verification voltage level V. V Related. When the threshold voltage V of a given target memory cell is... TH Higher than the verification voltage V associated with the memory state allocated to the target memory cell. V At that time, the given target memory cell is programmed into its assigned memory state. This is contingent upon the threshold voltage V of the given target memory cell. V Below the associated verification voltage VV The control gate of the target memory cell can then be subjected to programming pulses to adjust the threshold voltage V of the target memory cell. TH Increase to the threshold voltage range associated with the memory state assigned to a given target memory cell. Alternatively, when the threshold voltage V of a given target memory cell... TH Increase to above the associated verification voltage level V V When the time is right, programming can be completed for a given target memory cell. As described in further detail below, the sensing block 146 can participate in the program operation to determine whether programming of a given memory cell is complete.

[0107] As previously described, target memory cells undergoing program operations may also undergo verification operations, which determine when programming of each target memory cell is complete. Verification operations are performed between programming pulses, thus programming and verification operations are executed alternately or cyclically. A combination of programming and verification operations is called a program operation. Therefore, a program operation comprises multiple programming operations and multiple verification operations executed alternately. That is, a program operation involves a programming operation followed by a verification operation, then another programming operation, then another verification operation, and so on, until the program operation no longer has any programming or verification operations to perform. Furthermore, a single programming operation of a program operation includes power control circuitry 160 providing one or more programming pulses to a selected word line for that single programming operation, and a single verification operation of a program operation includes power control circuitry 160 providing one or more verification pulses to a selected word line for that single programming operation. Therefore, program operation may include power control circuitry 160 providing a pulse train or a series of voltage pulses to a selected word line, wherein the pulse train includes one or more programming pulses, followed by one or more verification pulses, followed by one or more programming pulses, followed by one or more verification pulses, and so on, until the programming-verification process no longer has any more programming or verification pulses for power control circuitry 160 to supply to the selected word line.

[0108] When the verification part of the program operation identifies that all memory cells have been programmed to their assigned threshold voltage V TH At this point, the program operation is complete. As mentioned, this occurs when the verification process determines that the threshold voltage of the target memory cell has increased to a level higher than the verification voltage level V associated with the memory state to which the target cell will be programmed. V At that time, the verification process verifies or determines that a given target memory cell has been programmed.

[0109] For some example program operations, all target memory cells undergoing the program operation do not simultaneously undergo a single verification operation. Alternatively, for a single verification operation, only those target memory cells allocated to the same memory state undergo the verification operation. For a single verification operation, the target memory cells undergoing the single verification operation are referred to as selected memory cells or selected target memory cells, and the target memory cells not undergoing the single verification operation are referred to as unselected memory cells or unselected target memory cells. Similarly, for a set of bit lines connected to the target memory cells of the program operation, the bit lines connected to the selected memory cells for the single verification operation are referred to as selected bit lines, and the bit lines connected to the unselected memory cells for the single verification operation are referred to as unselected bit lines. In this context, the state of a bit line can refer to whether the bit line is selected or unselected. In other words, a bit line can be in one of two states: selected or unselected.

[0110] For each of the verification operations, power control circuitry 160, or some combination of power control circuitry 160, read / write circuitry 144, and sensing block 146, provides an appropriate level of voltage to the selected word lines and unselected word lines, as well as the selected bit lines and unselected bit lines, to perform a verification operation on the selected memory cell of the target memory cell undergoing the program operation. For clarity, and unless otherwise specified, the combination of power control circuitry 160, read / write circuitry 144, and sensing block 146 used to bias the selected and unselected word lines and bit lines at appropriate levels during a given memory operation (e.g., programming operation, verification operation, program operation, read operation, or erase operation) is collectively referred to herein as voltage supply circuitry. Voltage supply circuitry may refer to other circuit components of power control circuitry 160, sensing block circuitry 146, read / write circuitry 144, or any combination thereof.

[0111] To perform the verification operation in the block, the voltage supply circuit can respond by supplying an appropriate level of voltage to the bit line on the common source line SL to turn on the drain-select gate transistor and the source-select gate transistor, and set the drain-select gate bias voltage V on the drain-select gate bias line SGD. SGD Supply to drain-select gate transistor (e.g., Figure 6 The control gate of transistor 606 and the source select gate bias voltage V on the source select gate bias line SGS. SGS Supply to drain-select gate transistor (e.g., Figure 6 The control gate of the transistor 608.

[0112] Additionally, the voltage supply circuit supplies a source line voltage on the common source line SL at the cell source voltage level Vcelsrc (or simply cell source voltage Vcelsrc). Furthermore, the voltage supply circuit biases the drain side of the selected bit line with a high supply voltage VHSA, which is substantially higher than the cell source voltage Vcelsrc. The difference between the high supply voltage VHSA and the cell source voltage level Vcelsrc can be sufficiently large to allow current to flow through the selected target memory cell at a threshold voltage V that allows it to conduct current. TH In this case, the flow originates from the drain side of the string containing the selected target memory cell and flows to the source side. During the verification operation, the threshold voltage V of the selected memory cell is adjusted accordingly. TH The selected memory cell can typically be characterized as fully conductive, slightly conductive, or non-conductive. Additionally, the voltage supply circuitry biases the drain side of the unselected bit line to the cell source voltage Vcelsrc. By biasing both the drain and source sides of the unselected bit line to the cell source voltage Vcelsrc, the voltage difference between the drain and source sides will prevent current from flowing through the NAND string connected to the unselected bit line. Furthermore, the voltage supply circuitry biases the unselected word line, and subsequently the control gate of the FGT coupled to the unselected word line, to the read voltage Vread. The read voltage is high enough that the FGT coupled to the unselected word line conducts current regardless of its threshold voltage V. TH How so? Furthermore, the voltage supply circuit uses the control gate reference voltage V. CGRV The bias-selected word line, the control gate reference voltage, can be in the form of one or more verification pulses as described above. Control gate reference voltage V CGRV The voltage supply circuit can be different to verify target memory cells in different memory states. For example, when verifying a target memory cell programmed into state A, but not when verifying a target memory cell programmed into state B, the voltage supply circuit can supply different control gate reference voltages V. CGRV (or different levels of control gate reference voltage V) CGRV ),etc.

[0113] Once the voltage supply circuit supplies voltage to the selected and unselected word lines and bit lines, as well as to the drain-select-gate transistor, source-select-gate transistor, drain-select-gate bias line SGD, and source-select-gate bias line SGS, the sensing block can perform a sensing operation to identify whether the selected target memory cell is conducted and subsequently fully programmed. Further details of the sensing operation portion of the verification operation are described in more detail below.

[0114] As mentioned earlier, the threshold voltage V of the memory cell THThe data value that identifies the data stored within it. For a given read operation within a block, the memory cell from which data is to be read is called the selected memory cell, and the memory cell from which data is not read is called the unselected memory cell. Therefore, when data is to be read from a page of a memory cell used for a specific read operation, those memory cells within the page are selected memory cells, and the memory cells in the block that are not part of a page are unselected memory cells. Additionally, the word line of the page connected to the selected memory cell is called the selected word line, and the other word lines in the block are called the unselected word lines.

[0115] During a read operation to read data stored in a target memory cell of the page, sensing block 146 is configured to perform a sensing operation that senses whether current flows through the bit line connected to the target memory cell of the page. The voltage supply circuit may be based on a threshold voltage V of the target memory cell. TH An appropriate voltage level is provided on the select word line and the unselected word line to cause current to flow or not flow. For some configurations, the voltage level provided to the select word line may vary depending on the state of the memory cell.

[0116] The voltage supply circuit can also bias the bit line, applying a high supply voltage VDDSA to the drain side of the bit line and a cell source voltage Vcelsrc to the source side of the bit line to allow current flow, provided that the threshold voltage V of the memory cell is selected. TH Allow its flow. For some example read configurations, sensing block 146 may perform sensing operations on less than all memory cells of a page. In such configurations, the target memory cells of a page that undergo a given sensing operation and / or are selected for the given sensing operation are referred to as selected memory cells or selected target memory cells. Conversely, the target memory cells of a page that do not undergo a sensing operation and / or are not selected for the sensing operation are referred to as unselected memory cells. Thus, bit lines connected to selected target memory cells are called selected bit lines, and bit lines connected to unselected target memory cells are called unselected bit lines. In this context, the state of a bit line can refer to whether the bit line is selected or unselected. In other words, a bit line can be in one of two states: selected or unselected. Voltage supply circuitry may supply voltage to selected and unselected word lines and selected and unselected bit lines in various combinations and / or sequences and / or through various sensing operations to determine the threshold voltage of the target memory cell, thereby allowing the determination of the data value of the data stored in the target memory cell.

[0117] Figure 12 This is a block diagram of an example configuration of sensing block 1200, which can represent Figure 2BThe sensing block 1200 may include one of the sensing blocks 146(1) to 146(p). The sensing block 1200 may include a plurality of sensing circuits 1202 and a plurality of latches 1204. Each sensing circuit (also referred to as a sensing amplifier circuit) 1202 may be associated with a corresponding latch 1204. That is, each sensing circuit 1202 may be configured to communicate with sensing operations using data and / or perform sensing operations and / or store data into its associated latch group 1204. Additionally, the sensing block 1200 may include a sensing circuit controller 1206 configured to control the operation of the sensing circuits 1202 and latch groups 1204 of the sensing block 1200. The sensing circuit controller 1206 may communicate with and / or be part of control logic 154. The sensing circuit controller 1206 may be implemented in hardware or a combination of hardware and software. For example, the sensing circuit controller 1206 may include a processor that executes computer instructions stored in memory to perform at least some of its functions.

[0118] As discussed earlier, a host or device using a memory device or apparatus may have current consumption limits. For example, the current limit from the host may be a predetermined host current limit. Alternatively, the predetermined host current limit that the host or system can tolerate is typically a fixed number that should not be exceeded.

[0119] In other memory devices, it is possible that even more peak currents may be required for multiple planes (e.g., four planes) of multiple dies operating in parallel. Therefore, operating parameters can be trimmed to account for the worst-case scenario of multiple planes operating at once, and these optimized trimmed parameters for the multiple planes used for program operation should be able to survive the worst-case scenario.

[0120] Based on the device's or system's use of memory cells, it happens very frequently that fewer planes than the total number actually available are used. For example, if the amount of data the host attempts to program is less than the full capacity (4 planes, all pages), the system or device will only program the required planes (even though all pages are in a complete sequence, and in some cases, the device "fills" some garbage to fill other pages). The host typically does not have enough data to write an entire meta-block. In this case, the system or device can use "residual" or dummy data for the next data block. Alternatively, data can be collected in RAM (e.g., DRAM) to fill all planes (i.e., the device waits for more data); however, not all products include RAM due to their cost, or there may not be enough RAM to store all the data.

[0121] Another scenario is when the host queries "commit" after sending data. This means the host will not send the next data until the memory device has finished writing the current data (which typically means not using a cache). Therefore, the device needs to write the data to the memory cell and check data integrity before committing. In this case, the device will rarely be able to program the entire plane together.

[0122] Figure 13A The diagram shows the programming time versus bit line voltage ramp rate parameter and the forbidden bit line ramp rate IBLRR_P for various target values ​​of the forbidden bit line voltage VHSATGT. The ramp rate is adjusted (or controlled) before the target value of the forbidden bit line voltage VHSATGT is reached. After the forbidden bit line voltage VHSATGT is reached, there is no longer control over the ramp rate or ramp speed. Therefore, the lower the percentage, the less bit line voltage is required for ramping up, but the more current is consumed, and vice versa. This parameter also represents a trade-off between performance and power consumption.

[0123] Figure 13B The peak current (Icc) and bit line voltage ramp rate parameter IBLRR_P are shown for various target values ​​of the disabled bit line voltage VHSATGT. Here, the bit line voltage ramp rate parameter IBLRR_P is related to the high sense amplifier voltage VHSA used to bias the bit line. The larger the amount of the bit line voltage ramp rate parameter IBLRR_P (i.e., current) in each graph, the greater and more aggressive the ramp rate of the high sense amplifier voltage. As shown, there is a trade-off between programming performance or speed and the peak current Icc. Specifically, better programming performance results in a higher peak Icc.

[0124] Figure 14A A graph is shown showing the peak current (Icc) versus the bit line voltage ramp rate parameter IBLRR_P with various timings (i.e., smoothing) for a device with two planes. Different power specifications may need to be utilized. In the example shown, the current consumption Icc is measured every 10 ns. If the power specification is 1 µs, the measurement data will have a moving average between 100 rows of data. Similarly, if the specification is 5 µs, the measurement data will have a moving average between 500 rows of data. Therefore, the higher the "smoothing" rating, the flatter the graph, and the smaller the power specification target. As shown, due to word line limitations, the minimum set difference (DAC) for full smoothing or the power specification is 4 DAC. Figure 14BThe graph shows the current consumption of the device over a period of time during program operation for multiple values ​​(P, Q, R, S, T, U, V, W) of the bit line voltage ramp rate parameter IBLRR_P. As shown, the peak current is primarily attributed to the voltage ramp rate on the bit line (the higher amplitude peak at either end of the graph), rather than the voltage ramp variation on the word line (the central region of the graph with lower amplitude).

[0125] When program operations involve a smaller number of planes, using parameters optimized for many plane operations (e.g., four planes) will result in the same performance (programming time / Tprog) but with much lower peak current. Therefore, since the allowable peak current is fixed, fewer planes can use a more aggressive ramp rate of the optimized parameters and their corresponding clocks or timings on the bit lines (BL) and word lines (WL) for further performance gains.

[0126] Therefore, this document provides an apparatus (e.g., Figures 1A to 2B The memory system 100 includes connections to word lines (e.g., Figure 6 WL0 to WL M-1 ) and bit lines (e.g., Figure 6 BL0 to BL P-1 And arranged on multiple planes (e.g., Figure 5B Multiple memory cells in plane 0, plane 1) (e.g., Figure 2B Memory cell 142 Figure 3 Floating gate transistor 300 Figure 6 The FGT 604). Control circuitry (e.g., Figures 1A to 2B The controller 102 and peripheral circuit 152, Figure 1C The memory controller 202 and sensing block 1200 are coupled to word lines and bit lines and configured to determine whether program operations on a plurality of memory cells involve all of the plurality of planes. In response to program operations on a plurality of memory cells not involving all of the plurality of planes, the control circuitry is configured to adjust, during program operations on the plurality of memory cells, at least one of the bit line ramp rate of the bit line voltage applied to the bit lines and the word line ramp rate of at least one word line voltage applied to the word lines based on the amount of the plurality of planes associated with the plurality of memory cells being programmed and verified during program operations. Alternatively, the control circuitry is further configured to apply bit line voltages to the bit lines with a predetermined default trimmed bit line ramp rate in response to program operations on a plurality of memory cells involving all of the plurality of planes. Similarly, the control circuitry is configured to apply at least one word line voltage to the word lines with a predetermined default trimmed word line ramp rate during program operations on a plurality of memory cells in response to program operations on a plurality of memory cells involving all of the plurality of planes.

[0127] As referenced above Figures 11A to 11C The discussed program operation may include multiple loops, each loop including a programming pulse to apply a threshold voltage V. TH Increase to the target threshold voltage V TH And a verification operation or programming verification to check the threshold voltage V of the programmed memory cell. TH Therefore, if a memory cell connected to one of the bit lines reaches the expected or target threshold voltage V... TH If no further programming pulse is needed, then no further programming pulse is required. Therefore, bit lines include multiple un-disabled bit lines that are programmed at a certain time during program operation, and multiple disabled bit lines that are not programmed at that time. According to one aspect, the bit line voltage is a suppression voltage (i.e., VHSA) applied to the multiple disabled bit lines. Specifically, the bit lines slope up to VDDSA or remain at Vss (0V), depending on whether the memory cells associated with these bit line memory cells will be programmed. Therefore, if the memory cell connected to one of the bit lines reaches the expected or target threshold voltage V... TH If this is not the case, the bit line will rise to VDDSA to disable further programming. However, it should be understood that the bit line voltage can be another voltage.

[0128] To adjust the bit line ramp rate of the applied bit line voltage to the bit line, the "shift" parameter "DIBLRR_P_PB" can be stored in memory (e.g., stored in...). Figure 2A and Figure 2B In ROM 118, a more aggressive bit line ramp rate is used for fewer than a full number of planes. How "aggressive" the bit line ramp rate variation will be for fewer planes during program operation can be determined in advance (e.g., before production). Therefore, according to one aspect, the apparatus includes a default bit line voltage ramp rate lookup table with multiple default bit line voltage ramp rates IBLRR_P having a bit line voltage ramp rate parameter or bit line voltage. The apparatus also includes a shifted bit line voltage ramp rate lookup table with multiple "shift" parameters or bit line shift offsets DIBLRR_P_PB. Figure 15A and Figure 15B An example default bit line voltage ramp rate lookup table and an example shifted bit line voltage ramp rate lookup table are shown for adjusting the bit line ramp rate applied to the bit line. The control circuit is configured to reference the default bit line voltage ramp rate lookup table and the shifted bit line voltage ramp rate lookup table, and determine which of the multiple default bit line voltage ramp rates IBLRR_P is used in program operation based on one of the multiple bit line shift offsets DIBLRR_P_PB selected and based on the amount of multiple planes associated with multiple memory cells that are programmed and verified during program operation.

[0129] Therefore, for example, if multiple planes comprise a total of four planes, program operations involving all four planes use one of a plurality of default bit line voltage ramp rates IBLRR_P for the bit line voltages. Specifically, a default bit line voltage ramp rate IBLRR_P is pre-selected for the device (e.g., determined during product development and used during production). Similarly, a bit line shift offset DIBLRR_P_PB is pre-selected for the device (e.g., determined during product development and used during production). If program operations involve fewer than the total number of planes, a bit line shift offset DIBLRR_P_PB is referenced from a lookup table of bit line shift offsets to select the bit line voltage ramp rate to use. For example, the bit line voltage ramp rate used is one of the default bit line ramp rates IBLRR_P plus one of the bit line shift offsets DIBLRR_P_PB (i.e., for three planes, IBLRR_P + DIBLRR_P_PB). Similarly, if the program operation involves only two of the four planes, the bit line voltage ramp rate used is one of the default bit line ramp rates IBLRR_P plus two times one of the bit line shift offsets DIBLRR_P_PB (i.e., for two planes, IBLRR_P + 2 * DIBLRR_P_PB). Furthermore, if the program operation involves only one of the four planes, the bit line voltage ramp rate used is one of the default bit line ramp rates IBLRR_P plus three times one of the bit line shift offsets DIBLRR_P_PB (i.e., for one plane, IBLRR_P+3*DIBLRR_P_PB).

[0130] Therefore, if, for a programming verification operation involving all four planes, one of the default bit line voltage ramp rates in the default bit line voltage ramp rate lookup table is selected as B2, and one of the bit line shift offsets selected for the device is +1DAC, then program operations involving only three of the four planes will use ramp rate B3. Program operations involving only two of the four planes will use ramp rate B4, and program operations involving only one of the four planes will use ramp rate B5. However, if, instead, one of the bit line shift offsets selected for the device, DIBLRR_P_PB, is +2DAC, then program operations involving only three of the four planes will use ramp rate B4. Program operations involving only two of the four planes will use ramp rate B6, and program operations involving only one of the four planes will use ramp rate B8.

[0131] Furthermore, whenever the bit line voltage ramp rate determined based on the default bit line voltage ramp rate lookup table and the shifted bit line voltage ramp rate lookup table exceeds the largest default bit line voltage ramp rate (i.e., DAC) among the multiple default bit line voltage ramp rates IBLRR_P, the control circuit is configured to use the largest default bit line voltage ramp rate (e.g., B8 ramp rate) among the multiple default bit line voltage ramp rates IBLRR_P.

[0132] Therefore, during the bit line voltage ramp change period of the program operation, the bit line voltage ramps according to a default bit line voltage ramp rate lookup table and a shifted bit line voltage ramp rate lookup table, and based on the amounts of multiple planes associated with multiple memory cells that are programmed and verified in the program operation. According to one aspect, the control circuit is configured to automatically determine the bit line voltage ramp change period used in the program operation based on the bit line voltage ramp change, according to the default bit line voltage ramp rate lookup table and the shifted bit line voltage ramp rate lookup table, and based on the amounts of multiple planes associated with multiple memory cells that are programmed and verified in the program operation. Timing for the ramp change inactivation bit line voltage includes self-feedback in the bit line power circuitry. The faster the ramp rate, the shorter the timing is automatically made. Therefore, for the bit line ramp change clock, the bit line voltage ramp change period (e.g., P5) is automatically determined when the high voltage supply VHSA reaches 75%-90% of the high voltage supply level VDDSA. Figure 16 Example graphs of VDDSA, VHSA, and the corresponding VHSA peak current are shown.

[0133] As discussed previously, word lines include selected word lines that are programmed and verified at a certain time during program operation, and multiple unselected word lines that are not programmed and verified at that time. Furthermore, at least one word line voltage includes a pass voltage Vpass applied to the multiple selected and unselected word lines during the programming portion of program operation. To adjust the word line ramp rate of the pass voltage Vpass applied to the multiple unselected word lines, the device includes a default pass voltage ramp rate lookup table having multiple default pass voltage ramp rates RRC_VPASS. The device also includes a shifted pass voltage ramp rate lookup table having multiple pass voltage shift offsets DRRC_VPASS_PB. Figure 17A and Figure 17BAn example default pass voltage ramp rate lookup table and an example shifted pass voltage ramp rate lookup table are shown. In the example shown, the larger the number, the slower the ramp rate. The control circuit is further configured to shift one of the multiple default pass voltage ramp rates RRC_VPASS used in program operation based on a pass voltage shift offset from one of the multiple pass voltage shift offsets DRRC_VPASS_PB and based on the amount of multiple planes associated with multiple memory cells that are programmed and verified in program operation.

[0134] Therefore, for example, if multiple planes comprise a total of four planes, then when at least one word line voltage is a pass voltage Vpass, program operations involving all four planes use one of a plurality of default pass voltage ramp rates RRC_VPASS. Similar to one of a plurality of default bit line voltage ramp rates IBLRR_P, one of a plurality of default pass voltage ramp rates RRC_VPASS is pre-selected for the device (e.g., determined during product development and used during production). Similarly, one of a plurality of pass voltage shift offsets DRRC_VPASS_PB is pre-selected for the device (e.g., determined during product development and used during production). If program operations involve fewer than all four planes, the pass voltage ramp rate used is selected by referring to one of a plurality of pass voltage shift offsets DRRC_VPASS_PB in the shift pass voltage ramp lookup table. For example, the through voltage ramp rate used for three planes is one of the default through voltage ramp rates RRC_VPASS plus one of the through voltage shift offsets DRRC_VPASS_PB (i.e., for three planes, RRC_VPASS + DRRC_VPASS_PB). Similarly, if the program operation involves only two of the four planes, the through voltage ramp rate used is one of the default through voltage ramp rates RRC_VPASS plus two times one of the through voltage shift offsets DRRC_VPASS_PB (i.e., for three planes, RRC_VPASS + 2 * DRRC_VPASS_PB). Furthermore, if the program operation involves only one of the four planes, the through voltage ramp rate used is one of the multiple default through voltage ramp rates RRC_VPASS plus two times the through voltage shift offset of one of the multiple through voltage shift offsets DRRC_VPASS_PB (i.e., for three planes, RRC_VPASS + 3 * DRRC_VPASS_PB).

[0135] Therefore, if, for a programming verification operation involving all four planes, one of the default pass voltage ramps in the default pass voltage ramp lookup table is selected as RRC disabled (meaning no ramp control is used), and one of the pass voltage shift offsets selected for the device is -1DAC, then program operations involving only three of the four planes will use the Y3 pass voltage ramp. Program operations involving only two of the four planes will use the Y2 pass voltage ramp, and program operations involving only one of the four planes will use the Y1 pass voltage ramp. Here, the Y1 ramp is less than the Y2 and Y3 ramps.

[0136] Furthermore, whenever the pass voltage ramp rate determined based on the default pass voltage ramp rate lookup table and the shifted pass voltage ramp rate lookup table exceeds the smallest default pass voltage ramp rate (i.e., DAC) among multiple default pass voltage ramp rates RRC_VPASS, the control circuit is configured to use the smallest default pass voltage ramp rate (e.g., Y4 pass voltage ramp rate or another value less than Y1) among multiple default pass voltage ramp rates RRC_VPASS.

[0137] Furthermore, at least one word line voltage includes a read voltage Vread applied to multiple selected and unselected word lines during the verification portion of the program operation. This ramp change to the read voltage Vread occurs before program verification and is also known as a "Vread spike" operation. The purpose of the Vread spike is to deplete any remaining electrons in the channel before the subsequent sensing operation. If the Vread spike operation is not used, dummy word lines (e.g., Figure 9 Hot carrier injection occurs in WLDS and WLDD. After several erase / programming cycles, the threshold voltage V of the memory cell associated with the dummy word line... TH The reading of data word lines (i.e., word lines that are not dummy word lines) will be interfered with and will affect the reading of data word lines.

[0138] Therefore, similar to voltage Vpass, in order to adjust the word line ramp rate of the read voltage Vread applied to multiple selected and unselected word lines, the device includes a default read pass voltage ramp rate lookup table with multiple default read voltage ramp rates RRC_VREAD_PVFY. The device also includes a shift read voltage ramp rate lookup table with multiple read voltage shift offsets DRRC_VREAD_PVFY_PB. Figure 18A and Figure 18BAn example default read voltage ramp rate lookup table and an example shifted read voltage ramp rate lookup table are shown. In the examples shown, larger numbers correspond to slower ramp rates. Therefore, the control circuit is further configured to shift one of the multiple default read voltage ramp rates RRC_VREAD_PVFY used in program operation based on a read voltage shift offset from one of the multiple read voltage shift offsets DRRC_VREAD_PVFY_PB and based on the amount of multiple planes associated with multiple memory cells that are programmed and verified in program operation.

[0139] Therefore, for example, if multiple planes comprise a total of four planes, then when at least one word line voltage is a read voltage, program operations involving all four planes use one of a plurality of default read voltage ramp rates RRC_VREAD_PVFY. One of the plurality of default read voltage ramp rates is pre-selected for the device (e.g., determined during product development and used during production). Similarly, one of a plurality of read voltage shift offsets is pre-selected for the device (e.g., determined during product development and used during production). If program operations involve fewer than all four planes, the read voltage ramp rate used is selected by referring to one of a plurality of read voltage shift offsets in the shift read voltage ramp lookup table. For example, the read voltage ramp rate used for three planes is one of the default read voltage ramp rates RRC_VREAD_PVFY plus one of the read voltage shift offsets DRRC_VREAD_PVFY_PB (i.e., for three planes, RRC_VREAD_PVFY + DRRC_VREAD_PVFY_PB). Similarly, if the program operation involves only two of the four planes, the read voltage ramp rate used is one of the default read voltage ramp rates RRC_VREAD_PVFY plus two times one of the read voltage shift offsets DRRC_VREAD_PVFY_PB (i.e., for three planes, RRC_VREAD_PVFY + 2 * DRRC_VREAD_PVFY_PB). In addition, if the program operation involves only one of the four planes, the read voltage ramp rate used is the default read voltage ramp rate RRC_VREAD_PVFY plus two times one of the multiple read voltage shift offsets DRRC_VPASS_PB (i.e., for three planes, RRC_VREAD_PVFY + 3 * DRRC_VREAD_PVFY_PB).

[0140] Therefore, if, for a programming verification operation involving all four planes, one of the default read voltage ramp rates in the default read voltage ramp rate lookup table is selected as Z6, and one of the read voltage shift offsets selected for the device (DRRC_VREAD_PVFY_PB) is -1DAC, then program operations involving only three of the four planes will use the Z5 read voltage ramp rate. Program operations involving only two of the four planes will use the Z4 read voltage ramp rate, and program operations involving only one of the four planes will use the Z3 read voltage ramp rate. However, if one of the bit line shift offsets (DRRC_VREAD_PVFY_PB) for the device is replaced with -2DAC, then program operations involving only three of the four planes will use the Z4 read voltage ramp rate. Program operations involving only two of the four planes will use the Z2 read voltage ramp rate, and program operations involving only one of the four planes will use the disabled read voltage ramp rate. Here, the slope ratio of Z2 is smaller than that of Z3 and Z4.

[0141] Additionally, whenever the read voltage ramp rate determined based on the default read voltage ramp rate lookup table and the shift read voltage ramp rate lookup table exceeds the smallest default read voltage ramp rate (i.e., DAC) among multiple default read voltage ramp rates RRC_VREAD_PVFY, the control circuitry is configured to use the smallest default read voltage ramp rate among multiple default read voltage ramp rates RRC_VREAD_PVFY (e.g., disable ramp rate). Although at least one word line voltage is discussed as the pass voltage Vpass and the read voltage Vread, it should be understood that the ramp variations of other voltages applied to the word line can be adjusted instead.

[0142] The timing of bit line ramp changes described above is automatically adjusted based on the default bit line voltage ramp rate lookup table and the shift bit line voltage ramp rate lookup table, and on the quantities of multiple planes associated with multiple memory cells being programmed and verified during program operation. In contrast, according to one aspect, the ramp change of at least one word line voltage (e.g., Vpass or Vread) is not automatic, but determined based on an additional lookup table. In other words, unlike the feedback control used for timing bit line ramp changes, word line ramp changes do not have feedback control; instead, the corresponding timing parameters are manually optimized. More specifically, the pass voltage ramp rate RRC_VPASS clock or pass voltage ramp change time period (e.g., P13, the thirteenth time period of the P clock cycle associated with the program operation) and the read voltage ramp rate RRC_VREAD_PVFY clock or read voltage ramp change time period (e.g., R2_PVFY, the second time period of the R clock cycle during programming verification) of the program operation depend on the number of planes involved, as discussed in more detail below. Therefore, the device disclosed herein can use a more aggressive bit line ramp rate and a more aggressive word line ramp rate, as well as corresponding timing for program operation, which further improves the performance of the device.

[0143] As discussed, during the pass voltage ramp change time period of program operation, the pass voltage Vpass ramp is changed according to a default pass voltage ramp rate lookup table and a shifted pass voltage ramp rate lookup table, and based on the amounts of multiple planes associated with multiple memory cells programmed and verified during program operation. Therefore, the device further includes a default pass voltage ramp change time period lookup table having multiple default pass voltage ramp change time periods P13. Additionally, the device includes a shifted pass voltage ramp change time period lookup table having multiple pass voltage ramp change time period offsets DP13_PB. Figure 19A and Figure 19B An example default pass-through voltage ramp change time lookup table and an example shifted pass-through voltage ramp change time lookup table are shown. The control circuit is further configured to shift one of the multiple default pass-through voltage ramp change times P13 used in program operation based on the offset of one of the multiple pass-through voltage ramp change time offsets DP13_PB and based on the amount of multiple planes associated with multiple memory cells that are programmed and verified in program operation.

[0144] Therefore, for example, if multiple planes comprise a total of four planes, program operations involving all four planes use one of a plurality of default voltage ramp change times P13 when determining the corresponding timing for reading the voltage ramp change (i.e., the voltage ramp change time period). One of the plurality of default voltage ramp change times P13 is pre-selected for the device (e.g., determined during product development and used during production). Similarly, one of the plurality of voltage ramp change time period offsets DP13_PB is pre-selected for the device (e.g., determined during product development and used during production). If program operations involve fewer than all four planes, the voltage ramp change time period used is selected by referring to one of the plurality of voltage ramp change time period offsets DP13_PB in the shifted voltage ramp change time period lookup table. For example, the through voltage ramp change time period used for three planes is one of the default through voltage ramp change times P13 plus one of the through voltage ramp change time period offsets DP13_PB (i.e., for three planes, P13 + DP13_PB). Similarly, if the program operation involves only two of the four planes, the through voltage ramp change time period used is one of the default through voltage ramp change times P13 plus two times the through voltage ramp change time period offset DP13_PB (i.e., for two planes, P13 + 2 * DP13_PB). Furthermore, if the program operation involves only one of the four planes, the through voltage ramp change time period used is one of the default through voltage ramp change times P13 plus two times the through voltage ramp change time period offset DP13_PB (i.e., for one plane, P13 + 3 * DP13_PB).

[0145] Therefore, if, for a programming verification operation involving all four planes, one of the default through voltage ramp change times P13 in the default through voltage ramp change time lookup table is selected as T7, and one of the through voltage ramp change time offsets DP13_PB selected for the device is -1DAC, then program operations involving only three of the four planes will use the through voltage ramp change time T6. Program operations involving only two of the four planes will use the through voltage ramp change time T5, and program operations involving only one of the four planes will use the through voltage ramp change time T4.

[0146] Furthermore, whenever the through voltage ramp change time determined based on the default through voltage ramp change time lookup table and the shifted through voltage ramp change time lookup table exceeds the smallest default through voltage ramp change time (i.e., DAC) among the default through voltage ramp change times P13, the control circuit is configured to use the smallest default through voltage ramp change time among the multiple default through voltage ramp change times P13 (e.g., T1 default through voltage ramp change time P13).

[0147] Similarly, as discussed, during the read voltage ramp change time period of program operation, the read voltage Vread ramps according to a default read voltage ramp rate lookup table and a shifted read voltage ramp rate lookup table. Therefore, the device further includes a default read voltage ramp change time period lookup table having multiple default read voltage ramp change times R2_PVFY. The device also includes a shifted read voltage ramp change time period lookup table having multiple read voltage ramp change time period offsets DR2_PVFY. Figure 20A and Figure 20B An example default read voltage ramp change time lookup table and an example shifted read voltage ramp change time lookup table are shown. The control circuitry is further configured to shift one of the multiple default read voltage ramp change time offsets DR2_PVFY used in program operation based on the offset of one of the multiple read voltage ramp change time offsets DR2_PVFY and on the amount of multiple planes associated with multiple memory cells programmed and verified in program operation.

[0148] Therefore, for example, if multiple planes comprise a total of four planes, program operations involving all four planes use one of a plurality of default read voltage ramp change times R2_PVFY when determining the corresponding timing of the ramp change of the read voltage Vread (i.e., via the voltage ramp change time period). A default read voltage ramp change time R2_PVFY is pre-selected for the device (e.g., determined during product development and used during production). Similarly, a read voltage ramp change time period offset DR2_PVFY is pre-selected for the device (e.g., determined during product development and used during production). If program operations involve fewer than all four planes, the read voltage ramp change time period used is selected by referring to a read voltage ramp change time period offset DR2_PVFY from the shifted read voltage ramp change time period lookup table. For example, the read voltage ramp change time period used for three planes is one of the default read voltage ramp change times R2_PVFY plus one of the read voltage ramp change time period offsets DR2_PVFY (i.e., for three planes, R2_PVFY + DR2_PVFY). Similarly, if the program operation involves only two of the four planes, the read voltage ramp change time period used is one of the default read voltage ramp change times R2_PVFY plus two times one of the read voltage ramp change time period offsets DR2_PVFY (i.e., for two planes, R2_PVFY + 2 * DR2_PVFY). Furthermore, if the program operation involves only one of the four planes, the time period for the read voltage ramp change is one of the multiple default read voltage ramp change times R2_PVFY plus two times the offset of one of the multiple read voltage ramp change time periods DR2_PVFY (i.e., for one plane, R2_PVFY+3*DR2_PVFY).

[0149] Therefore, if, for a programming verification operation involving all four planes, one of the default read voltage ramp change times R2_PVFY in the default pass voltage ramp change time lookup table is selected as T22, and one of the pass voltage ramp change time offsets DR2_PVFY selected for the device is offset by -1DAC, then program operations involving only three of the four planes will use the pass voltage ramp change time T21. Program operations involving only two of the four planes will use the pass voltage ramp change time T20, and program operations involving only one of the four planes will use the pass voltage ramp change time T19.

[0150] Furthermore, whenever the read voltage ramp change time determined based on the default read voltage ramp change time lookup table and the shifted read voltage ramp change time lookup table exceeds the smallest default read voltage ramp change time (i.e., DAC) among the default read voltage ramp change times R2_PVFY, the control circuit is configured to use the smallest default read voltage ramp change time among the multiple default read voltage ramp change times R2_PVFY (e.g., T17 defaults to the voltage ramp change time R2_PVFY).

[0151] Figure 21 The diagram illustrates how to determine the ramp rate by referencing a graph of voltage (e.g., via voltage or read voltage) versus time. Voltage steps VS1 and VS2 are shown, where VS1 is less than VS2. According to one aspect, the ramp rate can be determined by dividing one of a plurality of time steps of the total time period (e.g., via voltage ramp change time period or read voltage ramp change time period) by one of a plurality of voltage steps VS1, VS2 of the total change in voltage (e.g., via voltage or read voltage).

[0152] See again Figure 14A and Figure 14BThe simulation results show that, since the ramp variation parameter IBLRR_P (disable bit line ramp variation) determines the peak current during program operation, word line ramp variation on fewer planes (one plane in the simulation) can be disabled. This indicates that, compared to operation using two planes, there is no word line ramp rate control, but the peak current still does not exceed the limit. Therefore, while the word line ramp rate of at least one word line voltage (e.g., Vpass or Vread) applied to the word line during program operation has been discussed above as being adjusted when the multiple memory cells do not span all of the multiple planes, instead, the word line ramp rate of at least one word line voltage can be adjusted without being based on the number of planes involved. Therefore, according to one aspect, the control circuit is further configured to not adjust (i.e., disable) the word line ramp rate control of at least one word line voltage applied to the word line during program operation of the multiple memory cells in response to the program operation of the multiple memory cells not involving all of the multiple planes. However, it should be understood that for devices with many word lines (e.g., 162 word lines), the component of the peak current due to word lines is expected to change (increase).

[0153] See now Figure 22 An operational memory device (e.g., is shown) is illustrated. Figures 1A to 2B A method for a memory system 100. As described above, the memory device includes connections to word lines (e.g., Figure 6 WL0 to WL M-1 ) and bit lines (e.g., Figure 6 BL0 to BL P-1 And arranged on multiple planes (e.g., Figure 5B Multiple memory cells in plane 0, plane 1) (e.g., Figure 2B Memory cell 142 Figure 3 Floating gate transistor 300 Figure 6 (FGT 604). The method includes step 2200, receiving a program command for initiating program operation. The next step of the method is 2202, determining whether program operation of the plurality of memory cells involves all of the plurality of planes. The method proceeds to 2204, in response to the program operation of the plurality of memory cells not involving all of the plurality of planes, during program operation of the plurality of memories, adjusting at least one of the bit line ramp rate of the bit line voltage applied to the bit line and the word line ramp rate of at least one word line voltage applied to the word line based on the amount of the plurality of planes associated with the plurality of memory cells being programmed and verified in the program operation. The method also includes step 2206, in response to the program operation of the plurality of memory cells involving all of the plurality of planes, during program operation of the plurality of memory cells, applying the bit line voltage to the bit line with a predetermined default trimmed bit line ramp rate, and applying at least one word line voltage to the word line with a predetermined default trimmed word line ramp rate.

[0154] As discussed above, the memory device further includes a default bit line voltage ramp rate lookup table having a plurality of default bit line voltage ramp rates IBLRR_P for bit line voltages. The memory device also includes a shift bit line voltage ramp rate lookup table having a plurality of bit line shift offsets DIBLRR_P_PB. Therefore, the method further includes the steps of: referring to the default bit line voltage ramp rate lookup table and the shift bit line voltage ramp rate lookup table, and determining which of the plurality of default bit line voltage ramp rates IBLRR_P is used for program operation based on a bit line shift offset selected from the plurality of bit line shift offsets DIBLRR_P_PB and based on a quantity of a plurality of planes associated with a plurality of memory cells that are programmed and verified in program operation.

[0155] Therefore, during the bit line voltage ramp change period of program operation, the bit line voltage ramps according to a default bit line voltage ramp rate lookup table and a shifted bit line voltage ramp rate lookup table, and based on the amounts of multiple planes associated with multiple memory cells that are programmed and verified during program operation. Therefore, the method further includes the step of automatically determining the bit line voltage ramp change period used in program operation based on the bit line voltage ramp change, according to the default bit line voltage ramp rate lookup table and the shifted bit line voltage ramp rate lookup table, and based on the amounts of multiple planes associated with multiple memory cells that are programmed and verified during program operation.

[0156] As discussed above, at least one word line voltage includes a pass voltage Vpass applied to a plurality of selected and unselected word lines during the programming portion of program operation. Therefore, the memory device further includes a default pass voltage ramp lookup table having a plurality of default pass voltage ramp rates RRC_VPASS and a shifted pass voltage ramp lookup table having a plurality of pass voltage shift offsets DRRC_VPASS_PB. Therefore, the method further includes the step of shifting a default pass voltage ramp rate among the plurality of default pass voltage ramp rates RRC_VPASS used in program operation based on a pass voltage shift offset from one of the plurality of pass voltage shift offsets DRRC_VPASS_PB and based on the amount of a plurality of planes associated with a plurality of memory cells being programmed and verified in program operation.

[0157] Furthermore, as discussed, the memory device further includes a default through voltage ramp change time lookup table having multiple default through voltage ramp change times P13. The memory device also includes a shifted through voltage ramp change time lookup table having multiple through voltage ramp change time offsets DP13_PB. Therefore, the method further includes the step of shifting one of the multiple default through voltage ramp change times P13 used in program operation, based on one of the multiple through voltage ramp change time offsets DP13_PB and on a quantity of multiple planes associated with multiple memory cells that are programmed and verified in program operation.

[0158] As described above, at least one word line voltage includes a read voltage Vread applied to a plurality of selected and unselected word lines during the verification portion of program operation (i.e., programming verification). Therefore, the memory device further includes a default read voltage ramp rate lookup table having a plurality of default read voltage ramp rates RRC_VREAD_PVFY. The memory device also includes a shifted read voltage ramp rate lookup table having a plurality of read voltage shift offsets DRRC_VREAD_PVFY_PB. The method further includes the step of shifting one of the plurality of default read voltage ramp rates RRC_VREAD_PVFY used in program operation according to a read voltage shift offset from one of the plurality of read voltage shift offsets DRRC_VREAD_PVFY_PB and based on the amount of a plurality of planes associated with a plurality of memory cells being programmed and verified in program operation.

[0159] Additionally, as discussed, the memory device further includes a default read voltage ramp change time lookup table having multiple default read voltage ramp change times R2_PVFY. The memory device also includes a shifted read voltage ramp change time lookup table having multiple read voltage ramp change time offsets DR2_PVFY. Therefore, the method further includes the step of shifting one of the multiple default read voltage ramp change times R2_PVFY used in program operation based on a read voltage ramp change time offset from one of the multiple read voltage ramp change time offsets DR2_PVFY and based on a quantity of multiple planes associated with multiple memory cells that are programmed and verified in program operation.

[0160] Although the word line ramp rate of at least one word line voltage applied to the word line during program operation has been discussed above as being adjusted when the plurality of memory cells do not span all of the plurality of planes, conversely, the word line ramp rate of at least one word line voltage may not be adjusted based on the number of planes involved. Therefore, according to one aspect, the method further includes the step of: in response to program operation of the plurality of memory cells not involving all of the plurality of planes, not adjusting the word line ramp rate of at least one word line voltage applied to the word line during program operation of the plurality of memory cells.

[0161] While this paper primarily discusses adjustments to the ramp rate and corresponding time periods with reference to lookup tables, it should be understood that the disclosed apparatus and methods can alternatively utilize alternative techniques to perform the adjustments. For example, one or more additional formulas or algorithms can be stored in ROM and used to determine when and by how much to adjust the ramp rate and corresponding time periods based on the number of planes involved.

[0162] Obviously, changes may be made to what is described and shown herein without departing from the scope defined in the appended claims. The foregoing description of embodiments has been provided for purposes of illustration and description. It is not intended to be exhaustive or limiting of this disclosure. Various elements or features of a particular embodiment are generally not limited to that particular embodiment, but are interchangeable where applicable and can be used in selected embodiments, even if not specifically shown or described. The same applies to many other aspects. Such variations should not be considered as departing from this disclosure, and all such modifications are intended to be included within the scope of this disclosure.

[0163] The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “an,” “a,” and “the” are intended to include the plural forms as well. The terms “comprises,” “comprising,” “including,” and “having” are inclusive and therefore specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Unless specifically identified as an order of execution, the method steps, processes, and operations described herein should not be construed as requiring them to be performed in the particular order discussed or shown. It should also be understood that additional or alternative steps may be employed.

[0164] When an element or layer is referred to as “on another element or layer,” “joined to another element or layer,” “connected to another element or layer,” or “coupled to another element or layer,” the element or layer may be directly on, joined to, connected to, or coupled to the other element or layer, or an intermediary element or layer may be present. In contrast, when an element is referred to as “directly on another element or layer,” “directly joined to another element or layer,” “directly connected to another element or layer,” or “directly coupled to another element or layer,” an intermediary element or layer may not be present. Other terms used to describe relationships between elements should be interpreted in a similar manner (e.g., “between” vs. “directly between,” “adjacent” vs. “directly adjacent,” etc.). As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0165] While the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or section from another. Unless the context clearly indicates otherwise, terms such as “first,” “second,” and other numerical terms used herein do not imply order or sequence. Therefore, without departing from the teachings of the example embodiments, the first element, component, region, layer, or section discussed below may be referred to as the second element, component, region, layer, or section.

[0166] For ease of description, this document uses spatial relative terms such as “inner,” “outer,” “beneath,” “below,” “lower,” “above,” “upper,” “top,” and “bottom” to describe the relationship of one element or feature to another element or feature, as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms may be intended to cover different orientations of the device in use or operation. For example, if the device in the figure is flipped, an element described as “below” or “beneath” of other elements or features would be oriented as “above” of other elements or features. Thus, the example term “below” can cover both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.

Claims

1. A memory device, the memory device comprising: Multiple memory cells, which are connected to word lines and bit lines and arranged in multiple planes; and Control circuitry, coupled to the word line and the bit line and configured to: Determine whether the program operations of the plurality of memory units involve all of the plurality of planes, and In response to program operations on the plurality of memory cells, which do not involve all of the plurality of planes, at least one of the bit line ramp rate of the bit line voltage applied to the bit line and the word line ramp rate of at least one word line voltage applied to the word line is adjusted based on the amount of the plurality of planes associated with the plurality of memory cells being programmed and verified in the program operation during program operations.

2. The memory device according to claim 1, wherein the memory device further comprises: A default bit line voltage ramp rate lookup table, wherein the default bit line voltage ramp rate lookup table has multiple default bit line voltage ramp rates for the bit line voltage, and A lookup table for shifted bit line voltage ramp rate, wherein the lookup table has multiple bit line shift offsets; Furthermore, the control circuitry is further configured to refer to the default bit line voltage ramp rate lookup table and the shift bit line voltage ramp rate lookup table, and determine which of the plurality of default bit line voltage ramp rates is used in the program operation based on one of the plurality of bit line shift offsets and on the amount of the plurality of planes associated with the plurality of memory cells programmed and verified in the program operation.

3. The memory device of claim 2, wherein during a bit line voltage ramp change time period of the program operation, the bit line voltage ramp is changed according to the default bit line voltage ramp rate lookup table and the shifted bit line voltage ramp rate lookup table and based on the amounts of the plurality of planes associated with the plurality of memory cells programmed and verified in the program operation, and the control circuitry is further configured to automatically determine the bit line voltage ramp change time period used in the program operation based on the ramp change of the bit line voltage according to the default bit line voltage ramp rate lookup table and the shifted bit line voltage ramp rate lookup table and based on the amounts of the plurality of planes associated with the plurality of memory cells programmed and verified in the program operation.

4. The memory device of claim 1, wherein the word lines include selected word lines that are programmed and verified at a certain time during program operation and a plurality of unselected word lines that are not programmed and verified at that time, and the at least one word line voltage includes a pass voltage applied to the plurality of selected word lines and the plurality of unselected word lines during a programming portion of the program operation, the memory device further comprising: The default pass voltage ramp rate lookup table has multiple default pass voltage ramp rates. The shift is performed through a voltage ramp rate lookup table, which has multiple voltage shift offsets. Furthermore, the control circuit is further configured to shift one of the plurality of default pass voltage ramp rates used in the program operation based on one of the plurality of pass voltage shift offsets and the amount of the plurality of planes associated with the plurality of memory cells programmed and verified in the program operation.

5. The memory device of claim 4, wherein during the through voltage ramp variation time period of the program operation, the through voltage ramp variation is caused according to the default through voltage ramp rate lookup table and the shifted through voltage ramp rate lookup table and based on the amount of the plurality of planes associated with the plurality of memory cells programmed and verified in the program operation, and the memory device further comprises: The system uses a default lookup table based on voltage ramp change time periods. This lookup table contains multiple default voltage ramp change time periods. The shift is achieved through a voltage ramp change time period lookup table, which has multiple voltage ramp change time period offsets. Furthermore, the control circuit is further configured to shift one of the plurality of default voltage ramp change times used in the program operation based on one of the plurality of voltage ramp change time offsets and the amount of the plurality of planes associated with the plurality of memory cells programmed and verified in the program operation.

6. The memory device of claim 1, wherein the word lines include selected word lines that are programmed and verified at a certain time during program operation and a plurality of unselected word lines that are not programmed and verified at that time, and the at least one word line voltage includes a read voltage applied to the plurality of selected word lines and the plurality of unselected word lines during the verification portion of the program operation, the memory device further comprising: A default read voltage ramp rate lookup table, wherein the default read voltage ramp rate lookup table has multiple default read voltage ramp rates, and A shift-read voltage ramp rate lookup table, wherein the shift-read voltage ramp rate lookup table has multiple read voltage shift offsets; Furthermore, the control circuit is further configured to shift one of the plurality of default read voltage ramp rates used in the program operation based on one of the plurality of read voltage shift offsets and based on the amount of the plurality of planes associated with the plurality of memory cells programmed and verified in the program operation.

7. The memory device of claim 6, wherein during the read voltage ramp change time period of the program operation, the read voltage ramp is changed according to the default read voltage ramp rate lookup table and the shift read voltage ramp rate lookup table, and the memory device further comprises: A default voltage ramp change time period lookup table is used, which has multiple default voltage ramp change time periods. A shift-read voltage ramp change time period lookup table, wherein the shift-read voltage ramp change time period lookup table has multiple read voltage ramp change time period offsets; Furthermore, the control circuit is further configured to shift one of the multiple default read voltage ramp change times used in the program operation based on one of the multiple read voltage ramp change time offsets and the amount of the multiple planes associated with the multiple memory cells programmed and verified in the program operation.

8. The memory device of claim 1, wherein the control circuitry is further configured to, in response to program operations of the plurality of memory cells not involving all of the plurality of planes, not adjust the word line ramp rate of the at least one word line voltage applied to the word line during program operations of the plurality of memory cells.

9. A controller communicating with a memory device, the memory device including a plurality of memory cells connected to word lines and bit lines and arranged in a plurality of planes, the controller being configured to: Determine whether the program operations of the plurality of memory units involve all of the plurality of planes; and In response to a program operation of the plurality of memory cells not involving all of the plurality of planes, the memory device is instructed to adjust, during the program operation of the plurality of memory cells, at least one of the bit line ramp rate of the bit line voltage applied to the bit line and the word line ramp rate of at least one word line voltage applied to the word line based on the amount of the plurality of planes associated with the plurality of memory cells being programmed and verified in the program operation.

10. The controller according to claim 9, wherein the controller further comprises: A default bit line voltage ramp rate lookup table, wherein the default bit line voltage ramp rate lookup table has multiple default bit line voltage ramp rates for the bit line voltage, and A lookup table for shifted bit line voltage ramp rate, wherein the lookup table has multiple bit line shift offsets; Furthermore, the controller is further configured to refer to the default bit line voltage ramp rate lookup table and the shift bit line voltage ramp rate lookup table, and determine which of the plurality of default bit line voltage ramp rates is used in the program operation based on one of the selected plurality of bit line shift offsets and based on the amount of the plurality of planes associated with the plurality of memory cells programmed and verified in the program operation.

11. The controller of claim 9, wherein the word lines include selected word lines that are programmed and verified at a certain time during the program operation and a plurality of unselected word lines that are not programmed and verified at that time, and the at least one word line voltage includes a pass voltage applied to the plurality of selected word lines and the plurality of unselected word lines during the programming portion of the program operation, the controller further comprising: The default pass voltage ramp rate lookup table has multiple default pass voltage ramp rates. The shift is performed through a voltage ramp rate lookup table, which has multiple voltage shift offsets. Furthermore, the controller is configured to shift one of the plurality of default pass voltage ramp rates used in the program operation based on one of the plurality of pass voltage shift offsets and on the amount of the plurality of planes associated with the plurality of memory cells programmed and verified in the program operation.

12. The controller of claim 9, wherein the word lines include selected word lines that are programmed and verified at a certain time during the program operation and a plurality of unselected word lines that are not programmed and verified at that time, and the at least one word line voltage includes a read voltage applied to the plurality of selected word lines and the plurality of unselected word lines during the verification portion of the program operation, the controller further comprising: A default read voltage ramp rate lookup table, wherein the default read voltage ramp rate lookup table has multiple default read voltage ramp rates, and A shift-read voltage ramp rate lookup table, wherein the shift-read voltage ramp rate lookup table has multiple read voltage shift offsets; Furthermore, the controller is configured to shift one of the plurality of default read voltage ramp rates used in the program operation based on one of the plurality of read voltage shift offsets and based on the amount of the plurality of planes associated with the plurality of memory cells programmed and verified in the program operation.

13. A method of operating a memory device, the memory device comprising a plurality of memory cells connected to word lines and bit lines and arranged in a plurality of planes, the method comprising the steps of: Determine whether the program operations of the plurality of memory units involve all of the plurality of planes; as well as In response to program operations on the plurality of memory cells, which do not involve all of the plurality of planes, at least one of the bit line ramp rate of the bit line voltage applied to the bit line and the word line ramp rate of at least one word line voltage applied to the word line is adjusted based on the amount of the plurality of planes associated with the plurality of memory cells being programmed and verified in the program operation during program operations.

14. The method of claim 13, wherein the memory device further comprises a default bit line voltage ramp lookup table having a plurality of default bit line voltage ramp rates, and a shifted bit line voltage ramp lookup table having a plurality of bit line shift offsets, and the method further comprises the following steps: Referring to the default bit line voltage ramp rate lookup table and the shift bit line voltage ramp rate lookup table, and based on one of the plurality of bit line shift offsets and the amount of the plurality of planes associated with the plurality of memory cells programmed and verified in the program operation, it is determined which of the plurality of default bit line voltage ramp rates is used in the program operation.

15. The method of claim 14, wherein during the bit line voltage ramp change time period of the program operation, the bit line voltage ramp is changed according to the default bit line voltage ramp rate lookup table and the shifted bit line voltage ramp rate lookup table and based on the amount of the plurality of planes associated with the plurality of memory cells programmed and verified in the program operation, and the method further comprises the following steps: The time period for the bit line voltage ramp change used in the program operation is automatically determined based on the ramp change of the bit line voltage, according to the default bit line voltage ramp rate lookup table and the shifted bit line voltage ramp rate lookup table, and based on the quantities of the multiple planes associated with the multiple memory cells that are programmed and verified in the program operation.

16. The method of claim 13, wherein the word lines include selected word lines that are programmed and verified at a certain time during the program operation and a plurality of unselected word lines that are not programmed and verified at that time, and the at least one word line voltage includes a pass voltage applied to the plurality of selected word lines and the plurality of unselected word lines during the programming portion of the program operation, the memory device further comprising a default pass voltage ramp lookup table having a plurality of default pass voltage ramp rates and a shift pass voltage ramp lookup table having a plurality of pass voltage shift offsets, the method further comprising the steps of: Based on one of the plurality of through voltage shift offsets and based on the amount of the plurality of planes associated with the plurality of memory cells programmed and verified in the program operation, one of the plurality of default through voltage ramp rates used in the program operation is shifted.

17. The method of claim 16, wherein during the through voltage ramp change time period of the program operation, the through voltage ramp is changed according to the default through voltage ramp rate lookup table and the shifted through voltage ramp rate lookup table and based on the amount of the plurality of planes associated with the plurality of memory cells programmed and verified in the program operation, and the memory device further includes a default through voltage ramp change time period lookup table having a plurality of default through voltage ramp change times and a shifted through voltage ramp change time period lookup table having a plurality of through voltage ramp change time period offsets, the method further comprising the following steps: Based on one of the plurality of through voltage ramp change time offsets and based on the amount of the plurality of planes associated with the plurality of memory cells programmed and verified in the program operation, a default through voltage ramp change time used in the program operation is shifted.

18. The method of claim 13, wherein the word lines include selected word lines that are programmed and verified at a certain time during the program operation and a plurality of unselected word lines that are not programmed and verified at that time, and the at least one word line voltage includes a read voltage applied to the plurality of selected word lines and the plurality of unselected word lines during the verification portion of the program operation, and the memory device further includes a default read voltage ramp lookup table having a plurality of default read voltage ramp rates and a shift read voltage ramp lookup table having a plurality of read voltage shift offsets, the method further comprising the steps of: Based on one of the plurality of read voltage shift offsets and based on the amount of the plurality of planes associated with the plurality of memory cells programmed and verified in the program operation, a default read voltage ramp rate is shifted from one of the plurality of default read voltage ramp rates used in the program operation.

19. The method of claim 18, wherein during the read voltage ramp change time period of the program operation, the read voltage ramp is changed according to the default read voltage ramp rate lookup table and the shifted read voltage ramp rate lookup table, and the memory device further includes a default read voltage ramp change time period lookup table having a plurality of default read voltage ramp change times and a shifted read voltage ramp change time period lookup table having a plurality of read voltage ramp change time period offsets, the method further comprising the following steps: Based on one of the read voltage ramp change time offsets and the amount of the plurality of planes associated with the plurality of memory cells programmed and verified in the program operation, a default read voltage ramp change time used in the program operation is shifted.

20. The method of claim 13, further comprising the following steps: In response to program operations on the plurality of memory cells that do not involve all of the plurality of planes, the word line ramp rate of the at least one word line voltage applied to the word line is not adjusted during program operations on the plurality of memory cells.

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