Integrated circuit structure and method of fabricating the same

Abstract

The present application discloses an integrated circuit structure and a method for fabricating the same. The integrated circuit structure includes a substrate having a circuit region formed thereon, a copper interconnect structure formed on the substrate, the copper interconnect structure including an uppermost copper layer covered by a dielectric layer, an aluminum pad layer formed on the dielectric layer, and a metal layer formed on the circuit region and between the uppermost copper layer and the aluminum pad layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular, to an integrated circuit (IC) structure with a shield layer and a manufacturing method thereof. BACKGROUND

[0002] An integrated circuit (IC) chip usually includes a plurality of layers (e.g., 3-12 layers) of metal interconnect structures disposed on a substrate (e.g., a silicon substrate). These metal interconnect structures can be high-density metal patterns fabricated with deep sub-micron (e.g., less than 100 nm) design rules, such as copper damascene interconnect structures. On top of the copper damascene interconnect structures, there is a single layer of aluminum metal for bonding pads or a redistribution layer (RDL) for fan-out input / output (I / O) terminals.

[0003] IC chips can be subject to various security attacks in which an unauthorized party attempts to intercept confidential information processed or stored in the IC chip. In the past, in order to protect the IC chip and prevent attacks applied to the IC chip, a shield layer was mainly provided in the bonding pad layer composed of aluminum metal. However, with the development of high-performance computing chips and artificial intelligence chips, in order to increase the bandwidth, the number of I / O terminals on the IC chip has increased significantly, which makes it very difficult to simultaneously fabricate a shield layer and a bonding pad on a single layer of aluminum metal. SUMMARY

[0004] The main purpose of the present application is to provide an improved integrated circuit structure and a manufacturing method thereof to solve the above-mentioned problems and shortcomings of the prior art.

[0005] In one aspect, the present application provides an integrated circuit structure, comprising a substrate including a circuit region; a copper interconnect structure disposed on the substrate, wherein the copper interconnect structure includes an uppermost copper layer covered by a dielectric layer; an aluminum bonding pad layer disposed on the dielectric layer; and a metal layer disposed on the circuit region and between the uppermost copper layer and the aluminum bonding pad layer.

[0006] According to an embodiment of the present application, the metal layer is an aluminum shield metal layer.

[0007] According to an embodiment of the present application, the aluminum shield metal layer is electrically connected to the uppermost copper layer by a tungsten via.

[0008] According to an embodiment of the present application, the width of the tungsten via is microns.

[0009] According to an embodiment of the present application, the dielectric layer comprises a lower dielectric layer and an upper dielectric layer, wherein the tungsten via is disposed in the lower dielectric layer.

[0010] According to an embodiment of the present application, the upper dielectric layer covers the aluminum shield metal layer.

[0011] According to an embodiment of the present application, the aluminum shield metal layer has a width of about microns.

[0012] According to an embodiment of the present application, the upper dielectric layer and the lower dielectric layer are composed of the same dielectric material.

[0013] According to an embodiment of the present application, the upper dielectric layer and the lower dielectric layer comprise silicon oxide.

[0014] According to an embodiment of the present application, the aluminum pad layer is electrically connected to the metal layer through an aluminum via.

[0015] According to an embodiment of the present application, the integrated circuit structure further comprises a passivation layer, which partially covers the aluminum pad layer and partially covers the dielectric layer.

[0016] According to an embodiment of the present application, the passivation layer comprises a phosphor-silicon glass layer and a silicon nitride layer.

[0017] Another aspect of the present application provides a method for forming an integrated circuit structure, comprising: providing a substrate comprising a circuit region thereon; forming a copper interconnection structure on the substrate, wherein the copper interconnection structure comprises an uppermost copper layer covered by a dielectric layer; forming a metal layer on the uppermost copper layer in the circuit region; and forming an aluminum pad layer on the dielectric layer.

[0018] According to an embodiment of the present application, the metal layer is an aluminum shield metal layer.

[0019] According to an embodiment of the present application, the aluminum shield metal layer is electrically connected to the uppermost copper layer through a tungsten via.

[0020] According to an embodiment of the present application, the tungsten via has a width of about microns.

[0021] According to an embodiment of the present application, forming the metal layer on the uppermost copper layer in the circuit region comprises: forming a lower dielectric layer; forming the tungsten via in the lower dielectric layer; forming the aluminum shield metal layer on the lower dielectric layer; and forming the upper dielectric layer on the aluminum shield metal layer and the lower dielectric layer.

[0022] According to an embodiment of the present application, the upper dielectric layer is thicker than the lower dielectric layer.

[0023] According to an embodiment of the present application, the upper dielectric layer and the lower dielectric layer are composed of the same dielectric material.

[0024] According to an embodiment of the present application, the method further comprises forming a passivation layer partially covering the aluminum pad layer and partially covering the dielectric layer. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 Partial cross-sectional view of an integrated circuit structure according to an embodiment of the present application;

[0026] Figure 2 Top view of an aluminum shield metal layer;

[0027] Figure 3 Schematic view of a tungsten via, an aluminum wiring pattern and a topmost copper layer, with partial layout and associated dimensions;

[0028] Figures 4 to 7 Schematic view of a method of forming an integrated circuit structure according to an embodiment of the present application.

[0029] MAIN ELEMENT SYMBOL EXPLANATION

[0030] 100 substrate

[0031] 110-118 dielectric layers

[0032] 118L lower dielectric layer

[0033] 118U upper dielectric layer

[0034] 120 passivation layer

[0035] 121 phosphosilicate glass layer

[0036] 122 silicon nitride layer

[0037] AL aluminum pad layer

[0038] AP, ARP pad patterns

[0039] ARL redistribution layer

[0040] AV, ARV aluminum via

[0041] C plug

[0042] CRP circuit region

[0043] CR circuit region

[0044] D1, D2 circuit elements

[0045] DD doped region

[0046] DF conductive region

[0047] DP, DI copper interconnect structure

[0048] OP, OPP opening

[0049] PC plug

[0050] PM1, PM2, PM3, M1, M2, M3 copper metal layer

[0051] PV1, PV2, V1, V2 copper metal via

[0052] S1, S2 distance

[0053] SL aluminum shield metal layer

[0054] SLR aluminum wire pattern

[0055] SLP aluminum link pad

[0056] W1, W2 width

[0057] WH, ARVH, AVH via

[0058] WV tungsten via DETAILED DESCRIPTION

[0059] In the following detailed description, reference will be made to the accompanying drawings, which form a part of this specification. The illustrative embodiments described in the detailed description, which are described in sufficient detail to enable those skilled in the art to practice the embodiments, can be combined with each other in order to produce the embodiments of the present application. The embodiments can also be implemented using well-known concepts, structures and technology's that are not necessarily further explained.

[0060] Of course, other embodiments can also be implemented or described herein, or modifications can be made to anything described herein, without departing from the scope of the present application. Accordingly, the teachings provided herein can be modified through various changes not described herein, and such changes are proposed to be covered by the appended claims.

[0061] Referring to Figure 1 , which is a partial cross-sectional view of an integrated circuit structure according to an embodiment of the present application, as shown in Figure 1 , the integrated circuit structure 1 includes a substrate 100, such as a silicon substrate. There can be a circuit region CRP and a circuit region CR on the substrate 100. According to an embodiment of the present application, the circuit region CRP can be a circuit region that stores confidential information and needs to be protected, such as an embedded memory region, but is not limited thereto. According to an embodiment of the present application, the circuit region CR can be a logic core circuit region or other functional circuit block, but is not limited thereto.

[0062] According to an embodiment of the present application, at least one circuit element D1 and at least one circuit element D2 can be formed on the substrate 100 within the circuit region CRP and the circuit region CR, respectively. According to an embodiment of the present application, the circuit element D1 can be, for example, an embedded flash memory cell, and the circuit element D2 can be, for example, a field effect transistor, but the present application is not limited thereto. It should be understood by those skilled in the art that the number and structure of the circuit element D1 and the circuit element D2 in Figure 1 are only illustrative.

[0063] According to an embodiment of the present application, a plurality of dielectric layers 110-118, such as silicon oxide, silicon nitride, or low-k material layers, are further provided on the substrate 100. For example, the dielectric layer 110 can be a silicon oxide layer, the dielectric layers 111 and 113 can be carbon-doped silicon nitride (SiCN) layers, the dielectric layer 112 can be a fluorosilicate glass (FSG) layer, the dielectric layers 114 and 116 can be silicon oxide layers, and the dielectric layers 115 and 117 can be silicon nitride layers, but the present application is not limited thereto.

[0064] According to an embodiment of the present application, at least one copper interconnect structure DP is formed in the plurality of dielectric layers 110-118 within the circuit region CRP. According to an embodiment of the present application, the copper interconnect structure DP can include copper metal layers PM1, PM2, and PM3, wherein the copper metal layer PM1 can be electrically connected to the conductive region DF on the substrate 100 through the plug PC, the copper metal layer PM2 can be electrically connected to the copper metal layer PM1 through a copper metal via PV1, and the copper metal layer PM3 can be electrically connected to the copper metal layer PM2 through a copper metal via PV2. It should be understood by those skilled in the art that the number and structure of the metal layers of the copper interconnect structure DP in Figure 1 are only illustrative.

[0065] According to an embodiment of the present application, the copper metal layer PM1 and the plug PC can be formed in the dielectric layer 110, the copper metal layer PM2 and the copper metal via PV1 can be formed in the dielectric layers 111 and 112, and the copper metal layer PM3 and the copper metal via PV2 can be formed in the dielectric layers 113-116. According to an embodiment of the present application, the copper interconnect structure DP can be formed by a copper damascene process, and details of the copper damascene process are not described herein since it is a well-known technique. In this embodiment, the copper metal layer PM3 is the uppermost copper layer of the copper interconnect structure DP. After chemical mechanical polishing (CMP) of the copper metal layer PM3 is completed, the copper surface of the copper metal layer PM3 is finally covered by the dielectric layer 117 to avoid oxidation.

[0066] Similarly, at least one copper interconnect structure DI can be formed in the plurality of dielectric layers 110-118 in the circuit region CR. According to embodiments of the present application, the copper interconnect structure DI can include copper metal layers Ml, M2 and M3, wherein the copper metal layer Ml can be electrically connected to the doped region DD on the substrate 100 through the plug C, the copper metal layer M2 can be electrically connected to the copper metal layer Ml through the copper metal via Vl, and the copper metal layer M3 can be electrically connected to the copper metal layer M2 through the copper metal via V2.

[0067] According to embodiments of the present application, the topmost copper layers of the copper interconnect structure DP and the copper interconnect structure DI, the copper metal layer PM3 and the copper metal layer M3, are covered by the dielectric layer 118. According to embodiments of the present application, the dielectric layer 118 can include a silicon oxide layer. According to embodiments of the present application, the dielectric layer 118 can include a lower dielectric layer 118L and an upper dielectric layer 118U. According to embodiments of the present application, the upper dielectric layer 118U and the lower dielectric layer 118L can be composed of the same dielectric material. According to embodiments of the present application, for example, the upper dielectric layer 118U and the lower dielectric layer 118L can both include silicon oxide. In other embodiments, the upper dielectric layer 118U and the lower dielectric layer 118L can be composed of different dielectric materials. According to embodiments of the present application, the upper dielectric layer 118U is thicker than the lower dielectric layer 118L.

[0068] According to embodiments of the present application, an aluminum pad layer AL is disposed on the dielectric layer 118. For example, the aluminum pad layer AL can include a pad pattern AP in the circuit region CR, which is electrically connected to the copper metal layer M3 through aluminum vias AV formed in the dielectric layer 118 and the dielectric layer 117. For example, the aluminum pad layer AL can include a pad pattern ARP and a redistribution layer ARL in the circuit region CRP, and the aluminum pad layer AL is electrically connected to an aluminum shield metal layer SL through aluminum vias ARV formed in the upper dielectric layer 118U. According to embodiments of the present application, the aluminum shield metal layer SL is disposed directly above the circuit region CRP and between the topmost copper layer PM3 and the aluminum pad layer AL to protect the circuit region CRP. According to embodiments of the present application, the aluminum shield metal layer SL can include at least one aluminum wire pattern SLR and at least one aluminum pad SLP, and the aluminum vias ARV are disposed directly on the aluminum pad SLP.

[0069] Figure 2 An upper view of the aluminum shield metal layer SL is shown. According to embodiments of the present application, as shown in FIG. 15, the aluminum shield metal layer SL can be composed of a plurality of concentric circular aluminum wire patterns SLR, which can overlap the circuit region CRP, but is not limited thereto. The layout pattern of the aluminum wire SLR can be determined according to actual design requirements. Those skilled in the art should understand that the number and layout of the aluminum wire SLR in FIG. 15 are only illustrative. Figure 2 Figure 2 For example, the aluminum wire pattern SLR can include a plurality of concentric circular aluminum wire patterns SLR, which can overlap the circuit region CRP, but is not limited thereto. The layout pattern of the aluminum wire SLR can be determined according to actual design requirements. Those skilled in the art should understand that the number and layout of the aluminum wire SLR in FIG. 15 are only illustrative. For example, the aluminum wire pattern SLR can include a plurality of concentric circular aluminum wire patterns SLR, which can overlap the circuit region CRP, but is not limited thereto. The layout pattern of the aluminum wire SLR can be determined according to actual design requirements. Those skilled in the art should understand that the number and layout of the aluminum wire SLR in FIG. 15 are only illustrative.​Figure 2 As shown, the aluminum pads SLP for electrically connecting with the aluminum vias ARV can be disposed on the same side of the aluminum shielding metal layer SL, for example, but not limited thereto.

[0070] According to an embodiment of the present application, as shown in Figure 1 The integrated circuit structure 1 can further include a passivation layer 120 partially covering the aluminum pad layer AL and partially covering the dielectric layer 118. According to an embodiment of the present application, the passivation layer 120 can include a phosphor-silicon glass layer 121 and a silicon nitride layer 122, but not limited thereto. The passivation layer 120 can include an opening OP exposing part of the pad pattern AP and an opening OPP exposing part of the pad pattern ARP.

[0071] According to an embodiment of the present application, as shown in Figure 1 The aluminum wire pattern SLR of the aluminum shielding metal layer SL can be electrically connected to the uppermost copper layer PM3 through at least one tungsten via WV. According to an embodiment of the present application, the tungsten via WV is disposed in the lower dielectric layer 118L. Since the size of the via between the aluminum wire pattern SLR and the uppermost copper layer PM3 is small, and the filling ability or step coverage ability of the aluminum metal fabrication process is poor, in order to avoid the problem that the aluminum metal fabrication process cannot completely fill such a small via, resulting in defects, the present application uses a tungsten via to electrically connect the aluminum wire pattern SLR and the uppermost copper layer PM3.

[0072] Figure 3 The local layout and related dimensions of the tungsten via WV, the aluminum wire pattern SLR and the uppermost copper layer PM3 are illustrated. According to an embodiment of the present application, as shown in Figure 3 The width Wl of the tungsten via WV is about microns, and the distance S1 between the tungsten vias WV is about 0.7-1.5 microns. In addition, the width (line width) W2 of the aluminum wire pattern SLR is about microns, and the distance S2 between the aluminum wire patterns SLR is about 0.5-2 microns.

[0073] Please refer to Figures 4 to 7 which is a schematic diagram of a method for forming an integrated circuit structure according to an embodiment of the present application, wherein the same regions, layers or elements still use the same symbols to represent. As shown in Figure 4 First, a substrate 100 including a circuit region CRP and a circuit region CR is provided. Then, a copper interconnection structure DP including an uppermost copper layer PM3 covered by a dielectric layer 117 and a copper interconnection structure DI including an uppermost copper layer M3 covered by a dielectric layer 117 are formed on the substrate 100 in the circuit region CRP and the circuit region CR, respectively. Those skilled in the art should understand Figure 4The number and structure of the copper interconnect structures DP and DI in the example are only for illustration.

[0074] According to an embodiment of the present invention, multiple dielectric layers 110 to 118 are sequentially deposited on a substrate 100 using a chemical vapor deposition (CVD) process. These layers may be, for example, silicon oxide, silicon nitride, or a low dielectric constant material layer. For instance, dielectric layer 110 may be a silicon oxide layer, dielectric layers 111 and 113 may be doped silicon carbonitride layers, dielectric layer 112 may be a fluorosilicone glass layer, dielectric layers 114 and 116 may be silicon oxide layers, and dielectric layers 115 and 117 may be silicon nitride layers, but the method is not limited to these.

[0075] According to embodiments of the present invention, copper interconnect structures DP are formed in multilayer dielectric layers 110 to 118 within the circuit region CRP. According to embodiments of the present invention, for example, the copper interconnect structure DP may include copper metal layers PM1, PM2, and PM3, wherein copper metal layer PM1 is electrically connected to the conductive region DF on the substrate 100 via a plug PC, copper metal layer PM2 is electrically connected to copper metal layer PM1 via a copper metal via PV1, and copper metal layer PM3 is electrically connected to copper metal layer PM2 via a copper metal via PV2.

[0076] According to an embodiment of the present invention, copper metal layer PM1 and plug PC can be formed in dielectric layer 110, copper metal layer PM2 and copper via PV1 can be formed in dielectric layers 111 and 112, and copper metal layer PM3 and copper via PV2 can be formed in dielectric layers 113-116. According to an embodiment of the present invention, the copper interconnect structure DP can be formed using a copper damascene fabrication process. Since the copper damascene fabrication process is a known technology, its details will not be elaborated further. In this embodiment, after the chemical mechanical polishing of copper metal layer PM3 is completed, the copper surface of copper metal layer PM3 is finally covered with dielectric layer 117 to prevent oxidation.

[0077] like Figure 5 As shown, a chemical vapor deposition process can then be performed to deposit a lower dielectric layer 118L, such as a silicon oxide layer, over the entire surface of the dielectric layer 117. Next, photolithography and etching processes are performed to form at least one via WH in the lower dielectric layer 118L within the circuit region CRP. Then, a tungsten metal deposition process is performed, for example, by chemical vapor deposition, to fill the via WH with a tungsten metal layer. Finally, a chemical mechanical polishing process is performed to remove excess tungsten metal outside the via WH, thus forming a tungsten via WV in the lower dielectric layer 118L. According to an embodiment of the present invention, the width of the tungsten via WV is... Micrometer.

[0078] like Figure 6As shown, an aluminum metal deposition process is then performed to deposit an aluminum metal layer over the lower dielectric layer 118L and the tungsten via WV. According to an embodiment of the invention, the thickness of the aluminum metal layer can be, for example, between 0.3 and 0.7 micrometers, but is not limited thereto. Then, a photolithography and etching process is performed to pattern the aluminum metal layer, forming an aluminum shielding metal layer SL. According to an embodiment of the invention, the aluminum shielding metal layer SL is directly disposed above the circuit region CRP to protect the circuit region CRP. According to an embodiment of the invention, the aluminum shielding metal layer SL may include at least one aluminum wire loop pattern SLR and at least one aluminum pad SLP. According to an embodiment of the invention, the aluminum shielding metal layer SL is electrically connected to the uppermost copper layer PM3 through the tungsten via WV. Next, an upper dielectric layer 118U is deposited on the aluminum shielding metal layer SL and the lower dielectric layer 118L. According to an embodiment of the invention, the upper dielectric layer 118U is thicker than the lower dielectric layer 118L. According to an embodiment of the invention, the upper dielectric layer 118U and the lower dielectric layer 118L may be composed of the same dielectric material.

[0079] like Figure 7 As shown, photolithography and etching processes are then performed to form vias ARVH and AVH in the dielectric layer 118 within the circuit region CRP and circuit region CR, respectively. The ARVH is formed only in the upper dielectric layer 118U, while the AVH penetrates the upper dielectric layer 118U, the lower dielectric layer 118L, and the dielectric layer 117. According to an embodiment of the present invention, the ARVH and AVH expose portions of the aluminum pad SLP and the copper metal layer M3, respectively. Next, an aluminum metal deposition process is performed to form an aluminum metal layer within the ARVH and AVH and on the dielectric layer 118, with a thickness greater than the thickness of the aluminum shielding metal layer SL. The aluminum metal layer is then patterned using photolithography and etching processes to form the aluminum pad layer AL. For example, the aluminum pad layer AL may contain a pad pattern AP within the circuit region CR, and be electrically connected to the copper metal layer M3 via aluminum vias AV formed in the dielectric layers 118 and 117. The aluminum pad layer AL may contain a pad pattern ARP and a redistribution layer ARL within the circuit region CRP, and the aluminum pad layer AL may be electrically connected to the aluminum shielding metal layer SL via aluminum vias ARV formed in the upper dielectric layer 118L.

[0080] According to an embodiment of the present invention, a passivation layer 120 is finally deposited, partially covering the aluminum pad layer AL and partially covering the dielectric layer 118. According to an embodiment of the present invention, the passivation layer 120 may include a phosphosilicate glass layer 121 and a silicon nitride layer 122, but is not limited thereto. The passivation layer 120 may include openings OP, exposing a portion of the pad pattern AP, and openings OPP, exposing a portion of the pad pattern ARP.

[0081] The above merely describes the preferred embodiments of the present application, and any equivalent changes and modifications made according to the claims of the present application shall fall within the scope of the present application.

Claims

1. An integrated circuit structure, characterized by An integrated circuit structure comprising: a substrate comprising a circuit region thereon; a copper interconnect structure disposed on the substrate, wherein the copper interconnect structure comprises an uppermost copper layer covered by a dielectric layer; an aluminum pad layer disposed on the dielectric layer; and a metal layer disposed on the circuit region and between the uppermost copper layer and the aluminum pad layer, wherein the metal layer comprises at least one wire pattern in the form of a plurality of concentric circles and at least one pad.

2. The integrated circuit structure of claim 1, wherein the metal layer is an aluminum shield metal layer.

3. The integrated circuit structure of claim 2, wherein the aluminum shield metal layer is electrically connected to the uppermost copper layer by a tungsten via.

4. The integrated circuit structure of claim 3, wherein the tungsten via has a width of 0.3 0.8 microns.

5. The integrated circuit structure of claim 3, wherein the dielectric layer comprises a lower dielectric layer and an upper dielectric layer, wherein the tungsten via is disposed in the lower dielectric layer.

6. The integrated circuit structure of claim 5, wherein the upper dielectric layer covers the aluminum shield metal layer.

7. The integrated circuit structure of claim 5, wherein the aluminum shield metal layer has a width of about 0.5 2 microns.​ 8. The integrated circuit structure of claim 5, wherein the upper dielectric layer and the lower dielectric layer are composed of the same dielectric material.

9. The integrated circuit structure of claim 5, wherein the upper dielectric layer and the lower dielectric layer comprise silicon oxide.

10. The integrated circuit structure of claim 1, wherein the aluminum pad layer is electrically connected to the metal layer by an aluminum via.

11. The integrated circuit structure of claim 1, further comprising: a passivation layer partially covering the aluminum pad layer and partially covering the dielectric layer.

12. The integrated circuit structure of claim 11, wherein the passivation layer comprises a phosphosilicate glass layer and a silicon nitride layer.

13. A method of forming an integrated circuit structure, comprising: providing a substrate comprising a circuit region thereon; forming a copper interconnect structure on the substrate, wherein the copper interconnect structure comprises an uppermost copper layer covered by a dielectric layer; forming a metal layer on the uppermost copper layer within the circuit region; and forming an aluminum pad layer on the dielectric layer, wherein, the metal layer comprising at least one wire pattern in the form of a plurality of concentric circles and at least one pad.

14. The method of claim 13, wherein the metal layer is an aluminum shield metal layer.

15. The method of claim 14, wherein the aluminum shield metal layer is electrically connected to the uppermost copper layer by a tungsten via.

16. The method of claim 15, wherein the tungsten via has a width of 0.3 0.8 microns.

17. The method of claim 15, wherein forming the metal layer on the uppermost copper layer within the circuit region comprises: forming a lower dielectric layer; forming the tungsten via in the lower dielectric layer; forming the aluminum shield metal layer on the lower dielectric layer; and forming an upper dielectric layer on the aluminum shield metal layer and the lower dielectric layer.

18. The method of claim 17, wherein the upper dielectric layer is thicker than the lower dielectric layer.

19. The method of claim 17, wherein the upper dielectric layer and the lower dielectric layer are composed of the same dielectric material.

20. The method of claim 13, further comprising: forming a passivation layer partially covering the aluminum pad layer and partially covering the dielectric layer.

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