analog / digital conversion circuit

Abstract

An A / D conversion circuit is provided that can eliminate the excessive allocation of [capacitor DAC settling time] to achieve high speed. An analog / digital conversion circuit (10) is of the successive approximation type, which converts analog input into digital conversion value by repeatedly performing conversion data generation operation, potential generation operation and comparison operation with a quantity corresponding to the resolution bits, and converts analog input into digital conversion value by repeatedly performing conversion data generation operation of conversion data generator (40), potential generation operation of capacitor DAC (2) and comparison operation of comparator (3) with a quantity corresponding to the resolution bits. The analog / digital conversion circuit (10) has a comparator operation signal generation circuit (5), which predicts the time when the potential generated by capacitor DAC (2) is stable based on the charging and discharging time of capacitor element (51) with characteristics equal to the capacitors C0 to C(n-1) used in capacitor DAC (2), and generates a comparator operation signal that causes comparator (3) to start comparison operation.

Description

Technical Field

[0001] This invention relates to successive approximation type analog-to-digital conversion circuits (hereinafter referred to as A / D conversion circuits). Background Technology

[0002] An A / D conversion circuit is a device that "digitizes" the input analog "voltage" for the purpose of digital processing. Successive approximation type circuits, which offer a good balance between high speed, area, and power consumption, are often used.

[0003] Reference Figure 7 The successive approximation type A / D conversion circuit 1 compares the potential generated by capacitor DAC 2 based on the potential of the simulated input through comparator 3, and feeds the result back to the conversion data generator 4, which then passes the approximate data candidate to capacitor DAC 2. This process is repeated in a number of bits corresponding to the resolution (n bits: n times) to obtain the digital conversion value.

[0004] Prior art literature

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 62-133821

[0007] Patent Document 2: Japanese Patent Application Publication No. 51-015363 Summary of the Invention

[0008] The problem that the invention aims to solve

[0009] Capacitors C0 to C of DAC 2 (n-1) For the bit(n-1) to be switched, such as 2 (n-1) That's how the weighting is performed. Here, the settling time of each bit until capacitor DAC 2 reaches the target level is proportional to the change in output potential, and the change in output potential is proportional to the capacitance C0~C10. (n-1) The amount of charge during charging and discharging is proportional to the capacitance C0 to C0. (n-1) The amount of charge used for charging and discharging is proportional to the capacitance of the bit to be switched. Therefore, the settling time of capacitor DAC 2 is inconsistent with the bit to be switched.

[0010] Assuming the resolution of the successive approximation type A / D conversion circuit 1 is (n) bits, in order to obtain a digital value from an analog value, the conversion data generation operation [conversion data generation time] of the conversion data generator 4, the potential generation operation [capacitor DAC stabilization time] of the capacitor DAC 2, and the comparison operation [comparison operation time] of the comparator 3 are repeatedly performed n times, and finally the conversion data generation operation [conversion data generation time] of the conversion data generator 4 is executed.

[0011] Therefore, the conversion time is

[0012] {[Conversion data generation time] + [Capacitor DAC stabilization time] + [Comparison operation time]} × n (times) + [Conversion data generation time].

[0013] When using equally spaced switching clocks to control this action, such as Figure 8 As shown in (a), the [capacitor DAC settling time] allocated for the potential generation action of capacitor DAC 2 assumes that the settling time of each bit is the largest, and the time T is set to be the same from the high bit to the low bit. Figure 8 An example with a 12-bit resolution is shown.

[0014] However, in reality, the settling time in capacitor DAC 2 is inconsistent with the bit to be switched, tending to be shorter for lower-order bits. Therefore, Figure 8 In (b), the useless time indicated by the slash is allocated as the [capacitor DAC settling time], which hinders the high-speed operation of A / D conversion circuit 1.

[0015] In addition, techniques have been proposed to advance the conversion clock for determining the low-order bits compared to the conversion clock for determining the high-order bits (for example, see Patent Documents 1 and 2).

[0016] However, in patent documents 1 and 2, shift registers and counters are used to change the conversion clock, without considering the possibility that the capacitor value may change due to process factors, thus altering the settling time of capacitor DAC 2. Therefore, sufficient margin is needed to cover the expected amount of capacitor value variation when setting the conversion clock period; this margin becomes the allocation of excess [capacitor DAC settling time].

[0017] This invention was made in view of the following problems, and its object is to provide an A / D conversion circuit that can achieve high speed by eliminating the allocation of excessive [capacitor DAC settling time].

[0018] Methods for solving problems

[0019] To achieve the above-mentioned objectives, the A / D conversion circuit of the present invention is configured as follows.

[0020] The A / D conversion circuit of the present invention is a successive approximation type. It converts analog input into digital value by repeatedly performing the conversion data generation operation of the conversion data generator, the potential generation operation of the capacitor DAC, and the comparison operation of the comparator with an amount corresponding to the resolution bits. The analog / digital conversion circuit is characterized in that it has a comparator operation signal generation circuit. The comparator operation signal generation circuit predicts the moment when the potential generated by the capacitor DAC stabilizes based on the charging and discharging time of a capacitor element with characteristics equal to that used in the capacitor DAC, and generates a comparator operation signal that causes the comparator to start the comparison operation.

[0021] Invention Effects

[0022] The A / D conversion circuit of the present invention has the following effect: by using a capacitor element 51 with the same characteristics as the capacitor used in the capacitor DAC 2, it is possible to predict the actual required [capacitor DAC settling time], and to eliminate the allocation of excessive [capacitor DAC settling time] to achieve a high-speed effect. Attached Figure Description

[0023] Figure 1 This is a block diagram illustrating the structure of a first embodiment of the A / D conversion circuit of the present invention.

[0024] Figure 2 This is a diagram illustrating the operation of an A / D conversion circuit.

[0025] Figure 3 It is shown Figure 1 The diagram shows a first variation of the comparator action signal generation circuit.

[0026] Figure 4 It is shown Figure 1 The diagram shows a second variation of the comparator operation signal generation circuit.

[0027] Figure 5 It is shown Figure 1 The diagram shows a third variation of the comparator action signal generation circuit.

[0028] Figure 6 It is shown Figure 1 The diagram shows a fourth variation of the comparator action signal generation circuit.

[0029] Figure 7 This is a diagram showing the structure of an existing A / D conversion circuit.

[0030] Figure 8 This is an operational diagram illustrating the existing A / D conversion circuit. Detailed Implementation

[0031] The preferred embodiments of the present invention will now be described with reference to the accompanying drawings. Furthermore, in the embodiments, structures representing the same functions are labeled with the same reference numerals, and descriptions are appropriately omitted.

[0032] The A / D conversion circuit 10 in this embodiment is a successive approximation type, refer to... Figure 1 It has a capacitor DAC 2, a comparator 3, a conversion data generator 40, and a comparator action signal generation circuit 5.

[0033] The A / D conversion circuit 10 compares the potential generated by capacitor DAC 2 based on the potential of the simulated input using comparator 3, and feeds the result back to the conversion data generator 40, which then passes the approximate data candidate to capacitor DAC 2. This process is repeated in increments corresponding to the resolution bits (n bits: n times) to obtain the digital conversion value.

[0034] In capacitor DAC 2, for the bit(n-1) to be switched, such as 2... (n-1) The capacitors C0 to C are weighted in that way. (n-1) Each capacitor has one end connected to a common comparison wiring 21, and the potential of comparison wiring 21 is compared with the reference potential Vref by comparator 3. Capacitors C0 to C... (n-1) The other ends of each are respectively connected to switches 220-22 (n-1) Connect any one of the following: analog input (potential), reference potential (High), and reference potential (Low). Additionally, capacitor C... a It is a virtual capacitor with a capacitance value of C0, where C is the capacitance value. a One end is connected to the comparator wiring 21, and the other end is connected to the switch 22. a Choose either the analog input (potential) or the reference potential (Low) and connect them.

[0035] In capacitor DAC 2, capacitors C0 to C1 are switched according to the bit to be switched. (n-1) Each of them is connected via switches 220 to 22 (n-1) It is connected to a reference potential (High) or a reference potential (Low), thereby achieving the target level. Therefore, via switches 220 to 22... (n-1) Make the capacitor C0~C (n-1) The time taken to charge to the reference potential (High) or discharge to the reference potential (Low) is called the settling time.

[0036] The comparator action signal generation circuit 5 predicts the moment when the potential generated by the capacitor DAC 2 stabilizes based on the conversion data generated by the conversion data generator 40, and generates a comparator action signal that causes the comparator 3 to start comparison operation.

[0037] The comparator action signal generation circuit 5 has the characteristics of capacitors C0 to C1 used in DAC 2. (n-1) The circuit includes an equal capacitor element 51, a charge / discharge switch 52 for the capacitor element 51, a potential switching switch 53 for switching the charging potential of the capacitor element 51, and an inverter circuit 54 that outputs a comparison start signal when the potential of the capacitor element 51 is lower than the threshold potential.

[0038] One end of capacitor element 51 is connected to the ground terminal, and the other end is connected to the input terminal of inverter circuit 54 and one end of charge / discharge switch 52. Charge / discharge switch 52 has a charging switch 521 that connects the other end of capacitor element 51 to one end of potential switching switch 53, and a discharging switch 522 that connects the other end of capacitor element 51 to the ground terminal. The on / off state of charging switch 521 and discharging switch 522 is controlled by a charge / discharge indication signal from conversion data generator 40. For example, if the charge / discharge indication signal is Low, charging switch 521 is controlled to be on and discharging switch 522 is controlled to be off; if the charge / discharge indication signal is High, charging switch 521 is controlled to be off and discharging switch 522 is controlled to be on.

[0039] Discharge switch 522 uses capacitors C0 to C (n-1) Switches 220-22 are used when connecting to a reference potential (High) or a reference potential (Low). (n-1) The switch has the same on-resistance as the discharge switch 522. Furthermore, the charging switch 521 uses a switch with a lower on-resistance than the discharging switch 522 to handle rapid charging.

[0040] The potential switching switch 53 has n connection switches 531 corresponding to the resolution bits, which connect the other end of the capacitor element 51 to n injection potentials (n-1) to (0) corresponding to the resolution bits, respectively. (n-1) ~531 (0) The injection potential is selected from the injection potential (n-1) to the injection potential (0) to inject (charge) charge into the capacitor element 51 by means of the potential switching indication signal from the conversion data generator 40, and the switching is performed.

[0041] The injection potentials (n-1) to (0) are potentials used to simulate the amount of charge injected or discharged into capacitor DAC 2. They are set to the maximum value of the settling time (which becomes the reference potential by charging) of each most significant bit to least significant bit when the capacitor element 51 discharges and the time until it reaches the threshold potential of the inverter circuit 54.

[0042] Next, refer to Figure 2 The operation of the A / D conversion circuit 10 is explained in detail.

[0043] The conversion data generator 40 instructs the comparator action signal generation circuit 5 to connect to the injection potential (n-1) corresponding to the most significant bit via a potential switching indication signal, and pre-sets the charge / discharge indication signal to Low to charge the capacitor element 51 to the injection potential (n-1). When a conversion start signal is input, the conversion data generation operation begins.

[0044] Next, the conversion data generator 40, at the timing of the action start signal generated after a predetermined time from the conversion start signal (after the conversion data generation action is completed), outputs the highest bit of the capacitor DAC input value to the capacitor DAC 2, and at the same time instructs the comparator action signal generation circuit 5 to switch the charge / discharge indication signal to High and discharge from the capacitor element 51.

[0045] The capacitor DAC 2 generates a potential for determining the most significant bit through a potential generation operation. When the injection potential (n-1) of the capacitor element 51, which is charged into the capacitor element 51, drops below the threshold potential of the inverter circuit due to discharge, the comparator operation signal generation circuit 5 outputs a comparison start signal to the comparator 3 and the conversion data generator 40. That is, the comparator operation signal generation circuit 5 uses a capacitor element 51 with characteristics equal to the capacitor used in the capacitor DAC 2 and injection potentials (0) to (n-1) to predict the settling time of the capacitor DAC 2, which varies according to each bit to be switched, and outputs a comparison start signal at the timing when the settling time ends.

[0046] By inputting the start comparison signal, comparator 3 compares the potential generated by the potential generation operation of capacitor DAC 2 with the reference potential and outputs the comparison result to conversion data generator 40. Furthermore, by inputting the start comparison signal, conversion data generator 40 instructs the potential switching switch 53 of comparator operation signal generation circuit 5 to connect to the injection potential (n-2) corresponding to the next bit via a switching indication signal, and sets the charge / discharge indication signal to Low to charge capacitor element 51. Additionally, based on the timing of the conversion signal generated by conversion data generator 40 after a predetermined time from the start comparison signal (after the conversion comparison operation ends), it begins generating the conversion data D of the most significant bit according to the comparison result of comparator 3. (n-1) The data generation action of transformation.

[0047] Next, the conversion data generator 40 generates an action start signal after a predetermined time from the conversion start signal (after the conversion data generation action is completed). Based on the conversion data of the highest bit (the comparison result of comparator 3), it outputs the next bit of the capacitor DAC input value to capacitor DAC 2. At the same time, it instructs the comparator action signal generation circuit 5 to change the charge / discharge indication signal to High and discharge from capacitor element 51.

[0048] The capacitor DAC 2 generates a potential for determining the next bit through a potential generation action. When the potential of the capacitor element 51 drops below the threshold potential of the inverter circuit 54 due to discharge, the comparator action signal generation circuit 5 outputs a comparison start signal to the comparator 3 and the conversion data generator 40.

[0049] By inputting the start comparison signal, comparator 3 compares the potential generated by the potential generation operation of capacitor DAC 2 with the reference potential and outputs the comparison result to conversion data generator 40. Furthermore, by inputting the start comparison signal, conversion data generator 40 instructs the potential switching switch 53 of comparator operation signal generation circuit 5 to connect to the injection potential (n-3) corresponding to the next bit via a switching indication signal, and sets the charge / discharge indication signal to Low to charge capacitor element 51. Additionally, based on the comparison result of comparator 3, conversion data generator 40 starts generating the next bit of conversion data D at the timing of the conversion signal generated a predetermined time after the start comparison signal (after the conversion comparison operation ends). (n-2) The data generation action of transformation.

[0050] The above actions are repeated until the most significant bit is generated, by repeatedly comparing the quantity corresponding to the resolution bits (a 12-bit quantity). The conversion data generator 40 will then generate the conversion data D. (n-1) ~D (0) Output as the transformed value.

[0051] Therefore, the [capacitor DAC settling time] T1~T2 allocated to the potential generation operation of capacitor DAC 2 is... 12 By setting the settling time of each bit to decrease from the most significant bit to the least significant bit, high speed can be achieved. Furthermore, the less significant the bit, the shorter its settling time, but the reduction in time is also smaller. Therefore, multiple pre-defined less significant bits can correspond to the same injection potential.

[0052] Next, refer to Figure 3 The first variation of the comparator action signal generation circuit 5 is described in detail.

[0053] Reference Figure 3 The comparator operation signal generation circuit 5a, as the first variation, has: generation circuit 50 (n-1) ~Generation circuit 50 (0) They respectively predict the settling time of the capacitor DAC 2, which varies according to each bit to be switched, and output a comparison start signal at the timing of the end of the settling time; and output switching switch 55, which controls the output generation circuit 50. (n-1) ~Generation circuit 50 (0)The selection is based on which of the following comparison signals is initiated.

[0054] Generation circuit 50 (n-1) ~Generation circuit 50 (0) Each component has a capacitor element 51, a charge / discharge switch 52, and an inverter circuit 54. One end of each capacitor element 51 is connected to a ground terminal, and the other end is connected to the input terminal of the inverter circuit 54 and one end of the charge / discharge switch 52.

[0055] Generation circuit 50 (n-1) ~Generation circuit 50 (0) The charge / discharge switch 52 has a charging switch 521 that connects the other end of the capacitor element 51 to the injection potential (n-1) to the injection potential (0) respectively, and a discharging switch 522 that connects the other end of the capacitor element 51 to the ground terminal. The charging switch 521 and the discharging switch 522 are controlled to be turned on and off by the charge / discharge indication signal from the conversion data generator 40.

[0056] The output switching switch 55 has n connection switches 551 corresponding to the number of resolution bits. (n-1) ~551 (0) The switching indication signal from the output of the conversion data generator 40 is used to select and switch the data from the generation circuit 50. (n-1) ~Generation circuit 50 (0) The circuit that generates the start signal for output comparison.

[0057] Furthermore, in the comparator action signal generation circuit 5a, the generation circuit 50... (n-1) ~Generation circuit 50 (0) If the charge / discharge switch 52 is configured to be able to switch to discharge independently, the output switching switch 55 can be omitted.

[0058] Next, refer to Figure 4 The second variation of the comparator action signal generation circuit 5 is described in detail.

[0059] Reference Figure 4 In the second variation, the comparator operation signal generation circuit 5b has an output switching switch 55. A timing generation circuit 501, which generates an output comparison start signal using a capacitor element 51 with characteristics identical to the capacitor used in capacitor DAC 2, is connected in N series to this output switching switch 55. The output switching switch 55 selects which comparison start signal to output to comparator 3. Each of the N generation circuits 501 has a capacitor element 51, a charge / discharge switch 52, and an inverter circuit 54, connected in such a way that the comparison start signal output from the inverter circuit 54 is input as a discharge indication signal to the next stage's charge / discharge switch 52.

[0060] In the generation circuit 501, one end of the capacitor element 51 is connected to the ground terminal, and the other end is connected to the input terminal of the inverter circuit 54 and one end of the charge / discharge switch 52. Moreover, the charge / discharge switch 52 has a charging switch 521 that connects the other end of the capacitor element 51 to the injection potential, and a discharging switch 522 that connects the other end of the capacitor element 51 to the ground terminal. Charge is injected into the capacitor element 51 by turning on the charging switch 521 and turning off the discharging switch 522 through the charging indication signal from the conversion data generator 40.

[0061] When all stages of capacitor elements 51 are charged, and a charging indication signal is input from the conversion data generator 40 to the first-stage generation circuit 501, the charging switch 521 is turned off and the discharging switch 522 is turned on in the first-stage generation circuit 501, initiating the discharge from capacitor elements 51. When the potential of capacitor elements 51 falls below the threshold potential of inverter circuit 54 due to discharge, a comparison start signal is output and input as a discharge indication signal to the next-stage charge / discharge switch 52.

[0062] Therefore, by adjusting the output switching switch 55 (connection switch) (N-1) ~551 (0) The control selects the level of the discharge indication signal, thereby predicting the settling time of the capacitor DAC 2, which is different for each bit to be switched. At the timing of the end of the settling time, the comparison start signal is output to the comparator 3.

[0063] Next, refer to Figure 5 The third variation of the comparator action signal generation circuit 5 is described in detail.

[0064] Reference Figure 5 As a third variation, the comparator operation signal generation circuit 5c has an output switching switch 55. A timing generation circuit 501 that generates an output comparison start signal using a capacitor element 51 with characteristics equal to the capacitor used in capacitor DAC 2 is connected to the output switching switch 55 in two stages. The output switching switch 55 selects which comparison start signal to output to comparator 3. Each of the two generation circuits 501 has a capacitor element 51, a charge / discharge switch 52, and an inverter circuit 54, and is connected in such a way that the comparison start signal output from the inverter circuit 54 is input as a discharge indication signal to the charge / discharge switch 52 of the other stage.

[0065] In the generation circuit 501, one end of the capacitor element 51 is connected to the ground terminal, and the other end is connected to the input terminal of the inverter circuit 54 and one end of the charge / discharge switch 52. Moreover, the charge / discharge switch 52 has a charging switch 521 that connects the other end of the capacitor element 51 to the injection potential, and a discharging switch 522 that connects the other end of the capacitor element 51 to the ground terminal. Charge is injected into the capacitor element 51 by turning on the charging switch 521 and turning off the discharging switch 522 through the charging indication signal from the conversion data generator 40.

[0066] When all stages of capacitor elements 51 are charged, and a discharge indication signal is input from the conversion data generator 40 to the first-stage generation circuit 501, the first-stage generation circuit 501 opens the charging switch 521 and opens the discharging switch 522, initiating discharge from capacitor elements 51. When the potential of capacitor elements 51 falls below the threshold potential of inverter circuit 54 due to discharge, a comparison start signal is output. The comparison start signal output from the first-stage generation circuit 501 is input as a discharge indication signal to the second-stage charge / discharge switch 52 and as a completion signal to the conversion data generator 40.

[0067] Therefore, in the second-stage generation circuit 501, the charging switch 521 is turned off and the discharging switch 522 is turned on to begin discharging from the capacitor element 51. The conversion data generator 40 outputs a charging indication signal to the first-stage generation circuit 501 and begins charging the capacitor element 51. Furthermore, when the potential of the capacitor element 51 in the first-stage generation circuit 501 falls below the threshold potential of the inverter circuit 54 due to discharge, a comparison start signal is output and input as a discharging indication signal to the first-stage charge / discharge switch 52, and as a completion signal to the conversion data generator 40.

[0068] Next, at the time after repeated quantization, the comparison start signal is output. The conversion data generator 40 counts the input completion signal and outputs the output switching indication signal to the output switching switch 55 at the desired timing, so that either of the connection switches 5511 and 5512 of the output switching switch 55 is turned on and the comparison start signal is output to the comparator 3.

[0069] Thus, the settling time of the capacitor DAC 2, which varies according to each bit to be switched, can be predicted by the two-stage generation circuit 501, and a comparison start signal is output to the comparator 3 at the timing when the settling time ends.

[0070] Next, refer to Figure 6 The fourth variation of the comparator action signal generation circuit 5 is described in detail.

[0071] Reference Figure 6The comparator operation signal generation circuit 5d, as a fourth variation, includes: a generation circuit 502, which has a capacitor element 51, a charge / discharge switch 52a, an inverter circuit 54, and a buffer circuit 56 that outputs a comparison start signal when the potential of the capacitor element 51 is higher than a threshold potential; and an output switching switch 55a that selects which of the inverter circuit 54 and the buffer circuit 56 to output the comparison start signal to the comparator 3.

[0072] In the generation circuit 502, one end of the capacitor element 51 is connected to the ground terminal, and the other end is connected to the input terminal of the inverter circuit 54, the input terminal of the buffer circuit 56, and one end of the charge / discharge switch 52a. Furthermore, the charge / discharge switch 52a includes a charging switch 521a that connects the other end of the capacitor element 51 to the injection potential, and a discharging switch 522 that connects the other end of the capacitor element 51 to the ground terminal. Charge is injected into the capacitor element 51 by turning on the charging switch 521a and turning off the discharging switch 522, simultaneously with the operation indication signal for the capacitor DAC 2, output from the conversion data generator 40.

[0073] The charging switch 521a and the discharging switch 522 use capacitors C0 to C (n-1) Switches 220-22 are used when connecting to a reference potential (High) or a reference potential (Low). (n-1) A switch with equal on-resistance.

[0074] When the potential of capacitor element 51 is higher than the threshold potential of buffer circuit 56, a comparison start signal is output from buffer circuit 56. The comparison start signal output from buffer circuit 56 is input to charge / discharge switch 52a as a discharge indication signal, and to conversion data generator 40 as a completion signal.

[0075] When a discharge indication signal is input from the buffer circuit 56, the charging switch 521a is opened and the discharge switch 522 is opened to begin discharging from the capacitor element 51. When the potential of the capacitor element 51 falls below the threshold potential of the inverter circuit 54 due to discharge, a comparison start signal is output from the inverter circuit 54. The comparison start signal output from the inverter circuit 54 is input to the charge / discharge switch 52a as a charging indication signal and to the conversion data generator 40 as a completion signal.

[0076] Next, at the time point after repeated quantization, a comparison start signal is output. The conversion data generator 40 counts the input completion signal, thereby outputting an output switching indication signal to the output switching switch 55a at the desired timing, causing the output switching switch 55a to connect to the switch 551. a 551 bThe comparison start signal is output to comparator 3 when any one of them is turned on.

[0077] Thus, the settling time of the capacitor DAC2, which varies according to each bit to be switched, can be predicted by a single generation circuit 502, and a comparison start signal is output to the comparator 3 at the timing when the settling time ends.

[0078] As explained above, this embodiment is an A / D conversion circuit 10, which is a successive approximation type. It converts the analog input into a digital value by repeatedly performing the conversion data generation operation of the conversion data generator 40, the potential generation operation of the capacitor DAC 2, and the comparison operation of the comparator 3 in amounts corresponding to the resolution bits. The A / D conversion circuit 10 includes a comparator operation signal generation circuit 5, which generates the comparator operation signal based on the characteristics of the capacitors C0 to C1 used in the capacitor DAC 2. (n-1) The equal charging and discharging time of capacitor element 51 is used to predict the moment when the potential generated by capacitor DAC 2 stabilizes, and a comparator operation signal is generated to start the comparison operation of comparator 3.

[0079] According to this structure, by using a capacitor element 51 with the same characteristics as the capacitor used in capacitor DAC 2, it is possible to predict the actual required [capacitor DAC settling time], thereby eliminating the allocation of excessive [capacitor DAC settling time] and achieving a high-speed effect.

[0080] Furthermore, in this embodiment, the comparator operation signal generation circuits 5 and 5a predict the stabilization time of the capacitor DAC 2, which varies according to each bit to be switched, based on the discharge time of the capacitor elements 51 that have been charged at multiple injection potentials (n-1) to injection potential (0).

[0081] Furthermore, in this embodiment, the comparator operation signal generation circuits 5b and 5c predict the settling time of the capacitor DAC 2, which varies according to each bit to be switched, by repeatedly measuring the discharge time of the capacitor element 51 that has been charged at the injection potential.

[0082] Based on this structure, it is possible to predict the [capacitor DAC settling time] without preparing multiple injection potentials.

[0083] Furthermore, in this embodiment, the capacitor element 51 is discharged via a discharge switch 522, which has a connection with capacitors C0 to C1. (n-1) Switches 220-22 are used when connecting to a reference potential (High) or a reference potential (Low). (n-1) The on-resistance is equal to the on-resistance.

[0084] Based on this structure, the settling time can be predicted more accurately.

[0085] Furthermore, in this embodiment, the comparator operation signal generation circuit 5d predicts the settling time of the capacitor DAC 2, which varies according to each bit to be switched, by repeatedly charging the capacitor element 51 at the injection potential and discharging the capacitor element 51 at the injection potential.

[0086] Based on this structure, the [capacitor DAC settling time] can be predicted by using only one capacitor element 51.

[0087] Furthermore, in this embodiment, the capacitor element 51 is charged and discharged via a charging switch 521a and a discharging switch 522, respectively. The charging switch 521a and the discharging switch 522 are connected to the capacitors C0 to C0. (n-1) Switches 220-22 are used when connecting to a reference potential (High) or a reference potential (Low). (n-1) The on-resistance is equal to the on-resistance.

[0088] Based on this structure, the settling time can be predicted more accurately.

[0089] Furthermore, the present invention is not limited to the above-described embodiments, and it is understood that appropriate modifications can be made to each embodiment within the scope of the technical concept of the present invention. Additionally, the number, position, shape, etc., of the above-described structural components are not limited to the above-described embodiments, and can be adapted to suit the implementation of the present invention. Furthermore, in the accompanying drawings, the same structural elements are labeled with the same reference numerals.

[0090] Label Explanation

[0091] 1, 10: Analog / digital conversion circuit (A / D conversion circuit);

[0092] 2: Capacitor DAC;

[0093] 3: Comparator;

[0094] 4, 40: Transformation data generator;

[0095] 5, 5a, 5b, 5c, 5d: Comparator action signal generation circuit;

[0096] 21: Compare wiring;

[0097] 22: Switch;

[0098] 50: Generation circuit;

[0099] 51: Capacitor element;

[0100] 52, 52a: Charge / discharge switch;

[0101] 53: Potential switching switch;

[0102] 54: Inverter circuit;

[0103] 55, 55a: Output switching switches;

[0104] 56: Buffer circuit;

[0105] 521, 521a: Charging switch;

[0106] 522: Discharge switch;

[0107] 531, 551: Connecting switches.

Claims

1. An analog-to-digital conversion circuit, which is a successive approximation type, converts an analog input into a digital value by repeatedly performing conversion data generation operations of a conversion data generator, potential generation operations of a capacitor DAC, and comparison operations of a comparator with quantities corresponding to the resolution bits. The characteristic of this analog-to-digital conversion circuit is that... The analog-to-digital converter circuit includes a comparator action signal generation circuit. This circuit predicts the moment when the potential generated by the capacitor DAC stabilizes based on the charging and discharging time of a capacitor element with characteristics identical to the capacitor used in the capacitor DAC, and generates a comparator action signal that causes the comparator to begin its comparison operation. The comparator operation signal generation circuit includes the capacitor element, a charge / discharge switch for the capacitor element, a potential switching switch for switching the charging potential of the capacitor element, and an inverter circuit that outputs a comparison start signal when the potential of the capacitor element is lower than a threshold potential. One end of the capacitor element is connected to the ground terminal, and the other end is connected to the input terminal of the inverter circuit and one end of the charge / discharge switch. The charge / discharge switch includes a charging switch that connects the other end of the capacitor element to one end of the potential switching switch, and a discharging switch that connects the other end of the capacitor element to a ground terminal. The potential switching switch has multiple connection switches that connect the other end of the capacitor element to multiple injection potentials corresponding to a resolution bit.

2. The analog-to-digital conversion circuit according to claim 1, characterized in that, The comparator action signal generation circuit predicts the settling time of the capacitor DAC, which varies for each bit to be switched, based on the discharge time of each capacitor element that has been charged at multiple injection potentials.

3. The analog-to-digital conversion circuit according to claim 1, characterized in that, The comparator action signal generation circuit predicts the settling time of the capacitor DAC, which varies for each bit to be switched, by repeatedly testing the discharge time of the capacitor element charged at the injection potential.

4. The analog-to-digital conversion circuit according to claim 2 or 3, characterized in that, The capacitor element is discharged via a discharge switch. The discharge switch has an on-resistance equal to that of the switch that connects the capacitor used in the capacitor DAC to a reference potential (High) or a reference potential (Low).

5. The analog-to-digital conversion circuit according to claim 1, characterized in that, The comparator action signal generation circuit predicts the settling time of the capacitor DAC, which varies for each bit to be switched, by repeatedly charging the capacitor element at the injection potential and discharging the capacitor element at the injection potential.

6. The analog-to-digital conversion circuit according to claim 5, characterized in that, The capacitor element is charged and discharged via a charging switch and a discharging switch, respectively. The charging switch and the discharging switch have on-resistance equal to the on-resistance of the switch that connects the capacitor used in the capacitor DAC to a reference potential (High) or a reference potential (Low).

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