A message caching method, integrated circuit system and storage medium

Abstract

The present application relates to the field of data communication, and in particular to a message caching method, an integrated circuit system and a storage medium. The method can reasonably allocate the on-chip cache and improve the utilization efficiency of the on-chip cache. The message caching method can be applied to a network device, which includes a first storage medium and a second storage medium, the first storage medium is in a processor chip of the network device, and the second storage medium is outside the processor. The method may include: receiving a first message, identifying a queue number in the first message, the queue number is used to indicate a queue that stores a cache address of the first message. Then, according to the queue number, query the queue delay of the queue. And, query the occupancy of the first storage medium, and determine the first delay threshold according to the occupancy. If the queue delay is less than the first delay threshold, the first message is cached in the first storage medium; if the queue delay is greater than the first delay threshold, the first message is cached in the second storage medium.

Description

Technical Field

[0001] The present application relates to the field of data communications, and in particular to a message caching method, an integrated circuit system, and a storage medium. Background Art

[0002] Devices in a communication network can receive messages transmitted by other devices and store the received messages in an on-chip cache or an off-chip cache. Among them, the on-chip cache is the cache inside the main chip of the device. The off-chip cache is the cache outside the main chip. The on-chip cache has the characteristics of large bandwidth and small capacity, while the off-chip cache has the characteristics of small bandwidth and large capacity.

[0003] In a current message cache solution, the on-chip cache can be divided into multiple storage spaces, which correspond to messages of multiple priorities. After a device receives a message, if the storage space corresponding to the priority of the message in the on-chip cache is sufficient to store the message, the message is cached in the on-chip cache; if the storage space is insufficient to store the message, the message is cached in the off-chip cache.

[0004] Among them, the messages can be divided into messages of congested traffic and messages of non-congested traffic. Messages of non-congested traffic refer to messages that occupy the cache for a short time, that is, the messages will be read out soon after being cached; messages of congested traffic refer to messages that occupy the cache for a long time, that is, it takes a long time for the messages to be read out after being cached. In the above scheme, messages of congested traffic and messages of non-congested traffic are not distinguished. In this way, there may be a problem of caching a large number of messages of congested traffic in the on-chip cache and caching a large number of messages of non-congested traffic in the off-chip cache. In this way, since the bandwidth of the off-chip cache is small, the messages of non-congested traffic may be discarded due to insufficient bandwidth of the off-chip cache.

[0005] In order to solve the above problems, another message cache solution is proposed. In this solution, the device can use the queue depth of each queue used to cache messages as a judgment indicator of the queue congestion state, and allocate storage space for each queue in the on-chip cache according to the queue depth of each queue. Among them, the congestion of the message in the queue can be reflected as the congestion state of the queue. The larger the queue depth of a queue, the more serious the congestion state of the queue, and the smaller the storage space allocated for the queue. However, the queue depth of a queue is not the only indicator that reflects the congestion state of the queue, and the queue depth of a queue cannot accurately reflect the congestion state of the queue. Therefore, using the above solution, there may still be a situation where the message of non-congested traffic is cached in the off-chip cache as the message of congested traffic, so that the message of non-congested traffic is discarded due to insufficient bandwidth of the off-chip cache.

[0006] In summary, the queue depth cannot accurately distinguish the packets of congested traffic and the packets of non-congested traffic in the queue, and thus the on-chip cache cannot be reasonably allocated, resulting in low utilization efficiency of the on-chip cache. Summary of the invention

[0007] The present application provides a message caching method, an integrated circuit system and a storage medium, which can reasonably allocate on-chip cache and improve the utilization efficiency of the on-chip cache.

[0008] In order to achieve the above technical objectives, this application adopts the following technical solutions:

[0009] In a first aspect, the present application provides a message caching method, which can be applied to a network device, the network device comprising a first storage medium and a second storage medium, the first storage medium being in a processor chip of the network device, and the second storage medium being outside the processor chip. The method may include:

[0010] A first message is received, and a queue number in the first message is identified, where the queue number is used to indicate a queue storing a cache address of the first message. Then, according to the queue number, a queue delay of the queue is queried. Also, the occupancy of the first storage medium is queried, and a first delay threshold is determined according to the occupancy. If the queue delay is less than the first delay threshold, the first message is cached in the first storage medium; if the queue delay is greater than the first delay threshold, the first message is cached in the second storage medium.

[0011] It is understandable that the queue stores the cache addresses of multiple messages. The time that the messages in the queue occupy the cache can represent the current congestion state of the queue. The queue delay is the time that the messages in the queue occupy the cache. Therefore, the queue delay can represent the congestion state of the queue. In addition, the queue depth is the number of read and write messages waiting to be sent in a queue, that is, the sequence of instructions sent by the queue to the storage device each time. The queue depth cannot reflect the length of time that the messages in the queue occupy the cache. Therefore, the congestion state of the queue can be accurately judged based on the congestion state of the queue.

[0012] The first storage medium includes a cache in a main chip of the storage device, and the second storage medium is not a cache in the main chip. For example, the first storage medium may be an on-chip cache, and the second storage medium may be an off-chip cache. The on-chip cache is characterized by large bandwidth and small capacity; the off-chip cache is characterized by large capacity and small bandwidth. If the queue delay is less than the first delay threshold, indicating that the queue is a queue of non-congested traffic, the first message can be cached in the on-chip cache; if the queue delay is greater than the first delay threshold, indicating that the queue is a queue of congested traffic, the first message can be cached in the off-chip cache.

[0013] In summary, since queue delay can reflect the congestion state of the queue, in this application, queue delay is used as an indicator for judging the congestion state of the queue, and the congestion state of the queue can be accurately judged. It can ensure that the messages of non-congested traffic are cached in the on-chip cache, reduce the risk of the on-chip cache being filled with messages of congested traffic, reasonably utilize the on-chip cache, and improve the utilization rate of the on-chip cache.

[0014] In one possible implementation, if the queue delay is less than a first delay threshold, the first message is cached in a first storage medium; and if the queue delay is greater than the first delay threshold, before the first message is cached in a second storage medium, the method further includes: determining that the second message is cached in the first storage medium; wherein the message header of the second message includes a queue number of the queue, and the cache address of the second message is the previous enqueued element of the cache address of the first message in the queue.

[0015] In another possible implementation, the message caching method further includes: determining that the second message is cached in a second storage medium; if the queue delay is less than a second delay threshold, caching the first message in a first storage medium; if the queue delay is greater than the second delay threshold, caching the first message in a second storage medium; wherein the second delay threshold is less than the first delay threshold, and the difference between the second delay threshold and the first delay threshold is a preset value.

[0016] It can be understood that the third message is the last message to be queued before the first message, if the third message is cached in the second storage medium. For the on-chip cache, the third message is a message of congested traffic, and the queue is a queue of congested traffic. After the network device receives the first message, the queue delay is less than the second preset threshold, and the first message is cached in the on-chip cache. The second preset threshold is less than the first preset threshold, which improves the judgment index of whether the first message is a message of congested traffic. It can ensure that the messages of non-congested traffic are cached in the on-chip cache, further reducing the risk of the on-chip cache being filled with messages of congested traffic, and improving the utilization rate of the on-chip cache.

[0017] In another possible implementation, the queue delay of the queue is the message delay of the third message; wherein the third message is the last message dequeued from the queue, and the message delay is determined based on the time difference between the dequeuing time and the enqueuing time of the cache address of the third message in the queue.

[0018] It can be understood that the queue delay of the queue is determined based on the time difference between the entry time and the exit time of the third message in the queue, that is, the queue delay is the length of time that the third message occupies the storage medium. The third message is the most recent message that has been exited from the queue, and the length of time that the third message occupies the cache can reflect the congestion state of the third message. Among them, the queue may include multiple messages, and the length of time that each message occupies the cache can reflect the congestion state of the queue. Only after the message of the queue is exited, the length of time that the message occupies the cache, that is, the congestion state of the message, can be determined. Therefore, the congestion state of the most recent message that has been exited from the queue can characterize the current congestion state of the queue.

[0019] In another possible implementation manner, the network device includes a queue delay table of the queue, the queue delay table includes an entry time and a dequeue time of a last dequeued message in the queue; the message caching method further includes:

[0020] Before the first storage medium or the second storage medium caches the third message, add a first timestamp to the third message, wherein the first timestamp is the time when the third message is queued; add the cache address of the third message to the queue; after receiving a read request for the third message, read the third message from the first storage medium or the second storage medium according to the cache address, identify the first timestamp in the third message, and determine the second timestamp, record the first timestamp and the second timestamp in the queue delay table, wherein the second timestamp is the time when the third message is dequeued; wherein the second timestamp is the global time of the network device.

[0021] In another possible implementation, the message delay is the time difference between the dequeue time and the enqueue time of the cache address of the third message in the queue, or the message delay is a delay level determined based on the time difference between the dequeue time and the enqueue time of the cache address of the third message in the queue; wherein, the network device stores multiple delay levels and the time difference corresponding to each delay level.

[0022] In another possible implementation, the network device includes a first storage medium occupancy status table, which includes the storage space occupied by the first storage medium and the delay threshold corresponding to the occupied storage space; therefore, querying the occupancy of the first storage medium and determining the first delay threshold based on the occupancy may include: querying the occupancy of the first storage medium to determine the occupied storage space corresponding to the occupancy; and determining that the delay threshold corresponding to the occupied storage space is the first delay threshold.

[0023] In another possible implementation, before the second storage medium caches the first message, the method also includes: obtaining back pressure information of the second storage medium; wherein, when the back pressure information is a first value, it indicates that the bandwidth of the second storage medium is sufficient to cache the first message; the bandwidth of the second storage medium is used to characterize the amount of data that the second storage medium can store per unit time; and caching the first message in the second storage medium includes: if the back pressure information is the first value, caching the first message in the second storage medium.

[0024] In another possible implementation, when the back pressure information is a second value, it indicates that the bandwidth of the second storage medium is insufficient to cache the first message; the method further includes: if the back pressure information is the second value, discarding the first message.

[0025] The back pressure information is used to characterize the cache pressure of the off-chip cache, and the bandwidth of the off-chip cache is small. When the back pressure information is the first value, it means that the bandwidth of the off-chip cache can still meet the requirements of the system line speed bandwidth, and the bandwidth of the off-chip cache is sufficient to cache the first message; when the back pressure information is the second value, it means that the bandwidth of the off-chip cache can no longer meet the requirements of the system line speed bandwidth, and the bandwidth of the off-chip cache is insufficient to cache the first message, and the first message will be discarded.

[0026] In a second aspect, the present application also provides an integrated circuit system, which may include: a message write control module PWC, a queue management module QM and a message cache control module PMC; the PMC includes a first storage medium, and the PMC is connected to a second storage medium.

[0027] The PWC is used to receive a first message and identify a queue number in the first message, where the queue number is used to indicate a queue storing a cache address of the first message.

[0028] The QM is used to query the queue delay of the queue according to the queue number; and query the occupancy of the first storage medium, and determine the first delay threshold according to the occupancy. If the QM determines that the queue delay is less than the first delay threshold, it sends a first indication message to the PWC to instruct the PWC to request the PMC to cache the first message in the first storage medium. If the QM determines that the queue delay is greater than the first delay threshold, it sends a second indication message to the PWC to instruct the PWC to request the PMC to cache the first message in the second storage medium.

[0029] It can be understood that the queue management module QM compares the queue delay and the first delay threshold, and determines the cache address of the first message based on the comparison result. For example, the first storage medium may be an on-chip cache, and the second storage medium may be an off-chip cache. Since the queue delay can reflect the congestion state of the queue. Therefore, in the present application, the queue delay is used as an indicator for judging the congestion state of the queue, and the congestion state of the queue can be accurately judged. If the queue delay is less than the first delay threshold, indicating that the queue is a queue of non-congested traffic, the first message can be cached in the on-chip cache; if the queue delay is greater than the first delay threshold, indicating that the queue is a queue of congested traffic, the first message can be cached in the off-chip cache. It can ensure that the messages of non-congested traffic are cached in the on-chip cache, reduce the risk of the on-chip cache being filled with messages of congested traffic, make rational use of the on-chip cache, and improve the utilization rate of the on-chip cache.

[0030] In a possible implementation, the QM is further used to determine, before sending the first indication information or the second indication information to the PWC, that the second message is cached in the first storage medium, wherein the message header of the second message includes the queue number of the queue, and the cache address of the second message is the last queued element of the cache address of the first message in the queue.

[0031] In another possible implementation, the QM is further configured to, after determining that the second message is cached in the second storage medium, if the QM determines that the queue delay is less than the second delay threshold, the QM sends a first indication message to the PWC to instruct the PWC to request the PMC to cache the first message in the first storage medium. If the QM determines that the queue delay is greater than the second delay threshold, the QM sends a second indication message to the PWC to instruct the PWC to request the PMC to cache the first message in the second storage medium. The second delay threshold is less than the first delay threshold, and the difference between the second delay threshold and the first delay threshold is a preset value.

[0032] In another possible implementation, the queue delay of the queue is the message delay of the third message, wherein the third message is the last message dequeued from the queue, and the message delay is determined according to the time difference between the dequeuing time and the enqueuing time of the cache address of the third message in the queue.

[0033] In another possible implementation, the integrated circuit system further includes a message read control module PRC, in which a delay table of a queue is stored, wherein the delay table of the queue stores an entry time and an exit time of a message corresponding to the queue; and the queue is stored in QM.

[0034] The PWC is further configured to, before requesting the PMC to cache the first message in the first storage medium or the second storage medium, add a first timestamp to the third message; wherein the first timestamp is the time when the third message is queued.

[0035] The QM is further configured to add the cache address of the third message to the queue, and if the QM receives a read request for the third message, send the read request for the third message and the cache address of the third message to the PRC.

[0036] The PRC is used to, after receiving a read request for the third message from the QM, read the third message from the first storage medium or the second storage medium according to the cache address of the third message, determine the first timestamp in the third message, and determine the second timestamp; record the first timestamp and the second timestamp in the queue delay table; wherein the second timestamp is the global time of the network device; and the second timestamp is the dequeue time of the cache address of the first message in the queue.

[0037] In another possible implementation, the message delay is the time difference between the dequeue time and the enqueue time of the cache address of the third message in the queue; or, the message delay is a delay level determined based on the time difference between the dequeue time and the enqueue time of the cache address of the third message in the queue; wherein, the network device stores multiple delay levels and the time difference corresponding to each delay level.

[0038] In another possible implementation, a first storage medium occupancy status table is stored in the integrated circuit system, wherein the first storage medium occupancy status table includes the storage space occupied by the first storage medium and the delay threshold corresponding to the occupied storage space; QM is used to query the occupancy of the first storage medium, and when determining the first delay threshold based on the occupancy, it is specifically used to query the occupancy of the first storage medium and determine the occupied storage space corresponding to the occupancy; and determine that the delay threshold corresponding to the occupied storage space is the first delay threshold.

[0039] In another possible implementation, before the QM sends the second indication information to the PWC, the PMC is further used to obtain back pressure information of the second storage medium and send the back pressure information to the QM. When the back pressure information is a first value, it indicates that the bandwidth of the second storage medium is sufficient to cache the first message; the bandwidth of the second storage medium is used to characterize the amount of data that the second storage medium can store per unit time.

[0040] The QM is further configured to receive back pressure information sent by the PMC. If the QM determines that the back pressure information is a first value, the QM sends second indication information to the PWC.

[0041] In another possible implementation, when the back pressure information is the second value, it indicates that the bandwidth of the second storage medium is insufficient to cache the first message. The QM is also used to send third indication information to the PMC if the QM determines that the back pressure information is the second value, and the third indication information is used to instruct the PMC to discard the first message. The PMC is also used to receive the third indication information from the QM and discard the first message according to the third indication information.

[0042] In a third aspect, the present application further provides an integrated circuit system, the integrated circuit system comprising a processor, a first storage medium and a second storage medium, the processor being configured to:

[0043] A first message is received, and a queue number in the first message is identified, where the queue number is used to indicate a queue storing a cache address of the first message. Then, according to the queue number, a queue delay of the queue is queried. Also, the occupancy of the first storage medium is queried, and a first delay threshold is determined according to the occupancy. If the queue delay is less than the first delay threshold, the first message is cached in the first storage medium; if the queue delay is greater than the first delay threshold, the first message is cached in the second storage medium.

[0044] In one possible implementation, the processor is also used to: if the queue delay is less than the first delay threshold, cache the first message in the first storage medium; and if the queue delay is greater than the first delay threshold, before caching the first message in the second storage medium, the method also includes: determining that the second message is cached in the first storage medium; wherein the message header of the second message includes the queue number of the queue, and the cache address of the second message is the cache address of the first message in the queue. The previous enqueued element.

[0045] In another possible implementation, the processor is also used to: determine whether the second message is cached in the second storage medium; if the queue delay is less than the second delay threshold, cache the first message in the first storage medium; if the queue delay is greater than the second delay threshold, cache the first message in the second storage medium; wherein the second delay threshold is less than the first delay threshold, and the difference between the second delay threshold and the first delay threshold is a preset value.

[0046] In another possible implementation, the queue delay of the queue is the message delay of the third message; wherein the third message is the last message dequeued from the queue, and the message delay is determined based on the time difference between the dequeuing time and the enqueuing time of the cache address of the third message in the queue.

[0047] In another possible implementation manner, the network device includes a queue delay table of the queue, the queue delay table including an entry time and a dequeue time of a last dequeued message in the queue; and the processor is further configured to:

[0048] Before the first storage medium or the second storage medium caches the third message, add a first timestamp to the third message, wherein the first timestamp is the time when the third message is queued; add the cache address of the third message to the queue; after receiving a read request for the third message, read the third message from the first storage medium or the second storage medium according to the cache address, identify the first timestamp in the third message, and determine the second timestamp, record the first timestamp and the second timestamp in the queue delay table, wherein the second timestamp is the time when the third message is dequeued; wherein the second timestamp is the global time of the network device.

[0049] In another possible implementation, the message delay is the time difference between the dequeue time and the enqueue time of the cache address of the third message in the queue, or the message delay is a delay level determined based on the time difference between the dequeue time and the enqueue time of the cache address of the third message in the queue; wherein, the network device stores multiple delay levels and the time difference corresponding to each delay level.

[0050] In another possible implementation, the network device includes a first storage medium occupancy status table, which includes the storage space occupied by the first storage medium and the delay threshold corresponding to the occupied storage space; therefore, the processor is also used to: query the occupancy amount of the first storage medium to determine the occupied storage space corresponding to the occupancy amount; determine that the delay threshold corresponding to the occupied storage space is the first delay threshold.

[0051] In another possible implementation, the processor is also used to: obtain back pressure information of the second storage medium; wherein, when the back pressure information is a first value, it indicates that the bandwidth of the second storage medium is sufficient to cache the first message; the bandwidth of the second storage medium is used to characterize the amount of data that the second storage medium can store per unit time; and cache the first message in the second storage medium, including: if the back pressure information is a first value, caching the first message in the second storage medium.

[0052] In another possible implementation, when the back pressure information is a second value, it indicates that the bandwidth of the second storage medium is insufficient to cache the first message; the processor is further configured to: discard the first message if the back pressure information is the second value.

[0053] The back pressure information is used to characterize the cache pressure of the off-chip cache, and the bandwidth of the off-chip cache is small. When the back pressure information is the first value, it means that the bandwidth of the off-chip cache can still meet the requirements of the system line speed bandwidth, and the bandwidth of the off-chip cache is sufficient to cache the first message; when the back pressure information is the second value, it means that the bandwidth of the off-chip cache can no longer meet the requirements of the system line speed bandwidth, and the bandwidth of the off-chip cache is insufficient to cache the first message, and the first message will be discarded.

[0054] In a fourth aspect, the present application also provides a computer-readable storage medium, comprising computer instructions, which, when executed on a network device, enable the network device to execute a method as in the first aspect and any possible implementation manner thereof.

[0055] In a fifth aspect, the present application also provides a computer program product, which, when executed on a computer, enables the computer to execute the method in the above-mentioned first aspect and any possible implementation manner thereof.

[0056] It can be understood that the integrated circuit system of the second aspect provided above, the integrated circuit system provided by the third aspect, the computer-readable storage medium provided by the fourth aspect, or the computer program product provided by the fifth aspect are all used to execute the method in the first aspect and any possible implementation manner thereof. Therefore, the effective effects that can be achieved can refer to the beneficial effects in the corresponding methods and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 A schematic diagram of the structure of a network device provided in an embodiment of the present application;

[0058] Figure 2 A flowchart of a message caching method provided in an embodiment of the present application;

[0059] Figure 3 A schematic diagram of the structure of an integrated circuit system provided in an embodiment of the present application;

[0060] Figure 4 A flowchart of another message caching method provided in an embodiment of the present application;

[0061] Figure 5 A schematic diagram of the structure of another integrated circuit system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0062] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this embodiment, unless otherwise specified, "plurality" means two or more.

[0063] The following is an explanation of the communication terms that may appear in this application:

[0064] External Buffer (EB): refers to the cache configured outside the main chip. The on-chip cache can be composed of DRAM (Dynamic Random Access Memory) as the storage medium. The more common ones include Double Data Rate SDRAM (DDR SDRAM), Graphics Double Data Rate version (GDDR) or High Bandwidth Memory (HBM).

[0065] On-chip Buffer (OCB): refers to the cache configured outside the main chip. Generally speaking, on-chip cache is also called cache. On-chip cache can exist in the form of static random-access memory (SRAM).

[0066] Bandwidth Convergent System (BCS): If the off-chip cache bandwidth of a system is less than the system line speed bandwidth, then the system is called a bandwidth convergent system.

[0067] Line speed: It is the maximum amount of data that can be handled between the switch interface processor or interface card and the data bus in the network device. It indicates the maximum amount of data that the network device can exchange and forward under ideal conditions.

[0068] Line speed bandwidth: Indicates the current amount of data throughput between the switch interface processor or interface card and the data bus in the network device, and indicates the amount of data exchanged and forwarded by the network device under the current conditions.

[0069] Convergence Ratio (CR): The ratio of off-chip bandwidth to system line-rate bandwidth is called the convergence ratio. For a bandwidth-convergent system, the convergence ratio is a value less than 1. For example, a convergence ratio of 0.9 means that the off-chip cache can provide 90% of the system line-rate bandwidth.

[0070] Packet Descriptor (PD): It is divided into local PD (LPD) and external PD (EPD). LPD points to a continuous storage space in an on-chip cache, and EPD points to a continuous storage space in an off-chip cache. The storage space sizes of LPD and EPD can be different. Due to the packet processing of packets, each LPD or EDP may contain multiple independent packets. Queue depth: The number of packets in a queue in a network device waiting to be sent for input / output (I / O) read and write operations.

[0071] Generally speaking, after receiving a message, the storage device may cache the received message in an on-chip cache or an off-chip cache. The storage device may determine the cache address of the message (such as an on-chip cache or an off-chip cache) according to the congestion status of the message. If the message is a message of congested traffic, the storage device may store the message in an off-chip cache; if the message is a message of non-congested traffic, the storage device may store the message in an on-chip cache.

[0072] It is understandable that the length of time a message occupies the cache can characterize the degree of congestion of the message. If the message occupies the cache for a long time, it is determined that the message is a message of congested traffic. After a message is dequeued, that is, the message leaves the cache, the length of time the message occupies the cache can be determined. If all the messages that have been dequeued in a queue are messages of congested traffic, it can be determined that the queue is a queue of congested traffic. When the storage device determines that the first message has been received, the congestion state of the first message can be determined according to the congestion state of the queue where the first message is located. If the queue where the first message is located is a queue of congested traffic, then the first message is a message of congested traffic; if the queue where the first message is located is a queue of non-congested traffic, then the first message is a message of non-congested traffic.

[0073] In some implementations, the queue depth may be used as an indicator for determining the queue congestion state. For example, if the queue depth is greater than a preset threshold, the queue is determined to be a queue of congested traffic.

[0074] Exemplarily, different storage thresholds are set in the on-chip cache according to different queue depths. If the preset threshold of the first queue depth is the first preset threshold, and the queue depths of the first queue and the second queue are both the first queue depth, then the total cache space of the messages in the first queue and the messages in the second queue in the on-chip cache is the cache space corresponding to the first preset threshold. For example, after the storage device receives the messages in the first queue, if the occupied amount of the queue depth in the on-chip cache is less than the storage threshold of the queue depth, the storage device can cache the messages in the first queue in the on-chip cache. If the occupied amount of the queue depth in the on-chip cache exceeds the storage threshold of the queue depth, the storage device caches the messages in the first queue in the off-chip cache.

[0075] It is understandable that the queue depth indicates the number of concurrent input / output read / write operations sent by the queue to the storage device each time, that is, the instruction sequence sent by the queue to the storage device each time. The larger the queue depth of a queue, the more instruction sequences the queue sends to the storage device each time, and the more likely the queue is to become a queue with congested traffic.

[0076] Among them, the queue input bandwidth will also affect the queue congestion state. If the queue congestion state is judged only based on the queue depth, the congestion states of two queues with the same queue depth may be different. For example, there are two queues (taking the first queue and the second queue as examples) with the same queue depth. The amount of occupancy of the on-chip cache by the packets in the two queues does not exceed the storage threshold corresponding to the queue depth. The packets in the first queue and the second queue can both be stored in the on-chip cache. If the output bandwidth of the two queues is different, so that the length of time that the packets in the first queue and the packets in the second queue occupy the cache is different, then the queue delay of the first queue and the queue delay of the second queue are also different, that is, the congestion state of the first queue and the congestion state of the second queue are also different. Therefore, when the queue depth is used as an indicator to judge the queue congestion state, the queue depth cannot accurately judge the congestion state of the queue.

[0077] It should be noted that queue delay = queue depth / queue output bandwidth. In the embodiment of the present application, the queue delay is used as a method to judge the congestion state of the queue. The queue delay indicates the length of time that the messages in the queue occupy the cache. For example, the messages in a queue with a short queue delay occupy the cache for a short time, and the messages in a queue with a long queue delay occupy the cache for a long time. The length of time that the messages in the queue occupy the cache represents the degree of congestion of the queue. Therefore, the congestion state of the queue can be accurately judged based on the queue delay.

[0078] A method for message caching provided in an embodiment of the present application can be applied to a network device. The network device receives a first message, and queries the queue delay of the queue according to the queue number in the message header of the first message. The queue delay of the queue is the message delay of the third message that has been most recently dequeued in the queue. Then, the storage device queries the occupancy of the on-chip cache, and determines a first delay threshold according to the occupancy of the on-chip cache. If the queue delay is less than the first delay threshold, the first message is cached in the on-chip cache; if the queue delay is greater than the first delay threshold, the first message is cached in the off-chip cache.

[0079] By implementing the method in the embodiment of the present application, it is possible to ensure that messages with small queue delays are cached in the on-chip cache, thereby reducing the risk of the on-chip cache being filled with messages of congested traffic, rationally utilizing the on-chip cache, and improving the utilization rate of the on-chip cache.

[0080] The method in the embodiment of the present application can be applied to a network device. Therefore, the execution subject of the message caching method provided in the embodiment of the present application can be a network device. Exemplarily, the network device can be a mobile phone, a tablet computer, a desktop, a laptop, a handheld computer, a notebook computer, an ultra-mobile personal computer (ultra-mobile personal computer, UMPC), a netbook, and a cellular phone, a personal digital assistant (personal digital assistant, PDA), augmented reality (augmented reality, AR)\virtual reality (virtual reality, VR) and other devices. The embodiment of the present application does not impose any special restrictions on the specific form of the network device. In the embodiment of the present application, the method for caching a message executed by a network device is taken as an example to illustrate the method for caching a message provided in the embodiment of the present application.

[0081] The following will describe in detail the implementation of the embodiment of the present application in conjunction with the accompanying drawings. Figure 1 As shown, the network device 100 may include: a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a sensor module 180, a button 190, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc.

[0082] The internal memory (or storage device) 121 includes an on-chip cache (or first storage medium) 122 and an off-chip cache (or second storage medium) 123. The on-chip cache 122 is a cache configured in the processor 110, and the off-chip cache 123 is a cache configured outside the processor 110.

[0083] It is to be understood that the structure illustrated in this embodiment does not constitute a specific limitation on the network device 100. In other embodiments, the network device 100 may include more or fewer components than shown in the figure, or combine some components, or split some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0084] The processor 110 may include one or more processing units, for example, the processor 110 may include an application processor (AP), a modem processor, a graphics processor (GPU), an image signal processor (ISP), a controller, an on-chip cache 122, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc. Different processing units may be independent devices or integrated into one or more processors.

[0085] The controller may be the nerve center and command center of the network device 100. The controller may generate an operation control signal according to the instruction operation code and the timing signal to complete the control of fetching and executing instructions.

[0086] An on-chip cache 122 may also be provided in the processor 110 for storing instructions and data. In some embodiments, the on-chip cache 122 in the processor 110 is a high-speed cache storage medium. The on-chip cache 122 may store instructions or data that the processor 110 has just used or cyclically used. If the processor 110 needs to use the instruction or data again, it may be directly called from the on-chip cache 122. Repeated access is avoided, the waiting time of the processor 110 is reduced, and the efficiency of the system is improved. In some embodiments, when the processor 110 caches a message received by a network device, the message is cached in the on-chip cache 122. If the message needs to be read, the message is directly read from the on-chip cache 122.

[0087] In some embodiments, the processor 110 may include one or more interfaces. The interface may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface, etc.

[0088] The off-chip cache 123 (or referred to as the second storage medium) can be used to store computer executable program codes, and the executable program codes include instructions. The processor 110 executes various functional applications and data processing of the network device 100 by running the instructions stored in the off-chip cache 123. For example, in an embodiment of the present application, the processor 110 can execute instructions stored in the off-chip cache 123, and the off-chip cache 123 may include a program storage area and a data storage area. In some embodiments, the off-chip cache 123 can be used to store messages received by the network device. For example, after the network device receives the message, the processor 110 stores the message in the off-chip cache through decision. If the message is read, the message is read from the off-chip cache.

[0089] The program storage area may store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc. The data storage area may store data created during the use of the network device 100 (such as audio data, a phone book, etc.), etc. In addition, the internal memory 121 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, a universal flash storage (UFS), etc.

[0090] The external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the network device 100. The external memory card communicates with the processor 110 through the external memory interface 120 to implement a data storage function, such as storing music, video and other files in the external memory card.

[0091] It is understandable that the interface connection relationship between the modules illustrated in this embodiment is only for illustrative purposes and does not constitute a structural limitation on the network device 100. In other embodiments, the network device 100 may also adopt different interface connection methods in the above embodiments, or a combination of multiple interface connection methods.

[0092] The charging management module 140 is used to receive charging input from a charger, where the charger can be a wireless charger or a wired charger.

[0093] The power management module 141 is used to connect the battery 142, the charging management module 140 and the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140, and supplies power to the processor 110, the internal memory 121, the display screen 194, the camera 193, and the wireless communication module 160. The power management module 141 can also be used to monitor parameters such as battery capacity, battery cycle number, and battery health status (leakage, impedance).

[0094] The wireless communication function of the network device 100 can be implemented through the antenna 1, the antenna 2, the mobile communication module 150, the wireless communication module 160, the modem processor and the baseband processor.

[0095] The network device 100 implements the display function through a GPU, a display screen 194, and an application processor. The GPU is a microprocessor for image processing, which connects the display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. The processor 110 may include one or more GPUs, which execute program instructions to generate or change display information.

[0096] The display screen 194 is used to display images, videos, etc. The display screen 194 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode or an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), Miniled, MicroLed, Micro-oLed, a quantum dot light-emitting diode (QLED), etc.

[0097] The network device 100 can realize the shooting function through ISP, camera 193, video codec, GPU, display screen 194 and application processor.

[0098] The methods in the following embodiments can all be implemented in the network device 100 having the above hardware structure. In the embodiment of the present application, the message caching method is applied to the network device 100 as an example to illustrate the message caching method.

[0099] Please refer to Figure 2 , is a flowchart of a message caching method provided in an embodiment of the present application, and the method can be applied to the above-mentioned network device. Figure 2 As shown, the message caching method includes steps 201 to 206. Among them, the memory (or storage device) in the network device includes an on-chip cache (or a first storage medium) and an off-chip cache (or a second storage medium). The on-chip cache is a cache configured in the main chip, and the off-chip cache is a cache configured outside the main chip.

[0100] Step 201: A network device receives a first message. The message header of the first message includes a queue number of a queue. The queue number is used to indicate a queue that stores a cache address of the first message.

[0101] The queue may also be referred to as a queue linked list. Each queue corresponds to a queue linked list, and the queue linked list (or queue) is used to store the cache address of the message in the queue.

[0102] It is understandable that each queue may include multiple messages. The message header of each message includes the queue number of the queue where the message is located, so that the network device can determine the queue where the message is located according to the queue number of the message.

[0103] Exemplarily, the network device may include a temporary cache, and when the network device has not determined the cache address of the first message, the network device may temporarily store the first message in the temporary cache. For example, after receiving the first message, the network device stores the first message in the temporary cache, and after the network device determines the cache address of the first message, the network device reads the first message from the temporary cache.

[0104] Step 202: The network device queries the queue delay of the queue according to the queue number of the queue.

[0105] Among them, a queue may include multiple messages, and the length of time each message occupies the cache can reflect the congestion state of the queue. Only after a message in the queue is dequeued can the length of time the message occupies the cache, that is, the congestion state of the message, be determined. Therefore, the congestion state of the most recently dequeued message in the queue can represent the current congestion state of the queue.

[0106] Exemplarily, the most recently dequeued message in the queue is the third message. The queue delay is the message delay of the third message in the queue. The message delay is determined according to the time difference between the dequeuing time and the enqueuing time of the cache address of the third message in the queue.

[0107] For example, a delay list for each queue may be preset in the network device, and the delay list for each queue is used to record the message delay of each message in the queue. When the network device receives a message of the queue, the queue delay of the queue may be determined by querying the message delay corresponding to the most recently dequeued message in the delay list of the queue.

[0108] It is understandable that when a queue obtains a dequeue opportunity, the cache addresses of the messages in the queue are taken out from the first list one by one. Among them, after the cache address of the message in the queue is read from the first list, the queue can delete the cache address of the message. In the queue, the message delay corresponding to each dequeued message may be different. The congestion state of the messages in the queue can characterize the congestion state of the queue, and the message delay corresponding to the most recent message that has been dequeued from the queue can reflect the current queue delay of the queue. The message delay corresponding to the most recent message that has been dequeued from the queue is used as the queue delay of the queue. For example, if the third message is the most recent message that has been dequeued from the queue, the message delay of the third message can accurately represent the congestion state of the queue.

[0109] Exemplarily, the queue is used to store the cache address of the message in the queue. Wherein, when the network device determines the cache address of the third message and caches the third message to the corresponding cache address, the entry time of the third message is recorded. If the third message is read, the cache address of the third message is taken out of the queue, and the exit time of the third message is recorded.

[0110] In the first case, the message delay of the third message is the time difference between the dequeue time and the entry time of the cache address of the third message in the queue. If the entry time of the cache address of the third message in the queue is T1 (e.g., 15:30:20:30), and the dequeue time of the cache address of the third message in the queue is T2 (e.g., 15:30:25:30), the message delay of the third message is T2-T1, that is, 5 seconds.

[0111] In the second case, the message delay of the third message is determined according to the time difference between the dequeue time and the entry time of the cache address of the third message in the queue. The network device may include a delay level query table, as shown in Table 1, and the delay level table includes multiple delay levels and the time difference corresponding to each delay level. If the time difference between the dequeue time and the entry time of the cache address of the third message in the queue is 5 seconds, the delay level of the third message is L1.

[0112] Table 1:

[0113]

[0114] It is understandable that the time lengths corresponding to each delay level in Table 1 above are different. This is just an example. In specific settings, they can also be set to equal time lengths. For example, if the time difference is 0-50 seconds, the corresponding delay level is L1; if the time difference is 51 seconds-100 seconds, the corresponding delay level is L2; ​​if the time difference is 101 seconds-150 seconds, the corresponding delay level is L3, etc.

[0115] Exemplarily, the network device may include a global timestamp module, which can generate a global timestamp, and the network device adds a timestamp to the cached message according to the global timestamp generated by the global timestamp module. For example, the method of determining the dequeue time and the entry time of the cache address of the third message in the queue can be: before caching the third message in the on-chip cache or the off-chip cache, the network device obtains the current first timestamp of the global timestamp module, and the network device adds the first timestamp (such as T1) to the message header of the third message. When the queue obtains a dequeue opportunity, after the network device receives a read request for the third message, the third message is read from the on-chip cache or the off-chip cache according to the cache address of the third message, and the network device obtains the current second timestamp (such as T2) of the global timestamp module. Among them, T1 is the entry time of the third message, and T2 is the dequeue time of the third message.

[0116] When reading the third message, the network device obtains the first timestamp in the message header of the third message, and records T1 in the delay table of the queue, and records T2 in the delay table of the queue.

[0117] It is understandable that after the third message is read out from the queue, the third message leaves the cache of the network device, and therefore, the second timestamp does not need to be added to the message header of the third message. When the second message is read from the queue, the network device can read the current time of the global timestamp module as the second timestamp, and the second timestamp is the time when the third message is dequeued.

[0118] Step 203: The network device queries the occupancy of the on-chip cache and determines a first delay threshold according to the occupancy.

[0119] The occupied amount of the on-chip cache is used to represent the size of the storage space occupied in the on-chip cache. The network device stores a corresponding relationship between the occupied amount of the on-chip cache and the first delay threshold.

[0120] Exemplarily, the network device is preset with an on-chip cache occupancy status table, as shown in Table 2, including the occupancy of the on-chip cache (or waterline), and the delay threshold corresponding to the occupancy. When the network device determines that the occupancy of the on-chip cache is 25%, it can determine that the first delay threshold is TH2.

[0121] Table 2:

[0122]

[0123] It is understandable that the latency thresholds correspond to different amounts of cache occupancy, and this is just an example. In actual settings, the same amount of cache occupancy can be set for each latency threshold. For example, if the cache occupancy is 0-16.6%, the corresponding latency threshold is TH1; if the cache occupancy is 16.7%-33.3%, the corresponding latency threshold is TH2, and so on.

[0124] Step 204: Determine whether the queue delay is less than a first delay threshold.

[0125] Specifically, if the queue delay is less than the first delay threshold, step 205 is executed; if the queue delay is greater than the first delay threshold, step 206 is executed.

[0126] Among them, the queue delay is less than the first delay threshold, and the first message is cached in the on-chip cache. That is to say, when the queue delay time is less than the first delay threshold, the network device can determine that the first message is a message of non-congested traffic, and cache the first message in the on-chip cache. In addition, it can be seen from the above Table 2 that when the occupancy of the on-chip cache is higher, the delay threshold is also higher, and the time corresponding to the delay threshold is also shorter. Therefore, it can be determined that when the occupancy of the on-chip cache is low, the network device allows messages with larger delays to be cached in the on-chip cache; when the occupancy of the on-chip cache is high, the network device allows messages with smaller delays to be cached in the on-chip cache.

[0127] It can be understood that the queue delay is the message delay of the third message. Therefore, the queue delay can be the time difference between the dequeue time and the enqueue time of the cache address of the third message in the queue, or the queue delay can be the delay level determined according to the time difference between the dequeue time and the enqueue time of the cache address of the third message in the queue. When comparing the queue delay with the first delay threshold, the data corresponding to the queue delay and the first delay threshold are the same type of data. For example, when the message delay of the third message is the time difference between the dequeue time and the enqueue time of the cache address of the third message in the queue, the delay threshold can be a time length. For another example, when the message delay of the third message is the delay level determined according to the time difference between the dequeue time and the enqueue time of the cache address of the third message in the queue, the delay threshold can be a delay level.

[0128] In the first case above, when the message delay of the third message is the time difference between the time when the cache address of the third message is dequeued and the time when it is entered in the queue, the delay threshold can be a time length (such as 400 seconds, 200 seconds or 120 seconds, etc.). As shown in Table 3, the delay threshold in the on-chip cache occupancy status table corresponds to a specific delay time. If the occupancy of the on-chip cache is 1-10%, it means that there is still a lot of cache space in the on-chip cache, allowing messages with larger delays to be cached in the on-chip cache, TH1 can be 400 seconds; or, if the occupancy of the on-chip cache is 66%-80%, it means that the occupancy of the cache space of the on-chip cache is relatively high. At this time, messages with very small delays can be cached in the on-chip cache, and TH5 can be 5 seconds.

[0129] Table 3:

[0130]

[0131] In addition, when the message delay of the third message is the time difference between the dequeue time and the enqueue time of the cache address of the third message in the queue, the delay threshold may be a delay level. If the queue delay is the time difference between the dequeue time and the enqueue time of the third message, the delay threshold may be a delay level, and the maximum value of the time difference corresponding to the delay level in the first delay threshold may be obtained by querying Table 1, and the maximum value of the time difference may be determined as the first delay threshold. For example, the first delay threshold is L5, and when comparing the queue delay with the first delay threshold, querying Table 1 determines that the time difference corresponding to the first delay threshold is 200 seconds, and the queue delay is compared with 200 seconds.

[0132] In the second case above, when the message delay of the third message is determined based on the time difference between the dequeue time and the enqueue time of the cache address of the third message in the queue, the delay level is determined, then the delay threshold can be a delay level. As shown in Table 4, the delay threshold in the on-chip cache occupancy status table is the delay level. It can be understood that the delay level here has the same meaning as the delay level in Table 1. If the occupancy of the on-chip cache is 1-10%, it means that there is still a lot of cache space in the on-chip cache, allowing messages with longer delays to be stored in the on-chip cache, and TH1 can be L7. In other words, when the delay level of the message received by the network device is L7, that is, the delay of the message is greater than 400 seconds, and the occupancy of the on-chip cache in the network device is less than or equal to 10%, the message can be cached in the on-chip cache.

[0133] Table 4:

[0134]

[0135] If the queue delay is less than the first delay level, the cache address of the first message is determined to be the on-chip cache. If the queue delay is L5, the first delay threshold is L6, and the queue delay L5 is less than the first delay threshold L6, the cache address of the first message is determined to be the on-chip cache.

[0136] Step 205: Cache the first message in the on-chip cache.

[0137] Exemplarily, when the network device determines to cache the first message into the on-chip cache, it performs splicing processing on the message to determine the cache address of the first message, and caches the first message into the on-chip cache corresponding to the cache address.

[0138] It should be noted that the cache area corresponding to a cache address can store at least one message, and splicing the messages is to determine the cache address of the message. For example, the cache size corresponding to a cache address is 10MB, the size of the first message is 5MB, and the cache corresponding to the cache address can cache the first message. The first message is cached to the cache address, and the cache address of the first message is saved in the queue. For another example, the cache size corresponding to a cache address is 10MB, and other messages are cached in the cache address, and the other messages occupy 2MB of the cache space in the cache space. If the size of the first message is 5MB, the first message can still be stored in the cache space corresponding to the cache address. The first message cache is spliced ​​with other messages and stored together in the cache space corresponding to the cache address.

[0139] It is worth mentioning that the process of caching the first message by the network device also includes determining the time when the first message enters the queue. For example, the cache address of the first message is added to the queue, and the network device stamps the first message with a first timestamp according to the time when the first message enters the queue. When the network device receives a read request for the first message, it reads the cache address of the first message from the queue, that is, deletes the cache address of the first message from the queue. When the network device reads the first message according to the cache address, it obtains the first timestamp in the first message, and the network device records the first timestamp in the delay table of the queue, and the network device records the second timestamp. Among them, the second timestamp is the time when the cache address of the queue is read from the queue, which is the global time of the network device, and the global time is the second timestamp recorded by the network device in the delay table of the queue.

[0140] Step 206: Cache the first message in an off-chip cache.

[0141] It is understandable that caching the first message in the off-chip cache also requires splicing the message to determine the cache address of the first message and cache the first message in the off-chip cache corresponding to the cache address.

[0142] Among them, the method of splicing the messages is the same as the above-mentioned splicing method, which will not be repeated here.

[0143] Exemplarily, if a temporary cache is set in the network device, after the network device obtains the first message, the first message is cached in the temporary cache. After the cache address of the first message is determined, the first message is read out from the temporary cache, and the first message is cached in the cache area corresponding to the cache address. If the network device does not have a temporary cache, after the network device obtains the first message, the cache address of the first message is determined, and the first message is cached in the cache area corresponding to the cache address.

[0144] It is worth mentioning that the off-chip cache is characterized by large capacity but limited bandwidth. If the write bandwidth of the off-chip cache is insufficient, the message cannot be written to the off-chip cache. When caching the first message to the off-chip cache, if the off-chip cache has back pressure information, and the back pressure information indicates that the write bandwidth of the off-chip cache is insufficient, the message cannot be written. Therefore, when it is determined that the cache address of the first message is the off-chip cache, the germination information of the off-chip cache can be obtained to determine whether to discard the first message.

[0145] Exemplarily, the network device obtains back pressure information of the off-chip cache. If the back pressure information is a first value, for example, the first value of the back pressure information is 0, indicating that the bandwidth of the off-chip cache is sufficient to cache the first message, the network device caches the first message in the off-chip cache. If the back pressure information is a second value, for example, the second value of the back pressure information is 1, indicating that the bandwidth of the off-chip cache is insufficient to cache the first message, the network device discards the first message. The bandwidth of the off-chip cache is used to characterize the amount of data that the off-chip cache can store per unit time.

[0146] It should be noted that when the network device receives each message, it needs to determine the cache address of the message. If the network device receives two consecutive messages in the queue, and the cache addresses of the previous message and the next message correspond to different cache areas, the cache address included in the queue will oscillate between the on-chip cache and the off-chip cache. For example, if the cache address of the previous message is the cache address of the off-chip cache, then the cache area of ​​the previous message is the off-chip cache; if the cache address of the next message is the cache address of the on-chip cache, then the cache area of ​​the next message is the on-chip cache.

[0147] Exemplarily, the network device may set a first delay threshold according to the cache area of ​​the message before the first message, so that the messages in the same queue can be cached in the same cache area. For example, after determining the queue delay, if the network device determines that the second message is cached in the on-chip cache, the above steps 204 to 206 are executed. If it is determined that the second message is cached in the off-chip cache, it is determined whether the queue delay is less than the second delay threshold, and if so, the first message is cached in the on-chip cache, otherwise, the first message is cached in the off-chip cache.

[0148] Among them, the third message is the previous message of the first message in the queue, that is, the cache address of the second message is the cache address of the first message in the queue. The previous entry element. Moreover, the second delay threshold is less than the first delay threshold, and the difference between the second delay threshold and the first delay threshold is a preset value. For example, if the first delay threshold is L6, and the difference between the second delay threshold and the first delay threshold is 1, then the second delay threshold can be L5. For another example, if the first delay threshold is 200 seconds, and the difference between the second delay threshold and the first delay threshold is 60 seconds, then the second delay threshold is 120 seconds.

[0149] Take the queue delay as L5, the first delay threshold as L6, and the second delay threshold as L5 as an example. If the third message is cached in the on-chip cache, it is determined that the queue delay L5 is less than the first delay threshold L6, and the first message is cached in the on-chip cache. If the second message is cached in the off-chip cache, the second delay threshold is L5, it is determined that the queue delay L5 is equal to the second delay threshold L5, and the first message is cached in the off-chip cache.

[0150] It is understandable that if the third message is cached in the off-chip cache, and if the cache address of the first message is also cached off-chip, then the cache address of the second message and the cache address of the first message included in the queue are both in the off-chip cache. In the same queue, the cache addresses of consecutive messages will not oscillate between the on-chip cache and the off-chip cache. When a message in the queue gets a chance to be dequeued, the network device can read out consecutive messages in the queue in the off-chip cache when reading out the message in the queue, and the message read address will not oscillate between the off-chip cache and the on-chip cache.

[0151] In the embodiment of the present application, the method of determining the cache address of the first message by the queue delay threshold and the first delay threshold can be called the local buffer management scheme (LBMS). Among them, the LBMS determines the first delay threshold according to the occupancy of the on-chip cache, determines the cache address of the first message by comparing the delay of the queue where the message is located with the first delay threshold, completes the allocation of the cache in the network device, and can ensure that the message with a small queue delay is cached in the on-chip cache, reduces the risk of the on-chip cache being filled with messages of congested traffic, reasonably utilizes the on-chip cache, and improves the utilization rate of the on-chip cache.

[0152] It should be noted that, in the above embodiment, the first delay threshold is determined according to the occupancy state of the on-chip cache, and the cache address of the message is allocated according to the first delay threshold. In practical applications, the congestion state of the message can also be determined according to the port receiving the message or the priority of the message, and the cache address is allocated to the message.

[0153] Please refer to Figure 3 , provides an integrated circuit system structure diagram for an embodiment of the present application. The method in the embodiment of the present application can be applied to include Figure 3 The modular structure of the network device is shown.

[0154] The network device may include a packet write control module (PWC), a queue manager module (QM), a packet memory control module (PMC), a packet read control module (PRC) and a global time stamp module (GLB_TS). The PMC includes an on-chip cache (or a first storage medium).

[0155] The PWC is configured to: receive the first message, obtain the queue number on the message header of the first message. The PWC sends a queue entry request for the first message to the QM (such as Figure 3The queue request pre-req in the queue includes the queue number of the first message.

[0156] Exemplarily, the PWC may further include a temporary buffer (TMP_PKT_BUF). When the PWC receives a first message and the storage device has not yet determined a buffer address of the first message, the PWC may temporarily buffer the first message in the TMP_PKT_BUF.

[0157] The QM is configured to: receive a queue entry request from the PWC, and query the queue delay of the queue according to the queue number of the queue in the queue entry request. In addition, the QM can also query the occupancy of the on-chip cache and determine the first delay threshold according to the occupancy.

[0158] Among them, the queue delay is the message delay of the third message, and the third message is the most recent message that has been dequeued from the queue, that is, the third message is the last message that has been dequeued from the queue, and the message delay is determined based on the time difference between the dequeuing time and the enqueuing time of the cache address of the third message in the queue.

[0159] It can be understood that the LBMS in the QM is called a local buffer management scheme (LBMS), and the QM can implement the relevant steps in the method provided in the embodiment of the present application through the LBMS (ie, the algorithm).

[0160] It should be noted that the QM determines the queue delay of the queue based on the message delay of the third message that has been out of the queue most recently. The QM may be the message delay of the third message obtained from the PRC.

[0161] It is understandable that the QM is used to maintain the occupancy status of the on-chip cache. A correspondence table between the on-chip cache occupancy status and the first latency threshold is set in the QM. For example, the QM can query the occupancy of the on-chip cache (On-chip buffer status, OB_STS) and the latency threshold corresponding to the occupancy (queue latency threshold table, QL_TH_TBL).

[0162] The QM queries the queue delay and the first delay threshold of the queue. If it is determined that the queue delay is less than the first delay threshold, the cache address of the first message is determined to be the on-chip cache, and the QM sends a first indication message (such as res) to the PWC to instruct the PWC to request the PMC to cache the first message in the on-chip cache. If it is determined that the queue delay is greater than the first delay threshold, the cache address of the first message is determined to be the off-chip cache, and the QM sends a second indication message to the PWC to instruct the PWC to request the PMC to cache the first message in the off-chip cache.

[0163] It is worth mentioning that a write buffer (W-Buf) is set in the PMC. The depth of W-Buf is used to characterize the cache pressure of the off-chip cache. The PMC can feed back the cache pressure of the off-chip cache to the QM in real time, such as Figure 3 After the QM determines that the cache address of the first message is an off-chip cache, the QM sends third indication information to the PWC to instruct the PWC to discard the first message.

[0164] In the first case, the PWC receives the first indication information from the QM. The PWC reads the first message from the temporary buffer (TMP_PKT_BUF), sends the first message to the PMC, and instructs the PMC to cache the first message in the on-chip buffer. The PMC is configured to receive the first message from the PMC and cache the first message in the on-chip buffer according to the indication information of the PMC.

[0165] In the second case, the PWC receives the second indication information from the QM. The PWC reads the first message from the temporary buffer (TMP_PKT_BUF), sends the first message to the PMC, and instructs the PMC to cache the first message in the off-chip buffer. The PMC is configured to receive the first message from the PMC and cache the first message in the off-chip buffer according to the indication information of the PMC.

[0166] In the third case, the PWC receives the third indication information from the QM. The PWC reads the first message from the temporary buffer (TMP_PKT_BUF) and deletes the first message.

[0167] It should be noted that QM may be the message delay of the third message obtained from the PRC, wherein the message delay of the third message is determined according to the dequeue time and the enqueue time of the third message. The PRC may include a queue delay table.

[0168] The PRC is configured to read messages and maintain a delay table for the queue. Taking the determination of the message delay of the third message as an example, the first timestamp in the message header of the third message is the time when the third message enters the queue. When the third message is read, the PRC reads the first timestamp in the message header of the third message to determine the time when the third message enters the queue; and the PRC obtains the current global timestamp as the time when the third message exits the queue. The QM obtains the time when the third message exits the queue and the time when the third message enters the queue in the PRC to determine the message delay of the third message, that is, the queue delay of the queue.

[0169] The PWC is further configured to obtain a first timestamp from the GLB_TS and add the first timestamp to a message header of the first message when the PWC reads the first message from the temporary buffer (TMP_PKT_BUF) and sends the first message to the PMC.

[0170] It can be understood that the global time stamp module (global time stamp, GLB_TS) is configured to be responsible for generating a global time stamp and sending the generated global time stamp to the PWC or PRC, so that the PRC can record the dequeue time of the message according to the global time stamp and maintain the delay table of the queue.

[0171] When a message is read, the specific process is as follows: the queues in the QM are scheduled, and a queue gets a chance to dequeue (such as a queue). The PD at the head of the queue (the PD may be LPD or EPD) is taken out of the queue and sent to the PRC through the interface of the dequeue PD. The PRC receives the read request of the queue, decomposes the read request of the queue into the read request of the message, and sends it to the PMC through the rd_req interface. The PMC receives the read request of the message from the queue of the PRC. If it is a message in the on-chip cache, it reads the message directly from the OCB and sends the message to the PRC; otherwise, it reads the message from the EB and sends the message to the PRC. The PRC receives the message returned by the PMC, decompresses the package to obtain the original independent message and sends it out of the storage module.

[0172] Exemplary process of calculating the message delay of a message: before the PWC reads the message TMP_PKT_BUF and writes it to the PMC, it puts a timestamp on the message header. The timestamp comes from the GLB_TS and is named HEAD_TS. When the PMC reads the message from the OCB or EB and returns it to the PRC, the PRC obtains the current global timestamp free_TS from the GLB_TS. The PRC obtains the delay QL of the current message based on the HEAD_TS and free_TS of the message when reading the message; the PRC uses the queue number of the current message as an index to address QL_TBL in the QM, and writes the QL of the current message into the delay table of the queue where the message is located as the latest delay of the queue.

[0173] The present application embodiment provides a message caching method which can be applied to the integrated circuit system in the above embodiment. The specific process of the method is as follows: Figure 4 As shown, it includes steps 301 to 306.

[0174] The embodiment of the present application takes modularization of an integrated circuit system as an application scenario, wherein the storage device includes a PWC, a QM and a PMC. The PMC includes an on-chip cache (or a first storage medium), and the storage device also includes an off-chip cache (or a second storage medium).

[0175] It should be noted that steps 301 to 306 in the embodiment of the present application correspond to steps 201 to 206 in the above embodiment, respectively. Therefore, the relevant technical details or implementation methods in steps 201 to 206 can also be applied to steps 301 to 306, which will not be described in detail here. Similarly, the relevant technical details or implementation methods in the embodiment of the present application can also be applied to the above embodiment.

[0176] Step 301: The PWC receives a first message. The message header of the first message includes a queue number of a queue. The queue number is used to indicate a queue storing a cache address of the first message. The PWC sends the queue number of the queue to the QM.

[0177] Exemplarily, the PWC receives the first message, identifies the queue number of the queue in the message header of the first message, and may send an enqueue request to the QM, where the enqueue request includes the queue number of the queue.

[0178] It can be understood that what the PWC sends to the QM is the queue number of the queue where the first message is located. The PWC can temporarily cache the first message, and cache the first message after the cache address of the first message is determined.

[0179] Step 302: The QM queries the queue delay of the queue according to the queue number of the queue.

[0180] The queue delay is the message delay of the third message, the third message is the most recent message that has been dequeued from the queue, and the message delay is determined according to the time difference between the dequeuing time and the enqueuing time of the cache address of the third message in the queue.

[0181] Exemplarily, a queue latency table (QL_TBL) of each queue may be preset in the QM. When the QM receives the queue number of the queue, or the QM receives a queue entry request from the PWC, the queue number of the queue is determined from the queue entry request. The QM may query the queue latency table according to the queue number of the queue to determine the queue latency of the queue.

[0182] As another example, the storage device may also include a packet read control module (PRC). The PRC stores a delay table of the queue, and the delay table of the queue stores the queue entry time and queue exit time of the message corresponding to the queue. When the QM receives the queue number of the queue, the QM may query the queue delay of the queue from the queue delay table stored in the PRC according to the queue number of the queue.

[0183] It should be noted that the queue delay table includes the dequeue time and enqueue time of the cache address of the third message in the queue, so that the storage device can determine the message delay based on the time difference between the dequeue time and enqueue time of the cache address of the third message in the queue.

[0184] The global timestamp module (GLB_TS) is responsible for generating a global timestamp and sending the generated global timestamp to the PWC or PRC, so that the PRC can record the dequeue time of the message according to the global timestamp and maintain the delay table of the queue.

[0185] For example, before requesting PMC to cache the third message in the on-chip cache or off-chip cache, PWC receives the first timestamp sent by GLB_TS and adds the first timestamp to the message header of the third message. QM adds the cache address of the third message to the queue and indicates the first timestamp to PRC; PRC records the first timestamp in the delay table of the queue, and the first timestamp is the time when the cache address of the third message enters the queue. After receiving the read request for the third message, PRC reads the third message from the first storage medium or the second storage medium, and PRC receives the second timestamp sent by GLB_TS; the second timestamp is the time when the cache address of the third message exits the queue; PRC records the second timestamp in the delay table of the queue.

[0186] For another example, before requesting PMC to cache the third message in the on-chip cache or off-chip cache, PWC receives the first timestamp sent by GLB_TS and adds the first timestamp to the third message. When the third message is read out of the queue, PRC is responsible for reading the first timestamp in the third message, and PRC receives the second timestamp from GLB_TS when reading the third message, and the second timestamp is the time when the cache address of the third message is dequeued from the queue. PRC records the first timestamp and the second timestamp in the delay table of the queue.

[0187] It is understandable that in the embodiment of the present application, the queue delay is determined by the message delay of the third message. Wherein, the storage device determines the message delay of the third message according to the dequeue time and the enqueue time of the third message. The above method for determining the message delay of the first message is the same as the method for determining the message delay of the first message, and will not be repeated here.

[0188] Step 303: The QM queries the occupancy of the on-chip cache and determines a first delay threshold according to the occupancy.

[0189] The occupied amount is used to characterize the size of the occupied storage space in the on-chip cache; the storage device stores the corresponding relationship between the occupied amount and the first delay threshold.

[0190] It is understandable that the QM is used to maintain the occupancy status of the on-chip cache. An on-chip cache occupancy status table is preset in the on-chip cache, including the occupancy of the on-chip cache (on-chip buffer status, OB_STS), and the latency threshold (queue latency threshold table, QL_TH_TBL) corresponding to the occupancy. When the storage device determines the first latency threshold, the QM queries the on-chip cache occupancy status table to determine the first latency threshold.

[0191] Step 304: The QM determines whether the queue delay is less than the first delay threshold.

[0192] Specifically, the QM compares the queue delay with the first delay threshold, and if the QM determines that the queue delay is less than the first delay threshold, executes steps 305 to 305b. If the QM determines that the queue delay is greater than the first delay threshold, executes steps 306 to 306b.

[0193] It is understandable that before executing step 304, the QM may set a first delay threshold for the cache address of the third message in the queue. The cache address of the second message is the message before the cache address of the first message in the queue. For example, if the storage device determines that the cache address of the third message is an on-chip cache, step 304 is executed and steps 305-305b or steps 306-306b are executed according to the execution result of step 304. If the storage device determines that the cache address of the second message is an off-chip cache, if the QM determines that the queue delay is less than the second delay threshold, the QM instructs the PWC to request the PMC to cache the first message in the on-chip cache; if the QM determines that the queue delay is greater than the second delay threshold, the QM instructs the PWC to request the PMC to cache the first message in the off-chip cache. The second delay threshold is less than the first delay threshold, and the difference between the second delay threshold and the first delay threshold is a preset value.

[0194] Step 305: The QM sends first indication information to the PWC.

[0195] If the cache address of the first message is cached on-chip, the first indication information indicates that the cache address of the first message is cached on-chip.

[0196] Step 305a: The PWC sends a first message and first indication information to the PMC.

[0197] It is understandable that after determining to cache the first message in the on-chip cache, the first message needs to be spliced ​​to determine the cache address of the first message. The method of splicing the first message has been described in step 205 of the above embodiment and will not be repeated here.

[0198] The queue entry request sent by the PWC to the QM also includes the message length of the first message, so that the QM can perform message splicing on the first message according to the message length of the first message to determine the cache address of the first message.

[0199] Step 305b: The PMC caches the first message in the on-chip cache according to the first indication information.

[0200] The PMC caches the first message in an on-chip cache according to the cache address in the first indication information.

[0201] It can be understood that the difference between the above steps 305 to 306a and steps 306 to 306b is that the indication information of the QM is different. The specific implementation method can refer to the above steps and will not be described in detail here.

[0202] Step 306: The QM sends second indication information to the PWC.

[0203] If the cache address of the first message is in an off-chip cache, the second indication information indicates that the cache address of the first message is in the off-chip cache.

[0204] Step 306a: The PWC sends the first message and the second indication information to the PMC.

[0205] The specific implementation of step 305a is the same as that of step 306a, except that the first indication information and the second indication information are carried. The specific implementation of this step can refer to the above step 305a, which will not be described in detail here.

[0206] Step 306b: The PMC caches the first message in an off-chip cache according to the second indication information.

[0207] It is understandable that the off-chip cache is characterized by large capacity but limited bandwidth. When the bandwidth pressure of the off-chip cache is high, the message cannot be written into the off-chip cache. Therefore, before performing message splicing on the first message, it is necessary to determine the back pressure information of the off-chip cache. For example, if the back pressure information of the off-chip cache is 0, it means that the bandwidth of the off-chip cache is sufficient to cache the first message, and the first message is spliced ​​to determine the cache address of the message. The second indication information includes the cache address, indicating that the PWC requests the PMC to cache the first message in the off-chip cache corresponding to the cache address. If the back pressure information of the off-chip cache is 1, it means that the bandwidth of the off-chip cache is insufficient to cache the first message, and the QM decides to discard the first message, then there is no need to perform splicing on the first message.

[0208] Exemplarily, since the PMC is connected to the off-chip cache, the PMC can obtain the back pressure information of the off-chip cache in real time, and send the back pressure information of the off-chip cache to the QM, so that the QM can decide the cache address of the message according to the back pressure information.

[0209] It should be noted that QM can implement the relevant steps in the method provided in the embodiment of the present application through LBMS (i.e., algorithm), which can ensure that the messages with small queue delay are cached in the on-chip cache, reduce the risk of the on-chip cache being filled with messages of congested traffic, reasonably utilize the on-chip cache, and improve the utilization rate of the on-chip cache.

[0210] It is worth mentioning that the PRC includes a write buffer (W-Buf), and the depth of W-Buf is used to characterize the cache pressure of the off-chip cache. When the cache pressure of the off-chip cache increases, the depth of W-Buf increases. If the bandwidth of the off-chip cache is not enough to cache the message, the depth of W-Buf will exceed the preset threshold, which indicates that the bandwidth of the off-chip cache is not enough to cache the message. W-Buf can generate back pressure information. If the depth of W-Buf exceeds the preset threshold, the back pressure information generated is a first value. If the depth of W-Buf does not exceed the preset threshold, the back pressure information generated is a second value.

[0211] The present application also provides an integrated circuit system, such as Figure 5 As shown, the integrated circuit system includes a processor 501, an on-chip cache 502 and an off-chip cache 503. Among them, the on-chip cache 502 is inside the chip of the processor 501, and the off-chip cache 503 is outside the chip of the processor 501. The processor 501 and the off-chip cache 503 can be interconnected through a line. The processor is used to: receive a first message, identify a queue number in the first message, and the queue number is used to indicate a queue that stores a cache address of the first message. Then, according to the queue number, query the queue delay of the queue. And, query the occupancy of the first storage medium, and determine the first delay threshold according to the occupancy. If the queue delay is less than the first delay threshold, the first message is cached in the first storage medium; if the queue delay is greater than the first delay threshold, the first message is cached in the second storage medium.

[0212] It is understandable that the processor 501 in the integrated circuit system can be used to implement the implementation steps in the above-mentioned message caching method, and in order to avoid repetition, they are not described here.

[0213] An embodiment of the present application also provides a computer storage medium, which includes computer instructions. When the computer instructions are executed on the above-mentioned network device, the network device executes each function or step executed by the mobile phone in the above-mentioned method embodiment.

[0214] The embodiment of the present application also provides a computer program product. When the computer program product is run on a computer, the computer is enabled to execute each function or step executed by the mobile phone in the above method embodiment.

[0215] Through the description of the above implementation methods, technical personnel in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0216] In the several embodiments provided in the present application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0217] The units described as separate components may or may not be physically separated, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0218] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0219] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium, including several instructions to enable a device (which can be a single-chip microcomputer, chip, etc.) or a processor (processor) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0220] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A message caching method, characterized in that: Applied to a network device, the network device includes a first storage medium and a second storage medium, the first storage medium is in a processor chip of the network device, and the second storage medium is outside the processor chip; the method includes: receiving a first message, identifying a queue number in the first message, where the queue number is used to indicate a queue storing a cache address of the first message; According to the queue number, query the queue delay of the queue; querying the occupancy of the first storage medium, and determining a first delay threshold according to the occupancy; Determine that a second message is cached in the first storage medium; wherein the message header of the second message includes the queue number of the queue, and the cache address of the second message is the last queued element of the cache address of the first message in the queue; if the queue delay is less than the first delay threshold, cache the first message in the first storage medium; if the queue delay is greater than the first delay threshold, cache the first message in the second storage medium; Determine that the second message is cached in the second storage medium; if the queue delay is less than the second delay threshold, cache the first message in the first storage medium; if the queue delay is greater than the second delay threshold, cache the first message in the second storage medium; wherein the second delay threshold is less than the first delay threshold, and the difference between the second delay threshold and the first delay threshold is a preset value.

2. The method according to claim 1, characterized in that The queue delay of the queue is the message delay of the third message; The third message is the last message that has been dequeued from the queue, and the message delay is determined according to the time difference between the dequeuing time and the enqueuing time of the cache address of the third message in the queue.

3. The method according to claim 2, characterized in that The network device includes a queue delay table of the queue, wherein the queue delay table includes an entry time and an exit time of a last message that has been exited from the queue; and the method further includes: Before the first storage medium or the second storage medium caches the third message, adding a first timestamp to the third message, wherein the first timestamp is the time when the third message is queued; Adding the cache address of the third message to the queue; After receiving a read request for the third message, the third message is read from the first storage medium or the second storage medium according to the cache address, a first timestamp in the third message is identified, and a second timestamp is determined, and the first timestamp and the second timestamp are recorded in the queue delay table, where the second timestamp is a dequeue time of the third message; wherein the second timestamp is a global time of the network device.

4. The method according to claim 2, characterized in that: The message delay is the time difference between the dequeue time and the enqueue time of the cache address of the third message in the queue; or, The message delay is a delay level determined according to the time difference between the dequeue time and the enqueue time of the cache address of the third message in the queue; wherein the network device stores multiple delay levels and the time difference corresponding to each delay level.

5. The method according to claim 1, characterized in that The network device includes the first storage medium occupation status table, wherein the first storage medium occupation status table includes the storage space occupied by the first storage medium and the delay threshold corresponding to the occupied storage space; The querying the occupancy of the first storage medium and determining the first delay threshold according to the occupancy includes: Querying the occupied amount of the first storage medium to determine the occupied storage space corresponding to the occupied amount; Determine that the delay threshold corresponding to the occupied storage space is a first delay threshold.

6. The method according to claim 1, characterized in that Before the second storage medium caches the first message, the method further includes: Acquire back pressure information of the second storage medium; wherein, when the back pressure information is a first value, it indicates that the bandwidth of the second storage medium is sufficient to cache the first message; the bandwidth of the second storage medium is used to characterize the amount of data that the second storage medium can store per unit time; The step of caching the first message in the second storage medium includes: If the back pressure information is the first value, the first message is cached in the second storage medium.

7. The method according to claim 6, characterized in that When the back pressure information is a second value, it indicates that the bandwidth of the second storage medium is insufficient to cache the first message; the method further includes: If the back pressure information is the second value, discarding the first message.

8. An integrated circuit system, characterized in that: include: A message writing control module PWC, a queue management module QM and a message buffer control module PMC; the PMC includes a first storage medium, and the PMC is connected to a second storage medium; The PWC is used to receive a first message and identify a queue number in the first message, where the queue number is used to indicate a queue storing a cache address of the first message; The QM is used to query the queue delay of the queue according to the queue number; and query the occupancy of the first storage medium, and determine the first delay threshold according to the occupancy; determine that the second message is cached in the first storage medium; wherein the message header of the second message includes the queue number of the queue, and the cache address of the second message is the last queued element of the cache address of the first message in the queue; if the QM determines that the queue delay is less than the first delay threshold, send first indication information to the PWC to instruct the PWC to request the PMC to cache the first message in the first storage medium; if the QM determines that the queue delay is greater than the first delay threshold, send second indication information to the PWC to instruct the PWC to request the PMC to cache the first message in the second storage medium; The QM is also used to determine that the second message is cached in the second storage medium; if the QM determines that the queue delay is less than a second delay threshold, the QM sends the first indication information to the PWC to instruct the PWC to request the PMC to cache the first message in the first storage medium; if the QM determines that the queue delay is greater than the second delay threshold, the QM sends the second indication information to the PWC to instruct the PWC to request the PMC to cache the first message in the second storage medium; wherein the second delay threshold is less than the first delay threshold, and the difference between the second delay threshold and the first delay threshold is a preset value.

9. The integrated circuit system according to claim 8, characterized in that: The queue delay of the queue is the message delay of the third message; The third message is the last message that has been dequeued from the queue, and the message delay is determined according to the time difference between the dequeuing time and the enqueuing time of the cache address of the third message in the queue.

10. The integrated circuit system according to claim 9, characterized in that: The integrated circuit system further comprises a message reading control module PRC, wherein the PRC stores a delay table of the queue, and the delay table of the queue stores an entry time and an exit time of a message corresponding to the queue; The queue is stored in the QM; The PWC is further configured to, before requesting the PMC to cache the third message in the first storage medium or the second storage medium, add a first timestamp to the third message; wherein the first timestamp is the time when the third message is queued; The QM is further configured to add the cache address of the third message to the queue, and if the QM receives a read request for the third message, send the read request for the third message and the cache address of the third message to the PRC; The PRC is used to, after receiving a read request for the third message from the QM, read the third message from the first storage medium or the second storage medium according to the cache address of the third message, determine the first timestamp in the third message, and determine the second timestamp; record the first timestamp and the second timestamp in the queue delay table; wherein the second timestamp is the global time of the integrated circuit system; and the second timestamp is the dequeue time of the cache address of the third message in the queue.

11. The integrated circuit system according to claim 9, characterized in that: The message delay is the time difference between the dequeue time and the enqueue time of the cache address of the third message in the queue; or, The message delay is a delay level determined based on the time difference between the dequeue time and the enqueue time of the cache address of the third message in the queue; wherein the integrated circuit system stores multiple delay levels and the time difference corresponding to each delay level.

12. The integrated circuit system according to claim 8, characterized in that: The integrated circuit system stores the first storage medium occupation status table, wherein the first storage medium occupation status table includes the storage space occupied by the first storage medium and the latency threshold corresponding to the occupied storage space; The QM is used to query the occupancy of the first storage medium. When determining the first delay threshold based on the occupancy, it is specifically used to query the occupancy of the first storage medium and determine the occupied storage space corresponding to the occupancy; and determine that the delay threshold corresponding to the occupied storage space is the first delay threshold.

13. The integrated circuit system according to claim 8, characterized in that: Before the QM sends the second indication information to the PWC, The PMC is further used to obtain back pressure information of the second storage medium; and send the back pressure information to the QM; the QM receives the back pressure information from the PMC; wherein, when the back pressure information is a first value, it indicates that the bandwidth of the second storage medium is sufficient to cache the first message; the bandwidth of the second storage medium is used to characterize the amount of data that the second storage medium can store per unit time; The QM is further configured to receive the back pressure information sent by the PMC, and if the QM determines that the back pressure information is the first value, the QM sends the second indication information to the PWC.

14. The integrated circuit system according to claim 13, characterized in that: When the back pressure information is a second value, it indicates that the bandwidth of the second storage medium is insufficient to cache the first message; The QM is further configured to, if the QM determines that the back pressure information is a second value, send third indication information to the PMC, where the third indication information is used to instruct the PMC to discard the first message. The PMC is further configured to receive third indication information from the QM, and discard the first message according to the third indication information.

15. An integrated circuit system, characterized in that: The integrated circuit system includes a processor, a first storage medium and a second storage medium, wherein the processor is configured to: Receive a first message, and identify a queue number in the first message, where the queue number is used to indicate a queue storing a cache address of the first message; According to the queue number, query the queue delay of the queue; querying the occupancy of the first storage medium, and determining a first delay threshold according to the occupancy; Determine that a second message is cached in the first storage medium; wherein the message header of the second message includes the queue number of the queue, and the cache address of the second message is the last queued element of the cache address of the first message in the queue; if the queue delay is less than the first delay threshold, cache the first message in the first storage medium; if the queue delay is greater than the first delay threshold, cache the first message in the second storage medium; Determine that the second message is cached in the second storage medium; if the queue delay is less than the second delay threshold, cache the first message in the first storage medium; if the queue delay is greater than the second delay threshold, cache the first message in the second storage medium; wherein the second delay threshold is less than the first delay threshold, and the difference between the second delay threshold and the first delay threshold is a preset value.

16. The integrated circuit system according to claim 15, characterized in that: The queue delay of the queue is the message delay of the third message; The third message is the last message that has been dequeued from the queue, and the message delay is determined according to the time difference between the dequeuing time and the enqueuing time of the cache address of the third message in the queue.

17. The integrated circuit system according to claim 16, characterized in that: The integrated circuit system stores a queue delay table of the queue, wherein the queue delay table includes an entry time and a dequeue time of a last dequeued message in the queue; and the processor is further configured to: Before the first storage medium or the second storage medium caches the third message, adding a first timestamp to the third message, wherein the first timestamp is the time when the third message is queued; Adding the cache address of the third message to the queue; After receiving a read request for the third message, the third message is read from the first storage medium or the second storage medium according to the cache address, a first timestamp in the third message is determined, and a second timestamp is determined, and the first timestamp and the second timestamp are recorded in the queue delay table, where the second timestamp is a dequeue time of the third message; wherein the second timestamp is a global time of the integrated circuit system.

18. The integrated circuit system according to claim 16, wherein: The message delay is the time difference between the time when the cache address of the third message is dequeued and the time when it is enqueued in the queue; or, The message delay is a delay level determined based on the time difference between the dequeue time and the enqueue time of the cache address of the third message in the queue; wherein the integrated circuit system stores multiple delay levels and the time difference corresponding to each delay level.

19. The integrated circuit system according to claim 15, characterized in that: The integrated circuit system stores the first storage medium occupation status table, wherein the first storage medium occupation status table includes the storage space occupied by the first storage medium and the latency threshold corresponding to the occupied storage space; When the processor is used to query the occupancy of the first storage medium and determine the first delay threshold according to the occupancy, the processor is specifically used to: querying the occupied amount of the first storage medium, and determining the occupied storage space corresponding to the occupied amount; Determine that the delay threshold corresponding to the occupied storage space is a first delay threshold.

20. The integrated circuit system according to claim 15, wherein: The processor is further configured to: Acquire back pressure information of the second storage medium; wherein, when the back pressure information is a first value, it indicates that the bandwidth of the second storage medium is sufficient to cache the first message; the bandwidth of the second storage medium is used to characterize the amount of data that the second storage medium can store per unit time; The step of caching the first message in the second storage medium includes: If the back pressure information is the first value, the first message is cached in the second storage medium.

21. The integrated circuit system according to claim 20, characterized in that: When the back pressure information is a second value, it indicates that the bandwidth of the second storage medium is insufficient to cache the first message; and the processor is further configured to: If the back pressure information is the second value, discarding the first message.

22. A computer-readable storage medium, characterized in that: The method comprises computer instructions, and when the computer instructions are executed on a network device, the network device is caused to execute the method according to any one of claims 1 to 7.

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