Control circuit for a random access memory, random access memory and electronic device

Abstract

The embodiment of the application provides a random memory control circuit, a random memory and an electronic device, and relates to the technical field of signal processing. The random memory control circuit comprises a control component and a weak pull-down component. The control end of the weak pull-down component is electrically connected with a controller. The output end of the weak pull-down component is electrically connected with a gating pin circuit. The controller controls the weak pull-down component to output a low-level signal when the controller determines the gating opening position of the DQS signal, so as to pull down the indeterminate state of the DQS signal to a low-level state. The technical problem that the gating opening position determination cost of the gating signal of the current DDR memory is high is solved. The artificial cost of the gating opening position determination of the gating signal is greatly reduced. Meanwhile, the compatibility and adaptability of the random memory are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of signal processing, in particular to a random memory control circuit, a random memory and an electronic device. BACKGROUND

[0002] When the DDR (Double Data Rate, double data rate synchronous dynamic random) memory reads data, a set of data read command signals are generated by an internal controller, and are sent to the memory particles after a delay t1 of the command signal line. The memory particles return the DQS signal (read data selection signal) and the DQ signal (data signal) to the controller after a fixed RL (Read Latency, read latency) time. The controller receives the DQS signal and the DQ signal fed back by the memory particles after a delay t2 of the data signal line. That is, the delay from the issuance of the data read command by the controller to the reception of the DQS signal and the DQ signal fed back by the memory particles is t1+RL+t2.

[0003] That is, the controller needs to open the gate of the gate signal between 0 and one clock cycle before the time t1+RL+t2 after the issuance of the command signal to receive the DQS signal and the DQ signal fed back by the memory particles. The gate opening interval is narrow and the accuracy requirement is high. However, there is an indefinite state area before the DQS signal pulse leading area. The indefinite state area randomly generates 01 or 10 transition glitches. Different transition glitches have different effects on the opening position of the gate signal, which requires different gate signal gate opening position determination algorithms for different DDR memories.

[0004] Therefore, the determination of the gate opening position of the gate signal of the current DDR memory has a high cost. SUMMARY

[0005] To solve the above technical problems, the present application provides a random memory control circuit, a random memory and an electronic device to reduce the cost of gate signal opening position determination.

[0006] The first aspect of the present application provides a random memory control circuit, comprising:

[0007] The control component comprises a controller and a gate pin circuit for receiving a read data selection signal;

[0008] The weak pull-down component is electrically connected to the controller at the control end, and is electrically connected to the gate pin circuit at the output end;

[0009] The controller is configured to control the weak pull-down component to output a low-level signal when the controller determines the gate opening position, so as to pull down the indeterminate state of the read data selection signal to a low-level state; wherein the strength of the low-level signal is less than the driving level of the read selection signal in the working mode.

[0010] In an optional embodiment of the present application, the weak pull-down component comprises:

[0011] The first inverting component, a control end of the first inverting component is electrically connected with the controller;

[0012] The first resistance component, a first end of the first resistance component is electrically connected with an output end of the first inverting component, and a second end of the first resistance component is electrically connected with a first input end of the gate pin circuit;

[0013] The second inverting component, a control end of the second inverting component is electrically connected with an output end of the first inverting component;

[0014] The second resistance component, a first end of the second resistance component is electrically connected with an output end of the second inverting component, and a second end of the second component is electrically connected with a second input end of the gate pin circuit.

[0015] In an optional embodiment of the present application, the first inverting component comprises:

[0016] The first field effect tube, a gate of the first field effect tube is electrically connected with the controller, and a drain of the first field effect tube is electrically connected with the control end of the second inverting component;

[0017] The second field effect tube, a gate of the second field effect tube is electrically connected with the controller, and a drain of the second field effect tube is electrically connected with the control end of the second inverting component;

[0018] The third field effect tube, a gate of the third field effect tube is electrically connected with the drain of the first field effect tube and the drain of the second field effect tube respectively, and a drain of the third field effect tube is electrically connected with the first end of the first resistance component.

[0019] In an optional embodiment of the present application, the second inverting component comprises:

[0020] The fourth field effect tube, a gate of the fourth field effect tube is electrically connected with the drain of the first field effect tube and the drain of the second field effect tube respectively;

[0021] The fifth field effect tube, a gate of the fifth field effect tube is electrically connected with the drain of the first field effect tube and the drain of the second field effect tube respectively;

[0022] The sixth field effect tube, a gate of the sixth field effect tube is electrically connected with the drain of the fourth field effect tube and the drain of the fifth field effect tube respectively, and a drain of the sixth field effect tube is electrically connected with the first end of the second resistance component.

[0023] In an optional embodiment of the present application, the first field effect transistor, the third field effect transistor and the fourth field effect transistor have the same first channel type; the second field effect transistor, the fifth field effect transistor and the sixth field effect transistor have the same second channel type; and the first channel type is different from the second channel type.

[0024] In an optional embodiment of the present application, the first field effect transistor, the third field effect transistor and the fourth field effect transistor are P-type field effect transistors; and the second field effect transistor, the fifth field effect transistor and the sixth field effect transistor are N-type field effect transistors.

[0025] In an optional embodiment of the present application, the first resistance component and the second resistance component each include a ground resistor.

[0026] In an optional embodiment of the present application, the first resistance component and the second resistance component have the same resistance value.

[0027] In an optional embodiment of the present application, the first resistance component and the second resistance component have a resistance value not less than one kilo-ohm.

[0028] A second aspect of the embodiments of the present application provides a random memory, comprising:

[0029] The control circuit of the random memory as in any of the above, the controller in the control circuit of the random memory is configured to generate a read data command and a gate signal;

[0030] The memory cell, which is electrically connected to the gate pin circuit in the control circuit of the random memory, is configured to generate a read data gate signal and a data signal according to the read data command;

[0031] The controller is further configured to determine a gate opening position of the gate signal when the weak pull-down component outputs a low-level signal to pull the indeterminate state of the read data gate signal to a low-level state.

[0032] A third aspect of the embodiments of the present application provides an electronic device, comprising:

[0033] The electronic device body;

[0034] The random memory as above is configured to control the electronic device body to boot up.

[0035] The control circuit of a random access memory provided in an embodiment of the present application includes: a control component and a weak pull-down component, the control end of the weak pull-down component being electrically connected to a controller, the output end of the weak pull-down component being electrically connected to a selection pin circuit, and the controller controlling the weak pull-down component to output a low-level signal when the controller determines the gate opening position, thereby pulling down the unstable state of the DQS signal to a low-level state. That is, in the embodiment of the present application, the unstable state region of the DQS signal is always in a low-level state without any influence of transition glitches. Therefore, by simply adding the control circuit of the random access memory provided in an embodiment of the present application to the pin circuit corresponding to the DQS signal, all random access memories can use a set of gate signal gate opening position determination algorithms, without the need to configure different algorithms for different circuits. This solves the technical problem of the high cost of determining the gate opening position of the gate signal of the current DDR memory, greatly reduces the labor cost of determining the gate opening position of the gate signal, and simultaneously improves the compatibility and adaptability of the random access memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0037] 100, random access memory; 110, controller; 120, memory chip; 130, command signal routing; 140, data signal routing; 300, random access memory control circuit; 310, control component; 311, controller; 312, selection pin circuit; 320, weak pull-down component; 321, first inverting component; 322, second inverting component; 323, first resistor component; 324, second resistor component; 700, electronic device; 710, electronic device body.

[0038] Figure 1 A schematic diagram of the random access memory structure provided in one embodiment of the present application;

[0039] Figure 2 A timing diagram of data reading from a memory chip port during the gate opening position determination process provided by one embodiment of the present application;

[0040] Figure 3 A schematic diagram of a control circuit of a random access memory provided in one embodiment of the present application;

[0041] Figure 4 A timing diagram of data reading from a memory chip port when a random access memory control circuit determines a gated open position of a gate signal provided in one embodiment of the present application;

[0042] Figure 5 A schematic diagram of a control circuit of a random access memory provided in one embodiment of the present application;

[0043] Figure 6 A structure diagram of a random memory provided for an embodiment of the application is shown in the following figure;

[0044] Figure 7 A structure diagram of an electronic device provided for an embodiment of the application is shown in the following figure. DETAILED DESCRIPTION

[0045] In the process of implementing the application, the applicant finds that the determination cost of the gate opening position of the gate signal of the current DDR memory is high.

[0046] In view of the above problems, the application provides a random memory control circuit and a random memory in the embodiments of the application to reduce the cost of determining the opening position of the gate signal.

[0047] In order to make the purpose, technical scheme and advantages of the application more clear, the application is further described in detail below by embodiments, and combined with the drawings. It should be understood that the specific embodiments described herein are only used to explain the application, and not to limit the application.

[0048] The serial numbers of components in this paper, such as "first", "second", etc., are only used to distinguish the described objects, and have no technical meaning. Unless otherwise specified, "connection" and "coupling" in the application include direct and indirect connection (coupling). In the description of the application, it should be understood that the terms "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the application and simplify the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, therefore it cannot be understood as a limitation of the application.

[0049] In the application, unless otherwise specified and limited, the first feature is "on" or "under" the second feature, which can be direct contact between the first and second features, or indirect contact between the first and second features through an intermediate medium. Moreover, the first feature "above", "above" and "above" the second feature can be directly above or obliquely above the first feature, or only indicate that the horizontal height of the first feature is higher than that of the second feature. The first feature "below", "below" and "below" the second feature can be directly below or obliquely below the first feature, or only indicate that the horizontal height of the first feature is less than that of the second feature.

[0050] The following briefly introduces the application environment of the control circuit of the random access memory provided in the embodiment of the present application:

[0051] The control circuit 300 of the random access memory provided in the embodiment of the present application is applied to the random access memory 100. The random access memory 100 in the embodiment of the present application refers to a DDR memory, such as any one of DDR3, DDR4, DDR5, and LPDDR3. Taking DDR3 as an example, see Figure 1 The DDR3 memory includes a DDR controller 110, a plurality of DDR memory chips 120, and a daisy-chain data read and write link composed of command signal lines 130 and data signal lines 140.

[0052] Please continue to see Figure 1 When reading data, the DDR controller 110 generates a command signal and sends it to the memory chip 120 via the command signal trace 130. The memory chip 120 receives the command signal after a delay of t1 along the command signal trace 130. After a fixed RL (Read Latency) time, the memory chip 120 sends the DQS and DQ signals to the controller 110. After a data signal delay of t2, the controller 110 receives the DQS and DQ signals. Therefore, the total delay from the controller 110 issuing the data read command to receiving the DQS and DQ signals from the memory chip 120 is T = t1 + RL + t2. It should be noted that the command trace delay t1 and the feedback signal trace delay t2 are determined by the specific PCB traces; longer traces increase the delay. The RL read delay is determined by the characteristics of the memory chip 120 and is specified in the DDR standard protocol, generally a fixed number of clock cycles, such as 8 clock cycles.

[0053] Please also see Figure 2 , where node 21 is the moment when the DQS signal arrives, and node 22 is the moment when the gate is opened. The controller 110 needs to open the gate of the gate signal after the command signal is sent and before the total delay T, that is, before the DQS signal arrives. Therefore, the total delay T is pushed forward half a clock cycle in the clock direction to open the gate to receive the DQS signal and DQ signal fed back by the memory chip 120.

[0054] The control circuit 300 of the random access memory provided in the embodiment of the present application is Figure 1The DQS pin in the controller 110 is electrically connected. When the gate opening position needs to be determined, the electronic switch K1 is turned on to connect the control circuit 300 of the random memory and the DQS pin in the controller 110, and a low level is output, so that the potential on the DQS pin is pulled down to a low level, even 0, thereby achieving the purpose of pulling the indeterminate state of the read data gating signal to a low level state.

[0055] Please refer to Figure 3 The embodiment of the application provides a control circuit 300 of a random memory, which comprises a control component 310 and a weak pull-down component 320.

[0056] The control end of the weak pull-down component 320 is electrically connected with the controller 110, and the output end of the weak pull-down component 320 is electrically connected with the gating pin circuit 312. The weak pull-down component 320 can be a grounding resistor, a current leakage electronic device, an N-type MOS tube, etc., and the embodiment is not limited specifically. Generally, for example, when the gate opening position of the gate signal does not need to be determined, for example, when the controller 110 is in a normal working mode after exiting the gate training mode, the weak pull-down component 320 can be in an off state. When the gate opening position of the gate signal needs to be determined, for example, the controller 110 starts the weak pull-down component 320 to generate a low level signal after the gate training mode is performed. The low level signal is used to pull the indeterminate state of the read data gating signal to a low level state, for example Figure 2 The high level state of the indeterminate state region of the DQS signal in the embodiment is pulled down to Figure 4 The low level state in the embodiment. It should be explained that the low level signal refers to a voltage less than 0.3 volts, represented by the number "0", and the high level signal with a voltage not less than 0.3 volts, represented by the number "1".

[0057] The control component 310 comprises a controller 110 and a gating pin circuit 312 for receiving a read data gating signal, and the controller 110 is used to control the weak pull-down component 320 to output a low level signal when the controller 110 determines the gate opening position, so as to pull the indeterminate state of the read data gating signal to a low level state.

[0058] In contrast to the weak pull-down component 320 described above, the controller 110 can control the weak pull-down component 320 to generate a low-level signal in the following ways. In a first case, if the weak pull-down component 320 is a grounding resistor, the controller 110 generates a control signal to turn on the electronic switch between the weak pull-down component 320 and the DQS pin, thereby generating a low-level signal. In a second case, if the weak pull-down component 320 is a bleeder electronic device, the controller 110 generates a control signal to turn on the bleeder electronic device, thereby introducing the electrical signal generated by the DQS pin into the ground, so as to pull the indeterminate state of the DQS signal to a low-level state. In a third case, the weak pull-down component 320 is an N-type MOS tube electrically connected to the DQS pin. The controller 110 generates a high-level signal as a gate input signal, turns off the source and drain, and outputs a low-level signal, so as to pull the DQS signal in the DQS pin to a low-level state. Of course, the weak pull-down component 320 is not limited to the above three cases, and the present application does not exhaustively list them. The weak pull-down component 320 only needs to be able to output a low-level signal.

[0059] The following embodiments briefly describe the working principle of the control circuit 300 of the random memory provided by the embodiments of the present application.

[0060] Please continue to refer to Figure 3 In the embodiments of the present application, when the opening position of the gate signal needs to be determined, that is, after entering the gate training mode, the controller 110 outputs a control signal to turn on the electrical connection between the weak pull-down component 320 and the DQS pin in the controller 110, so that the weak pull-down component 320 outputs a low-level signal, thereby pulling the potential on the DQS pin to a low-level state or even 0 in the indeterminate state without the driving of the DDR particle, so as to achieve the purpose of pulling the indeterminate state of the DQS signal in the DQS pin to a low-level state. However, because the strength of the low-level signal is much smaller than the driving strength of the DDR particle, the weak pull-down component 320 can only pull the indeterminate state without the particle driving to a low-level state, and the other leading edge and normal reading area with particle driving are not affected, so that the normal reading can be guaranteed. At the same time, when the opening position of the gate signal does not need to be determined, for example, after exiting the gate training mode and entering the normal working mode, the weak pull-down component 320 is turned off, so that there is no low-level signal and no response to the normal reading work, thereby further improving the stability and reliability of the data read and write of the DDR memory.

[0061] After pulling the indeterminate state of the DQS signal to a low-level state, the controller 110 can determine the opening position of the gate signal in the following ways.

[0062] The sampling position of the gating signal is moved in the direction of the sampling clock, and the read data selection signal is sampled based on the gating signal at the moved sampling position; if the read data selection signal is successfully sampled, the gating opening position of the gating signal is determined based on the moved sampling position.

[0063] The working mode of the weak pull-down component 320 in the embodiment of the present application is briefly introduced as follows:

[0064] The controller 110 continuously sends a read data command signal at a certain period, and the memory grain 120 generates a DQS signal and a DQ signal after receiving the command signal. The DQS signal generally sequentially experiences a high impedance state area of an undefined state, a leading area of a low level and a clock signal transmission area of multiple clock periods in a period, and reenters the high impedance state area in the next period to continue the cycle. In the high impedance state area, the jump glitches of "01" or "10" are prone to occur, and the controller 110 needs to determine the gating opening position of the gating signal by training in the gating training mode, that is, the gating is opened at different clock positions to continuously collect the DQS signal until the DQS signal is successfully collected. Then, the clock position returned based on the current successfully collected clock position is half a clock period or longer, and the returned clock position is determined as the gating opening position of the gating signal. However, in this process, the jump glitches of the undefined state will affect the collection of the DQS signal, leading to reading errors, so that the gating training fails. Therefore, the gating opening position determination method provided in the embodiment of the present application adds a weak pull-down component 110 to the DQS pin to pull the undefined state to a low level state, so as to realize stable collection of the DQS signal, and the specific working principle is as follows:

[0065] When the controller 110 enters the gating training mode, the weak pull-down component 110 generates a low level signal, and the low level signal is used as a weak pull-down drive to pull the undefined state without grain drive to a low level state, so that the high impedance state is always in a low level state instead of the original undefined state, thereby avoiding the influence of the undefined state on the sampling of the DQS signal and causing the failure of the gating training. However, the leading area and the normal reading area with grain drive are not affected, and the normal reading can be guaranteed. In the present application, the sampling of the DQS signal is always stable in the low level state, so that the obtained gating opening position avoids the original undefined area and is stably in the low level leading area.

[0066] After the controller 110 exits the gate training mode and enters the normal working mode, the gate signal is opened based on the gate opening position obtained in the training mode, and the DQS signal sent by the memory cell 120 is received based on the gate opening position, so as to ensure the reliability of signal receiving. At the same time, after exiting the training mode and entering the normal working mode, the weak pull-down component can be turned off, so that there is no low-level signal and no response to normal reading work.

[0067] In a first aspect, the control circuit 300 of the random memory provided in the embodiments of the present application comprises a control component 310 and a weak pull-down component 320. The control end of the weak pull-down component 320 is electrically connected to the controller 110, and the output end of the weak pull-down component 320 is electrically connected to the gate pin circuit 312. The controller 110 controls the weak pull-down component 320 to output a low-level signal when the controller 110 determines the gate opening position, so as to pull down the indeterminate state of the DQS signal to the low-level state. That is, in the embodiments of the present application, the indeterminate state region of the DQS signal is always in the low-level state without any jump glitch influence. Therefore, only the control circuit 300 of the random memory provided in the embodiments of the present application needs to be added to the pin circuit corresponding to the DQS signal, and a set of gate signal gate opening position determination algorithms can be used for all random memories 100, without the need to configure different algorithms correspondingly, thereby solving the technical problem of high cost of determining the gate opening position of the gate signal of the current DDR memory, greatly reducing the artificial cost of determining the gate opening position of the gate signal, and improving the compatibility and adaptability of the random memory 100.

[0068] In a second aspect, different gate signal gate opening position determination algorithms need to be configured with corresponding algorithm circuits, and the control circuit 300 of the random memory provided in the embodiments of the present application only needs to add a weak pull-down component 320 to the control component 310, which greatly simplifies the circuit of the random memory 100 and reduces the hardware cost of determining the gate opening position of the gate signal.

[0069] Please refer to Figure 5 In an optional embodiment of the present application, the weak pull-down component 320 comprises a first inverting component 321, a second inverting component 322, a first resistance component R1 and a second resistance component R2, wherein:

[0070] The control end of the first inverting component 321 is electrically connected with the controller 110, the output end of the first inverting component 321 is electrically connected with the first resistance component R1, and the control end of the second inverting component 322 is electrically connected with the output end of the first inverting component 321. Wherein, the first inverting component 321 and the second inverting component 322 can be inverters, or other electronic devices containing inverters, etc., which are not limited in the embodiment. The first inverter and the second inverter can be any one or any combination of TTL non-gate, CMOS inverter or HPM disturbance effect inverter, which is not limited in the embodiment, as long as the phase of the control signal generated by the controller 110 can be reversed by 180 degrees.

[0071] The first end of the first resistance component R1 is electrically connected with the output end of the first inverting component 321, and the second end of the first resistance component R1 is electrically connected with the first input end of the gate pin circuit 312. The first end of the second resistance component R2 is electrically connected with the output end of the second inverting component 322, and the second end of the second component is electrically connected with the second input end of the gate pin circuit 312. It needs to be explained that the first input end and the second input end of the gate pin circuit 312 are N pole pin (PADN) and P pole pin (PADP) in the pin circuit. Figure 5 Figure 5 In addition, the first resistance component R1 and the second resistance component R2 can be composed of fixed resistance or sliding rheostat, so as to facilitate the adjustment of the size of the resistance value according to different situations.

[0072] The weak pull-down component 320 in the embodiment of the application comprises: the first inverting component 321, the second inverting component 322, the first resistance component R1 and the second resistance component R2. In the first aspect, by setting the first inverting component 321 and the second inverting component 322, the control signal generated by the controller 110 can be phase-reversed, that is, no matter whether the controller 110 outputs a low-level signal or a high-level signal, the corresponding circuit can be turned on or turned off through the first inverting component 321 and the second inverting component 322, which has high flexibility; in the second aspect, by setting the first resistance component R1 and the second resistance component R2, the current flowing into the first input end and the second input end of the gate pin circuit 312 in the circuit can be consumed to a low-level state, which maximally guarantees the stability of the output low-level signal.

[0073] In one specific embodiment of the application, the first resistance component R1 and the second resistance component R2 both contain grounding resistors. Once the first resistance component R1 and the second resistance component R2 are grounded, no matter how large the current generated in the circuit is, it can be guided into the ground through the first resistance component R1 and the second resistance component R2, which further guarantees the stability and reliability of the weak pull-down component 320 outputting a low-level signal in the embodiment of the application.​

[0074] In one embodiment of the present application, the resistance values of the first resistance component R1 and the second resistance component R2 are equal, so that the current flowing into the first input end and the second input end of the selection pin circuit 312, or the potential difference between the first input end and the second input end of the selection pin circuit 312 is relatively balanced, further improving the stability of the low-level signal output by the embodiment of the present application.

[0075] In one embodiment of the present application, the resistance values of the first resistance component R1 and the second resistance component R2 are not less than kilo-ohms, for example, can be 4000K ohms, 6000K ohms, etc. Using high resistance resistors can greatly consume the current flowing into the first input end and the second input end of the selection pin circuit 312, or reduce the potential difference between the first input end and the second input end of the selection pin circuit 312, to the greatest extent to guarantee the stability and reliability of the output low-level signal.

[0076] At the same time, using high resistance resistors to output very weak low-level signals, the DQS signal has no memory particle driving level in the undefined state area, and based on the very weak low-level signal, it can be pulled down to a low-level state, but it will not affect the leading area and normal reading area with memory particle driving. After exiting the gated training mode and entering the normal working mode, the weak pull-down component will be turned off, so there is no low-level signal generated, which will not have any impact on the normal working mode.

[0077] Please continue to see Figure 5 In one optional embodiment of the present application, the first inverting component 321 includes: a first field effect transistor Q1, a second field effect transistor Q2 and a third field effect transistor Q3, wherein:

[0078] The gate G of the first field effect transistor Q1 is electrically connected with the controller 110, the drain D of the first field effect transistor Q1 is electrically connected with the control end of the second inverting component 322, and the source S of the first field effect transistor Q1 is electrically connected with the supply voltage (VDDQ) in the Figure 5 The controller 110 controls the on-off of the first field effect transistor Q1 through the generated control signal.

[0079] The gate G of the second field effect transistor Q2 is signal connected with the controller 110, the drain D of the second field effect transistor Q2 is electrically connected with the control end of the second inverting component 322, and the source S of the second field effect transistor Q2 is grounded. The controller 110 controls the on-off of the second field effect transistor Q2 through the generated control signal.

[0080] The gate G of the third field effect transistor Q3 is electrically connected to the drain D of the first field effect transistor Q1 and the drain D of the second field effect transistor Q2, respectively. The drain D of the third field effect transistor Q3 is electrically connected to the first end of the first resistor component R1. The source S of the third field effect transistor Q3 is electrically connected to the power supply voltage ( Figure 5 The first field effect tube Q1 and the second field effect tube Q2 output a level signal to control the on and off of the third field effect tube Q3.

[0081] The first inverting component 321 in the embodiment of the present application includes: a first field-effect transistor Q1, a second field-effect transistor Q2 and a third field-effect transistor Q3. The field-effect transistor has high power utilization, changes in the output load have little impact on the input end, and has strong load driving capability and good thermal stability. Therefore, the embodiment of the present application uses the field-effect transistor and the controller 110 in combination with the output of the low-level signal in the control circuit to improve the stability and reliability of the low-level signal output by the embodiment of the present application.

[0082] Please continue to see Figure 5 In an optional embodiment of the present application, the second inverting component 322 includes: a fourth field effect transistor Q4, a fifth field effect transistor Q5 and a sixth field effect transistor Q6, wherein:

[0083] The gate G of the fourth field effect transistor Q4 is electrically connected to the drain D of the first field effect transistor Q1 and the drain D of the second field effect transistor Q2, respectively. The source S of the fourth field effect transistor Q4 is electrically connected to the power supply voltage ( Figure 5 The fourth field effect tube Q4 is electrically connected to the VDDQ in the circuit, and the level signal output by the first field effect tube Q1 and the second field effect tube Q2 controls the on and off of the fourth field effect tube Q4.

[0084] The gate G of the fifth field effect transistor Q5 is electrically connected to the drain D of the first field effect transistor Q1 and the drain D of the second field effect transistor Q2 respectively. The source S of the fifth field effect transistor Q5 is grounded. The on and off of the fifth field effect transistor Q5 is controlled by the level signal output by the first field effect transistor Q1 and the second field effect transistor Q2.

[0085] A sixth field-effect transistor Q6 has a gate G electrically connected to the drain D of the fourth field-effect transistor Q4 and the drain D of the fifth field-effect transistor Q5, respectively. The drain D of the sixth field-effect transistor Q6 is electrically connected to the first end of the second resistor component R2. The sixth field-effect transistor Q6 is controlled to be on and off by the level signal output by the fourth field-effect transistor Q4 and the fifth field-effect transistor Q5.

[0086] The second inversion component in the embodiment of the application includes a fourth field effect tube Q4, a fifth field effect tube Q5 and a sixth field effect tube Q6. The field effect tube has high power utilization rate, small influence of output end load change on input end, strong driving load capacity and good thermal stability. Therefore, the embodiment of the application adopts the field effect tube to combine with the controller 110 to control the output of low level signal in the control circuit, so that the stability and reliability of the output low level signal of the embodiment of the application can be improved.

[0087] In an optional embodiment of the application, the first field effect tube Q1, the third field effect tube Q3 and the fourth field effect tube Q4 have the same first channel type; the second field effect tube Q2, the fifth field effect tube Q5 and the sixth field effect tube Q6 have the same second channel type. The first channel type is different from the second channel type, for example, if the first channel type is N type, the second channel type is P type; conversely, if the first channel type is P type, the second channel type is N type. By cross-connection of the P type and N type field effect tubes, the output level signal of the previous node can be used as the control signal of the next node, so that the linkage of the whole circuit is realized, too many control signals are avoided, and the circuit is greatly simplified under the premise of ensuring the stability of the output low level signal.

[0088] In a specific embodiment of the application, the first field effect tube Q1, the third field effect tube Q3 and the fourth field effect tube Q4 are P type field effect tubes; the second field effect tube Q2, the fifth field effect tube Q5 and the sixth field effect tube Q6 are N type field effect tubes.

[0089] The N type field effect tube is turned on under the action of the high level signal and outputs a low level signal; the P type field effect tube is turned on under the action of the low level signal and outputs a high level signal. Please continue to refer to Figure 5 As shown in the following table (1), in the first case, if the control signal is a low level signal, the currents flowing into the first input end and the second input end of the gate pin circuit 312 are both turned off; in the second case, if the control signal output by the controller 110 is a high level signal, the first field effect tube Q1 does not act, the second field effect tube Q2 is turned on and outputs a low level signal, the third field effect tube Q3 is turned on under the action of the low level signal and outputs a high level signal, the high level signal is dissipated through the first resistor component R1 and then enters the first input end (PADN) of the gate pin circuit 312. The fourth field effect tube Q4 is turned on under the action of the low level signal and outputs a high level signal, the fifth field effect tube Q5 is turned off, the sixth field effect tube Q6 is turned on under the action of the high level signal and outputs a low level signal, the low level signal is dissipated through the second resistor component R2 and then enters the second input end (PADP) of the gate pin circuit 312. That is, when the control signal is a high level signal, Figure 6The current flowing into the gate selection circuit 312 includes two paths: the first path: the second field effect transistor Q2-the third field effect transistor Q3-the first resistor component R1-the first input end (PADN) of the gate selection circuit 312; the second path: the second field effect transistor Q2-the fourth field effect transistor Q4-the sixth field effect transistor Q6-the second resistor component R2-the second input end (PADP) of the gate selection circuit 312. Different field effect transistors coordinate with each other to realize the linkage of the entire circuit, avoid introducing too many control signals, and greatly simplify the circuit under the premise of ensuring the stability of the output low-level signal.

[0090]

[0091]

[0092] Table (1)

[0093] Please refer to Figure 7 In another embodiment of the present application, a random memory 100 is provided, comprising a control circuit 300 of the random memory and a memory particle 120, wherein:

[0094] The memory particle 120 is electrically connected to the gate selection circuit 312 in the control circuit 300 of the random memory, and the memory particle 120 is used to generate a DQS signal (read data selection signal) and a DQ signal (data signal) according to a read data command, i.e. a command signal, and send the generated DQS signal and DQ signal to the controller 110 through the data signal wire 140.

[0095] The control circuit 300 of the random memory includes the control component 310 and the weak pull-down component 320 described above, and the beneficial effects of the control component 310 and the weak pull-down component 320 have been described in detail in the above embodiment, which will not be repeated here. At the same time, the controller 110 is used to generate a read data command and a gate signal, and determine the gate opening position of the gate signal when the weak pull-down component 320 outputs a low-level signal to pull down the indeterminate state of the read data selection signal to a low-level state.

[0096] The process of the controller 110 determining the gate opening position of the gate signal is briefly described as follows:

[0097] The electrical connection between the weak pull-down component 320 and the gate selection circuit corresponding to the read data selection signal is turned on, and a low-level signal is continuously generated; wherein the strength of the low-level signal is less than the driving level of the read selection signal in the working mode;

[0098] In the indeterminate state area of the read data selection signal, the low-level signal and the read data selection signal are logically AND processed to obtain the read data selection signal in the low-level state;

[0099] determining a read data delay of the memory grain 120 in the random memory 100;

[0100] determining an initial sampling position based on the read data delay and a preset clock period;

[0101] sampling the read data selection signal based on the gate signal at the initial sampling position;

[0102] if the sampling of the read data selection signal fails, advancing the initial sampling position by a preset sampling period in a direction of a sampling clock to obtain a resampling position;

[0103] resampling the read data selection signal based on the gate signal at the resampling position;

[0104] if the sampling of the read data selection signal succeeds, returning a sampling position corresponding to the gate signal when the first sampling succeeds by a preset clock period in the direction of the sampling clock to obtain a gate opening position of the gate signal. The preset clock period can be half a clock period.

[0105] Referring to ​ In another embodiment of the present application, an electronic device 700 is provided, comprising an electronic device body 710 and a random memory 100, wherein:

[0106] The electronic device body 710 can be a mobile phone, a pad, a wearable device, etc.

[0107] The random memory 100 as described above is used to control the booting of the electronic device body 710. The process of the random memory 100 controlling the booting of the electronic device body 710 can include the following steps:

[0108] In response to a booting instruction for the electronic device 700, a gate opening position of a gate signal is determined according to the gate opening position determination method of any one of the above.

[0109] The gate opening position is used to determine a gate position of the read data selection signal.

[0110] The electronic device 700 is started, and data stored in the memory grain 120 in the random memory 100 is read based on the read data selection signal at the gate position.

[0111] The control of the electronic device body 710 in this embodiment is to start the complete start-up behavior of the electronic device 700, which is different from the received start-up instruction. In other words, before each start-up, the embodiment of the present application first determines the gate-on position of the gate signal and the gating position of the DQS signal. After the determination of the two positions is completed, the gate can be opened based on the gate-on position, the DQS signal is taken as a clock to collect the DQ signal, the normal reading behavior can be executed, and the subsequent reading is more stable.

[0112] The technical features of the above-described embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above-described embodiments are not described, but as long as the combinations of the technical features do not exist, they should be considered as the scope of the present disclosure.

[0113] The above-described embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the patent scope of the present application. It should be pointed out that for ordinary skilled persons in the art, some modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A control circuit of a random access memory, characterized in that: include: The control component includes: a controller and a strobe pin circuit for receiving a read data strobe signal; A weak pull-down component, wherein a control end of the weak pull-down component is electrically connected to the controller, and an output end of the weak pull-down component is electrically connected to the strobe pin circuit; The controller is used to control the weak pull-down component to output a low-level signal when the controller determines the gate open position, so as to pull down the indeterminate state of the read data selection signal to a low-level state; and move the sampling position of the gate signal along the sampling clock direction, and sample the read data selection signal based on the gate signal at the moved sampling position; if the sampling of the read data selection signal is successful, determine the gate open position of the gate signal based on the moved sampling position; wherein the intensity of the low-level signal is less than the driving level of the read data selection signal in the working mode.

2. The control circuit of the random access memory according to claim 1, wherein: The weak pull-down component includes: a first inverting component, wherein a control terminal of the first inverting component is electrically connected to the controller; a first resistor component, wherein a first end of the first resistor component is electrically connected to the output end of the first inverting component, and a second end of the first resistor component is electrically connected to the first input end of the strobe pin circuit; a second inverting component, wherein a control terminal of the second inverting component is electrically connected to an output terminal of the first inverting component; A second resistance component, wherein a first end of the second resistance component is electrically connected to the output end of the second inverting component, and a second end of the second resistance component is electrically connected to the second input end of the selection pin circuit.

3. The control circuit of the random access memory according to claim 2, wherein: The first inverting component includes: a first field effect transistor, wherein a gate of the first field effect transistor is electrically connected to the controller, and a drain of the first field effect transistor is electrically connected to a control terminal of the second inverting component; a second field effect transistor, wherein a gate of the second field effect transistor is signal-connected to the controller, and a drain of the second field effect transistor is electrically connected to the control terminal of the second inverting component; A third field effect transistor, wherein the gate of the third field effect transistor is electrically connected to the drain of the first field effect transistor and the drain of the second field effect transistor respectively, and the drain of the third field effect transistor is electrically connected to the first end of the first resistor component.

4. The control circuit of the random access memory according to claim 3, wherein: The second inverting component comprises: a fourth field effect transistor, wherein a gate of the fourth field effect transistor is electrically connected to the drain of the first field effect transistor and the drain of the second field effect transistor respectively; a fifth field effect transistor, wherein a gate of the fifth field effect transistor is electrically connected to the drain of the first field effect transistor and the drain of the second field effect transistor respectively; A sixth field effect transistor, wherein the gate of the sixth field effect transistor is electrically connected to the drain of the fourth field effect transistor and the drain of the fifth field effect transistor respectively, and the drain of the sixth field effect transistor is electrically connected to the first end of the second resistor component.

5. The control circuit of the random access memory according to claim 4, wherein: The first field effect transistor, the third field effect transistor and the fourth field effect transistor have the same first channel type; the second field effect transistor, the fifth field effect transistor and the sixth field effect transistor have the same second channel type; wherein the first channel type is different from the second channel type.

6. The control circuit of the random access memory according to claim 5, wherein: The first field effect transistor, the third field effect transistor, and the fourth field effect transistor are P-type field effect transistors; the second field effect transistor, the fifth field effect transistor, and the sixth field effect transistor are N-type field effect transistors.

7. The control circuit of the random access memory according to claim 2, wherein: The first resistance component and the second resistance component both include a grounding resistor.

8. The control circuit of the random access memory according to claim 2, wherein: The resistance values ​​of the first resistance component and the second resistance component are equal.

9. The control circuit of the random access memory according to claim 2, wherein: The resistance of the first resistance component and the second resistance component is not less than kilohm.

10. A random access memory, characterized in that: include: The control circuit of a random access memory according to any one of claims 1 to 9, wherein the controller in the control circuit of the random access memory is used to generate a read data command and a gating signal; A memory chip is electrically connected to a strobe pin circuit in the control circuit of the random access memory and is used to generate a read data strobe signal and a data signal according to the read data command; The controller is further configured to determine a gated open position of the gate control signal when the weak pull-down component outputs a low-level signal to pull down the indeterminate state of the read data strobe signal to a low-level state.

11. An electronic device, characterized in that: include: Electronic device body; The random access memory according to claim 10, wherein the random access memory is used to control the power on of the electronic device.

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