Method of programming memory, memory device, and memory system

Abstract

This disclosure provides a memory programming method, memory device, and memory system. The method includes: performing a first programming on each memory cell to be programmed, such that each memory cell is programmed into N different first programming states; wherein N is a positive integer greater than 1 and less than M, and M is the total number of target programming states for the memory cells to be programmed; performing a second programming on the i-th group of memory cells in the first programming states, such that the i-th group of memory cells in the first programming states is programmed into k target programming states; wherein at least two groups of memory cells in the first programming states obtain different values ​​of the number of target programming states k after the second programming; k is greater than or equal to 1 and less than N; i is greater than or equal to 1 and less than or equal to N.

Description

Technical Field

[0001] This disclosure relates to the field of memory, and includes, but is not limited to, a memory programming method, a memory device, and a memory system. Background Technology

[0002] The ever-growing demand for high-capacity storage devices has spurred the development of various multi-level NAND flash memory cells, including MLC (Multi-Level Cell) which stores 2 bits of data per cell, TLC (Triple-Level Cell) which stores 3 bits of data per cell, QLC (Quad-Level Cell) which stores 4 bits of data per cell, and cell flash memory that stores even more bits per cell. As the number of bits stored in a memory cell increases, the programming time also increases, and the more bits a cell stores, the narrower the read margin between adjacent cells becomes. Therefore, there is a pressing need for a method that enables efficient programming of various multi-level cells and allows for more accurate reading after programming. Summary of the Invention

[0003] In view of the above, embodiments of the present disclosure provide a method for programming a memory, a memory device, and a memory system.

[0004] In a first aspect, embodiments of this disclosure provide a method for programming a memory, the method comprising:

[0005] Each memory cell to be programmed is first programmed, so that each memory cell is programmed to N different first programming states; where N is a positive integer greater than 1 and less than M, and M is the total number of target programming states of the memory cell to be programmed;

[0006] The storage units of the first programming state in the i-th group are second-programmed, so that the storage units of the first programming state in the i-th group are programmed into k target programming states; wherein, the number of target programming states k obtained after the second programming of the storage units of at least two groups of the first programming states is different; k is greater than or equal to 1 and less than N; i is greater than or equal to 1 and less than or equal to N.

[0007] In some embodiments, the first programming corresponds to N groups; the N groups are determined based on the coupling offset of each target programming state during the programming process, and each group corresponds to k target programming states.

[0008] In some embodiments, the first programming of each memory cell to be programmed, such that each memory cell is programmed to N different first programming states, includes:

[0009] According to the grouping, each storage unit is first programmed, so that each storage unit is programmed to the first programming state corresponding to the N groups.

[0010] In some embodiments, multiple adjacent target programming states whose coupling offsets are within a preset range are identified as the same group.

[0011] In some embodiments, multiple adjacent target programming states whose coupling offsets are within a preset range are determined to be in the same group, including at least one of the following:

[0012] The multiple adjacent target programming states whose coupling offset is less than a first preset threshold are determined as the first group;

[0013] The multiple adjacent target programming states whose coupling offset is greater than or equal to the first preset threshold and less than the second preset threshold are determined as the second group;

[0014] The multiple adjacent target programming states whose coupling offset is greater than or equal to the second preset threshold are determined as the third group.

[0015] In some embodiments, the coupling offset of each target programming state during the programming process is obtained based on the coupling offset test of each memory cell on adjacent word lines for each target programming state.

[0016] In some embodiments, the method further includes:

[0017] After the first programming is performed, each memory cell is first verified based on the first verification voltage of the first programming state; wherein, the first verification is used to determine whether each memory cell has been programmed to the corresponding first programming state.

[0018] In some embodiments, the first programming of each memory cell to be programmed, such that each memory cell is programmed to N different first programming states, includes:

[0019] Perform the first programming multiple times on each memory unit to be programmed;

[0020] Specifically, after each first programming, the first verification result corresponding to each first programming state is used to determine whether to perform the first programming again;

[0021] If the verification result indicates that the verification of the first programming state is successful, then the first programming is stopped;

[0022] If the verification result indicates that the verification of the first programming state fails, the first programming continues until each memory unit is programmed to N different first programming states.

[0023] In some embodiments, the N different first programming states each have N different first verification voltages.

[0024] In some embodiments, the method further includes:

[0025] After the second programming, each memory cell is second verified based on the second verification voltage of each target programming state; wherein, the second verification is used to determine whether each memory cell has been programmed to the target programming state; the second verification voltages corresponding to the k target programming states of the i-th group of the first programming states are different.

[0026] In some embodiments, the first verification voltage corresponding to the first programming state in the i-th group is less than any second verification voltage of the k target programming states after the second programming.

[0027] In some embodiments, the storage unit includes: a TLC with 8 states or a QLC with 16 states.

[0028] In a second aspect, embodiments of this disclosure provide a memory device, the memory device comprising:

[0029] A storage cell array, comprising multiple storage cells;

[0030] Peripheral circuitry, coupled to the memory cell array, is configured as follows:

[0031] Each memory cell to be programmed is first programmed, so that each memory cell is programmed to N different first programming states; where N is a positive integer greater than 1 and less than M, and M is the total number of target programming states of the memory cell to be programmed;

[0032] The storage units of the first programming state in the i-th group are second-programmed, so that the storage units of the first programming state in the i-th group are programmed into k target programming states; wherein, the number of target programming states k obtained after the second programming of the storage units of at least two groups of the first programming states is different; k is greater than or equal to 1 and less than N; i is greater than or equal to 1 and less than or equal to N.

[0033] In some embodiments, the peripheral circuit is further configured to: after performing the first programming, perform a first verification on each memory cell based on a first verification voltage of the first programming state; wherein the first verification is used to determine whether each memory cell has been programmed to the corresponding first programming state.

[0034] In some embodiments, the peripheral circuit is further configured to: after the second programming, perform a second verification on each memory cell based on a second verification voltage of each of the target programming states; wherein the second verification is used to determine whether each memory cell has been programmed to the target programming state; and the second verification voltages corresponding to the k target programming states of the i-th group of the first programming states are different.

[0035] In some embodiments, the storage unit includes: a TLC with 8 states or a QLC with 16 states.

[0036] Thirdly, embodiments of this disclosure provide a memory system, the memory system comprising:

[0037] A memory device as described in any of the above embodiments; and a memory controller coupled to the memory device and configured to control the memory device.

[0038] In the first programming of this embodiment, multiple memory units to be programmed with different target programming states are programmed into the same first programming state, saving the time of the first programming. Furthermore, the programming method of this embodiment does not require the encoded data to be Gray code in the first programming; therefore, balanced Gray code can be used to program and / or read the data after the second programming. That is, after the second programming is completed, balanced Gray code can be used to read the data. Therefore, after the second programming, the read margin of each page is larger (due to the larger voltage difference between the read voltages of each page), resulting in fewer read failure bit counts and ensuring data readability and reliability. Attached Figure Description

[0039] Figure 1A A schematic diagram of the structure of an exemplary system provided in this disclosure embodiment;

[0040] Figure 1B This is a schematic diagram of the structure of a memory card provided in an embodiment of the present disclosure;

[0041] Figure 1C This is a schematic diagram of the structure of a solid-state drive (SSD) provided in an embodiment of the present disclosure;

[0042] Figure 1D and Figure 1E A schematic diagram of a memory structure including a memory cell array and peripheral circuitry, provided for embodiments of this disclosure;

[0043] Figure 2 A flowchart illustrating a memory programming method provided in this disclosure embodiment;

[0044] Figure 3A flowchart illustrating another memory programming method provided in this disclosure embodiment;

[0045] Figure 4 A threshold voltage change graph after performing a second programming on the i-th group, provided in an embodiment of this disclosure;

[0046] Figure 5 This is a schematic diagram of the structure of a memory device provided in an embodiment of the present disclosure;

[0047] Figure 6 This is a schematic diagram of the structure of a memory system provided in an embodiment of the present disclosure. Detailed Implementation

[0048] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, which illustrate preferred embodiments of the present disclosure. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0050] like Figure 1A As shown in the illustration, this disclosure presents an exemplary system 10, which may include a host 20 and a memory system 30. The exemplary system 10 may include, but is not limited to, a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a memory device 34 therein; the host 20 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)).

[0051] In this embodiment of the disclosure, the host 20 can be configured to send data to or receive data from the memory system 30. Here, the memory system 30 may include a memory controller 32 and one or more memory devices 34. The memory devices 34 may include, but are not limited to, NAND flash memory, vertical NAND flash memory, NOR flash memory, dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase change random access memory (PCRAM), resistive random access memory (RRAM), and nano random access memory (NRAM).

[0052] In this embodiment of the disclosure, the storage controller 32 may be coupled to the memory device 34 and the host 20, and is used to control the memory device 34. Exemplarily, the storage controller may be designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In some embodiments, the storage controller may also be designed to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC), and the SSD or eMMC may also be used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays. Further, the storage controller may manage data in the memory device and communicate with the host. The storage controller may be configured to control operations such as reading, erasing, and programming of the memory device; it may also be configured to manage various functions regarding data stored or to be stored in the memory device, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.; and it may also be configured to process error correction codes (ECC) regarding data read from or written to the memory device. In addition, the storage controller can perform any other suitable functions, such as formatting the storage device, or communicating with external devices (e.g., according to a specific communication protocol). Figure 1A(20) Communication with the host. For example, the storage controller can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Devices (IDE) protocol, Firewire protocol, etc.

[0053] In embodiments of this disclosure, the storage controller and one or more memory devices can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system can be implemented and packaged into different types of end electronic products. Figure 1B As shown, the storage controller 32 and a single memory device 34 can be integrated into the memory card 40. The memory card 40 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 40 may also include a connector for connecting the memory card 40 to a host computer (e.g., Figure 1A The host 20) is coupled to the memory card connector 42. In such a way... Figure 1C In another embodiment shown, the storage controller 32 and a plurality of memory devices 34 may be integrated into the SSD 50. The SSD 50 may also include a connection between the SSD 50 and a host (e.g., Figure 1A The host 20 is coupled to the SSD connector 52. In some embodiments, the storage capacity and / or operating speed of the SSD 50 is greater than that of the memory card 40.

[0054] It should be noted that the memory device involved in the embodiments of this disclosure can be a semiconductor memory device, which is a solid-state electronic device for storing data information manufactured using semiconductor integrated circuit technology. For example, Figure 1D This is a schematic diagram of an optional memory device 60 according to an embodiment of the present disclosure. The memory device 60 may be... Figures 1A to 1C The memory device 34 in the middle. For example Figure 1DAs shown, the memory device 60 may consist of a memory cell array 62 and peripheral circuitry 64 coupled to the memory cell array 62. Here, the memory cell array may be a NAND flash memory cell array, wherein the memory cells are provided in the form of an array of NAND memory strings 66, each NAND memory string 66 extending vertically above a substrate. In some embodiments, each NAND memory string 66 may include a plurality of memory cells coupled in series and stacked vertically. Each memory cell is configured to hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the memory cell region. Additionally, each memory cell in the aforementioned memory cell array 62 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0055] In embodiments of this disclosure, the aforementioned storage cell may be a single-level cell (SLC) having two possible storage states and thus capable of storing one bit of data. For example, a first storage state "0" may correspond to a first voltage range, and a second storage state "1" may correspond to a second voltage range. In other embodiments, each storage cell is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four storage states. For example, an MLC may store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC may be programmed to take a range of possible nominal storage values. Exemplarily, if each MLC stores two bits of data, the MLC may be programmed to take one of three possible programming levels from the erase state by writing one of the three possible nominal storage values ​​to the storage cell. A fourth nominal storage value may be used in the erase state.

[0056] In this embodiment of the disclosure, the aforementioned peripheral circuitry can be coupled to the memory cell array via bit lines (BL), word lines (WL), source lines, source select gates (SSG), and drain select gates (DSG). Here, the peripheral circuitry can include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of the memory cell array by applying voltage and / or current signals to each target memory cell via the bit lines, word lines, source lines, SSG, and DSG, and sensing voltage and / or current signals from each target memory cell. Furthermore, the peripheral circuitry can also include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, as... Figure 1E As shown. The peripheral circuitry 70 includes a page buffer / sensor amplifier 71, a column decoder / bit line driver 72, a row decoder / word line driver 73, a voltage generator 74, a control logic unit 75, a register 76, an interface 77, and a data bus 78. It should be understood that the aforementioned peripheral circuitry 70 can be integrated with… Figure 1D The peripheral circuit 64 is the same as that in some embodiments, and in other embodiments, the peripheral circuit 70 may also include Figure 1E Additional peripheral circuitry not shown.

[0057] Due to the need for higher storage capacity, memory cells in NAND flash memory devices are configured to store more than one bit of memory data. nLC NAND flash memory cells can have 2... n Each state (e.g., charge range) can store n bits of data. Specifically, an SLC flash cell can have 2 states, thus storing 1 bit of data; an MLC flash cell can have 4 states, thus storing 2 bits of data; a TLC flash cell can have 8 states, thus storing 3 bits of data; a QLC flash cell can have 16 states, thus storing 4 bits of data, and so on.

[0058] In 2 n The state can include one erase state and 2 states. n -1 programming state. nLC NAND flash memory can be programmed and / or read page by page. During the programming operation, the nLC NAND flash memory cell is programmed to have 2 nEach state is represented by an n-bit data field, which is then written into a QLC NAND flash cell. Each word line in the memory block is coupled to multiple pages of nLC NAND flash cells, allowing a single page of nLC NAND flash cells to store n pages of data. For example, an SLC NAND flash cell can store 1 page of data, an MLC NAND flash cell can store 2 pages of data, a TLC NAND flash cell can store 3 pages of data, and a QLC NAND flash cell can store 4 pages of data, and so on. For instance, a QLC NAND flash cell can store 4 bits of data, where the 4 pages can be the lower-level page data (LP), the middle-level page data (MP), the upper-level page data (UP), and the extra-level page data (XP).

[0059] In the encoding of a set of numbers, if the codes of any two adjacent states differ by only one binary digit, this encoding is called Gray Code. Because the codes of any two adjacent states differ by only one binary digit, using Gray Code in programming and / or reading operations makes it easier to correct errors in the programmed and / or read data.

[0060] In some embodiments, a full-sequence programming method can be used to program each memory cell. Specifically, for QLC NAND flash memory, a 16-16 two-pass programming scheme can be used to program and / or read the memory cells. Table 1 shows a Gray code lookup table for programming and / or reading QLC NAND flash memory. The Gray code lookup table describes the mapping between the state of the QLC NAND flash cell and the logical page. In a read operation, to read the state of the QLC NAND flash cell using the 16-16 two-pass programming scheme, four reads are required for LP, four reads for MP, four reads for UP, and three reads for XP.

[0061] In the operation of reading logical page data, various read voltages are applied to the memory cell through the word line control circuit, and the value of the logical page data is determined by whether the control gate of the memory cell is on and the corresponding arithmetic expression. For example, when a read voltage is applied to the memory cell and the control gate is on, the output value is "1"; when a read voltage is applied to the memory cell and the control gate is off, the output value is "0". Taking the LP page as an example, by substituting the four output values ​​corresponding to its four read operations into the corresponding arithmetic expression, the value of the current logical page data can be determined. It can be understood that different Gray code lookup tables correspond to different arithmetic expressions.

[0062] When adjacent bits of data change within the same logical page, it is recorded as a transition. Counting all transitions within a logical page reveals that LP has a transition count of 4, MP has a transition count of 4, UP has a transition count of 4, and XP has a transition count of 3. When the difference in transition counts between any two adjacent pages within a logical page does not exceed a predetermined transition count difference, for example, a predetermined transition count difference of 1, it is a balanced Gray code. Therefore, the Gray code used in the Gray code lookup table shown in Table 1 is a balanced Gray code. Balanced Gray codes enable faster read operations because the maximum number of transitions to distinguish for each memory page is minimized.

[0063] For example, when using balanced Gray code "4443" as shown in Table 1, a read operation can distinguish a maximum of 4 transitions per memory page. However, when an unbalanced Gray code is used in the Gray code lookup table, the excessive number of transitions required to distinguish a particular page can make it a read bottleneck relative to other pages.

[0064] Taking QLC NAND flash memory as an example, for a 16-to-16 two-pass programming scheme, the logical page LP, MP, UP, and XP data are used in both the first pass (coarse programming) and the second pass (fine programming). In the first pass, the NAND flash cell is first programmed with a wider distribution of 16 voltage levels, and then in the second pass, it is reprogrammed with a narrower distribution of 16 voltage levels. To read the levels, a corresponding read voltage is applied to the QLC NAND flash cell to read and determine the state. The 16-to-16 two-pass programming scheme is unreadable after the first pass and has a slower programming speed (the first pass also requires programming to 16 states), but after the second pass, the read margin is larger (the voltage difference between the read voltages of each page is larger), and the read time is shorter.

[0065]

[0066] Table 1

[0067] In some embodiments, a multi-stage programming approach is used to program each memory unit.

[0068] Taking QLC NAND flash memory as an example, a two-stage programming scheme of 8-16 is used. In the first programming pass, the flash cell is programmed to the voltage distribution after TLC mode programming. Table 2a shows the mapping relationship between the state after the first programming pass in TLC mode and the Gray code. The data of its logical pages LP, MP, and UP can be used for programming. Therefore, after the first programming pass, its voltage distribution is readable. Then, a second programming pass is performed to continue programming to the voltage distribution after QLC mode programming. Table 2b shows the mapping relationship between the state after the second programming pass in QLC mode and the Gray code. Using this programming mode, the number of reads of XP after the second programming pass is 8, much greater than the 2 reads of LP, 3 reads of MP, and 2 reads of UP. This results in a narrow read margin when reading XP, which easily leads to an excessive number of failure bits and thus read failures.

[0069]

[0070] Table 2a

[0071]

[0072] Table 2b

[0073] Therefore, embodiments of this disclosure provide a method for programming a memory, such as... Figure 2 As shown, the method includes:

[0074] S101. Perform a first programming on each memory unit to be programmed, so that each memory unit is programmed to N different first programming states; where N is a positive integer greater than 1 and less than M, and M is the total number of target programming states of the memory unit to be programmed;

[0075] S102. Perform a second programming on the storage units of the first programming state in the i-th group, so that the storage units of the first programming state in the i-th group are programmed into k target programming states; wherein, the number of target programming states k obtained after the second programming of the storage units of at least two groups of the first programming states is different; k is greater than or equal to 1 and less than N; i is greater than or equal to 1 and less than or equal to N.

[0076] The memories described in this disclosure include, but are not limited to, non-volatile memories, volatile memories, and novel memories. Non-volatile memories include, but are not limited to, electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), and flash memory; wherein, flash memory includes, but is not limited to, NOR flash memory and NAND flash memory; volatile memories include, but are not limited to, static random access memory (SRAM) and dynamic random access memory (DRAM). Novel memories include, but are not limited to, 3D Xpoint, magnetic random access memory (MRAM), resistive random access memory (RRAM), ferroelectric random access memory (FRAM), and phase change memory (PCM). For ease of description, this disclosure uses 3D NAND flash memory as an example for illustration.

[0077] For nLC NAND, its programmable memory cells have 2 n -1 target programming states, where the memory cells that do not require programming remain in the erased state. Each memory cell to be programmed is first programmed, resulting in N different first programming states; where 1 ≤ N < M, and N is a positive integer, and M is the total number of target programming states for the memory cells to be programmed, therefore M is 2. n -1. Therefore, after the first programming is completed, at least two memory units with different target programming states are programmed into the same first programming state. Here, the first programming state can be a programming state without clear data meaning, or it can be understood as an intermediate state in the programming process.

[0078] The storage units of the first programming state in the i-th group are second-programmed, so that the storage units of the first programming state in the i-th group are programmed into k target programming states; wherein, the number of target programming states k obtained after the second programming of the storage units of at least two groups of the first programming states is different; k is greater than or equal to 1 and less than N; i is greater than or equal to 1 and less than or equal to N.

[0079] After the first programming, the unit to be programmed is programmed into N first programming states; the i-th first programming state can correspond to k target programming states, which can be represented as k i Each target programming state, i.e., each first programming state, can also correspond to k1, k2, ..., k N There are k target programming states, meaning the memory units to be programmed into k1 different target programming states are all programmed into the same first programming state P1 after the first programming. Similarly, the memory units to be programmed into k2 different target programming states are all programmed into the same first programming state P2 after the first programming, and so on, until the memory units to be programmed into k different target programming states are all programmed into the same first programming state P2. N After the first programming, the memory units of each target programming state are all programmed into the same first programming state PN. This can be understood as k1+k2+…+k N =2 n -1.

[0080] Then, perform a second programming on N different first programming states, programming the first programming state P1 to k1 target programming states, programming the first programming state P2 to k2 target programming states, and so on, programming the first programming state PN to k N A target programming state is the process of programming a memory unit to be programmed into a target programming state.

[0081] In the first programming of this embodiment, multiple memory units to be programmed with different target programming states are programmed into the same first programming state, saving the time of the first programming. Furthermore, the programming method of this embodiment does not require the encoded data to be Gray code in the first programming; therefore, balanced Gray code can be used to program and / or read the data after the second programming. That is, after the second programming is completed, balanced Gray code can be used to read the data. Therefore, after the second programming, the read margin of each page is larger (due to the larger voltage difference between the read voltages of each page), resulting in fewer read failure bit counts and ensuring data readability and reliability.

[0082] In some embodiments, the first programming corresponds to N groups; the N groups are determined based on the coupling offset of each target programming state during the programming process, and each group corresponds to k i (1≤i≤N) target programming states.

[0083] The change in the threshold voltage of a memory cell caused by the influence of the threshold voltages of neighboring memory cells is defined as the coupling offset. A decrease in the threshold voltage of a memory cell is defined as a left offset, and an increase in the threshold voltage of a memory cell is defined as a right offset. In some embodiments, the coupling offset rate can also be used instead of the coupling offset. The coupling offset rate is defined as the ratio of the coupling offset to the target state threshold voltage. For ease of description, the coupling offset is used in this disclosure, but the coupling offset rate can also be used. Before the first programming of the memory cell to be programmed, the coupling offset of the memory cell to be programmed can be known and can be grouped according to certain rules, so the number of groups N is also determined at this time.

[0084] The grouping is determined based on the coupling offset of each target programming state during the programming process, such as dividing it into N groups. Here, the i-th group corresponds to k. i There are k target programming states (1 ≤ i ≤ N), meaning the first group contains k1 target programming states, the second group contains k2 target programming states, and so on, with the Nth group containing k N A target programming state.

[0085] In some embodiments, such as Figure 3 As shown, the first programming of each memory cell to be programmed, so that each memory cell is programmed to N different first programming states, includes:

[0086] S201. According to the grouping, perform a first programming on each storage unit, so that each storage unit is programmed to the first programming state corresponding to the N groups.

[0087] Taking a memory cell as an example of a floating-gate transistor, the floating gate material of the floating-gate transistor is a conductor. Any two conductors that are insulated from each other and very close together will form a capacitor. Therefore, the floating gates of any two memory cells constitute a capacitor, and a change in charge within one floating gate will cause a change in charge within the floating gates of other memory cells. A coupling capacitance exists between a floating gate and its neighboring floating gates. The magnitude of this capacitance is inversely proportional to the distance between them: the shorter the distance, the larger the capacitance, and the greater the mutual influence. The existence of coupling capacitance causes a shift in the threshold voltage of the memory cell after programming, i.e., a coupling offset. This coupling offset alters the threshold voltage distribution, leading to read failures during read operations.

[0088] Table 3 shows the coupling offset of memory cells in each programming state in one embodiment, caused by the influence of memory cells in adjacent word lines. In the first column, p1 to p7 represent the different states of memory cells on the current word line, and the first row represents the different states of memory cells on adjacent word lines. Taking TLC NAND flash memory as an example, Table 3 shows the coupling influence of memory cells in different states on adjacent word lines when memory cells on the current word line are in different states. It can be seen that for memory cells in a certain state, generally speaking, the higher the threshold voltage of memory cells on adjacent word lines, the greater the coupling influence, i.e., the greater the coupling offset or coupling offset rate. It can also be seen that for memory cells with different threshold voltages on the same word line, generally speaking, the coupling influence between memory cells with lower threshold voltages and memory cells on adjacent word lines is greater than the coupling influence between memory cells with higher threshold voltages and memory cells on adjacent word lines.

[0089]

[0090]

[0091] Table 3

[0092] Before programming the units to be programmed, they can be grouped according to the coupling offset relationship between each target programming state, such as into N groups. The i-th group contains k... i There are k target programming states, meaning the first group contains k1 target programming states, the second group contains k2 target programming states, and so on, with the Nth group containing k N A target programming state.

[0093] After grouping, all k1 target programming states within the first group are programmed into the same first programming state P1, that is, for k in the i-th group... i All target programming states are programmed into the same first programming state Pi, where 1 ≤ i ≤ N, and i is a positive integer. Each first programming state is distinct. Therefore, after dividing into N groups, each memory unit undergoes a first programming operation. After the first programming, each unit to be programmed is programmed into one of the N first programming states.

[0094] In this embodiment of the disclosure, the memory cells are grouped according to the coupling offset generated during the programming process of the target programming state. The memory cells with low or similar coupling offsets can be grouped into the same group, and the memory cells to be programmed in the same group can be programmed into the same first programming state. This not only saves programming time, but also reduces the coupling offset after the memory cells are programmed.

[0095] In some embodiments, multiple adjacent target programming states whose coupling offsets are within a preset range are identified as the same group.

[0096] The preset range division rule can be to divide the target programming states into N groups as evenly as possible based on the magnitude of the coupling offset, or to divide one or more target programming states with low threshold voltages into the same group and one or more target programming states with high threshold voltages into the same group based on the coupling offset. The preset range division can also be other user-defined rules. For example, one or more adjacent target programming states with coupling offsets within the same preset range can be divided into the same group, and there can be multiple preset ranges.

[0097] The target programming states of memory cells in the same group are adjacent, but adjacent target programming states are not necessarily in the same group: if the coupling offset difference between adjacent target programming states is large, they cannot be in the same group, but are instead placed in different groups. In fact, when the coupling offset of the target programming states exceeds a certain preset range, they can be grouped into a third group.

[0098] In this way, multiple target programming states to which each memory cell is to be programmed can be flexibly grouped, and memory cells in the same group can be programmed into the same first programming state through a first programming, and then programmed into one or more corresponding target programming states through a second programming. This can minimize the impact of coupling offsets between target programming states in the same group and improve programming accuracy.

[0099] In some embodiments, multiple adjacent target programming states whose coupling offsets are within a preset range are determined to be in the same group, including at least one of the following:

[0100] The multiple adjacent target programming states whose coupling offset is less than a first preset threshold are determined as the first group;

[0101] The multiple adjacent target programming states whose coupling offset is greater than or equal to the first preset threshold and less than the second preset threshold are determined as the second group;

[0102] The multiple adjacent target programming states whose coupling offset is greater than or equal to the second preset threshold are determined as the third group.

[0103] It should be noted that the above-mentioned first group, second group, and third group are three types of grouping, and are not limited to the first programming being divided into three groups. That is to say, the above-mentioned first group, second group, and third group can be one or more, or they can be none (for example, the first programming may only include two second groups and two third groups).

[0104] In this embodiment of the disclosure, the first preset threshold may be less than the second preset threshold. All adjacent target programming states that are less than the first preset threshold can be grouped into a first group.

[0105] The adjacent target programming states between the first preset threshold and the second preset threshold are divided into a second group.

[0106] The first and second preset thresholds mentioned here are merely exemplary thresholds. Multiple preset thresholds can be set as needed, such as a third preset threshold, a fourth preset threshold, etc. That is, in practical applications, the grouping rules can be flexibly set.

[0107] For example, the second group can be further divided, such as setting a third preset threshold between the first preset threshold and the second preset threshold, dividing adjacent target programming states between the first preset threshold and the third preset threshold into a fourth group, and dividing adjacent target programming states between the third preset threshold and the second preset threshold into a fifth group; more intermediate preset thresholds can also be set between the first preset threshold and the second preset threshold to divide more groups.

[0108] In addition, adjacent target programming states that are greater than the second preset threshold can be divided into a third group.

[0109] Whether it is the first group, the second group, or the third group, the target programming state within the group can be one or more.

[0110] Taking TLC NAND flash memory as an example, Table 3 shows the coupling offset between its memory cell and the memory cells of adjacent word lines. The memory cell is in the programming state from p1 to p7, and the adjacent memory cells are in the erase state from p0 and the programming state from p1 to p7. The coupling offset between them ranges from 1mV to 183mV, which is divided into at least two preset ranges.

[0111] The coupling offsets between the memory cell and its adjacent memory cells within a first preset range are divided into a first group. For example, if the first preset range is set to <40mV, the coupling offsets between the memory cell and its adjacent memory cells in states p0, p1, and p2 are all less than 40mV; therefore, p1 and p2 can be grouped into the same group (where the target state is the erase state, no programming is required).

[0112] Multiple adjacent target programming states whose coupling offsets with adjacent memory cells fall within a second preset range are designated as a second group. This second preset range can be one or more, with one or more second preset ranges corresponding to one or more second groups. For example, adjacent target programming states with coupling offsets between 40-100mV can be grouped into one second group, i.e., p3, p4, and p5 can be grouped together. Similarly, adjacent target programming states with coupling offsets between 40-60mV can be grouped into one second group, i.e., p3 can be grouped together; and adjacent target programming states with coupling offsets between 60-100mV can be grouped together, i.e., p4 and p5 can be grouped together. In other words, when there are two second preset ranges, adjacent target programming states can be divided into two second groups.

[0113] Finally, when the coupling offset is greater than 100mV, it is considered as the third group, so p6 and p7 can be divided into the third group.

[0114] The above is just one example of the division of the predetermined range. In actual use, there can be many ways to divide the range.

[0115] In some embodiments, the coupling offset of each target programming state during the programming process is obtained based on the coupling offset test of each memory cell on adjacent word lines for each target programming state.

[0116] Because coupling offset is affected by factors such as memory manufacturing process, memory bit width, and materials, the coupling offset may vary between different memories. Therefore, the coupling offset between memory cells can be determined through factory testing before the memory leaves the factory and used as a fixed attribute of the memory.

[0117] Silicon testing (SPT) can be used to obtain the coupling offset. In SPT, taking QLC NAND flash memory as an example, the states of the test cells are p1 to p15, and the states of the adjacent word lines are p0 to p15. The coupling offset is the difference between the threshold voltage of the test cell after being affected by the coupling of adjacent word lines and the threshold voltage of the test cell after programming. SPT can obtain the coupling offset of different memories. For a given memory, multiple preset ranges of coupling offset values ​​can be set to group it into multiple groups, such as 6 groups, 8 groups, or 10 groups.

[0118] Then, the distributed pairs are divided into 6, 8, and 10 groups of programmable units, and a Margin Loss test is performed. The group with the lowest test loss value is used as the default group in memory. In this way, during subsequent memory use, the first programming can be performed based on the above grouping, and then the second programming can be performed to achieve the desired target programming state.

[0119] In some embodiments, the method further includes:

[0120] After the first programming is performed, each memory cell is first verified based on the first verification voltage of the first programming state; wherein, the first verification is used to determine whether each memory cell has been programmed to the corresponding first programming state.

[0121] After the memory cell to be programmed is first programmed, a first verification voltage can be used to verify whether the memory cell has been programmed to the corresponding first programming state. For memory cells grouped together, the same verification voltage is used for verification; that is, one first programming state corresponds to one first verification voltage. Because the memory cell needs to undergo a second programming process after the first programming state to reach the target programming state, the first verification voltage used to verify the first programming state is less than the target verification voltage corresponding to the target programming state.

[0122] In this way, only one first verification voltage is used for the first programming of each group, which can save a lot of verification time and improve the overall programming speed.

[0123] In some embodiments, the first programming of each memory cell to be programmed, such that each memory cell is programmed to N different first programming states, includes:

[0124] Perform the first programming multiple times on each memory unit to be programmed;

[0125] Specifically, after each first programming, the first verification result corresponding to each first programming state is used to determine whether to perform the first programming again;

[0126] If the verification result indicates that the verification of the first programming state is successful, then the first programming is stopped;

[0127] If the verification result indicates that the verification of the first programming state fails, the first programming continues until each memory unit is programmed to N different first programming states.

[0128] The first programming step can be performed using ISPP (Incremental Step Pulse Program). When programming NAND flash memory, it's done on a page-by-page basis. For each memory cell within a page, a programming pulse with a starting voltage is used to program the cell. Then, a verification pulse is used to verify if the cell has been programmed into the first programming state. If not, the programming voltage is increased in increments, and the cell is programmed again using the same voltage. This verification process is repeated until the cell is programmed into the first programming state. Then, the cell is suppressed and no longer programmed. The first programming process ends when all the memory cells within the page have been programmed into the first programming state.

[0129] In this embodiment, after dividing the memory cells to be programmed into N groups, a first programming is performed on the memory cells to be programmed. After the first programming, the memory cells in the same group are subjected to a first verification using the same verification voltage to verify their corresponding first programming state. The first verification is used to determine whether each memory cell has been programmed to the corresponding first programming state. When the verification is successful, the first programming of that group is stopped. Then the first programming is performed on the next group of memory cells to be programmed, until all N groups have been programmed to the first programming state, and the complete first programming process ends.

[0130] In some embodiments, the N different first programming states each have N different first verification voltages.

[0131] It is understood that the N different first programming states each have corresponding N different first verification voltages. If at least two verification voltages are the same, then at least two groups of programming objects are programmed into the same first programming state. However, since the first programming states of each group of programming objects are different, this contradicts the rule that there are no at least two identical verification voltages. In other words, the number of first verification voltages corresponds to the number of first programming states.

[0132] In some embodiments, the method further includes:

[0133] After the second programming, each memory cell is second verified based on the second verification voltage of each target programming state; wherein, the second verification is used to determine whether each memory cell has been programmed to the target programming state; the second verification voltages corresponding to the k target programming states of the i-th group of the first programming states are different.

[0134] The second programming can also be performed using the ISPP method on the memory cells in the first programming state. Here, the i-th group of first programming states corresponds to k target programming states; therefore, after the i-th group of first programming states undergoes the second programming, it can be verified using k different second verification voltages.

[0135] In some embodiments, the first verification voltage corresponding to the first programming state in the i-th group is less than any second verification voltage of the k target programming states after the second programming.

[0136] The memory cell to be programmed needs to undergo a second programming process after the first programming state before reaching the target programming state. Therefore, the first verification voltage used to verify the first programming state is less than any second verification voltage of its corresponding target programming state. Figure 4 The threshold voltage change graph after the second programming of the i-th group is provided in the embodiments of this disclosure, so as to Figure 4 For example, after the first programming, the four types of memory cells to be programmed in the i-th group are all programmed to the first programming state Pi. The threshold voltage corresponding to the first programming state Pi is vth_C1. This threshold voltage is lower than any of the target threshold voltages vth_F1, vth_F2, vth_F3, and vth_F4 corresponding to the four types of memory cells to be programmed in the i-th group. The programming is completed by programming vth_C1 to vth_F1, vth_F2, vth_F3, and vth_F4 respectively through the second programming. Because the lower the threshold voltage of a memory cell, the lower its corresponding verification voltage, and vice versa, when the threshold voltage of the first programming state corresponding to the i-th group is less than the target threshold voltage corresponding to the second programming state of the i-th group, the first verification voltage corresponding to the first programming state of the i-th group is less than any of the second verification voltages of the k target programming states after the second programming.

[0137] It is worth noting that the vth_C1 of the first and i-th groups after the first programming is at a lower level compared to the lowest threshold voltage vth_F1 after the second programming. In fine programming, i.e., the second programming, multiple bit line voltages and multiple word line voltages can be used to control the amplitude of fine programming. Therefore, keeping vth_C1 at a lower level ensures that even with the lowest amplitude fine programming, vth_C1 will not be overprogrammed to exceed the range of vth_F1 after a second programming with the lowest amplitude.

[0138] Second, in the i-th group, during fine programming, i.e. from the first programming state to the target programming state, the threshold voltage offset of the lowest threshold voltage of the memory cell is Vth_F4-Vth_c1+Fine Vth width, where Fine Vth width is the threshold voltage width of the memory cell after fine programming.

[0139] Third, the total threshold voltage offset from the first programming state to the target programming state should be the coupling offset between word lines (i.e., between memory cells and adjacent memory cells) plus the threshold voltage offset of the programming voltage increase.

[0140] In some embodiments, the storage unit includes: a TLC with 8 states or a QLC with 16 states.

[0141] The storage cells used in this disclosure can be MLC, TLC or QLC, especially suitable for TLC with 8 states or QLC with 16 states, and even suitable for storage cells with five or more levels.

[0142] like Figure 5 As shown, this disclosure also provides a memory 700, the memory comprising:

[0143] The storage cell array 701 includes multiple storage cells;

[0144] Peripheral circuitry 702, coupled to the memory cell array, is configured as follows:

[0145] Each memory cell to be programmed is first programmed, so that each memory cell is programmed to N different first programming states; where N is a positive integer greater than 1 and less than M, and M is the total number of target programming states of the memory cell to be programmed;

[0146] The storage units of the first programming state in the i-th group are second-programmed, so that the storage units of the first programming state in the i-th group are programmed into k target programming states; wherein, the number of target programming states k obtained after the second programming of the storage units of at least two groups of the first programming states is different; k is greater than or equal to 1 and less than N; i is greater than or equal to 1 and less than or equal to N.

[0147] In some embodiments, the memory may be a non-volatile memory product such as a NAND chip.

[0148] In some embodiments, the peripheral circuit 702 is further configured to: after performing the first programming, perform a first verification on each memory cell based on a first verification voltage of the first programming state; wherein the first verification is used to determine whether each memory cell has been programmed to the corresponding first programming state.

[0149] In some embodiments, the peripheral circuit 702 is further configured to: after the second programming, perform a second verification on each memory cell based on a second verification voltage of each target programming state; wherein the second verification is used to determine whether each memory cell has been programmed to the target programming state; the k of the i-th group of the first programming statesi The second verification voltage is different for each target programming state.

[0150] In some embodiments, the storage unit includes: a TLC with 8 states or a QLC with 16 states.

[0151] like Figure 6 As shown, this disclosure provides a memory system 800, which includes:

[0152] The memory device 700 as described in the above embodiments; and the memory controller 801 coupled to the memory device 700 and configured to control the memory device 700.

[0153] In some embodiments, the memory system 800 may be a product such as an SSD, or an electronic device including a memory device 700, such as a computer device.

[0154] This disclosure also provides the following examples:

[0155] Taking QLC NAND flash memory cell as an example, QLC NAND has 16 states, of which p0 is the erase state and p1 to p15 are the programming states.

[0156] Use silicon testing to obtain the coupling offset between the 16 states (or 15 programmed states) of the QLC NAND.

[0157] Then, the coupling offset is divided into ranges, and multiple adjacent target programming states whose coupling offsets are within a preset range are identified as the same group. The preset range division rule can be to divide the coupling offsets into N groups as evenly as possible, or to divide the group with low threshold voltage into lower coupling offsets and the group with high threshold voltage into higher coupling offsets. The preset range division can also be other user-defined rules.

[0158] In one embodiment, the units to be programmed are divided into nine groups according to the target programming states p1 to p15 (memory units in the erase state do not need to be programmed, so they are not grouped), as shown in Table 4: the memory units to be programmed are divided into nine groups according to the target programming states. The first group includes p1, p2 and p3, the second group includes p4 and p5, the third group includes p6 and p7, the fourth group includes p8 and p9, the fifth group includes p10 and p11, the sixth group includes p12, the seventh group includes p13, the eighth group includes p14, and the ninth group includes p15.

[0159] After dividing the memory cells into 9 groups, the first programming is performed on the memory cells to be programmed. The target programming states of the first group are p1, p2, and p3. The corresponding memory cells to be programmed will be programmed to the first programming state P1 after the first programming. That is, p1 is programmed to the first programming state P1, p2 is also programmed to the first programming state P1, and p3 is also programmed to the first programming state P1. It can be understood that p1, p2, and p3 are all programmed to the same first programming state P1, so the verification voltage used for p1, p2, and p3 is also the same. That is, the verification voltage used for the memory cells to be programmed within the same group is the same in the first programming. Furthermore, the threshold voltage of the first programming state P1 is lower than the threshold voltages of the target programming states p1, p2, and p3. Compared to the 16-16 two-pass programming scheme, the time required to program to the P1 state with the same initial voltage is less than programming to a threshold voltage slightly lower than p1, less than programming to a threshold voltage slightly lower than p2, and much less than programming to a threshold voltage slightly lower than p3. Therefore, programming from the first state to P1 can save programming time compared to fuzzy-fine programming of 16-16.

[0160] The programming method for the remaining groups is the same as that for the first group, and so on. In each group, the storage unit to be programmed is first programmed to the first programming state.

[0161] Then, the memory cells with the first programming states P1 to P9 are programmed a second time. The second programming changes the first programming state P1 to the target programming states p1, p2, and p3, respectively. This process is repeated until all the first programming states are programmed to the target programming states. After the second programming, the Gray code mapping between the threshold voltage of the memory cell and the logic page can still use balanced Gray code, ensuring a uniform read margin for each page and preventing an excessively narrow read margin on any page, which could easily lead to an increased failure bit count.

[0162]

[0163] Table 4

[0164] In another embodiment, the units to be programmed are divided into 5 groups according to the target programming states p1 to p15 (the memory units in the target erasure state do not need to be programmed, so they are not grouped), as shown in Table 5: the memory units to be programmed are divided into five groups according to the target programming states. The first group includes p1, p2, p3 and p4, the second group includes p5, p6, p7 and p8, the third group includes p9, p10 and p11, the fourth group includes p12 and p13, and the fifth group includes p14 and p15.

[0165] After dividing the memory cells into 5 groups, the first programming is performed on the cells to be programmed. The target programming states for the first group are p1, p2, p3, and p4. The corresponding memory cells to be programmed will all be programmed to the first programming state P1 after the first programming. That is, p1 is programmed to the first programming state P1, p2 is also programmed to the first programming state P1, p3 is also programmed to the first programming state P1, and p4 is also programmed to the first programming state P1. It can be understood that p1, p2, p3, and p4 are all programmed to the same first programming state P1, so the verification voltage used for p1, p2, p3, and p4 is also the same, and the threshold voltage of the first programming state P1 is lower than the threshold voltage of the target programming states p1, p2, p3, and p4. Compared with the programming scheme of 16-16 traversal, the time required to program to the P1 state with the same initial voltage is less than programming to a threshold voltage slightly lower than p1, and even less than programming to a threshold voltage slightly lower than p2, slightly lower than p3, and slightly lower than p4. Therefore, programming from the first state to P1 can save programming time compared to fuzzy-fine programming of 16-16.

[0166] The programming method for the remaining groups is the same as that for the first group, and so on. In each group, the storage unit to be programmed is first programmed to the first programming state.

[0167] Then, the memory cells with the first programming states P1 to P5 are programmed a second time. This second programming reprograms the first programming state P1 to the target programming states p1, p2, p3, and p4, respectively. This process continues until all the first programming states have been programmed to the target programming states. After the second programming, the Gray code mapping between the threshold voltage of the memory cell and the logic page can still use balanced Gray code, ensuring a uniform read margin for each page and preventing excessively narrow read margins on any particular page, which could easily lead to an increased failure bit count.

[0168]

[0169] Table 5

[0170] The embodiments disclosed herein may have one or more of the following beneficial effects:

[0171] 1. The embodiments of this disclosure save time in the first programming pass by programming multiple target programming states into one state in the first programming.

[0172] 2. The embodiments of this disclosure can use balanced Gray code to map to the target threshold voltage, which gives it a better read margin than the two programming schemes of 8-16, making the read operation more accurate.

[0173] 3. The embodiments of this disclosure can also use the Gray code used in the two-programming scheme of 8-16, and the read margin obtained is the same as that of the two-programming scheme of 8-16.

[0174] 4. The embodiments disclosed herein do not require users to remap Gray codes and can be used directly.

[0175] 5. All the necessary operations in the embodiments of this disclosure can be completed within the NAND die, without the need for any additional operations outside the NAND die.

[0176] It should be understood that the phrases "some embodiments," "one embodiment," or "an embodiment" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0177] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0178] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for programming a memory, characterized in that, The method includes: Each memory cell to be programmed is first programmed, so that each memory cell is programmed to N different first programming states; where N is a positive integer greater than 1 and less than M, and M is the total number of target programming states of the memory cell to be programmed; The storage units of the first programming state in the i-th group are second-programmed, so that the storage units of the first programming state in the i-th group are programmed into k target programming states; wherein, the number of target programming states k obtained after the second programming of the storage units of at least two groups of the first programming states is different; k is greater than or equal to 1 and less than N; i is greater than or equal to 1 and less than or equal to N; The encoded data of the N different first programming states are non-Gray codes, and the encoded data of the k target programming states are balanced Gray codes.

2. The method according to claim 1, characterized in that, The first programming corresponds to N groups; the N groups are determined according to the coupling offset of each target programming state in the programming process, and each group corresponds to k target programming states.

3. The method according to claim 2, characterized in that, The first programming of each memory unit to be programmed, so that each memory unit is programmed to N different first programming states, includes: According to the grouping, each storage unit is first programmed, so that each storage unit is programmed to the first programming state corresponding to the N groups.

4. The method according to claim 3, characterized in that, Multiple adjacent target programming states whose coupling offsets are within a preset range are identified as the same group.

5. The method according to claim 4, characterized in that, Multiple adjacent target programming states whose coupling offsets are within a preset range are identified as the same group, including at least one of the following: The multiple adjacent target programming states whose coupling offset is less than a first preset threshold are determined as the first group; The multiple adjacent target programming states whose coupling offset is greater than or equal to the first preset threshold and less than the second preset threshold are determined as the second group; The multiple adjacent target programming states whose coupling offset is greater than or equal to the second preset threshold are determined as the third group.

6. The method according to claim 2, characterized in that, The coupling offset of each target programming state during the programming process is obtained by performing coupling offset tests on each memory cell on adjacent word lines for each target programming state.

7. The method according to any one of claims 1 to 6, characterized in that, The method further includes: After the first programming is performed, each memory cell is first verified based on the first verification voltage of the first programming state; wherein, the first verification is used to determine whether each memory cell has been programmed to the corresponding first programming state.

8. The method according to claim 7, characterized in that, The first programming of each memory unit to be programmed, so that each memory unit is programmed to N different first programming states, includes: Perform the first programming multiple times on each memory unit to be programmed; Specifically, after each first programming, the first verification result corresponding to each first programming state is used to determine whether to perform the first programming again; If the verification result indicates that the verification of the first programming state is successful, then the first programming is stopped; If the verification result indicates that the verification of the first programming state fails, the first programming continues until each memory unit is programmed to N different first programming states.

9. The method according to claim 8, characterized in that, The N different first programming states each have a corresponding N different first verification voltages.

10. The method according to claim 7, characterized in that, The method further includes: After the second programming, each memory cell is second verified based on the second verification voltage of each target programming state; wherein, the second verification is used to determine whether each memory cell has been programmed to the target programming state; the second verification voltages corresponding to the k target programming states of the i-th group of the first programming states are different.

11. The method according to claim 10, characterized in that, The first verification voltage corresponding to the first programming state in the i-th group is less than any second verification voltage of any of the k target programming states after the second programming.

12. The method according to claim 1, characterized in that, The storage unit includes: a three-level storage unit (TLC) with 8 states or a four-level storage unit (QLC) with 16 states.

13. A memory device, characterized in that, include: A storage cell array, comprising multiple storage cells; The peripheral circuitry, coupled to the memory cell array, is configured to: perform a first programming on each memory cell to be programmed, such that each memory cell is programmed into N different first programming states; where N is a positive integer greater than 1 and less than M, and M is the total number of target programming states of the memory cell to be programmed. The storage units of the first programming state in the i-th group are second-programmed, so that the storage units of the first programming state in the i-th group are programmed into k target programming states; wherein, the number of target programming states k obtained after the second programming of the storage units of at least two groups of the first programming states is different; k is greater than or equal to 1 and less than N; i is greater than or equal to 1 and less than or equal to N; The encoded data of the N different first programming states are non-Gray codes, and the encoded data of the k target programming states are balanced Gray codes.

14. The memory device according to claim 13, characterized in that, The peripheral circuit is also configured to: After the first programming is performed, each memory cell is first verified based on the first verification voltage of the first programming state; wherein, the first verification is used to determine whether each memory cell has been programmed to the corresponding first programming state.

15. The memory device according to claim 13, characterized in that, The peripheral circuit is further configured to: after the second programming, perform a second verification on each memory cell based on a second verification voltage of each target programming state; wherein the second verification is used to determine whether each memory cell has been programmed to the target programming state; the second verification voltages corresponding to the k target programming states of the i-th group of the first programming states are different.

16. The memory device according to claim 13, characterized in that, The storage unit includes: a TLC with 8 states or a QLC with 16 states.

17. A memory system, characterized in that, The memory system includes: One or more memory devices as described in any one of claims 13 to 16; and A memory controller coupled to the memory device and configured to control the memory device.

Images