Multi-step prefetching for write operations in memory devices

Abstract

This invention provides systems, methods, and apparatus related to multi-step prefetching for write operations in memory devices. In one method, the memory device has a memory array comprising memory cells. Before performing a write operation on a memory cell, a controller of the memory device applies multiple prefetch voltages to the memory cells. The controller applies a first prefetch voltage to determine which memory cells have a sensed current exceeding a threshold. In response to determining that the percentage of memory cells exceeding the threshold is too low (e.g., below a fixed limit), the controller determines to apply a second prefetch voltage to the memory cells. The magnitude of the second prefetch voltage is greater than the magnitude of the first prefetch voltage, and the second prefetch voltage can be applied to ensure greater reliability in appropriately determining the current programming state of the memory cells. The controller then appropriately applies a write voltage to the memory cells based on the target logic state of each memory cell and the programming mode to be used by the controller.

Description

Technical Field

[0001] At least some of the embodiments disclosed herein relate generally to memory devices, and more specifically to, but not limited to, memory devices that apply a plurality of read-ahead voltages to memory cells when performing a write operation. Background Technology

[0002] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming different states of the memory device. For example, a binary device has two states, typically represented by logic "1" or logic "0". In other systems, more than two states can be stored. To retrieve the stored information, components of the electronic device can read or sense the stored states in the memory device. To store information, components of the electronic device can write or program states into the memory device.

[0003] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, and phase-change memory (PCM). Memory devices can be volatile or non-volatile. Non-volatile memory cells can maintain their stored logic state for a long time, even without external power. Volatile memory cells may lose their stored state over time unless periodically refreshed by an external power source.

[0004] A storage device is an example of a memory device. A typical computer storage device has a controller that receives data access requests from a host computer and performs programmed computational tasks to fulfill those requests, in a manner that may be specifically tailored to the media and structure configured in the storage device. In one example, the memory controller manages the data stored in the memory and communicates with the computer device. In some examples, the memory controller is used in solid-state drives used in mobile devices or laptops, or in media used in digital cameras.

[0005] Firmware can be used to operate the memory controller of a specific storage device. In one instance, a computer system or device communicates with the memory controller when reading data from or writing data to the memory device.

[0006] Memory devices typically store data in memory cells. In some cases, memory cells exhibit non-uniform, variable electrical characteristics that may arise from a variety of factors, including statistical process variations, cyclic events (e.g., read or write operations on memory cells), or drift (e.g., resistance variations in chalcogenide alloys).

[0007] In one instance, reading a set of data (e.g., codewords, pages) is performed by determining the read voltage (e.g., the median of estimated threshold voltages) of the memory cell storing said set of data. In some cases, the memory device may comprise an array of PCM cells arranged in a 3D architecture, such as a crosspoint architecture, to store said set of data. A PCM cell in a crosspoint architecture may represent a first logic state (e.g., logic 1, set state) associated with a first set of threshold voltages or a second logic state (e.g., logic 0, reset state) associated with a second set of threshold voltages. In some cases, encoding (e.g., error-correcting coding (ECC)) may be used to store data to recover data from errors in the data stored in the memory cell.

[0008] For variable resistance memory cells (e.g., PCM cells), one of multiple states (e.g., resistance states) can be configured. For example, a single-level cell (SLC) can be programmed to be one of two states (e.g., logic 1 or 0), depending on whether the cell is programmed to have a resistance higher or lower than a certain level. As another example, various variable resistance memory cells can be programmed to be one of multiple different states corresponding to multiple data states, such as 10, 01, 00, 11, 111, 101, 100, 1010, 1111, 0101, 0001, etc. Such cells can be referred to as multi-state cells, multi-digit cells, and / or multi-level cells (MLCs).

[0009] The state of a variable-resistance memory cell can be determined (e.g., read) by sensing the current through the cell in response to an applied query voltage. The sensed current, which varies based on the cell's resistance, can indicate the cell's state (e.g., the binary data stored by the cell). The resistance of a programmed variable-resistance memory cell can drift (e.g., shift) over time. Resistance drift can lead to sensing errors in the variable-resistance memory cell (e.g., determining that the cell is in a state different from its programmed state, and other problems).

[0010] For example, a PCM cell can be programmed into a reset state (amorphous state) or a set state (crystalline state). A reset pulse (e.g., a pulse used to program the cell into a reset state) can contain a relatively high current pulse applied to the cell over a relatively short period of time, causing the phase change material of the cell to melt and cool rapidly, resulting in relatively little crystallization. Conversely, a set pulse (e.g., a pulse used to program the cell into a set state) can contain a relatively low current pulse applied to the cell over a relatively long period of time with a slower quenching rate, which increases the crystallization of the phase change material.

[0011] A programming signal can be applied to a selected memory cell to program the cell to a target state. A read signal can be applied to a selected memory cell to read the cell (e.g., to determine the state of the cell). For example, the programming signal and the read signal can be current and / or voltage pulses. Summary of the Invention

[0012] According to one aspect of this application, a system is provided. The system includes: a memory array comprising memory cells; and a controller configured to: apply a first prefetch voltage to the memory cells; sense a corresponding first current generated by the application of the first prefetch voltage in each memory cell; determine a first portion and a second portion of the memory cells, wherein for the first portion, the corresponding first current exceeds the first threshold, and for the second portion, the corresponding first current does not exceed the first threshold; determine that the first portion of the memory cells is less than a threshold number; and in response to determining that the first portion of the memory cells is less than the threshold number: apply a second prefetch voltage to the second portion of the memory cells, wherein the magnitude of the second prefetch voltage is greater than the magnitude of the first prefetch voltage; sense a corresponding second current generated by the application of the second prefetch voltage in each memory cell in the second portion; and determine a third portion of the memory cells, wherein the corresponding second current exceeds the second threshold for the third portion.

[0013] According to another aspect of this application, a method is provided. The method includes: applying a first read voltage to memory cells of a memory array; sensing a corresponding first current generated by the application of the first read voltage in each memory cell; determining a first portion and a second portion of the memory cells, wherein for the first portion, the corresponding first current exceeds the first threshold, and for the second portion, the corresponding first current does not exceed the first threshold; determining whether the first portion of the memory cells is less than a threshold number; and in response to determining that the first portion of the memory cells is less than the threshold number: applying a second read voltage to the second portion of the memory cells, wherein the magnitude of the second read voltage is greater than the magnitude of the first read voltage; sensing a corresponding second current generated by the application of the second read voltage in each memory cell of the second portion; and determining a third portion of the memory cells, wherein the corresponding second current exceeds the second threshold for the third portion.

[0014] According to another aspect of this application, a non-transitory computer-readable medium is provided. The non-transitory computer-readable medium stores instructions, which, when executed on at least one processing device, cause the at least one processing device to: apply a first read voltage to memory cells of a memory array, wherein each memory cell includes a chalcogenide; sense a corresponding first current generated by the application of the first read voltage in each memory cell; determine a first portion and a second portion of the memory cell, wherein for the first portion, the corresponding first current exceeds a threshold, and for the second portion, the corresponding first current does not exceed the threshold; determine whether the first portion of the memory cell is less than a threshold number; and in response to determining that the first portion of the memory cell is less than the threshold number: apply a second read voltage to the second portion of the memory cell, wherein the magnitude of the second read voltage is greater than the magnitude of the first read voltage; sense a corresponding second current generated by the application of the second read voltage in each memory cell of the second portion; and determine a third portion of the memory cell, wherein the corresponding second current exceeds a threshold. Attached Figure Description

[0015] The embodiments are illustrated by way of example rather than limitation in the accompanying drawings, in which similar reference numerals indicate similar elements.

[0016] Figure 1 A memory device is shown that applies multiple read-ahead voltages to memory cells of a memory array during a write operation, according to some embodiments.

[0017] Figure 2A diagram illustrating the multi-step read-ahead voltage applied to a memory cell during a write operation, according to some embodiments, is shown.

[0018] Figure 3 An example is shown, according to some embodiments, of determining the programming state of a memory cell by applying multiple read-ahead voltages to the memory cell during a write operation.

[0019] Figure 4 An example of a memory cell including a selection device according to some embodiments is shown.

[0020] Figure 5 A method for determining the current programming state of a memory cell by applying multiple read-ahead voltages, according to some embodiments, is shown.

[0021] Figure 6 A method for applying a write voltage to a memory cell based on the programming state of the memory cell, according to some embodiments, is shown. Detailed Implementation

[0022] The following disclosure describes various embodiments of a memory device that applies multiple read-ahead voltages to memory cells during a write operation. At least some of the embodiments herein relate to memory devices using bipolar operation on a memory array. In one example, a bipolar selection voltage is used to select memory cells of the memory array. In one example, the memory cells are arranged in a crosspoint architecture. In one example, each memory cell is formed using a single selection device. In one example, the selection device comprises a chalcogenide material.

[0023] Memory devices can, for example, store data used by a host device (e.g., a computing device in an autonomous vehicle, or another computing device that accesses data stored in the memory device). In one example, the memory device is a solid-state drive installed in an electric vehicle.

[0024] In some cases, a memory device may include an array of memory cells arranged in a 3D architecture, such as a crosspoint architecture, to store a set of data. Memory cells in a crosspoint architecture may represent a first logic state (e.g., logic 1, set state) associated with a first set of threshold voltages or a second logic state (e.g., logic 0, reset state) associated with a second set of threshold voltages.

[0025] In some memory devices, a single read-ahead voltage is applied to a memory cell before programming it. For example, a memory device may have memory cells that each contain a chalcogenide as a logic storage element. The read-ahead voltage is negative, and the corresponding write voltage is positive. As part of the programming operation, the read-ahead voltage is applied in a single step to each memory cell in the memory array before the write voltage is applied in a subsequent step to program the memory cell.

[0026] When chalcogenides are used as logic memory elements as in the examples above, the voltage requirements for read-ahead and write voltages are related. A negative read-ahead voltage is applied to determine the number of triggered bits (e.g., memory cells with sensed current exceeding a predetermined threshold) in a negative read-ahead polarity 'set' distribution. The 'set' distribution corresponds to a positive write polarity reset distribution. For example, a high threshold voltage for a positive polarity memory cell corresponds to a low threshold voltage for a negative polarity memory cell. Similarly, a low threshold voltage for a positive polarity memory cell corresponds to a high threshold voltage for a negative polarity memory cell.

[0027] Using a larger preflight voltage reduces the amount of write voltage required to program memory cells. However, using a larger preflight voltage causes the memory device to consume more power. Furthermore, using a larger preflight voltage can incorrectly trigger a larger proportion of memory cells in the memory array (e.g., bits in a block of the memory array). In one instance, using a larger preflight voltage can incorrectly trigger bits in a reset 'distribution' with negative preflight polarity. The reset 'distribution' corresponds to a set distribution with positive write polarity.

[0028] Using higher read-ahead voltages can significantly degrade the durability and performance of memory devices due to excessive energy consumption and / or lower durability caused by higher voltage cycling of memory cells, potentially leading to memory device malfunction. Consequently, systems using data from the memory device may fail. For example, a vehicle using the data to control a vehicle may be involved in a collision, resulting in physical damage or personal injury.

[0029] To address these and other technical issues, the memory device determines in real time when to apply multiple read-ahead voltages to the memory cells during a write operation. In one example, a first read-ahead voltage and a second read-ahead voltage are applied before the memory cells are programmed. In another example, three or more read-ahead voltages may be applied (e.g., to a selected portion of the memory cell to which the first and second read-ahead voltages are applied, such that the portion of the memory cell is selected based on the result of applying the first and second read-ahead voltages and / or based on the operating environment of the memory device determined in real time by the controller during operation).

[0030] In one embodiment, a first read-ahead voltage is applied. The memory controller determines the percentage of memory cells whose sensed current exceeds a threshold (e.g., the percentage of cells that have “snap”). If the percentage is low (e.g., five percent or less), a second read-ahead voltage is applied to those memory cells that have not yet snapped. The magnitude of the second read-ahead voltage is greater than the magnitude of the first read-ahead voltage (e.g., 100-500 mV). The controller then identifies additional memory cells that snap due to the application of the second read-ahead voltage.

[0031] In one instance, the controller uses one or more counters to count the number of cells that crash for each applied read-ahead voltage. The controller also determines and stores the existing programming state of each memory cell at the time of its crash. The controller uses the data stored by the crash counters to decide whether to apply an additional read-ahead voltage step. In one instance, the counter data is the input to an artificial neural network (ANN), whose output is used to determine whether to apply a read-ahead voltage and, if so, what form. Another input to the ANN is data about the operating history and / or operating environment of the memory array and / or memory device.

[0032] Next, the memory cell is appropriately programmed based on the programming mode to be implemented, the cell's existing programming state (e.g., determined by whether the cell has crashed), and / or the target programming state (e.g., corresponding to write commands and data received from the host device). In one instance, the programming mode is normal write mode. In another instance, the programming mode is forced write mode.

[0033] In one instance, a codeword is read from a memory array. Typically, the codeword is fully read using a single read-ahead voltage. For example, 50% of the memory cells corresponding to the codeword may fail. No further read-ahead voltage is applied, and the memory cells are then programmed.

[0034] In some cases, codewords are stored in a portion of the memory array where the memory cells suffer from high drift and / or significant interference (e.g., read interference due to reading adjacent memory cells). In this case, the percentage of crashed cells may be low (e.g., less than 5-10%), and the aforementioned second read-ahead voltage is applied before programming to perform a read-ahead of the cells.

[0035] In one embodiment, the memory device has a memory array comprising memory cells. The memory controller of the memory device is configured to: apply a first read-ahead voltage (e.g., -2.5V) to the memory cells; sense a corresponding first current generated by the application of the first read-ahead voltage in each memory cell; determine a first portion (e.g., collapsed cells) and a second portion (e.g., non-collapsed cells) of the memory cells, wherein for the first portion, the corresponding first current exceeds the first threshold, and for the second portion, the corresponding first current does not exceed the first threshold; and determine that the first portion of the memory cells is less than a threshold number (e.g., less than 5-10% of the total number of memory cells have collapsed).

[0036] In response to determining that the first portion of the memory cells is less than the threshold number, the memory controller is further configured to: apply a second prefetch voltage (e.g., negative 2.8V) to the second portion of the memory cells, wherein the second prefetch voltage has the same polarity as the first prefetch voltage and the magnitude of the second prefetch voltage is greater than the magnitude of the first prefetch voltage; sense a corresponding second current generated by the application of the second prefetch voltage in each memory cell in the second portion; and determine a third portion of the memory cells for which the corresponding second current exceeds a second threshold (e.g., an additional 45% of the total number of memory cells crashes).

[0037] In one example, each memory cell contains a chalcogenide as part of a select device (SD). In another example, each memory cell further includes a top electrode (e.g., carbon) above the chalcogenide and a bottom electrode (e.g., carbon) below the chalcogenide.

[0038] The various embodiments of memory devices described herein that apply multiple read-ahead voltages to memory cells during write operations offer advantages including one or more of the following: power consumption of the memory device can be reduced. As part of a write operation, the memory controller can dynamically customize the number and / or magnitude of the read-ahead voltages applied to the memory cells. Bit-line write voltages can be reduced. The durability of the memory device can be increased (e.g., due to lower voltage cycling of the memory cells).

[0039] Figure 1A memory device 101 is illustrated according to some embodiments, which applies multiple read-ahead voltages to memory cells 110, 112 of a memory array 102 during write operations. The memory device 101 has a memory controller 120 for applying the read-ahead voltages. The memory controller 120 includes one or more processing devices 116 and a memory 118. In one example, the memory 118 stores firmware executed by the processing device 116 to apply the read-ahead voltages.

[0040] The memory controller 120 may use the bias circuitry 124 to generate a voltage for applying a pre-read voltage. The bias circuitry 124 may also generate a voltage for applying a write voltage to memory cells 110, 112 as part of a programming operation. The bias circuitry 124 may further be used to generate a read voltage for read operations performed on the memory array 102 (e.g., in response to a read command from the host device 126).

[0041] Memory device 101 includes a sensing circuitry system 122 for sensing the state of each memory cell in memory array 102. In one example, the sensing circuitry system 122 includes a sensing amplifier for detecting current caused by various voltages applied to the memory cells in memory array 102. In one example, a biasing circuitry system 124 applies a pre-read voltage to memory cell 110. The sensing circuitry system 122 senses the current associated with each memory cell in memory cell 110 due to the applied pre-read voltage. In one example, the pre-read voltage is applied as described above.

[0042] In one instance, as discussed above, if the sensing circuitry 122 determines that the current in a memory cell is greater than a fixed threshold (e.g., a predetermined current level), the memory controller 120 determines that the memory cell has crashed.

[0043] In one embodiment, memory cells 110 and 112 correspond to different memory types (e.g., single-level cells or three-level cells). In one example, the materials used to form the selection means for each memory cell are different. The read-ahead voltage applied to memory cell 110 corresponds to the material used to form memory cell 110. The read-ahead voltage applied to memory cell 112 is different and corresponds to the material used to form memory cell 112.

[0044] In one embodiment, controller 120 determines the pre-read voltage to be applied to the memory cells in memory array 102 based on the physical location of the memory cells in memory array 102. In one instance, the physical location is the distance from the row and / or column decoders (e.g., stored in a lookup table in memory 118). In another instance, the physical location corresponds to an increase in the degree of drift or interference (e.g., as determined based on sensor or other data during manufacturing testing and / or operation).

[0045] In one embodiment, controller 120 determines the pre-read voltage to be applied to the memory cells of memory array 102 based on the voltage bias level previously applied to a particular memory cell in memory array 102.

[0046] In one embodiment, memory controller 120 receives a write command from host device 126. The write command is accompanied by data to be written to memory array 102 (e.g., user data of a user of host device 126). In response to receiving the write command, controller 120 initiates a programming operation by applying a first read-ahead voltage to memory cells 110. Controller 120 determines the number of memory cells 110 that have crashed. Controller 120 uses this number to determine the percentage of crashed memory cells 110. If the percentage is less than a fixed threshold, controller 120 applies a second read-ahead voltage to those memory cells 110 that did not crash when the first read-ahead voltage was applied. In one embodiment, controller 120 uses one of counters 104 to count the number of memory cells that crashed when each read-ahead voltage was applied.

[0047] Next, controller 120 determines a specific cell of memory cell 110, for which a write voltage is applied to program the memory cell. In one embodiment, controller 120 determines whether the existing programming state (e.g., logic state zero) and the target programming state (e.g., logic state zero) of each cell are equal. If the existing programming state and the target programming state are equal, no write voltage is applied (e.g., normal write mode). If the existing programming state and the target programming state are different, a write voltage is applied to the specific memory cell. In one example, the write voltage applied across the cell by applying voltage bias to the word line and bit line used to select the memory cell is 3-8 volts. In one example, in the case of a chalcogenide memory cell, a write voltage of a first polarity is applied to program the cell to a first logic state (e.g., a set state), and a write voltage of a second opposite polarity is applied to program the cell to a second different logic state (e.g., a reset state).

[0048] In one embodiment, the second read-ahead voltage is applied only to those memory cells that have not crashed after the first read-ahead voltage is applied. In other embodiments, the second read-ahead voltage may be applied to all memory cells, regardless of whether the memory cells have crashed (e.g., a threshold is set above a fixed current limit).

[0049] In one embodiment, a forced write operation is performed, wherein a specific memory cell is programmed to a target programmed state regardless of whether the memory cell has crashed. In one instance, the forced write is performed in response to controller 120 determining that the percentage of memory cells that crashed due to the application of a first read-ahead voltage is below a fixed threshold number (e.g., less than 5% of the cells or less than a fixed cell count). In one instance, the forced write is performed on all memory cells to which the first read-ahead voltage was applied. In one instance, the forced write is performed only on those memory cells that did not crash before a higher second read-ahead voltage was applied. In one instance, the forced write is performed to make the memory cells more robust in their ability to reliably store the target logic state.

[0050] In one example, during a write operation, controller 120 may use a write voltage (e.g., a write pulse) to write logic state to memory cells, such as memory cells 110, 112. The write pulse can be applied by providing a first voltage to a bit line used to select the memory cell and a second voltage to a word line used to select the memory cell. Circuitry coupled to access lines that may be coupled to the memory cell can be used to provide the write voltage (e.g., access line drivers included in decoder circuitry). This circuitry may be controlled by internal control signals provided by control logic (e.g., controller 120). The resulting voltage applied to the memory cell is the difference between the first voltage and the second voltage. In some embodiments, the duration of the write pulse may be the same as the duration of the read pulse. In some embodiments, the duration is 10-50 nanoseconds. In some embodiments, the duration is 1-100 nanoseconds. In some embodiments, the duration is 1 nanosecond to 1 microsecond. In some embodiments, the time spent writing to the memory cell may be the same as the time spent reading from the memory cell.

[0051] In one instance, the polarity of the write pulse can be either a first polarity or a second polarity (e.g., positive or negative). For example, the write pulse can apply a voltage to the memory cell with the first polarity (e.g., 6V for the bit line and 0V for the word line).

[0052] In one example, circuitry coupled to an access line to which the memory cell may be coupled is used to provide a read pulse (e.g., an access line driver included in decoder circuitry). This circuitry may be controlled by internal control signals provided by control logic (e.g., controller 120). The read voltage or pulse may be a voltage applied to the memory cell over a period of time (e.g., 10-50 nanoseconds, 1-100 nanoseconds, 1 nanosecond to 1 microsecond). In some embodiments, the read pulse may be a rectangular pulse. In some embodiments, the read pulse may be a ramp, i.e., a linearly increasing voltage may be applied across the memory cell.

[0053] In one instance, for a chalcogenide memory cell, the read voltage is always applied with the same fixed polarity. In another instance, the read voltage has the same polarity, and the read voltage has the opposite polarity to the read voltage.

[0054] In one example, after being accessed (e.g., selected), a memory cell can be read or sensed by a sensing component (e.g., sensing circuitry 122) to determine the stored state of the memory cell. For example, a voltage can be applied to the memory cell (using word lines and bit lines), and the presence of the resulting current can depend on the applied voltage and the threshold voltage of the memory cell. In some cases, more than one voltage can be applied. Additionally, if the applied voltage does not produce current, other voltages can be applied until the sensing component detects current. By evaluating the voltage that produces the current, the stored logic state of the memory cell can be determined. In some cases, the magnitude of the voltage can ramp up until current is detected (e.g., the memory cell is turned on, switched on, conducts, or becomes active). In other cases, predetermined voltages can be applied sequentially until current is detected. Similarly, current can be applied to the memory cell, and the magnitude of the voltage that produces the current can depend on the resistance of the memory cell or its threshold voltage.

[0055] In some cases, memory cells (e.g., PCM cells) contain a material that changes its crystallographic configuration (e.g., between a crystalline phase and an amorphous phase), which in turn determines the threshold voltage of the memory cell for storing information. In other cases, memory cells contain a material that remains in a crystallographic configuration (e.g., an amorphous phase) that can exhibit a variable threshold voltage for storing information.

[0056] The sensing component can contain various transistors or amplifiers to detect and amplify differences in the signal. The detected logic state of the memory cell can then be output by a column decoder. In some cases, the sensing component can be part of a column decoder or a row decoder.

[0057] Figure 2A diagram illustrating multi-step read-ahead voltages applied to memory cells during a write operation, according to some embodiments, is shown. In one example, as discussed above for a write operation on memory array 102, a read-ahead voltage is applied to memory cells 110 or 112. In one example, the read-ahead voltage is generated by a bias circuitry system 124 controlled by controller 120. In one example, memory cell 110 is a single-level cell (SLC).

[0058] The vertical axis represents the prefetch voltage value, and the horizontal axis represents time. In one example, the prefetch voltage is the voltage difference applied across the cell from the word line and the bit line of the voltage bias used to select the memory cell.

[0059] The read-ahead voltage can be applied in multiple steps 202, 204, 206, etc., as needed. Each level of read-ahead voltage can be applied for different durations 212, 214. In one example, the durations 212, 214 range from 10 to 100 nanoseconds.

[0060] The voltage differences 208 and 210 between each step can vary. In one example, the voltage differences 208 and 210 range from 50 to 600 millivolts. In another example, the voltage differences 208 and 210 range from 100 to 300 millivolts.

[0061] In one embodiment, at time T1, after the pre-read voltage 202 is applied, counter 104 is used to determine the number of memory cells 110 that have crashed. Controller 120 determines whether to apply the pre-read voltage 204 based on counter 104.

[0062] As needed, the number of crashed memory cells 110 is similarly determined at times T2, T3, etc. The controller 120 uses the number of crashed memory cells 110, as determined by the counter 104, to determine whether to apply an additional read-ahead voltage step.

[0063] exist Figure 2 In the illustrated example, the prefetch voltages 202 and 204 have the same polarity (e.g., as used with an SLC memory cell). In other embodiments, the memory cell may be a multi-state cell, such as an MLC, TLC, etc. In one example, in the case of an MLC cell, the second prefetch voltage 204 has the opposite polarity to the first prefetch voltage 202.

[0064] In one instance, for an MLC memory cell, a crash counter determines that a first read-ahead voltage (negative or positive polarity) has not crashed a sufficient number of cells. Therefore, the controller determines to apply a second read-ahead voltage and determines that a sufficient number of cells have crashed. The controller then applies a third read-ahead voltage with the opposite polarity to the second read-ahead voltage. In another case, the crash counter determines that the second read-ahead voltage has not crashed a sufficient number of cells. Therefore, the controller applies a third read-ahead voltage with a magnitude greater than the second read-ahead voltage and the same polarity as the second read-ahead voltage. The controller then applies a fourth read-ahead voltage with the opposite polarity to the third read-ahead voltage.

[0065] Figure 3 Examples are shown, according to some embodiments, of determining the programming state of a memory cell by applying multiple read-ahead voltages to the memory cell during a write operation. In one example, the memory cell is memory cell 110, and the read-ahead voltages are implemented by memory controller 120.

[0066] As a non-limiting example for illustrative purposes only, a first read-ahead voltage is applied to a total of 100 memory cells. The current through each memory cell is sensed by a sensing amplifier. Memory cell 302 has a current exceeding a fixed threshold and is considered to have crashed. Memory cell 304 has a current below the fixed threshold and is considered not to have crashed.

[0067] In this example, only five memory cells have failed, which is only five percent of the total 100 memory cells. Based on this result, the memory controller determines to apply a second read-ahead voltage to the memory cells 304 that have not failed.

[0068] After the second read-ahead voltage is applied, memory cell 312 has a current exceeding a fixed threshold (e.g., a fixed current limit) and is considered to have crashed. Memory cell 314 has a current not exceeding the fixed threshold and is considered not to have crashed. In this example, after applying the first and second read-ahead voltages and sensing the current in each memory cell, memory cells 302 and 312 are considered to have crashed, while memory cell 314 is considered not to have crashed.

[0069] In this example, based on the determination made by the memory controller of those crashed cells, the memory controller determines that memory cells 302 and 312 are in a first logic state 306 and 311 (e.g., a reset state). The memory controller further determines, based on these results, that memory cell 314 is in a second logic state 315 (e.g., a set state).

[0070] In one embodiment, if the percentage of failed memory cells 312 is less than a fixed threshold percentage of memory cells 304 (e.g., only 3 out of 95 cells 304 fail), the memory controller may determine to apply a third read-ahead voltage, similar to what was discussed above regarding the application of a second read-ahead voltage. Additional read-ahead voltage steps may be applied similarly as needed. The threshold percentage may vary for determining whether to apply each subsequent voltage step.

[0071] After determining the existing programming state of each memory cell as discussed above, the memory controller determines the programming mode for programming the memory cell. In one embodiment, a normal write programming mode is used. In this mode, the controller determines the target state for each memory cell.

[0072] In one instance of normal write programming mode, memory cells 302 and 312 are in a reset state. For each such cell with target set states 310 and 318, a write voltage is applied to the memory cell. For each such cell with target reset states 308 and 316, no write voltage is applied to the cell.

[0073] For example, memory cell 314 is in setup state 315. For each such cell having a target reset state 320, a write voltage is applied to the cell. For each such cell having a target setup state 322, no write voltage is applied.

[0074] In one embodiment, the controller determines to implement a forced write programming mode. In this mode, each memory cell is selected and an appropriate programming write voltage is applied to the memory cell based on the target state. For example, even if memory cell 312 is already in the existing programming reset state 311, memory cell 312 is programmed to the target reset state 316.

[0075] Figure 4 An example of a memory cell 402 including a selection device 410 according to some embodiments is shown. In one example, the selection device 410 includes a chalcogenide. The memory cell 402 is an example of memory cells 110, 112.

[0076] The top electrode 408 electrically connects the selector 410 to the bit line 404, and the bottom electrode 412 electrically connects the selector 410 to the word line 406. In one example, electrodes 408 and 412 are formed of carbon material.

[0077] In one example, the selection device 410 comprises a chalcogenide (e.g., a chalcogenide material and / or a chalcogenide alloy). The threshold voltage nature of the selection device may be based on the voltage polarity applied to the memory cell.

[0078] In one example, a logic state can be written to memory cell 402, which may correspond to one or more bits of data. The logic state can be written to the memory cell by applying voltages of different polarities with different voltage and / or current values. The memory cell can be read by applying a unipolar voltage. The write and read protocols can utilize different threshold voltages caused by different polarities of the selection device. In one example, the memory cell may require short, relatively low-power pulses for reading. The chalcogenide material of the selection device may or may not undergo a phase transition during reading and / or writing. In some cases, the chalcogenide material may not be a phase-change material.

[0079] Figure 5 A method for determining the current programming state of a memory cell by applying multiple read-ahead voltages, according to some embodiments, is illustrated. For example, Figure 5 The method can be found in Figure 1 This is implemented in the system. In one example, when a write operation is performed, the memory controller 120 applies multiple read-ahead voltages to the memory cell 110.

[0080] Figure 5 The method can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, special-purpose logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, Figure 5 The method comprises at least in part one or more processing devices (e.g., Figure 1 The processing device 116) performs the operation.

[0081] Although shown in a specific sequence or order, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as merely examples, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0082] At block 501, a first prefetch voltage is applied to the memory cell. In one example, controller 120 applies a first prefetch voltage 202 to memory cell 110.

[0083] At block 503, current is sensed for each memory cell. In one example, sensing circuitry 122 senses the current for each memory cell 110.

[0084] At box 505, a first portion of the memory cell is identified, for which the current exceeds a threshold. A second portion of the memory cell is identified, for which the current is below a threshold. In one example, the first portion is memory cell 302, and the second portion is... Figure 3 Memory unit 304.

[0085] At box 507, it is determined whether the first portion is less than a threshold number. In one example, the first portion of memory cell 302 consists of five memory cells, which is only five percent of the total number of memory cells. The threshold number is a fixed value of seven percent, so controller 120 determines to apply a second pre-read voltage 204 to the second portion of memory cell 304. In one example, the threshold number is determined in real time by controller 120 based on the output of an artificial neural network. In one example, the input to the artificial neural network is data from counter 104 and / or data from sensors and / or other sensors of memory device 101. In one example, the sensors provide sensor data about the operating environment of memory device 101 and / or devices such as autonomous vehicles using memory device 101.

[0086] At block 509, a second prefetch voltage is applied to a second portion of the memory cells in response to determining that the first portion is less than a threshold number. In one example, controller 120 uses bias circuitry 124 to apply the second prefetch voltage to those memory cells 110 that did not crash when the first prefetch voltage was applied.

[0087] At block 511, current is sensed for each memory cell in the second section. In one example, the current is sensed by a sense amplifier of the sensing circuit system 122.

[0088] At block 513, a third portion of the memory cell is identified for which the current exceeds a threshold. In one example, the third portion is memory cell 312 that is determined to be in a crash state (e.g., determined by controller 120 to be in a reset state).

[0089] In one embodiment, a system includes: a memory array (e.g., 102) comprising memory cells; and a controller (e.g., 120) configured to: apply a first read-ahead voltage to the memory cells; sense a corresponding first current generated by applying the first read-ahead voltage in each memory cell; determine a first portion and a second portion of the memory cells, wherein for the first portion, the corresponding first current exceeds the first threshold, and for the second portion, the corresponding first current does not exceed the first threshold; and determine that the first portion of the memory cells is less than a threshold number.

[0090] In response to determining that the first portion of the memory cells is less than the threshold number, the controller is further configured to: apply a second prefetch voltage to the second portion of the memory cells, wherein the second prefetch voltage has the same polarity as the first prefetch voltage and the magnitude of the second prefetch voltage is greater than the magnitude of the first prefetch voltage; sense a corresponding second current generated by applying the second prefetch voltage in each memory cell in the second portion; and determine a third portion of the memory cells, for which the corresponding second current exceeds the second threshold.

[0091] In one embodiment, each memory cell contains a chalcogenide.

[0092] In one embodiment, each memory cell further includes a top carbon electrode located above the chalcogenide and a bottom carbon electrode located below the chalcogenide.

[0093] In one embodiment, a method includes: applying a first read voltage to memory cells of a memory array; sensing a corresponding first current generated by the application of the first read voltage in each memory cell; determining a first portion and a second portion of the memory cell, wherein for the first portion, the corresponding first current exceeds the first threshold, and for the second portion, the corresponding first current does not exceed the first threshold; and determining whether the first portion of the memory cell is less than a threshold number (e.g., less than 5-10% of the total number of cells to which the first read voltage is applied).

[0094] The method further includes, in response to determining that the first portion of the memory cell is less than the threshold number: applying a second read voltage to the second portion of the memory cell, wherein the magnitude of the second read voltage is greater than the magnitude of the first read voltage (e.g., at least 100 mV); sensing a corresponding second current generated by the applied second read voltage in each memory cell in the second portion; and determining a third portion of the memory cell for which the corresponding second current exceeds the second threshold.

[0095] In one embodiment, the threshold number is five percent of the total number of memory cells.

[0096] In one embodiment, the first read voltage is a first read-ahead voltage, the second read voltage is a second read-ahead voltage, the first read-ahead voltage and the second read-ahead voltage have the same polarity, and the magnitude of the second read-ahead voltage is at least 100 millivolts greater than the magnitude of the first read-ahead voltage.

[0097] In one embodiment, the method further includes: comparing an existing programming state (e.g., a reset state) of each memory cell in the memory cells with a target programming state (e.g., a set state) of the memory cells; determining a fourth portion of the memory cells to be programmed based on the comparison of the existing programming state with the target programming state for each memory cell; and applying a write voltage to the fourth portion of the memory cells, wherein the corresponding write voltage applied to each memory cell corresponds to the target programming state of the memory cells.

[0098] In one embodiment, when programmed to a first logic state, the write voltage applied to each memory cell has a first polarity, and when programmed to a second logic state, the write voltage has the opposite second polarity.

[0099] In one embodiment, the target programming state is a logical state corresponding to a write command received from a host device (e.g., 126).

[0100] In one embodiment, the method further includes reading the memory cells by applying a third read voltage to each memory cell in the memory array 102, wherein the third read voltage has a polarity opposite to that of the first read voltage and the second read voltage. In one example, the third read voltage is applied to a block of memory cells in the memory array 102 in response to receiving a read command from the host device 126.

[0101] In one embodiment, each memory cell includes a chalcogenide as a logic storage element, the existing programming state of the first portion and the third portion of the memory cell is a reset state, and the target programming state of at least a portion of the first portion and the third portion of the memory cell is a set state.

[0102] In one embodiment, the first threshold and the second threshold are equal (e.g., the first threshold and the second threshold are equal to a fixed current limit). In other embodiments, the thresholds may be different.

[0103] In one embodiment, a non-transitory computer-readable media storage instruction, when executed on at least one processing device, causes the at least one processing device to: apply a first read voltage to memory cells of a memory array, wherein each memory cell contains a chalcogenide; sense a corresponding first current generated by the application of the first read voltage in each memory cell; determine a first portion and a second portion of the memory cell, wherein for the first portion, the corresponding first current exceeds a threshold, and for the second portion, the corresponding first current does not exceed the threshold; and determine whether the first portion of the memory cell is less than a threshold number. The instruction further causes the processing device, in response to determining that the first portion of the memory cell is less than the threshold number, to: apply a second read voltage to the second portion of the memory cell, wherein the magnitude of the second read voltage is greater than the magnitude of the first read voltage; sense a corresponding second current generated by the application of the second read voltage in each memory cell of the second portion; and determine a third portion of the memory cell, wherein for the third portion, the corresponding second current exceeds a threshold.

[0104] In one embodiment, the instructions further cause the at least one processing device to: apply a write voltage to at least a portion of the third portion of the memory cell; and after applying the write voltage, use a third read voltage to read the third portion of the memory cell, wherein the third read voltage has a polarity opposite to the first read voltage and the second read voltage.

[0105] Figure 6 A method for applying a write voltage to a memory cell based on the programming state of the memory cell, according to some embodiments, is illustrated. For example, Figure 6 The method can be found in Figure 1 This is implemented in the system. In one example, the memory controller 120 causes the bias circuitry 124 to apply a write voltage to the memory cell 110.

[0106] Figure 6 The method can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, special-purpose logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, Figure 6 The method comprises at least in part one or more processing devices (e.g., Figure 1 The processing device 116) performs the operation.

[0107] Although shown in a specific sequence or order, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as merely examples, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0108] At block 601, a first prefetch voltage is applied to the memory cell. In one example, controller 120 applies the first prefetch voltage to memory cell 110 in response to receiving a write command from host device 126.

[0109] At block 603, a second read-ahead voltage is applied to at least a portion of the memory cells. In one instance, the portion of memory cell 302 that has crashed is below a threshold percentage or number. In response, controller 120 applies the second read-ahead voltage.

[0110] At block 605, the current programming state is determined for each memory cell in the memory cell. In one example, controller 120 determines the current programming state of each memory cell in memory cell 110 based on the results from blocks 601 and 603 above.

[0111] At block 607, a target programming state is determined for each memory cell in the memory unit. In one example, controller 120 determines a target logic value for the bit corresponding to memory cell 110. The target logic value of the bit corresponds to data to be written in response to a write command received from host device 126. In one example, the data to be written is one or more data pages received from host device 126 via a serial data bus. The data page is associated with the write command.

[0112] At block 609, a write voltage is applied to at least a portion of the memory cell based on the existing programming state and / or the target programming state. In one example, bias circuitry 124 applies a write voltage having a polarity corresponding to the target programming state of at least a portion of the memory cell 110.

[0113] In one embodiment, a system includes: a memory array comprising memory cells, each memory cell (e.g., 402) comprising a selection device (e.g., 410); and a memory controller configured to: apply a first read-ahead voltage to the memory cells; sense a corresponding first current in each memory cell generated by the application of the first read-ahead voltage; determine a first portion and a second portion of the memory cells, wherein for the first portion, the corresponding first current exceeds the first threshold, and for the second portion, the corresponding first current does not exceed the first threshold; determine that the first portion of the memory cells is less than a threshold number; and in response to determining that the first portion of the memory cells is less than the threshold number: apply a second read-ahead voltage to the second portion of the memory cells, wherein the second read-ahead voltage has the same polarity as the first read-ahead voltage and the magnitude of the second read-ahead voltage is greater than the magnitude of the first read-ahead voltage; sense a corresponding second current in each memory cell in the second portion generated by the application of the second read-ahead voltage; and determine a third portion of the memory cells, wherein for the third portion, the corresponding second current exceeds the second threshold.

[0114] In one embodiment, as part of a programming operation, the first read-ahead voltage is applied to the memory cell, and the programming operation is performed in response to receiving a write command from a host device (e.g., 126).

[0115] In one embodiment, the controller is further configured to apply a write voltage to a fourth portion of the memory cell, wherein the write voltage has a first polarity when the memory cell is programmed to a first logic state (e.g., a reset state), and has an opposite second polarity when the memory cell is programmed to a second logic state (e.g., a set state).

[0116] In one embodiment, the controller is further configured to use a read voltage to read the fourth portion of the memory cell after the write voltage is applied, wherein the read voltage has the opposite polarity to the first read-ahead voltage and the second read-ahead voltage. In one example, the controller 120 uses the read voltage in response to receiving a read command from the host device 126.

[0117] In one embodiment, the fourth portion includes memory cells from at least one of the first portion or the second portion. In one example, the controller 120 applies the read voltage to read memory cells 302, 312, and / or 314.

[0118] In one embodiment, the existing programming state of the memory cell (e.g., memory cell 312) in the third part is a first logical state (e.g., reset state 311), and the target programming state of at least a portion of the memory cell in the third part is a second logical state (e.g., set state 318).

[0119] In one embodiment, for each memory cell in the fourth portion of the memory cells, the existing logical state and the target logical state requested by the host device are equal (e.g., set state 315 and set state 322 are equal logical states); and the controller is further configured to apply a write voltage to each memory cell in the fourth portion in response to determining that the first portion of the memory cells (e.g., memory cell 302) is less than the threshold number (e.g., less than seven percent), wherein the applied write voltage corresponds to the target logical state of the memory cell. In one example, controller 120 implements a forced write programming mode in response to determining that the percentage of memory cells 302 is less than seven percent.

[0120] This disclosure includes various means for performing the methods and implementing the systems described above, including a data processing system for performing these methods, and a computer-readable medium containing instructions that, when executed on the data processing system, cause the system to perform the methods.

[0121] The descriptions and accompanying drawings are illustrative and should not be construed as limiting. Numerous specific details are described to provide a thorough understanding. However, in some cases, well-known or conventional details have not been described to avoid obscuring the description. References to one or an embodiment in this disclosure are not necessarily references to the same embodiment; and such references indicate at least one.

[0122] As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which may be an indirect or direct communication connection (e.g., without intermediate components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0123] References to "one embodiment" or "an embodiment" in this specification mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure. The phrase "in one embodiment" appearing in various places throughout this specification does not necessarily refer to all of the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments. Furthermore, various features that may be exhibited by some embodiments but not by others are described. Similarly, various requirements are described that may be requirements of some embodiments but not others.

[0124] In this specification, various functions and / or operations may be described as being executed by or caused by software code for the sake of simplicity. However, those skilled in the art will recognize that such expressions mean that the functions and / or operations are caused by one or more processing devices executing code, such as microprocessors, application-specific integrated circuits (ASICs), graphics processors, and / or field-programmable gate arrays (FPGAs). Alternatively or in combination, functions and operations may be implemented using dedicated circuit systems (e.g., logic circuit systems) with or without software instructions. Embodiments may be implemented using hardwired circuit systems without software instructions or in combination with software instructions. Therefore, the techniques described are neither limited to any particular combination of hardware circuit systems and software, nor to any particular source of instructions executed by a computing device.

[0125] While some embodiments may be implemented in fully functional computers and computer systems, the various embodiments are capable of being distributed as computing products in various forms and can be applied regardless of the specific type of computer-readable medium in which the distribution is actually implemented.

[0126] At least some of the disclosed aspects can be embodied, at least partially, in software. That is, the technology can be implemented in a computing device or another system in response to its processing device (such as a microprocessor) executing a sequence of instructions contained in memory (such as ROM, volatile RAM, non-volatile memory, cache, or remote storage device).

[0127] The routines executed to implement the embodiments described may be implemented as part of an operating system, middleware, business delivery platform, software development kit (SDK) component, network service, or other specific application, component, program, object, module, or sequence of instructions (sometimes referred to as a computer program). The calling interface of these routines may be exposed to the software development community as an application programming interface (API). Computer programs typically include one or more sets of instructions stored in various memories and storage devices within a computer at various times, and these sets of instructions, when read and executed by one or more processors in the computer, cause the computer to perform operations necessary for carrying out elements involving various aspects.

[0128] Computer-readable media can be used to store software and data that, when executed by a computing device, cause the device to perform various methods. Executable software and data can be stored in various locations, including, for example, ROM, volatile RAM, non-volatile memory, and / or cache. Parts of this software and / or data can be stored in any of these storage devices. Furthermore, data and instructions can be obtained from a centralized server or a peer-to-peer network. Different portions of data and instructions can be obtained from different centralized servers and / or peer-to-peer networks at different times and in different communication sessions or in the same communication session. Data and instructions can be obtained entirely before the application is executed. Alternatively, portions of data and instructions can be obtained dynamically as needed for execution. Therefore, it is not required that all data and instructions be on the computer-readable media at any given moment.

[0129] Examples of computer-readable media include, but are not limited to, recordable and non-recordable media, such as volatile and non-volatile memory devices, read-only memory (ROM), random access memory (RAM), flash memory devices, solid-state drive storage media, removable disks, magnetic disk storage media, optical storage media (e.g., optical disc read-only memory (CD-ROM), digital versatile disc (DVD), etc.), and so on. Computer-readable media can store instructions. Other examples of computer-readable media include, but are not limited to, non-volatile embedded devices using NOR flash or NAND flash memory architectures. Media used in these architectures can include unmanaged NAND devices and / or managed NAND devices, including, for example, eMMC, SD, CF, UFS, and SSD.

[0130] Generally, non-transitory computer-readable media includes any means of providing (e.g., storing) information in a form accessible by computing devices (e.g., computers, mobile devices, network devices, personal digital assistants, manufacturing tools with controllers, any device having a collection of one or more processors, etc.). As used herein, “computer-readable media” can include a single medium or multiple media (e.g., storing one or more sets of instructions).

[0131] In various embodiments, the hardwired circuitry can be used in combination with software and firmware instructions to implement some of the techniques described. Therefore, the techniques are neither limited to any particular combination of hardware circuitry and software, nor to any particular source of instructions executed by a computing device.

[0132] The various embodiments described herein can be implemented using a wide variety of computing devices of different types. As used herein, examples of "computing device" include, but are not limited to, servers, centralized computing platforms, systems with multiple computing processors and / or components, mobile devices, user terminals, vehicles, personal communication devices, wearable digital devices, electronic self-service terminals, general-purpose computers, electronic document readers, tablet computers, laptop computers, smartphones, digital cameras, residential appliances, televisions, or digital music players. Additional examples of computing devices include portions of devices referred to as "Internet of Things" (IoT). Such "things" may interact incidentally with their owners or administrators who can monitor or modify settings for these things. In some cases, such owners or administrators act as users with respect to the "thing" devices. In some instances, a user's primary mobile device (e.g., an Apple iPhone) may be an administrator server regarding paired "thing" devices worn by the user (e.g., an Apple Watch).

[0133] In some embodiments, the computing device may be a computer or a host system, such as a desktop computer, laptop computer, web server, mobile device, or another computing device including memory and processing means. The host system may include or be coupled to a memory subsystem, such that the host system can read data from or write data to the memory subsystem. The host system may be coupled to the memory subsystem via a physical host interface. Generally, the host system can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0134] In one instance, the host system is host device 126. In one instance, the memory subsystem is memory device 101.

[0135] In some embodiments, the computing device is a system comprising one or more processing devices. Examples of processing devices may include a microcontroller, a central processing unit (CPU), a special-purpose logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), a system-on-a-chip (SoC), or another suitable processor.

[0136] In one example, the computing device is the controller of the memory system. The controller includes a processing device and a memory containing instructions executed by the processing device to control various operations of the memory system.

[0137] While some of the accompanying figures illustrate multiple operations in a specific order, non-sequentially dependent operations can be reordered and other operations can be combined or decomposed. Although some reorderings or other groupings are specifically mentioned, other reorderings or groupings will be apparent to those skilled in the art, and therefore an exhaustive list of alternatives is not provided. Furthermore, it should be recognized that stages can be implemented using hardware, firmware, software, or any combination thereof.

[0138] In the foregoing description, this disclosure has been described with reference to specific exemplary embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope set forth in the following claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A memory system comprising: a memory array including memory cells; and a controller configured to: apply a first pre-read voltage to the memory cells; sense a respective first current for each memory cell resulting from applying the first pre-read voltage; determine a first portion of the memory cells for which the respective first current exceeds a first threshold and a second portion of the memory cells for which the respective first current does not exceed the first threshold; determine that the first portion of the memory cells is less than a threshold number; and in response to determining that the first portion of the memory cells is less than the threshold number: apply a second pre-read voltage to the second portion of the memory cells, wherein a magnitude of the second pre-read voltage is greater than a magnitude of the first pre-read voltage; sense a respective second current for each memory cell in the second portion resulting from applying the second pre-read voltage; and determine a third portion of the memory cells for which the respective second current exceeds a second threshold.

2. The memory system of claim 1, wherein each memory cell includes a chalcogenide.

3. The memory system of claim 2, wherein each memory cell further includes a top carbon electrode positioned above the chalcogenide and a bottom carbon electrode positioned below the chalcogenide.

4. The memory system of claim 1, wherein the first pre-read voltage is applied to the memory cells as part of a program operation, and the program operation is performed in response to receiving a write command from a host device.

5. The memory system of claim 1, wherein the controller is further configured to apply a write voltage to a fourth portion of the memory cells, wherein the write voltage has a first polarity when the memory cells are programmed to a first logical state and a second, opposite polarity when the memory cells are programmed to a second logical state.

6. The memory system of claim 5, wherein the controller is further configured to, after applying the write voltage, use a read voltage to read the fourth portion of the memory cells, wherein the read voltage has an opposite polarity to the first pre-read voltage and the second pre-read voltage.

7. The memory system of claim 5, wherein the fourth portion includes memory cells from at least one of the first portion or the second portion.

8. The memory system of claim 1, wherein an existing programmed state of a memory cell in the third portion is a first logical state and a target programmed state of at least a portion of the memory cells in the third portion is a second logical state.

9. The memory system of claim 1, wherein: for each memory cell in a fourth portion of the memory cells, an existing logical state and a target logical state requested by a host device are equal; and ​ The controller is further configured to apply a write voltage to each memory cell in the fourth portion in response to determining that the first portion of the memory cells is less than the threshold number, wherein the applied write voltage corresponds to the target logic state of the memory cell.

10. A method of operating a memory device, comprising: applying a first read voltage to memory cells of a memory array; sensing a respective first current of each memory cell resulting from applying the first read voltage; determining a first portion of the memory cells for which the respective first current exceeds a first threshold and a second portion of the memory cells for which the respective first current does not exceed the first threshold; determining whether the first portion of the memory cells is less than a threshold number; and in response to determining that the first portion of the memory cells is less than the threshold number: applying a second read voltage to the second portion of the memory cells, wherein a magnitude of the second read voltage is greater than a magnitude of the first read voltage; sensing a respective second current of each memory cell in the second portion resulting from applying the second read voltage; and determining a third portion of the memory cells for which the respective second current exceeds a second threshold.

11. The method of claim 10, wherein the threshold number is five percent of a total number of the memory cells.

12. The method of claim 10, wherein the first read voltage is a first pre-read voltage, the second read voltage is a second pre-read voltage, the first and second pre-read voltages have a same polarity, and a magnitude of the second pre-read voltage is at least 100 millivolts greater than a magnitude of the first pre-read voltage.

13. The method of claim 10, further comprising: comparing an existing program state of each of the memory cells to a target program state of the memory cells; determining a fourth portion of the memory cells to be programmed based on comparing the existing program state to the target program state for each memory cell; and applying a write voltage to the fourth portion of the memory cells, wherein a respective write voltage applied to each memory cell corresponds to the target program state of the memory cell.

14. The method of claim 13, wherein the write voltage applied to each memory cell has a first polarity when programmed to a first logic state and has a second, opposite polarity when programmed to a second logic state.

15. The method of claim 13, wherein the target program state is a logic state corresponding to a write command received from a host device.

16. The method of claim 13, further comprising reading the memory cells by applying a third read voltage to each of the memory cells, wherein the third read voltage has a polarity opposite to a polarity of the first read voltage and the second read voltage.

17. The method of claim 13, wherein each memory cell includes a chalcogenide as a logic storage element, the existing programmed state of the first portion and the third portion of the memory cells is a reset state, and the target programmed state of at least a portion of the first portion and the third portion of the memory cells is a set state.

18. The method of claim 10, wherein the first threshold and the second threshold are equal.

19. A non-transitory computer-readable medium storing instructions that, when executed on at least one processing device, cause the at least one processing device to: apply a first read voltage to memory cells of a memory array, wherein each memory cell includes a chalcogenide; sense a respective first current of each memory cell resulting from applying the first read voltage; determine a first portion of the memory cells for which the respective first current exceeds a threshold and a second portion of the memory cells for which the respective first current does not exceed the threshold; determine whether the first portion of the memory cells is less than a threshold number; and in response to determining that the first portion of the memory cells is less than the threshold number: apply a second read voltage to the second portion of the memory cells, wherein a magnitude of the second read voltage is greater than a magnitude of the first read voltage; sense a respective second current of each memory cell in the second portion resulting from applying the second read voltage; and determine a third portion of the memory cells for which the respective second current exceeds a threshold.

20. The non-transitory computer-readable medium of claim 19, wherein the instructions further cause the at least one processing device to: apply a write voltage to at least a portion of the third portion of the memory cells; and after applying the write voltage, read the third portion of the memory cells using a third read voltage, wherein the third read voltage has a polarity opposite to the first read voltage and the second read voltage.

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