A method to improve the reliability of the gate oxide layer in SiC field-effect transistors

Abstract

This invention provides a method for improving the reliability of the gate oxide layer in a SiC field-effect transistor. This method involves performing three sequential annealing treatments on the SiO2 gate oxide layer using different gases under three different processing environments to reduce C-related defects at the SiO2 gate oxide layer interface. In other words, through three consecutive annealing treatments, various traps and defects at the SiO2 gate oxide layer interface in the SiC field-effect transistor can be eliminated, optimizing interface quality, enhancing density, reducing leakage current, and improving reliability, thereby enhancing the performance of the SiC field-effect transistor.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and more specifically, to a method for improving the reliability of the gate oxide layer in a SiC field-effect transistor. Background Technology

[0002] With the continuous development of science and technology, traditional Si material devices are gradually failing to meet the needs in many fields due to the limitations of their material properties.

[0003] SiC, as an ideal material for power electronic devices, plays an extremely important role in the field of semiconductor devices. Specifically, in aerospace, high temperature, and high pressure fields, SiC devices are valued for their excellent properties such as wide bandgap, high temperature resistance, high pressure resistance, high thermal conductivity, and high breakdown field strength.

[0004] Among them, SiC material MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) devices have become the core devices of SiC material devices due to their advantages such as high voltage resistance, fast switching speed and low loss.

[0005] However, the reliability of the gate oxide layer in SiC field-effect transistors is currently low, resulting in poor performance of SiC field-effect transistors. Summary of the Invention

[0006] In view of this, to solve the above problems, the present invention provides a method for improving the reliability of the gate oxide layer in SiC field-effect transistors, the technical solution of which is as follows:

[0007] A method for improving the reliability of the gate oxide layer in a SiC field-effect transistor, the method comprising:

[0008] Provide a SiC epitaxial wafer;

[0009] A SiO2 gate oxide layer is formed on the SiC epitaxial wafer;

[0010] Under a first preset processing environment, the SiO2 gate oxide layer is subjected to a first annealing treatment using a first gas;

[0011] Under a second preset processing environment, the SiO2 gate oxide layer is subjected to a second annealing treatment using a second gas;

[0012] In the third preset processing environment, the SiO2 gate oxide layer is subjected to a third annealing treatment using a third gas.

[0013] Optionally, in the above method, providing a SiC epitaxial wafer includes:

[0014] Provide a SiC substrate;

[0015] A SiC epitaxial layer is grown on the SiC substrate to form the SiC epitaxial wafer.

[0016] Optionally, in the above method, the first preset processing environment is:

[0017] The processing temperature is 800℃-1000℃;

[0018] The processing pressure is 800 Pa - 1200 Pa;

[0019] The processing time is 30-90 minutes.

[0020] Optionally, in the above method, the first gas is argon.

[0021] Optionally, in the above method, the second preset processing environment is:

[0022] The processing temperature is 800℃-1000℃;

[0023] The processing pressure is 800 Pa - 1200 Pa;

[0024] The processing time is 30-90 minutes.

[0025] Optionally, in the above method, the second gas is oxygen.

[0026] Optionally, in the above method, the third preset processing environment is:

[0027] The processing temperature is 200℃-400℃;

[0028] The processing pressure is 800 Pa - 1200 Pa;

[0029] The processing time is 30-90 minutes.

[0030] Optionally, in the above method, the third gas is hydrogen.

[0031] Compared with the prior art, the beneficial effects achieved by the present invention are as follows:

[0032] This invention provides a method for improving the reliability of the gate oxide layer in a SiC field-effect transistor. Under three processing environments, different gases are used to sequentially anneal the SiO2 gate oxide layer three times to reduce C-related defects at the SiO2 gate oxide layer interface. In other words, through three consecutive annealing processes, various traps and defects at the SiO2 gate oxide layer interface in the SiC field-effect transistor can be eliminated, optimizing interface quality, enhancing density, reducing leakage current, and improving reliability, thereby enhancing the performance of the SiC field-effect transistor. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0034] Figure 1 A flowchart illustrating a method for improving the reliability of the gate oxide layer in a SiC field-effect transistor, provided by an embodiment of the present invention;

[0035] Figures 2-3 for Figure 1 The structural diagram corresponding to the method shown is shown below;

[0036] Figure 4 A flowchart illustrating another method for improving the reliability of the gate oxide layer in a SiC field-effect transistor, provided by an embodiment of the present invention;

[0037] Figures 5-6 for Figure 4 The structural diagram corresponding to the method shown is shown. Detailed Implementation

[0038] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0039] In the process of inventing this invention, the inventors discovered that in SiC field-effect transistors, due to the lattice mismatch between SiO2 and SiC materials during the growth process, a large number of dangling bonds, carbon clusters and oxygen vacancies are generated at the SiO2 interface of the SiO2 gate oxide layer and the SiC interface of the SiC epitaxial layer, which in turn affects the performance of the SiC field-effect transistor.

[0040] Specifically, the high interface state density at the SiO2-SiC interface results in low mobility in SiC field-effect transistors, increases leakage current, leads to increased threshold voltage and low-frequency noise, and consequently reduces switching speed, increases on-state resistance, and deteriorates driving capability and high-temperature characteristics.

[0041] In other words, the interface reliability of the SiO2 gate oxide layer in SiC field-effect transistors is reduced.

[0042] Therefore, how to reduce the interface state density of SiC field-effect transistors, improve the interface quality, and improve the reliability of the SiO2 gate oxide layer are technical problems that urgently need to be solved by those skilled in the art.

[0043] Based on this, embodiments of the present invention provide a method for improving the reliability of the gate oxide layer in a SiC field-effect transistor, which greatly improves the reliability of the gate oxide layer in a SiC field-effect transistor, thereby improving the performance of the SiC field-effect transistor.

[0044] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0045] refer to Figure 1 , Figure 1 This is a flowchart illustrating a method for improving the reliability of the gate oxide layer in a SiC field-effect transistor, as provided in an embodiment of the present invention.

[0046] The method includes:

[0047] S101: As Figure 2 As shown, a SiC epitaxial wafer 11 is provided;

[0048] S102: As Figure 3 As shown, a SiO2 gate oxide layer 12 is formed on the SiC epitaxial wafer 11;

[0049] S103: Under a first preset processing environment, the SiO2 gate oxide layer 12 is subjected to a first annealing treatment using a first gas;

[0050] S104: Under a second preset processing environment, the SiO2 gate oxide layer 12 is subjected to a second annealing treatment using a second gas;

[0051] S105: Under the third preset processing environment, the SiO2 gate oxide layer 12 is subjected to a third annealing treatment using a third gas.

[0052] In this embodiment, the SiO2 gate oxide layer 12 is annealed three times sequentially using different gases under three different processing environments to reduce C-related defects at the interface of the SiO2 gate oxide layer 12. In other words, through three consecutive annealing processes, various traps and defects at the interface of the SiO2 gate oxide layer 12 in the SiC field-effect transistor can be eliminated, optimizing interface quality, enhancing density, reducing leakage current, improving reliability, and thus enhancing the performance of the SiC field-effect transistor.

[0053] Furthermore, based on the above embodiments of the present invention, refer to Figure 4 , Figure 4 This is a flowchart illustrating another method for improving the reliability of the gate oxide layer in a SiC field-effect transistor, provided by an embodiment of the present invention.

[0054] The provision of a SiC epitaxial wafer 11 in step S101 includes:

[0055] S1011: As Figure 5 As shown, a SiC substrate 13 is provided;

[0056] S1012: As Figure 6 As shown, a SiC epitaxial layer 14 is grown on the SiC substrate 13 to form the SiC epitaxial wafer 11.

[0057] In this embodiment, a SiC substrate 13 is first selected and pre-treated, such as by cleaning, etc.; then, a SiC epitaxial layer 14 is grown on the SiC substrate 13 to form the SiC epitaxial wafer 11.

[0058] For example, the formed SiC epitaxial wafer is an n-type 4H-SiC wafer with a crystal orientation of (0001)-Si plane, a thickness of 5 μm, and a doping concentration of 7.81 × 10⁻⁶. 15 cm -3 .

[0059] Furthermore, based on the above embodiments of the present invention, the formation of a SiO2 gate oxide layer 12 on the SiC epitaxial wafer 11 in step S102 specifically involves:

[0060] First, including but not limited to the SiC epitaxial wafer 11 formed in step S101 by cleaning with RCA (wet chemical cleaning method).

[0061] Specifically, in order to remove organic matter from the surface of the SiC epitaxial wafer 11, it is first immersed in acetone for ultrasonic cleaning until there is no obvious organic matter on the surface, and then ultrasonically cleaned with ethanol and deionized water to remove the acetone from the surface.

[0062] To remove the oxides from the surface of the SiC epitaxial wafer 11, it was then soaked in hydrofluoric acid buffer for 5-10 minutes, rinsed several times with deionized water, and finally dried.

[0063] In other words, the purpose of using RCA to clean the SiC epitaxial wafer 11 is to remove contaminants such as organic matter, particles, metal impurities and oxides that may exist on the surface of the SiC epitaxial wafer 11, thereby improving the electrical characteristics of the final SiC field-effect transistor.

[0064] Secondly, after the SiC epitaxial wafer 11 is cleaned, it is placed in a high-temperature oxidation furnace for growing the SiO2 gate oxide layer 12.

[0065] Then, the temperature of the high-temperature oxidation furnace is raised from room temperature to the oxidation temperature, so that the temperature inside the high-temperature oxidation furnace where the SiC epitaxial wafer 11 is placed reaches the temperature at which the SiO2 gate oxide layer 12 is grown by thermal oxidation.

[0066] Optionally, the oxidation temperature is 1200℃-1300℃.

[0067] For example, the oxidation temperature is 1200℃, 1250℃, 1278℃, or 1300℃, etc.

[0068] Afterwards, the temperature inside the high-temperature oxidation furnace is maintained at the oxidation temperature, and the oxidation gas is introduced into the high-temperature oxidation furnace. The oxidation gas introduced is dry oxygen oxidation gas.

[0069] Specifically, oxidizing gas is introduced into a high-temperature oxidation furnace to grow a SiO2 gate oxide layer 12 on the SiC epitaxial wafer 11. The oxidation reaction equation for SiC at this time is:

[0070] As can be seen from the equation, CO gas is generated during the reaction process. CO diffuses from the interface to the surface of the oxide layer and desorbs from the surface.

[0071] During the oxidation process of SiC, the growth of the SiC oxide layer is affected by gas diffusion. In the early stage of oxidation, the rate of CO release is faster than the rate of CO production, and there will be no interface state caused by C residue at the interface.

[0072] When the oxidizing environment is at a low temperature, the reaction between SiC and O2 is: SiC + O2 = SiO2 + C.

[0073] When the oxidizing environment temperature is too high, the reaction between SiC and O2 is: SiC + O2 = SiO↑ + C.

[0074] In the dry oxidation process, dry oxygen reacts with the SiC epitaxial wafer to generate SiO2 and CO. CO gas passes through SiO2 and escapes from the SiC / SiO2 interface, forming a SiO2 gate oxide layer 12 on the SiC epitaxial wafer 11.

[0075] Furthermore, based on the above embodiments of the present invention, after the SiO2 gate oxide layer 12 is grown, it is subjected to a first annealing treatment, that is, in a first preset processing environment, the SiO2 gate oxide layer 12 is subjected to a first annealing treatment using a first gas.

[0076] The first preset processing environment is:

[0077] The processing temperature (first annealing temperature) is 800℃-1000℃.

[0078] For example, the processing temperature is 850°C, 932°C, or 1000°C, etc.

[0079] The processing pressure (first annealing pressure) is 800 Pa - 1200 Pa.

[0080] For example, the processing pressure is 822 Pa, 916 Pa, 1000 Pa, 1154 Pa, or 1200 Pa, etc.

[0081] The processing time (first annealing time) is 30-90 minutes.

[0082] For example, the processing time is 30 min, 44 min, 68 min, or 90 min, etc.

[0083] The first gas includes, but is not limited to, argon.

[0084] In this embodiment, the selected processing temperature is 1000℃, the processing pressure is 1000pa, and the processing time is 30min.

[0085] In an argon atmosphere, annealing can remove the C element at the interface between the SiC epitaxial layer 14 and the SiO2 gate oxide layer 12, causing C-related defects to decompose and leave the interface location. This effectively reduces interface defects at shallow energy levels, effectively reduces the flat-band voltage of the SiC field-effect transistor device, and can also eliminate vacancy defects in the SiO2 gate oxide layer 12, enhance Si-Si bonds, improve oxide layer density, thereby reducing leakage current and enhancing the reliability of the SiC field-effect transistor device.

[0086] Furthermore, based on the above embodiments of the present invention, after the SiO2 gate oxide layer 12 is subjected to a first annealing treatment, the SiO2 gate oxide layer 12 is subjected to a second annealing treatment using a second gas under a second preset processing environment.

[0087] The second preset processing environment is:

[0088] The processing temperature (second annealing temperature) is 800℃-1000℃.

[0089] For example, the processing temperature is 853°C, 934°C, or 1000°C, etc.

[0090] The processing pressure (second annealing pressure) is 800 Pa - 1200 Pa.

[0091] For example, the processing pressure is 826 Pa, 919 Pa, 1000 Pa, 1158 Pa, or 1200 Pa, etc.

[0092] The processing time (second annealing time) is 30-90 minutes.

[0093] For example, the processing time is 30 min, 46 min, 64 min, or 90 min, etc.

[0094] The second gas includes, but is not limited to, oxygen.

[0095] In this embodiment, the processing temperature of the high-temperature oxidation furnace during the first annealing process is maintained, i.e., the selected processing temperature is 1000°C.

[0096] Oxygen is introduced into a high-temperature oxidation furnace to perform a second annealing treatment on the SiO2 gate oxide layer 12.

[0097] High-temperature oxidation annealing is used because the oxidation reaction is more complete under high temperature conditions. The exposed C atoms at the interface will also form CO gas and be released, which reacts with Si to generate SiO2, thereby optimizing the interface quality. This will reduce the interface state density at the interface and obtain a SiO2 gate oxide layer 12 with high inversion channel carrier mobility.

[0098] The process conditions for annealing the SiO2 gate oxide layer 12 are as follows: the pressure in the high-temperature oxidation furnace is 1000 Pa, and the oxygen introduction time is 30 min-60 min.

[0099] The annealing temperature in the high-temperature oxidation furnace was reduced to room temperature (25°C). When the temperature in the high-temperature oxidation furnace was below 25°C, the annealed sample was taken out of the high-temperature oxidation furnace to complete the second annealing treatment of the SiO2 gate oxide layer 12.

[0100] Furthermore, based on the above embodiments of the present invention, after the SiO2 gate oxide layer 12 is subjected to a second annealing treatment, the SiO2 gate oxide layer 12 is subjected to a third annealing treatment using a third gas under a third preset processing environment.

[0101] The third preset processing environment is:

[0102] The processing temperature (third annealing temperature) is 200℃-400℃.

[0103] For example, the processing temperature is 212℃, 300℃, 354℃, or 400℃, etc.

[0104] The processing pressure (third annealing pressure) is 800 Pa to 1200 Pa.

[0105] For example, the processing pressure is 827 Pa, 918 Pa, 1000 Pa, 1151 Pa, or 1200 Pa, etc.

[0106] The processing time (third annealing time) is 30-90 minutes.

[0107] For example, the processing time is 30 min, 42 min, 61 min, or 90 min, etc.

[0108] The third gas includes, but is not limited to, hydrogen.

[0109] In this embodiment, hydrogen gas is introduced and the temperature is raised to 300°C for a third annealing treatment in a hydrogen atmosphere.

[0110] Unlike conventional annealing methods using oxygen or other annealing gases, this method involves introducing low-temperature hydrogen gas for annealing after annealing with oxidizing gases. This prevents secondary oxidation and also removes defects such as dangling bonds at the interface, thereby improving interface quality.

[0111] As described above, the present invention provides a method for improving the reliability of the gate oxide layer in a SiC field-effect transistor. This method employs argon, oxygen, and hydrogen to perform a three-stage annealing of the SiO2 gate oxide layer, which helps reduce C-related defects at the interface. Argon annealing removes the interface state density of shallow energy levels, increases the compactness of the SiO2 gate oxide layer, and enhances its reliability. Furthermore, annealing in an argon atmosphere containing oxygen promotes the decomposition of C-related defects, improving the effect of oxygen annealing. Oxygen annealing reduces Si-Si bonds and C-related defects generated by high-temperature oxidation of SiC, thereby reducing interface states and improving the quality of the interface and oxide layer. Hydrogen annealing, before the temperature is lowered to room temperature, prevents secondary oxidation, further reducing the dangling bond density at the interface and improving interface quality.

[0112] In other words, by performing three consecutive annealing processes, various traps and defects at the SiO2 gate oxide interface in SiC field-effect transistors can be eliminated, thereby optimizing the interface quality, enhancing the compactness, reducing leakage current, improving reliability, and ultimately enhancing the performance of SiC field-effect transistors.

[0113] The above provides a detailed description of a method for improving the reliability of the gate oxide layer in a SiC field-effect transistor. Specific examples have been used to illustrate the principle and implementation of the invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the invention. Therefore, the content of this specification should not be construed as a limitation of the invention.

[0114] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0115] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that elements inherent to a process, method, article, or apparatus that comprises a list of elements, or elements inherent to such processes, methods, articles, or apparatus, are also included. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0116] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for improving the reliability of the gate oxide layer in a SiC field-effect transistor, characterized in that, The method includes: Provide a SiC epitaxial wafer; A SiO2 gate oxide layer is formed on the SiC epitaxial wafer; Under a first preset processing environment, the SiO2 gate oxide layer is subjected to a first annealing treatment using a first gas; wherein the first preset processing environment is: processing temperature of 800℃-1000℃; processing pressure of 800pa-1200pa; processing time of 30min-90min; and the first gas is argon. Under a second preset processing environment, the SiO2 gate oxide layer is subjected to a second annealing treatment using a second gas; wherein the second preset processing environment is: processing temperature of 800℃-1000℃; processing pressure of 800pa-1200pa; processing time of 30min-90min; and the second gas is oxygen. Under a third preset processing environment, the SiO2 gate oxide layer is subjected to a third annealing treatment using a third gas; wherein the third preset processing environment is: processing temperature of 200℃-400℃; processing pressure of 800pa-1200pa; processing time of 30min-90min; and the third gas is hydrogen.

2. The method according to claim 1, characterized in that, The provision of a SiC epitaxial wafer includes: Provide a SiC substrate; A SiC epitaxial layer is grown on the SiC substrate to form the SiC epitaxial wafer.

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