Source-drain limited epitaxy method, device preparation method, device, and equipment

Abstract

The present invention provides a method for controlled and restricted epitaxy of source and drain on a gate-all-around device, comprising: forming a plurality of fin structures arranged along a first direction on a substrate, forming a plurality of dummy gate structures arranged along a second direction on the plurality of fin structures, with each dummy gate structure spanning each of the plurality of fin structures; etching the fin structures to form a plurality of source / drain cavities; forming a first isolation layer arranged along the first direction between adjacent fin structures to isolate the source / drain cavities between adjacent fin structures; epitaxially growing a source / drain layer in the source / drain cavities; and removing the first isolation layer. The thickness of the source / drain layer can be limited to a critical thickness for stress release, thereby reducing stress relaxation caused by mismatch dislocation. Of course, by limiting the thickness of the source / drain layer, the area of ​​the contact surface between the source / drain layer and the gate can be limited, thereby limiting parasitic capacitance.

Description

Technical Field

[0001] The present invention relates to the field of GAAFET device manufacturing technology, and in particular to a source-drain limited epitaxy method, a device manufacturing method, a device, and equipment. Background Art

[0002] Gate-all-around devices at advanced nodes are relatively tall, providing the largest effective area. Applying stress to the channel using SiGe S / D epitaxial growth technology is essential for device performance.

[0003] The diamond-structured SiGe source and drain exert uneven stress on the channel of nanowires or nanosheets at different stacking levels, and it is difficult to control it uniformly.

[0004] In a gate-all-around device, the device current is increased by increasing the number of stacked nanowires or nanosheets, and the height of the fin structure increases with the increase in the number of stacked nanowires or nanosheets.

[0005] As the Fin height increases, the volume of epitaxial SiGe increases, and the SiGe source and drain between single Fins may still overlap. Dislocations are likely to occur at the overlapping position, causing stress relaxation of the SiGe source and drain. In particular, wrap-around contact (WAC) between the source and drain cannot be achieved, and the contact resistance is difficult to meet the requirements.

[0006] In addition, due to the significant increase in Fin height, the thickness of the SiGe source and drain epitaxy also increases significantly. If the SiGe source and drain thickness is maintained within the critical epitaxial thickness for stress release, the Ge content of the epitaxial SiGe needs to be reduced, which will not meet the stress required for the channel. If the Ge content is increased within this SiGe thickness, misfit dislocations may be generated between the SiGe source and drain and the Si nanowires or thin sheets and the Si substrate, causing stress relaxation and a corresponding increase in parasitic capacitance.

[0007] Therefore, how to control the source and drain thickness within the critical thickness for stress release, thereby reducing the mismatch and dislocation caused by excessive source and drain thickness, so as to reduce the stress relaxation caused by mismatch and dislocation, and eliminate the increase in parasitic capacitance caused by excessive source and drain thickness, thereby increasing the contact area between the source and drain and the gate; by controlling the source and drain thickness, further solve the source and drain overlapping fault phenomenon caused by the increase in source and drain thickness, so as to reduce the stress relaxation caused by this phenomenon, and realize wrap-around contact; these technical problems have become technical problems that the industry urgently needs to solve. Summary of the Invention

[0008] The present invention provides a source / drain restricted epitaxy method, a device preparation method, and corresponding devices and equipment to solve the problem of unrestricted source / drain layer thickness between adjacent Fins of a GAA device.

[0009] According to a first aspect of the present invention, a method for controlling source and drain confinement epitaxy on a gate-all-around device is provided, comprising:

[0010] providing a substrate;

[0011] forming a plurality of fin structures arranged along a first direction and a shallow trench isolation structure between adjacent fin structures on the substrate;

[0012] forming a plurality of dummy gate structures arranged along a second direction on the plurality of fin structures, wherein each dummy gate structure spans across each of the plurality of fin structures;

[0013] Etching the fin structure to form a plurality of source / drain cavities;

[0014] forming a first isolation layer arranged along the first direction between adjacent fin structures to isolate the source / drain cavities between the adjacent fin structures;

[0015] epitaxially growing a source / drain layer in the source / drain cavity;

[0016] removing the first isolation layer;

[0017] The first direction and the second direction are perpendicular to each other.

[0018] Optionally, the thickness of the first isolation layer is adapted to the thickness of the source / drain layer.

[0019] Optionally, the height of the first isolation layer is not lower than that of the fin structure.

[0020] Optionally, the material of the first isolation layer is SiO2.

[0021] Optionally, forming a first isolation layer arranged along the first direction between adjacent fin structures specifically includes:

[0022] depositing isolation layers in the plurality of source / drain cavities;

[0023] performing CMP treatment on the isolation layer;

[0024] The isolation layer after the CMP treatment is subjected to photolithography and etching, and only the isolation layer between adjacent fin structures is retained to form the first isolation layer.

[0025] Optionally, the source / drain layer is made of SiGe.

[0026] Optionally, after etching away the first isolation layer, the method further includes:

[0027] An interlayer dielectric layer is formed on the source / drain layer and the shallow trench isolation structure.

[0028] According to a second aspect of the present invention, there is provided a method for preparing a semiconductor device, comprising: a method for controlled source-drain confinement epitaxy on a gate-all-around device according to any one of the first aspects of the present invention.

[0029] According to a third aspect of the present invention, there is provided a semiconductor device manufactured using the method for manufacturing a semiconductor device according to the second aspect of the present invention.

[0030] According to a fourth aspect of the present invention, there is provided an electronic device comprising the semiconductor device according to the third aspect of the present invention.

[0031] The present invention provides a method for controllable and restricted epitaxy of the source and drain on a ring-gate device. Before the source / drain layer is epitaxially grown in the source / drain cavity, a first isolation layer arranged along the first direction is formed between adjacent fin structures to isolate the source / drain cavities between adjacent fin structures; thereby, under the restriction of the first isolation layer, the thickness of the source / drain layer is controllable, so that the thickness of the source / drain layer can be limited to the critical thickness for stress release, thereby reducing the mismatch and dislocation caused by excessive thickness of the source / drain layer, so as to reduce the stress relaxation phenomenon caused by mismatch and dislocation; of course, by limiting the thickness of the source / drain layer, the area of ​​the contact surface between the source / drain layer and the gate can be limited, thereby limiting the parasitic capacitance. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 1 is a flow chart of a method for controlled source-drain confinement epitaxy on a gate-all-around device according to an embodiment of the present invention;

[0034] Figure 2(a)-Figure 2(c) Schematic diagram of the gate-all-around device structure at different etching stages in one embodiment of the present invention Figure 1 ;

[0035] Figure 3(a)-Figure 3(c) 2 is a second schematic diagram of the structure of a gate-all-around device at different etching stages according to an embodiment of the present invention;

[0036] Figure 4(a)-Figure 4(c) Schematic diagram 3 of the gate-all-around device structure at different etching stages according to one embodiment of the present invention;

[0037] Figure 5(a)-Figure 5(c) Schematic diagram 4 of the gate-all-around device structure at different etching stages according to one embodiment of the present invention;

[0038] Figure 6(a)-Figure 6(c) Schematic diagram 5 of the gate-all-around device structure at different etching stages according to one embodiment of the present invention;

[0039] Description of reference numerals:

[0040] 101-Sacrificial layer

[0041] 102-Channel layer

[0042] 103-false gate spacer

[0043] 104-dummy gate structure;

[0044] 105-substrate;

[0045] 106-first isolation layer;

[0046] 107-source / drain layer;

[0047] 108-Device contact structure. DETAILED DESCRIPTION

[0048] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0049] The terms "first," "second," "third," "fourth," and the like (if any) in the description and claims of the present invention and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatus.

[0050] Gate-all-around devices at advanced nodes are relatively tall to maximize effective area. Compared to FinFETs, which use multiple fin structures to increase device current, GAAFET devices are more likely to use a single fin structure. By increasing the number or width of stacked nanowires or nanosheets to increase device current, the fin pitch can be appropriately relaxed without compromising performance. In GAAFET devices, applying stress to the channel using SiGe S / D epitaxial growth technology is essential for device performance.

[0051] However, in the process of performing SiGe S / D epitaxy to produce SiGe source / drain in the source / drain region, the following technical problems exist:

[0052] In a gate-all-around device, the fin height increases with the number of stacked nanowires or nanosheets. Furthermore, in a single-fin structure, the spacing requirements between fins are relatively loose. As the fin height increases significantly, the thickness of the SiGe source / drain produced by the SiGeS / D epitaxy also increases significantly. The thicker the SiGe source / drain, the greater the stress, which can lead to stress relaxation. Therefore, the SiGe source / drain should be kept within the critical epitaxial thickness required for stress release. The thickness of the SiGe source / drain epitaxy refers to the thickness along the dummy gate crossover direction.

[0053] At the same time, if the thickness of SiGe source / drain is larger, the overlapping area between the gate and SiGe source / drain will be larger, and the corresponding parasitic capacitance will also increase;

[0054] In the prior art, the thickness of the SiGe source / drain can be controlled by adjusting the Ge component of the SiGe source / drain during the SiGe S / D epitaxy process. However, the control of the Ge component content in the SiGe S / D epitaxy is difficult to grasp. If the thickness of the SiGe source / drain is kept within the critical epitaxial thickness for stress release to ensure the thickness of stress release, the Ge component of the epitaxial SiGe needs to be reduced. If the Ge component of the epitaxial SiGe is too low, the stress is insufficient and it may not meet the stress required to provide the channel. At this time, if the Ge component is increased, the thickness may be too thick or mismatch dislocations may be generated between the SiGe source / drain and the Si nanowires or thin sheets and the Si substrate, thereby causing stress relaxation. Mismatch dislocations refer to:

[0055] Normally, the SiGe lattice is larger than the Si lattice. During the epitaxial growth process, the SiGe film changes its lattice size to match the lattice constant of the Si substrate, thereby generating compressive strain. However, when the SiGe exceeds a critical thickness, misfit dislocations will form in the film, causing stress relaxation.

[0056] In addition, as the Fin height increases, the volume of epitaxial SiGe increases, and the SiGe source and drain between single Fins may still overlap. The overlapping position is prone to overlapping faults, causing stress relaxation of the SiGe source and drain. Moreover, ideally, graphic lithography is performed on the etch stop layer in the subsequent process, and windows are opened in the area where contact is required, and metal materials are filled to form contacts. At this time, not only can contacts be formed on the top of the SiGe source / drain, but its sides and bottom can also be wrapped by metal to form a wraparound contact, thereby reducing the contact resistance. However, when the SiGe source / drain between single Fins is still likely to overlap, the source / drain wraparound contact (WAC) cannot be achieved, and the contact resistance is difficult to meet the requirements.

[0057] Therefore, the existing technical means cannot well control the thickness of the SiGe source / drain, and thus cannot solve the above-mentioned overlapping fault problem.

[0058] Secondly, the diamond-structured SiGe source / drain has uneven width in the vertical direction. Therefore, the SiGe source / drain exerts uneven stress on the channel of nanowires or nanosheets at different stacking levels, and it is difficult to uniformly control it. Existing technical means have also failed to solve this technical problem.

[0059] In response to the above technical difficulties, the present invention creatively proposes the following solution: a spaced-apart Confinement isolation structure is set in the source / drain cavity formed after source / drain etching, and is set to isolate the SiGe source / drain along its thickness direction.

[0060] Due to the limitations of the Confinement isolation structure, the width of the SiGe source / drain in the vertical direction is evenly distributed, thereby achieving uniform stress application to different stacked channels; and at this time, by regulating the distribution of Ge components in the SiGe source and drain, it is easier to control the stress application effect on different stacked channels.

[0061] In addition, by controlling the width Wconfinement of the SiO2 Confinement, the volume of the SiGe source / drain can be effectively controlled, avoiding invalid stress or even stress relaxation caused by exceeding the critical thickness. At the same time, the increase in parasitic capacitance and resistance can be effectively controlled, and the problem of overlapping faults can be solved.

[0062] Due to the limitations of the Confinement isolation structure, the width of the SiGe source and drain is evenly distributed in the vertical direction, and the stress applied to different stacked channels is more uniform.

[0063] Therefore, the technical solution proposed by the present invention can effectively solve problems that cannot be solved by existing means.

[0064] The following specific embodiments are used to describe the technical solution of the present invention in detail. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0065] Please refer to Figure 1-Figure 6(c) ,in, Figure 2(a)-Figure 6(c) Figure (a) is a top view of the current device formed after steps S14, S15, S16, S17 and forming the device contact structure (only the top view of the fin structure and the gate structure is shown), Figure (b) is a schematic cross-sectional view of the current device formed along the direction of the dotted line ② in Figure (a), and Figure (c) is a schematic cross-sectional view of the current device formed along the direction of the dotted line ① in Figure (a).

[0066] by Figure 2(a)-Figure 2(c) The above contents will be specifically described by taking 2 as an example, wherein FIG2(a) is a top view of the current device formed after step S14 (wherein only the top view of the fin structure and the gate structure is shown), FIG2(b) is a schematic cross-sectional view of the current device formed along the direction of the dotted line ② in FIG2(a), and FIG2(c) is a schematic cross-sectional view of the current device formed along the direction of the dotted line ① in FIG2(a).

[0067] According to one embodiment of the present invention, a method for controlling source and drain confinement epitaxy on a gate-all-around device is provided, comprising:

[0068] S11: providing a substrate 105;

[0069] S12: forming a plurality of fin structures arranged along a first direction on the substrate, and shallow trench isolation structures between adjacent fin structures, wherein the first direction is the direction indicated by the arrow in FIG. 2( a );

[0070] The formation process of the plurality of fin structures is as follows: growing a sacrificial layer 101 and a channel layer 102 arranged at intervals on the substrate, etching the substrate and the sacrificial layer and the channel layer on the substrate to form a plurality of fin structures, and forming cavities between the plurality of fin structures after etching;

[0071] The specific process of forming the shallow trench isolation structure is as follows: filling the cavities between the above-mentioned plurality of fin structures with an isolation material to form an isolation layer;

[0072] S13: forming a plurality of dummy gate structures 104 arranged along a second direction on the plurality of fin structures, with each dummy gate structure spanning each of the plurality of fin structures, wherein the second direction is a direction perpendicular to the substrate plane as indicated by the arrow shown in FIG. 2( a );

[0073] Thus, the dummy gate structure covers a pair of sidewalls and a portion of the top of each fin structure, wherein the sidewalls are a pair of sidewalls in the first direction;

[0074] The formation process of the dummy gate structure is specifically as follows: depositing a dummy gate material on the surface of the device formed after executing step S12, performing CMP polishing on the top of the dummy gate material so that the dummy gate material reaches a specified height, and etching the dummy gate material to form the dummy gate structure;

[0075] After forming a plurality of dummy gate structures arranged along the second direction on the plurality of fin structures, step S13 further includes: covering both sides of each dummy gate structure with a dummy gate spacer layer 103 so as to isolate the dummy gate structure from the source and drain regions, wherein the two sides of the dummy gate structure refer to two side walls of the dummy gate structure along the second direction;

[0076] S14: etching the fin structure to form a plurality of source / drain cavities, such as Figure 2(a)-Figure 2(c) As shown,

[0077] Etching the fin structure extending out of the dummy gate structure and the spacer layer on both sides of the dummy gate structure along the second direction to form a source / drain cavity; the source / drain cavity refers to: a cavity formed in the gap between the dummy gate structures after step S14 is completed;

[0078] After etching the fin structure to form a plurality of source / drain cavities, the method further includes:

[0079] forming an inner spacer layer between the channel layers; specifically, filling the sidewalls of the channel layers with an isolation material to form the inner spacer layer, and since the inner spacer layer is formed between the sidewalls of the channel layers and the dummy gate structure, the channel layers and the dummy gate structure are isolated;

[0080] S15: forming a first isolation layer 106 arranged along the first direction between adjacent fin structures to isolate the source / drain cavities between the adjacent fin structures, such as Figure 3(a)-Figure 3(c) As shown, the thickness indicated by the double arrow in FIG3( a ) is the thickness of the first isolation layer;

[0081] Wherein, the first isolation layer is formed in the source-drain cavity;

[0082] S16: epitaxially grow a source / drain layer 107 in the source / drain cavity, as shown in FIG. Figure 4(a)-Figure 4(c) As shown;

[0083] Due to the limitation of the first isolation layer, the thickness of the source / drain layer is limited, so that the thickness of the source / drain layer can be limited to the critical thickness of stress release, thereby reducing the mismatch and dislocation caused by the excessive thickness of the source / drain layer, so as to reduce the stress relaxation phenomenon caused by the mismatch and dislocation; of course, by limiting the thickness of the source / drain layer, the area of ​​the contact surface between the source / drain layer and the gate can be limited, thereby controlling the parasitic capacitance.

[0084] S17: removing the first isolation layer; thereby removing the isolation between the epitaxial source / drain layers, such as Figure 5(a)-Figure 5(c) As shown;

[0085] The first direction and the second direction are perpendicular to each other.

[0086] In one embodiment, the thickness of the first isolation layer is adapted to the thickness of the source / drain layer.

[0087] The adaptation means that: since the volume of the epitaxial source / drain layer is controlled by the width Wconfinement of the first isolation layer, the volume of the epitaxial source / drain layer is controlled by adjusting the width of the first isolation layer, so that the thickness of the epitaxial source / drain layer along the first direction is controlled within the epitaxial critical thickness for achieving stress release, thereby avoiding invalid stress and stress relaxation. In addition, by controlling the thickness of the source / drain layer, the overlapping and misalignment phenomenon of the source / drain layer caused by the increase in the thickness of the source / drain layer is further solved, thereby reducing the stress relaxation phenomenon caused thereby.

[0088] In one embodiment, the height of the first isolation layer is not less than the height of the fin structure;

[0089] The height of the first isolation layer is not limited to be the same as the height of the fin structure, as long as it can effectively isolate the epitaxial source / drain layer and achieve corresponding technical effects.

[0090] In one embodiment, the material of the first isolation layer is SiO2;

[0091] In other embodiments, the material forming the first isolation layer may be other isolation materials that can achieve similar isolation effects.

[0092] In one embodiment, forming a first isolation layer arranged along the first direction between adjacent fin structures specifically includes:

[0093] depositing isolation layers in the plurality of source / drain cavities;

[0094] Performing a CMP treatment on the isolation layer; the CMP treatment is a polishing process so that the isolation layer in the plurality of source / drain cavities meets a specified height;

[0095] Performing photolithography and etching on the isolation layer after the CMP treatment, leaving only the isolation layer between adjacent fin structures to form the first isolation layer;

[0096] The specific steps of photolithography and etching the isolation layer after the CMP treatment are as follows: covering the device surface after the CMP treatment with photoresist, patterning the photoresist so that the photoresist covers the target isolation layer, the target isolation layer is the first isolation layer, and etching the isolation layer using the patterned photoresist as a mask to obtain the first isolation layer.

[0097] In another embodiment, the isolation layer may be photolithographically and etched first to retain only the isolation layer between adjacent fin structures, and then the isolation layer may be CMP treated to form the first isolation layer;

[0098] In one embodiment, the source / drain layer is made of SiGe.

[0099] Since the first isolation layer is added before the source / drain layer is epitaxially grown, the longitudinal thickness of the source / drain layer is consistent, so that the stress applied by the source / drain layer to the channel layer is uniform. Moreover, when the thickness of the source / drain layer is adjusted by regulating the Ge content in SiGe, it is easier to achieve than with a source / drain layer with a diamond structure.

[0100] In one embodiment, after etching away the first isolation layer, the method further includes the following steps:

[0101] 1) forming an interlayer dielectric layer on the source / drain layer and the shallow trench isolation structure.

[0102] The interlayer dielectric layer is formed in a plurality of source / drain cavities. Since step S15 is added before the epitaxial source / drain layer is formed, the interlayer dielectric layer covers the top and sidewalls of each source / drain layer.

[0103] Before depositing the interlayer dielectric layer on the source / drain layer and the shallow trench isolation structure, the method further includes: depositing a dielectric material on the source / drain layer and the shallow trench isolation structure, etching the dielectric material to a specific height using CMP, and etching the dielectric material to form the interlayer dielectric layer.

[0104] 2) Remove the dummy gate structure.

[0105] In one embodiment, the dummy gate structure is made of polysilicon material.

[0106] 3) Selectively etching the sacrificial layer to release the Si channel layer.

[0107] After the dummy gate structure is removed and the sacrificial layer is released, a dummy gate cavity is formed.

[0108] In one embodiment, the material constituting the sacrificial layer is SiGe;

[0109] In one embodiment, the selective etching method is dry etching;

[0110] In other implementations, other methods may also be used to selectively etch the sacrificial layer.

[0111] 4) Filling the dummy gate cavity with a metal gate material.

[0112] Before the metal gate material is filled in the dummy gate cavity, the method further includes: filling the dummy gate cavity with a high dielectric constant material; the metal gate material covers the high dielectric constant material; the high dielectric constant material and the metal gate (MG) complete the full encapsulation of the channel layer;

[0113] In one embodiment, the high dielectric constant material (High-k, HK) is a high-K material; and the metal gate material is a material widely used in the prior art.

[0114] The metal gate material and the high dielectric constant material are subjected to a CMP process, thereby removing the metal gate material and the high dielectric constant material on the top of the interlayer dielectric layer.

[0115] An etch barrier layer (Nitride) is deposited on the outer surface of the structure formed in the above step. The etch barrier layer is used as a mask to etch the interlayer dielectric layer on the top and sidewall of the source / drain layer to form a contact hole. Metal material is deposited in the contact hole to form a device contact structure 108. Figure 6(a)-Figure 6(c) shown.

[0116] Subsequently, graphic lithography can be performed on it to open windows in the areas where contact needs to be formed, and fill them with metal materials such as W, TiN, etc. to form a contact structure. At this time, not only can contact be formed on the top of the source and drain, but the side and bottom surfaces can also be wrapped with metal materials. The contact structure completely wraps the source / drain layer to form a wraparound contact, thereby reducing the contact resistance.

[0117] By limiting the thickness of the source / drain layer, the overlapping and stacking phenomenon of the source / drain layer caused by the increase in the thickness of the source / drain layer is further solved, thereby achieving a wraparound contact.

[0118] According to an embodiment of the present invention, a method for manufacturing a semiconductor device is further provided, comprising:

[0119] A method for controlled source-drain confinement epitaxy on a gate-all-around device according to any one of the aforementioned embodiments of the present invention.

[0120] According to an embodiment of the present invention, a semiconductor device is further provided, which is manufactured using the method for manufacturing a semiconductor device of the present invention.

[0121] According to an embodiment of the present invention, there is also provided an electronic device including a semiconductor device of the present invention.

[0122] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for controlled source-drain confinement epitaxy on a gate-all-around device, characterized in that: include: providing a substrate; forming a plurality of fin structures arranged along a first direction and a shallow trench isolation structure between adjacent fin structures on the substrate; forming a plurality of dummy gate structures arranged along a second direction on the plurality of fin structures, wherein each dummy gate structure spans across each of the plurality of fin structures; Etching the fin structure to form a plurality of source / drain cavities; forming a first isolation layer arranged along the first direction between adjacent fin structures to isolate the source / drain cavities between the adjacent fin structures; epitaxially growing a source / drain layer in the source / drain cavity; removing the first isolation layer; The first direction and the second direction are perpendicular to each other.

2. The method for controlled source-drain confinement epitaxy on a gate-all-around device according to claim 1, wherein: The thickness of the first isolation layer is adapted to the thickness of the source / drain layer.

3. The method for controlled source-drain confinement epitaxy on a gate-all-around device according to claim 1, wherein: The height of the first isolation layer is not lower than that of the fin structure.

4. The method for controlled source-drain confinement epitaxy on a gate-all-around device according to claim 3, wherein: The material of the first isolation layer is SiO2.

5. The method for controlled source-drain confinement epitaxy on a gate-all-around device according to any one of claims 1 to 3, wherein: The forming of the first isolation layer arranged along the first direction between adjacent fin structures specifically includes: depositing isolation layers in the plurality of source / drain cavities; performing CMP treatment on the isolation layer; The isolation layer after the CMP treatment is subjected to photolithography and etching, and only the isolation layer between adjacent fin structures is retained to form the first isolation layer.

6. The method for controlled source-drain confinement epitaxy on a gate-all-around device according to claim 3, wherein: The material of the source / drain layer is SiGe.

7. The method for controlled source-drain confinement epitaxy on a gate-all-around device according to claim 1, wherein: After etching away the first isolation layer, the method further includes: An interlayer dielectric layer is formed on the source / drain layer and the shallow trench isolation structure.

8. A method for preparing a semiconductor device, characterized in that: include: The method for controlled source-drain confinement epitaxy on a gate-all-around device according to any one of claims 1 to 7.

9. A semiconductor device, characterized in that: The semiconductor device is manufactured using the method for manufacturing a semiconductor device according to claim 8. 10 . An electronic device comprising the semiconductor device according to claim 9 .

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