Semiconductor memory device

Abstract

Embodiments provide a semiconductor storage device that is easily miniaturized. The semiconductor storage device of the embodiments has a first electrode and a second electrode, a phase change layer provided between the first electrode and the second electrode, and a first layer provided between the first electrode and the phase change layer. The phase change layer contains at least one of germanium (Ge), antimony (Sb), and tellurium (Te), and the first layer contains aluminum (Al) and antimony (Sb), or tellurium (Te), and at least one of zinc (Zn), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

Description

[0001] [Cross-reference to related applications]

[0002] This application claims priority to Japanese Patent Application No. 2021-008890 (filed on January 22, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Technology

[0004] A semiconductor memory device is known, comprising a first electrode and a second electrode, and a phase change layer disposed between the first electrode and the second electrode. The phase change layer may include, for example, germanium (Ge), antimony (Sb), and tellurium (Te). Summary of the Invention

[0005] The problem to be solved by the present invention is to provide a semiconductor memory device that is easy to miniaturize.

[0006] A semiconductor memory device according to one embodiment includes a first electrode and a second electrode, a phase change layer disposed between the first electrode and the second electrode, and a first layer disposed between the first electrode and the phase change layer. The phase change layer includes at least one of germanium (Ge), antimony (Sb), and tellurium (Te), and the first layer includes at least one of aluminum (Al) and antimony (Sb), or tellurium (Te), and zinc (Zn), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

[0007] One embodiment of a semiconductor memory device includes a first electrode and a second electrode, a phase change layer disposed between the first electrode and the second electrode, and a first layer disposed between the first electrode and the phase change layer. The phase change layer comprises a cubic crystal, and the first layer comprises a zincblende-type structure or a face-centered cubic lattice crystal. Attached Figure Description

[0008] Figure 1 This is a schematic circuit diagram showing a portion of the semiconductor memory device according to the first embodiment.

[0009] Figure 2 This is a schematic perspective view showing a portion of the configuration of the semiconductor memory device according to the first embodiment.

[0010] Figure 3A This is a schematic cross-sectional view of the memory cell MC of the semiconductor memory device according to the first embodiment.

[0011] Figure 3B This is a schematic cross-sectional view of the memory cell MC of the semiconductor memory device according to the first embodiment.

[0012] Figure 4 This is a schematic graph showing the current-voltage characteristics of the memory cell MC of the semiconductor memory device according to the first embodiment.

[0013] Figure 5A This is a schematic cross-sectional view used to illustrate the write operation of the storage unit MC in the first embodiment.

[0014] Figure 5B This is a schematic cross-sectional view used to illustrate the write operation of the storage unit MC in the first embodiment.

[0015] Figure 6A This is a schematic cross-sectional view used to illustrate the write operation of the memory cell MC in the comparative example.

[0016] Figure 6B This is a schematic cross-sectional view used to illustrate the write operation of the memory cell MC in the comparative example.

[0017] Figure 7A This is a schematic cross-sectional view of the memory cell MC of the semiconductor memory device in Variation Example 1.

[0018] Figure 7B This is a schematic cross-sectional view of the memory cell MC of the semiconductor memory device in Variation Example 1.

[0019] Figure 8A This is a schematic cross-sectional view of the memory cell MC of the semiconductor memory device in Variation Example 2.

[0020] Figure 8B This is a schematic cross-sectional view of the memory cell MC of the semiconductor memory device in Variation Example 2.

[0021] Figure 9 This is a schematic circuit diagram showing a portion of the semiconductor memory device according to the second embodiment.

[0022] Figure 10 This is a schematic cross-sectional view of the resistance changing element section VRP of the semiconductor memory device according to the second embodiment.

[0023] Figure 11 This is a schematic cross-sectional view of the resistance changing element section VRP2 of a semiconductor memory device in a variation example. Detailed Implementation

[0024] Next, the semiconductor memory device according to embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the scope of the invention. Additionally, the following drawings are schematic diagrams, and for ease of explanation, some components may be omitted. Furthermore, common parts in multiple embodiments are labeled with the same symbols, and descriptions may sometimes be omitted.

[0025] In addition, in this specification, the specified direction parallel to the substrate surface is called the X direction, the direction parallel to the substrate surface and perpendicular to the X direction is called the Y direction, and the direction perpendicular to the substrate surface is called the Z direction.

[0026] In addition, in this specification, the direction along a specified surface is sometimes referred to as the first direction, the direction along the specified surface and intersecting the first direction is referred to as the second direction, and the direction intersecting the specified surface is referred to as the third direction. The first, second, and third directions may correspond to any one of the X, Y, and Z directions, or they may not correspond.

[0027] Furthermore, in this specification, expressions such as "upper" or "lower" are based on the substrate. For example, when the first direction intersects the substrate surface, the direction away from the substrate along the first direction is called "upper," and the direction closer to the substrate along the first direction is called "lower." Additionally, when referring to a certain configuration as a lower surface or lower end, it means the surface or end of that configuration on the substrate side; when referring to an upper surface or upper end, it means the surface or end of that configuration on the side opposite to the substrate. Furthermore, surfaces intersecting with the second or third direction are called side surfaces, etc.

[0028] Furthermore, in this specification, when it is mentioned that the first component is "electrically connected to" the second component, it can mean that the first component is directly connected to the second component, or that the first component is connected to the second component via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in an OFF state, the first transistor is "electrically connected to" the third transistor.

[0029] In addition, when the first component and the second component are referred to as "electrically insulated" in this specification, it means, for example, that an insulating layer is provided between the first component and the second component, and that no connection or wiring is provided between the first component and the second component.

[0030] In addition, when this specification mentions that a circuit or the like "makes" two wirings "conduct", it sometimes means, for example, that the circuit or the like includes a transistor or the like, which is disposed in the current path between the two wirings, and that the transistor or the like is in a conducting (ON) state.

[0031] Hereinafter, the circuit configuration of the semiconductor memory device according to the embodiments will be described with reference to the accompanying drawings. Furthermore, the following drawings are schematic diagrams, and for ease of explanation, some configurations may be omitted.

[0032] [First Implementation]

[0033] [Brief Structure]

[0034] Figure 1 This is a schematic circuit diagram showing a portion of the semiconductor memory device according to the first embodiment. Figure 2 This is a schematic perspective view showing a portion of the configuration of the semiconductor memory device according to the first embodiment.

[0035] The semiconductor memory device of this embodiment includes a memory cell array (MCA) and peripheral circuitry (PC) for controlling the MCA.

[0036] For example, such as Figure 2 As shown, the memory cell array MCA has multiple memory pads MM arranged in the Z direction. Each memory pad MM has bit lines BL, word lines WL, and memory cells MC. Multiple bit lines BL are arranged in the X direction and extend in the Y direction. Multiple word lines WL are arranged in the Y direction and extend in the X direction. Correspondingly, multiple memory cells MC are arranged in both the X and Y directions, corresponding to the bit lines BL and word lines WL. As shown, either the bit line BL or the word line WL can be commonly set for two memory pads MM arranged in the Z direction. Figure 1 In this example, the cathode EC of the memory cell MC is connected to the bit line BL. Additionally, the anode EA of the memory cell MC is connected to the word line WL. The memory cell MC includes a resistance-changing element VR and a non-linear element NO.

[0037] The peripheral circuit PC is connected to the bit line BL and the word line WL. The peripheral circuit PC includes, for example, a buck converter, a selection circuit, a sense amplifier circuit, and a sequencer that controls them. The buck converter reduces the power supply voltage and outputs it to the voltage supply line. The selection circuit connects the bit line BL and the word line WL corresponding to the selected address to the corresponding voltage supply line. The sense amplifier circuit outputs data 0 or 1 based on the voltage or current of the bit line BL.

[0038] [Composition of a storage unit (MC)]

[0039] Figure 3A and Figure 3B This is a schematic cross-sectional view of the storage unit MC in this embodiment. Figure 3A This corresponds to the memory cell MC where the bit line BL is located at the bottom and the word line WL is located at the top. Figure 3B This corresponds to the memory cell MC where the word line WL is located at the bottom and the bit line BL is located at the top.

[0040] Figure 3A The memory cell MC shown includes a conductive layer 102, a chalcogenide layer 103, a conductive layer 104, a barrier conductive layer 105, a crystallization promoting layer 106, a chalcogenide layer 107, a barrier conductive layer 108, and a conductive layer 109 sequentially deposited on a barrier conductive layer 101 on the upper surface of the bit line BL. A barrier conductive layer 110 on the lower surface of the word line WL is disposed on the conductive layer 109.

[0041] The barrier conductive layer 101 functions as part of the potential line BL. The barrier conductive layer 101 can be, for example, tungsten nitride (WN), titanium nitride (TiN), or other conductive layers such as tungsten carbonitride (WCN) or tungsten carbonitride silicon alloy (WCNSi).

[0042] The conductive layer 102 is connected to the bit line BL located directly below the memory cell MC, and functions as the cathode EC of the memory cell MC. The conductive layer 102 can be, for example, carbon (C), carbon nitride (CN), or tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), vanadium (V), vanadium nitride (VN), zirconium (Zr), zirconium nitride (ZrN), hafnium (Hf), hafnium nitride (HfN), yttrium (Y), yttrium nitride (YN), scandium (Sc), scandium nitride (ScN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), rhenium (Re), niobium (Nb), aluminum (Al), etc. Furthermore, the conductive layer 102 can be, for example, polycrystalline silicon implanted with N-type impurities such as phosphorus (P), or other conductive layers such as tungsten carbide (WC), tungsten carbonitride (WCN), or tungsten carbonitride silicon alloy (WCNSi).

[0043] The chalcogenide layer 103 functions as a nonlinear element NO. For example, when a voltage below a specified threshold is applied to the chalcogenide layer 103, the chalcogenide layer 103 is in a high-resistance state. When the voltage applied to the chalcogenide layer 103 reaches the specified threshold, the chalcogenide layer 103 becomes a low-resistance state, and the current flowing through the chalcogenide layer 103 increases by a multi-digit number. If the voltage applied to the chalcogenide layer 103 is lower than the specified voltage for a certain period of time, the chalcogenide layer 103 becomes a high-resistance state again.

[0044] The chalcogen layer 103 may contain at least one chalcogenide. The chalcogen layer 103 may also contain compounds containing chalcogenides. Furthermore, the chalcogen layer 103 may contain at least one element selected from the group consisting of B, N, Al, Zn, Ga, In, C, Si, Ge, Sn, As, P, and Sb.

[0045] Furthermore, the chalcogenides mentioned here include all elements in Group 16 of the periodic table except for oxygen (O). Examples of chalcogenides include sulfur (S), selenium (Se), and tellurium (Te).

[0046] The conductive layer 104 functions as an electrode connecting the nonlinear element NO and the resistance-changing element VR. The conductive layer 104 may also contain, for example, the same material as the conductive layer 102.

[0047] The barrier conductive layer 105 may also contain, for example, the same material as the barrier conductive layer 101.

[0048] The crystallization promoting layer 106 is in contact with the cathode EC side of the chalcogenide layer 107, and functions as a crystallization substrate (template) capable of controlling the crystal structure of the chalcogenide layer 107. The crystallization promoting layer 106 may contain, for example, a cubic crystal. The cubic crystal may be, for example, a zincblende structure crystal, an fcc (Face-Centered Cubic) lattice structure crystal (hereinafter referred to as "fcc crystal"), etc. The crystallization promoting layer 106 has at least one layer containing the constituent atoms described below.

[0049] In addition, the crystallization promoting layer 106 also functions as a heater, supplying the chalcogen layer 107 with the heat required for the setting and resetting operations described below. To effectively function as a heater, the crystallization promoting layer 106 comprises a material with a large band gap, i.e., exhibiting low electrical conductivity, as described below.

[0050] In addition, the crystallization promoting layer 106 also functions as a heat shield. To prevent the Joule heat generated in the crystallization promoting layer 106 from escaping to the chalcogen layer 103, the crystallization promoting layer 106 contains a material with low thermal conductivity, as described below.

[0051] The chalcogen layer 107 functions as a resistance changing element VR. For example, the chalcogen layer 107 can be made into an amorphous state (reset state: high resistance state) by heating above the melting temperature and then rapidly cooling it. Alternatively, the chalcogen layer 107 can be made into a crystalline state (set state: low resistance state) by heating at a temperature below the melting temperature but above the crystallization temperature.

[0052] The chalcogen layer 107 may contain at least one chalcogenide. The chalcogen layer 107 may also contain compounds containing chalcogenides, i.e., chalcogenides. The chalcogen layer 107 may also be, for example, GeSbTe, GeCuTe, GeTe, SbTe, SiTe, etc. Furthermore, the chalcogen layer 107 may also contain at least one element selected from germanium (Ge), antimony (Sb), and tellurium (Te). Additionally, the chalcogen layer 107 may also contain nitrogen (N), carbon (C), boron (B), etc.

[0053] The barrier conductive layer 108 may also contain, for example, the same material as the barrier conductive layer 101.

[0054] The conductive layer 109 is connected to the word line WL located directly above the memory cell MC, and functions as the anode EA of the memory cell MC. The conductive layer 109 may also contain, for example, the same material as the conductive layer 102.

[0055] The barrier conductive layer 110 functions as part of the word line WL. The barrier conductive layer 110 may also contain, for example, the same material as the barrier conductive layer 101.

[0056] Figure 3B The storage cell MC shown is basically the same as Figure 3A The storage unit MC shown is similarly constructed. However, in Figure 3B In the memory cell MC shown, the barrier conductive layer 110, rather than the barrier conductive layer 101, functions as part of the bit line BL, and the barrier conductive layer 101, rather than the barrier conductive layer 110, functions as part of the word line WL. Additionally, the conductive layer 109, rather than the conductive layer 102, functions as the cathode EC, and the conductive layer 102, rather than the conductive layer 109, functions as the anode EA.

[0057] [Electrical characteristics of memory cell MC]

[0058] Figure 4 This is a schematic graph showing the current-voltage characteristics of the memory cell MC in this embodiment. The horizontal axis represents the voltage of the anode EA (hereinafter referred to as "cell voltage Vcell") based on the voltage of the cathode EC of the memory cell MC. The vertical axis represents the current flowing in the memory cell MC (hereinafter referred to as "cell current Icell") in logarithmic form.

[0059] Within a range where the cell current Icell is less than the specified current value I1, the cell voltage Vcell monotonically increases as the cell current Icell increases. At the point where the cell current Icell reaches the current value I1, the cell voltage Vcell of the memory cell MC in the low-resistance state reaches voltage V1. Conversely, the cell voltage Vcell of the memory cell MC in the high-resistance state reaches voltage V2. Voltage V2 is greater than voltage V1.

[0060] Within the range where the cell current Icell is greater than the current value I1 but less than the current value I2, the cell voltage Vcell monotonically decreases as the cell current Icell increases. Within this range, the cell voltage Vcell of the memory cell in the high-resistance state is greater than the cell voltage Vcell of the memory cell MC in the low-resistance state.

[0061] Within the range where the cell current Icell is greater than the current value I2 and less than the current value I3, as the cell current Icell increases, the cell voltage Vcell temporarily decreases and then increases. Within this range, as the cell current Icell increases, the cell voltage Vcell of the memory cell MC in the high-resistance state decreases sharply, becoming the same as the cell voltage Vcell of the memory cell MC in the low-resistance state.

[0062] Within the range where the unit current Icell is greater than the current value I3, as the unit current Icell increases, the unit voltage Vcell temporarily decreases and then increases.

[0063] When the unit current Icell is rapidly reduced to a value less than the current I1 from this state, the chalcogenide layer 107 becomes a high-resistance state. Conversely, when the unit current Icell is reduced to a specified value and maintained for a certain period before being reduced again, the chalcogenide layer 107 becomes a low-resistance state.

[0064] [action]

[0065] Figure 5A and Figure 5B This is a schematic cross-sectional view used to illustrate the write operation of the storage unit MC in this embodiment. Figure 5A and Figure 5B In the example, a set operation and a reset operation are shown as write operations. A set operation changes the resistance of the memory cell MC from a high-resistance state to a low-resistance state. A reset operation changes the resistance of the memory cell MC from a low-resistance state to a high-resistance state.

[0066] Figure 5A This indicates the state of the memory cell MC after a reset operation. Figure 5B This indicates the state of the memory cell (MC) after the configuration action has been performed.

[0067] Furthermore, in the following description, an example will be given where the main component of the chalcogen layer 107 is Ge2Sb2Te5.

[0068] If yes Figure 5B If the storage unit MC shown performs a reset action, then as follows: Figure 5A As shown, an amorphous chalcogenide layer 107_a is formed within the chalcogenide layer 107. During a reset operation, for example, the cell voltage Vcell is adjusted to be greater than the voltage V2. Figure 4The reset voltage Vreset is applied. Current flows through the storage cell MC, generating Joule heat in the chalcogen layer 107. Additionally, the crystallization promoting layer 106 also generates significant Joule heat, which is supplied to the chalcogen layer 107. This is because the crystallization promoting layer 106 has a higher resistance than the chalcogen layer 107. The magnitude of the Joule heat at this point is sufficient to melt the entire chalcogen layer 107. Next, the cell voltage Vcell is reduced to 0V. Joule heat is no longer supplied to the chalcogen layer 107, and the molten chalcogen layer 107 cools rapidly. During this period, the chalcogen layer 107 is not given the time required for crystallization. As a result, the chalcogen layer 107 solidifies in an amorphous state (reset state: high resistance state), forming an amorphous chalcogen layer 107_a.

[0069] If yes Figure 5A If the storage unit MC shown performs a setting action, then as follows: Figure 5B As shown, the amorphous chalcogenide layer 107_a transforms into a crystalline chalcogenide layer 107_c. During the setup operation, for example, the cell voltage Vcell is adjusted to a setup voltage Vset that is less than the reset voltage Vreset, and this state is maintained for a certain period of time. As a result, current flows through the storage cell MC, and Joule heat is supplied to the chalcogenide layer 107_a. The Joule heat at this time is sufficient to crystallize the chalcogenide layer 107_a without melting it. Furthermore, the setup voltage Vset is maintained for the time required for the chalcogenide layer 107_a to crystallize. Then, the cell voltage Vcell is set to 0V. Thus, the amorphous chalcogenide layer 107_a transforms into a crystalline chalcogenide layer 107_c (setup state: low resistance state).

[0070] Furthermore, during the setup process, the crystallization of Ge2Sb2Te5 in the chalcogenide layer 107 is based on the crystallization plane of the cubic crystals contained in the crystallization promotion layer 106, such as zincblende crystals or fcc crystals. Therefore, the Ge2Sb2Te5 in the chalcogenide layer 107_c is primarily formed as a cubic fcc crystal.

[0071] Similarly, if for Figure 5B When the storage cell MC shown is reset, the crystalline chalcogenide layer 107_c becomes the amorphous chalcogenide layer 107_a. Additionally, if... Figure 5A When the storage cell MC shown is configured, the amorphous chalcogenide layer 107_a is transformed into the crystalline chalcogenide layer 107_c.

[0072] [Comparative Example]

[0073] Figure 6A and Figure 6BThis is a schematic cross-sectional view used to illustrate the write operation of the memory cell MC in the comparative example. The memory cell MC in the comparative example is basically constructed the same as the memory cell MC in the first embodiment. However, the memory cell MC in the comparative example does not have the crystallization promoting layer 106.

[0074] Figure 6A This indicates the state of the memory cell MC after a reset operation. Figure 6B This indicates the state of the memory cell (MC) after the configuration action has been performed.

[0075] As shown in Figure 6, the setup and reset operations of the memory cell MC in the comparative example are performed in the same manner as those in the memory cell MC of the first embodiment. However, after the setup operation, the memory cell MC in the comparative example forms a chalcogenide layer 107_c' instead of a chalcogenide layer 107_c.

[0076] In the comparative example, the storage cell MC takes longer to crystallize from chalcogenide layer 107_a to chalcogenide layer 107_c' during setup compared to the first embodiment. This is because, since a crystallization promoting layer 106 is not provided adjacent to chalcogenide layer 107_c', a reference plane for the crystal growth of chalcogenide layer 107_a is absent, and the constituent atoms of chalcogenide layer 107 move freely among themselves. This is because, in this state, crystal nuclei that act as seed crystals repeatedly generate and disappear within chalcogenide layer 107, resulting in a longer crystallization time. Furthermore, because the crystallization promoting layer 106, which controls the orientation during crystal growth to chalcogenide layer 107_c', is not provided, it is difficult to generate fcc crystals in chalcogenide layer 107_c'.

[0077] Furthermore, the comparative example's storage cell MC does not have a crystallization promoting layer 106 that functions as a heater. As a result, the heat required for the setting and resetting operations cannot be efficiently supplied to the chalcogen layer 107, and the time required to complete the setting and resetting operations is longer compared to the first embodiment.

[0078] Furthermore, the comparative example's memory cell MC does not have a crystallization promoting layer 106 that also functions as a heat shield. As a result, the Joule heat generated in the chalcogen layer 107 tends to escape to the chalcogen layer 103 side, and the time required to complete the setting and resetting operations is longer compared to the first embodiment.

[0079] [Effect]

[0080] In order to perform high-speed write operations, the setup and reset operations must be made faster.

[0081] For high-speed setup operations, a shorter time until the chalcogen layer 107 completes crystallization is particularly preferred.

[0082] Therefore, in this embodiment, for example, refer to Figure 3A and Figure 3B As explained above, a crystallization promoting layer 106 containing cubic crystals is provided on the cathode EC side of the chalcogenide layer 107. With this structure, as described above, during the setting operation, crystals with a cubic fcc structure can be generated at high speed in the chalcogenide layer 107.

[0083] Next, in order to perform a high-speed resetting operation, it is preferable that the total heat required for melting the crystallized chalcogen layer 107_c is relatively small, and that the molten heat can be effectively supplied to the chalcogen layer 107_c.

[0084] The total heat required to melt the chalcogenide layer 107_c varies depending on the crystal structure and composition of the chalcogenide layer 107_c. Therefore, Ge2Sb2Te5 can be cited as an example of chalcogenide layer 107 below.

[0085] Ge₂Sb₂Te₅ possesses an hcp (hexagonal close-packed) lattice structure as its stable state and an fcc lattice structure as its metastable state. It is known that Ge₂Sb₂Te₅ with the fcc lattice structure melts with less thermal energy than Ge₂Sb₂Te₅ with the hcp lattice structure. Therefore, the presence of a large number of fcc-structured crystals in the chalcogenide layer 10⁷⁻¹ reduces the total heat required for melting.

[0086] However, generating FCC lattice structure crystals in the chalcogenide layer 107_c can sometimes be difficult. In particular, the proportion of HCP lattice structure crystals may increase when setting operations are performed after prolonged use when the overall temperature of the semiconductor memory device rises.

[0087] Therefore, in this embodiment, as described above, a crystallization promoting layer 106 comprising cubic crystals is provided. With this configuration, as described above, during the setting operation, Ge2Sb2Te5 with an fcc lattice structure can be stably generated in the chalcogenide layer 107_c. As a result, during the resetting operation, the total heat required for melting the chalcogenide layer 107_c can be reduced, enabling a high-speed resetting operation.

[0088] [Composition of crystallization promoting layer 106]

[0089] [Crystal structure of crystallization promoting layer 106]

[0090] For reference Figure 3A and Figure 3B As explained above, the crystallization promoting layer 106 includes crystals with a cubic zincblende structure, fcc crystals, etc.

[0091] Examples of materials constituting the zincblende structure crystal include AlSb (0.614 nm) and ZnTe (0.611 nm) (the lattice constants of the zincblende structure crystals formed by each material are in parentheses). The crystallization promoting layer 106 may also contain, for example, aluminum (Al) and antimony (Sb), or tellurium (Te) and zinc (Zn) constituting these materials.

[0092] Examples of materials that constitute fcc crystals include LaTe (0.642nm), CeTe (0.636nm), PrTe (0.632nm), NdTe (0.626nm), SmTe (0.659nm), EuTe (0.659nm), GdTe (0.614nm), TbTe (0.610nm), DyTe (0.609nm), HoTe (0.605nm), ErTe (0.606nm), TmTe (0.604nm), YbTe (0.635nm), and LuTe (0.595nm) (the values ​​in parentheses are the lattice constants of the fcc crystals formed by these materials). The crystallization promoting layer 106 may also include, for example, at least one of the following constituting these materials: tellurium (Te), zinc (Zn), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

[0093] Furthermore, the lattice constant of the zincblende structure crystals or FCC crystals contained in the crystallization promoting layer 106 is ideally close to the lattice constant of the FCC crystals contained in the chalcogenide layer 107_c. This is because having similar lattice constants allows for better control of the crystal structure of the crystals contained in the chalcogenide layer 107_c. Particularly preferred is that the lattice constant of the crystals contained in the crystallization promoting layer 106 is greater than 90% and less than 110% of the lattice constant of the crystals contained in the chalcogenide layer 107.

[0094] For example, consider the case where the chalcogenide layer 107 contains Ge2Sb2Te5. The fcc crystal of Ge2Sb2Te5 has a lattice constant of 0.598 nm, therefore, it is preferable that the crystal contained in the crystallization promoting layer 106 also has a lattice constant of the same degree. Materials used as the crystallization promoting layer 106 include, for example, AlSb (0.614 nm), ZnTe (0.611 nm), LaTe (0.642 nm), CeTe (0.636 nm), PrTe (0.632 nm), NdTe (0.626 nm), GdTe (0.614 nm), TbTe (0.610 nm), DyTe (0.609 nm), HoTe (0.605 nm), ErTe (0.606 nm), TmTe (0.604 nm), YbTe (0.635 nm), LuTe (0.595 nm), etc. (the lattice constants are in parentheses).

[0095] Furthermore, consider the case where the chalcogenide layer 107 contains GeCu2Te3. The lattice constant of the fcc crystal of GeCu2Te3 is 0.599 nm, so it is preferable that the crystal contained in the crystallization promoting layer 106 also has a lattice constant of the same degree. Materials used as the crystallization promoting layer 106 include, for example, AlSb (0.614 nm), ZnTe (0.611 nm), LaTe (0.642 nm), CeTe (0.636 nm), PrTe (0.632 nm), NdTe (0.626 nm), SmTe (0.659 nm), EuTe (0.659 nm), GdTe (0.614 nm), TbTe (0.610 nm), DyTe (0.609 nm), HoTe (0.605 nm), ErTe (0.606 nm), TmTe (0.604 nm), YbTe (0.635 nm), LuTe (0.595 nm), etc. (lattice constants are in parentheses).

[0096] Furthermore, when the chalcogenide layer 107 contains other materials, it is also preferable that the lattice constant of the crystal contained in the crystallization promoting layer 106 is greater than 90% and less than 110% of the lattice constant of the crystal contained in the chalcogenide layer 107.

[0097] Furthermore, the composition ratios of each material in the chalcogen layer 107 and the crystallization-promoting layer 106 can be observed, for example, by methods such as EDS (Energy Dispersive X-ray Spectrometry). Alternatively, the composition ratios obtained by methods such as EDS can be approximated using methods such as the least squares method or by performing moving average processing, and the composition ratios can be determined based on the results.

[0098] Furthermore, the crystal structure and lattice constant of the crystals contained in the chalcogenide layer 107 and the crystallization promotion layer 106 can be determined, for example, by methods such as NBD (Nano Beam Diffraction).

[0099] [Melting point of crystallization promoting layer 106]

[0100] As described above, during the reset operation, the chalcogen layer 107 is melted. Here, when the crystallization promoting layer 106 functions as a heater, the heat in the crystallization promoting layer 106 is greater than the heat in the chalcogen layer 107 during the reset operation. If the crystallization promoting layer 106 melts simultaneously with the chalcogen layer 107, there is a concern that the constituent elements may mix, altering the properties of each layer and causing problems in subsequent writing operations. Therefore, the melting point of the crystallization promoting layer 106 is preferably high enough to prevent it from melting during the reset operation. For example, the melting point of the crystallization promoting layer 106 is preferably about 300°C higher than the melting point of the chalcogen layer 107. At least, the melting point of the crystallization promoting layer 106 is preferably higher than the melting point of the chalcogen layer 107.

[0101] For example, consider the case where the chalcogenide layer 107 contains Ge2Sb2Te5. The melting point of the fcc crystal of Ge2Sb2Te5 is 630°C, therefore, the melting point of the crystallization promoting layer 106 is preferably higher than 630°C. More preferably, the melting point of the crystallization promoting layer 106 is higher than 930°C. Materials for the crystallization promoting layer 106 that meet these conditions are preferably, for example, AlSb (1060°C), ZnTe (1295°C), LaTe (1720°C), CeTe (1820°C), PrTe (1950°C), NdTe (2025°C), SmTe, EuTe (1526°C), GdTe (1825°C), TbTe, DyTe (1850°C), HoTe (1370°C), ErTe (1500°C), TmTe, YbTe (1730°C), LuTe, etc. (the melting points are in parentheses).

[0102] Furthermore, when the chalcogenide layer 107 contains other materials, it is also preferable that the melting point of the material contained in the crystallization promoting layer 106 is higher than that of the material contained in the chalcogenide layer 107. More preferably, the melting point of the crystallization promoting layer 106 is about 300°C higher than that of the chalcogenide layer 107.

[0103] Furthermore, the melting points of the materials contained in the chalcogenide layer 107 and the crystallization-promoting layer 106 can be determined, for example, by using TEM (Transmission Electron Microscope) to perform cross-sectional observation while the memory cell MC is heated, and measuring the temperature at which the crystal structure cannot be maintained. Additionally, the melting points of each material can be estimated based on literature values, etc.

[0104] [Band gap and conductivity of crystallization promoting layer 106]

[0105] As described above, when the crystallization promoting layer 106 functions as a heater, it is preferable that the crystallization promoting layer 106 has low conductivity, i.e., a larger band gap. Particularly preferable is that the band gap of the crystallization promoting layer 106 is larger than that of the chalcogen layer 107. The crystallization promoting layer 106 and the chalcogen layer 107 are connected in series, and the current flowing during operation is the same. By making the conductivity of the crystallization promoting layer 106 lower than that of the chalcogen layer 107, the temperature rise of the crystallization promoting layer 106 is greater than that of the chalcogen layer 107. Therefore, the crystallization promoting layer 106 functions more effectively as a heater.

[0106] For example, consider the case where the chalcogenide layer 107 contains Ge2Sb2Te5. The band gap of Ge2Sb2Te5 is 0.4 eV, therefore the band gap of the crystallization promoting layer 106 is preferably higher than 0.4 eV. Materials for the crystallization promoting layer 106 that meet these conditions are preferably, for example, AlSb (1.58 eV), ZnTe (2.26 eV), etc. (the melting points of each material are in parentheses).

[0107] Furthermore, when the chalcogen layer 107 contains other materials, it is also preferable that the band gap of the material contained in the crystallization promoting layer 106 is higher than that of the material contained in the chalcogen layer 107.

[0108] Furthermore, the band gap of the material contained in the crystallization promoting layer 106 can be determined, for example, by methods such as absorption spectroscopy.

[0109] [Thermal conductivity of crystallization promoting layer 106]

[0110] As described above, the crystallization promoting layer 106 also functions as a heat shield to efficiently utilize the heat required for the write operation. For it to function as a heat shield, a crystallization promoting layer 106 with low thermal conductivity is preferred. Particularly preferred is that the thermal conductivity of the crystallization promoting layer 106 is lower than that of the chalcogenide layer 107. This is to prevent the Joule heat generated in the crystallization promoting layer 106 from escaping towards the chalcogenide layer 103.

[0111] Furthermore, the thermal conductivity of the materials contained in the chalcogenide layer 107 and the crystallization promoting layer 106 can be estimated from literature values ​​based on measured values ​​of the composition, crystal structure, etc. of their constituent materials.

[0112] [Example 1 of the variation of the first embodiment]

[0113] [Composition of a storage unit (MC)]

[0114] Figure 7A and Figure 7B This is a schematic cross-sectional view of the storage unit MC of Variation Example 1 of the first embodiment. Figure 7A This corresponds to the memory cell MC where the bit line BL is located at the bottom and the word line WL is located at the top. Figure 7B This corresponds to the memory cell MC where the word line WL is located at the bottom and the bit line BL is located at the top.

[0115] like Figure 7A and Figure 7B As shown, the memory cell MC of this embodiment, like that of the first embodiment, includes a conductive layer 102, a chalcogenide layer 103, a conductive layer 104, a barrier conductive layer 105, a chalcogenide layer 107, a barrier conductive layer 108, and a conductive layer 109 sequentially deposited in the Z direction. However, unlike the first embodiment, the memory cell MC of this embodiment has a crystallization promoting layer 106_1 between the barrier conductive layer 105 and the chalcogenide layer 107 instead of the crystallization promoting layer 106. Furthermore, a crystallization promoting layer 106_2 is provided between the chalcogenide layer 107 and the barrier conductive layer 108.

[0116] Crystallization promoting layers 106_1 and 106_2 are in contact with the lower and upper surfaces of the chalcogenide layer 107, respectively. Crystallization promoting layers 106_1 and 106_2 function as a crystallization substrate (template) capable of controlling the crystal structure of the chalcogenide layer 107. By contacting the chalcogenide layer 107 from both its upper and lower surfaces, crystallization promoting layers 106_1 and 106_2 can better control the crystal structure of the chalcogenide layer 107. Furthermore, the time required for the chalcogenide layer 107 to complete crystallization can be further shortened.

[0117] Furthermore, the materials contained in crystallization promoting layers 106_1 and 106_2 may be the same as those contained in crystallization promoting layer 106 of the first embodiment. Additionally, the materials contained in crystallization promoting layers 106_1 and 106_2 may possess the same characteristics as those contained in crystallization promoting layer 106 of the first embodiment.

[0118] For example, the lattice constant of the crystals contained in the crystallization promoting layers 106_1 and 106_2 is preferably greater than 90% and less than 110% of the lattice constant of the crystals contained in the chalcogen layer 107.

[0119] Furthermore, the melting point of the materials contained in the crystallization promoting layers 106_1 and 106_2 is preferably higher than that of the chalcogen layer 107. More preferably, the melting point of the crystallization promoting layer 106 is about 300°C higher than that of the chalcogen layer 107.

[0120] Furthermore, the band gap of the material contained in the crystallization promoting layers 106_1 and 106_2 is preferably higher than the band gap of the material contained in the chalcogen layer 107.

[0121] In addition, the thermal conductivity of the materials contained in the crystallization promoting layers 106_1 and 106_2 is preferably lower than that of the chalcogen layer 107.

[0122] [Example 2 of the variation of the first embodiment]

[0123] [Composition of a storage unit (MC)]

[0124] Figure 8A and Figure 8B This is a schematic cross-sectional view of the storage unit MC in Variation Example 2 of the first embodiment. Figure 8A This corresponds to the memory cell MC where the bit line BL is located at the bottom and the word line WL is located at the top. Figure 8B This corresponds to the memory cell MC where the word line WL is located at the bottom and the bit line BL is located at the top.

[0125] like Figure 8A and Figure 8B As shown, the memory cell MC of this embodiment is similar to that of the first embodiment, comprising a conductive layer 102, a chalcogenide layer 103, a conductive layer 104, a barrier conductive layer 105, a barrier conductive layer 108, and a conductive layer 109 sequentially deposited in the Z direction. However, unlike the first embodiment, the memory cell MC of this embodiment has multiple alternating crystallization promoting layers 106_3 and multiple chalcogenide layer 107_1 deposited between the barrier conductive layer 105 and the barrier conductive layer 108.

[0126] Multiple crystallization promoting layers 106_3 are respectively in contact with the lower and upper surfaces of multiple chalcogenide layers 107_1. The multiple crystallization promoting layers 106_3 function as a crystallization substrate (template) capable of controlling the crystal structure of the chalcogenide layers 107_1.

[0127] In this variation, compared to the first embodiment, by dividing the chalcogenide layer 107_1 into multiple layers and thinning the thickness of each chalcogenide layer 107_1, the multiple chalcogenide layers 107_1 can be melted in a shorter time. Furthermore, by providing multiple crystallization promoting layers 106_3 in contact with the upper and lower surfaces of each thinned chalcogenide layer 107_1, the crystal structure of the chalcogenide layer 107_1 can be better controlled. Additionally, by making the chalcogenide layer 107_1 into multiple thinned layers, the time required for all multiple chalcogenide layers 107_1 to complete crystallization is shortened compared to the first embodiment.

[0128] Furthermore, the material contained in the crystallization promoting layer 106_3 may be the same as that contained in the crystallization promoting layer 106 of the first embodiment. Additionally, the material contained in the crystallization promoting layer 106_3 may possess the same characteristics as that contained in the crystallization promoting layer 106 of the first embodiment.

[0129] For example, the lattice constant of the crystal contained in the crystallization promoting layer 106_3 is preferably greater than 90% and less than 110% of the lattice constant of the crystal contained in the chalcogen layer 107_1.

[0130] Furthermore, the melting point of the material contained in the crystallization promoting layer 106_3 is preferably higher than that of the chalcogen layer 107_1. More preferably, the melting point of the crystallization promoting layer 106_3 is about 300°C higher than that of the chalcogen layer 107_1.

[0131] Furthermore, the band gap of the material contained in the crystallization promoting layer 106_3 is preferably higher than that of the material contained in the chalcogen layer 107_1.

[0132] In addition, the thermal conductivity of the material contained in the crystallization promoting layer 106_3 is preferably lower than that of the chalcogen layer 107_1.

[0133] [Other variations of the first embodiment]

[0134] refer to Figure 3A , Figure 3B , Figure 7A , Figure 7B , Figure 8A and Figure 8B The configuration described is for illustrative purposes only, and the specific configuration can be adjusted accordingly.

[0135] For example, in Figure 3A In the example shown, the crystallization promoting layer 106 can also be configured to be in contact with the anode EA side of the chalcogenide layer 107. That is, in Figure 3A In this configuration, the crystallization promoting layer 106 can also be disposed between the chalcogenide element layer 107 and the barrier conductive layer 108. Additionally, in... Figure 3B In the example shown, the crystallization promoting layer 106 can also be configured to be in contact with the cathode EC side of the chalcogenide layer 107. That is, in Figure 3B In this process, the crystallization promoting layer 106 can also be disposed between the chalcogen element layer 107 and the barrier conductive layer 108.

[0136] Additionally, in reference Figure 3A , Figure 3B , Figure 7A , Figure 7B , Figure 8A and Figure 8B In the illustrated example, a crystallization promoting layer 106 may also be provided on the sidewall portion of the chalcogenide layers 107 and 107_1 in at least one of the X and Y directions. In this case, the crystallization promoting layer 106 may or may not be provided on at least one of the upper and lower surfaces of the chalcogenide layers 107 and 107_1.

[0137] [Second Implementation]

[0138] [Brief Structure]

[0139] Next, refer to Figure 9 and Figure 10 The semiconductor memory device of the second embodiment is described. Figure 9 This is a schematic circuit diagram showing a portion of the semiconductor memory device according to the second embodiment. Figure 10 This is a schematic cross-sectional view of the resistance changing element section VRP in this embodiment.

[0140] like Figure 9 As shown, the semiconductor memory device of this embodiment includes a memory cell array MCA2 and peripheral circuitry PC2 for controlling the memory cell array MCA2. The memory cell array MCA2 includes multiple word lines WL2, multiple plate lines PL, and multiple bit lines BL2. Additionally, the memory cell array MCA2 may include, for example, multiple memory cells MC2.

[0141] The peripheral circuit PC2 is the same as in the first embodiment, for example, including a step-down circuit, a selection circuit, a sense amplifier circuit, and a sequencer that controls these circuits.

[0142] The memory cell MC2 is connected to the bit line BL2, the word line WL2, and the board line PL, respectively. For example, multiple memory cells MC2 connected to the same word line WL2 are connected to the same board line PL. On the other hand, multiple memory cells MC2 connected to the same word line WL2 are each connected to different bit lines BL2. The memory cell MC2 includes a field-effect transistor Tr and a resistance-varying element VRP.

[0143] Transistor Tr includes a gate terminal connected to word line WL2, a drain terminal connected to bit line BL2, and a source terminal connected to one end of the resistance-varying element section VRP, i.e., node N1. Transistor Tr has the function of selecting the memory cell MC2 that is being operated on.

[0144] like Figure 10 As shown, the resistance changing element VRP includes a conductive layer 202, a barrier conductive layer 205, a crystallization promoting layer 106-4, a chalcogenide layer 107, a barrier conductive layer 208, and a conductive layer 209 sequentially deposited on a semiconductor substrate (not shown). The conductive layers 202, 205, 208, and 209 are substantially aligned with a reference substrate. Figure 3A and Figure 3B The conductive layer 102, barrier conductive layer 105, barrier conductive layer 108, and conductive layer 109 described herein are similarly constructed. However, in Figure 3A and Figure 3B In the example, the widths of conductive layer 102, barrier conductive layer 105, barrier conductive layer 108, and conductive layer 109 in the X and Y directions are the same as the widths of crystallization promoting layer 106 and chalcogen element layer 107 in the X and Y directions. On the other hand, in Figure 10 In the example, the widths of conductive layer 202, barrier conductive layer 205, barrier conductive layer 208, and conductive layer 209 in the X and Y directions are greater than the widths of crystallization promoting layer 106_4 and chalcogen layer 107 in the X and Y directions. Furthermore, conductive layer 202 is connected to node N1, and not to bit line BL or word line WL. Similarly, conductive layer 209 is connected to board line PL, and not to word line WL or bit line BL.

[0145] The crystallization promoting layer 106_4 is in contact with the lower surface of the chalcogenide layer 107. The crystallization promoting layer 106_4 functions as a crystallization substrate (template) capable of controlling the crystal structure of the chalcogenide layer 107.

[0146] Furthermore, the material contained in the crystallization promoting layer 106_4 may be the same as the material contained in the crystallization promoting layer 106 of the first embodiment. Additionally, the material contained in the crystallization promoting layer 106_4 may possess the same characteristics as the material contained in the crystallization promoting layer 106 of the first embodiment.

[0147] For example, the lattice constant of the crystal contained in the crystallization promoting layer 106_4 is preferably greater than 90% and less than 110% of the lattice constant of the crystal contained in the chalcogen layer 107.

[0148] Furthermore, the melting point of the material contained in the crystallization promoting layer 106_4 is preferably higher than that of the chalcogen layer 107. More preferably, the melting point of the crystallization promoting layer 106 is about 300°C higher than that of the chalcogen layer 107.

[0149] Furthermore, the band gap of the material contained in the crystallization promoting layer 106_4 is preferably higher than the band gap of the material contained in the chalcogen layer 107.

[0150] In addition, the thermal conductivity of the material contained in the crystallization promoting layer 106_4 is preferably lower than that of the chalcogen layer 107.

[0151] [action]

[0152] First, the write operation performed on the memory cell MC2 in this embodiment will be explained. By applying an ON voltage to the word line WL2 connected to the target memory cell MC2 and an OFF voltage to the other word lines WL2, the transistor Tr of the target memory cell MC2 is set to the ON state, and the other transistors Tr are set to the OFF state. Next, for example, a write voltage and a ground voltage are applied to the bit line BL2 and board line PL connected to the target memory cell MC2, respectively. As a result, current is supplied to the resistance-changing element VRP of the target memory cell MC2, and data is written in the same way as in the setting operation.

[0153] Next, the read operation of this embodiment will be described. Similar to the write operation, the transistor Tr of the target memory cell MC is set to the ON state, and all other transistors Tr are set to the OFF state. Next, for example, a read voltage and a ground voltage are applied to the board line PL and bit line BL2 connected to the target memory cell MC, respectively. Next, the current flowing in the bit line BL2 or the voltage level of the bit line BL2 is detected to determine the data stored in the target memory cell MC.

[0154] [Example of a variation of the second embodiment]

[0155] Figure 11 This is a schematic cross-sectional view of the resistance changing element section VRP2 in a variation of the second embodiment.

[0156] like Figure 11 As shown, the resistance changing element section VRP2 in this variation example is basically constructed the same as the resistance changing element section VRP in the second embodiment. However, in Figure 11 In the resistance changing element section VRP2 shown, two crystallization promoting layers 106_5 are respectively provided in place of crystallization promoting layer 106_4, in a manner that is in contact with the upper and lower surfaces of the chalcogen element layer 107.

[0157] The crystallization promoting layer 106_5 functions as a crystallization substrate (template) capable of controlling the crystal structure of the chalcogen layer 107.

[0158] Furthermore, the material contained in the crystallization promoting layer 106_5 may be the same as that contained in the crystallization promoting layer 106 of the first embodiment. Additionally, the material contained in the crystallization promoting layer 106_5 may possess the same characteristics as that contained in the crystallization promoting layer 106 of the first embodiment.

[0159] For example, the lattice constant of the crystal contained in the crystallization promoting layer 106_5 is preferably greater than 90% and less than 110% of the lattice constant of the crystal contained in the chalcogen layer 107.

[0160] Furthermore, the melting point of the material contained in the crystallization promoting layer 106_5 is preferably higher than that of the chalcogen layer 107. More preferably, the melting point of the crystallization promoting layer 106 is about 300°C higher than that of the chalcogen layer 107.

[0161] Furthermore, the band gap of the material contained in the crystallization promoting layer 106_5 is preferably higher than the band gap of the material contained in the chalcogen layer 107.

[0162] In addition, the thermal conductivity of the material contained in the crystallization promoting layer 106_5 is preferably lower than that of the chalcogen layer 107.

[0163] [Other Implementation Methods]

[0164] The semiconductor memory devices of the first and second embodiments have been described above. However, the semiconductor memory devices described are merely illustrative, and the specific configuration may be adjusted accordingly.

[0165] For example in Figure 1 and Figure 2 In this example, two memory pads MM are arranged along the Z-direction. The lower memory pad MM has a lower bit line BL and an upper word line WL, while the upper memory pad MM has a lower word line WL and an upper bit line BL. Furthermore, the word line WL is shared by both the lower and upper memory pads MM. However, this configuration is only one example; for instance, it could also be... Figure 2 Replace the bit line BL shown with the word line WL, and... Figure 2 The word line WL shown is replaced with the bit line BL.

[0166] [Other] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope or spirit of the invention, and are included within the scope of the invention as set forth in the claims and its equivalents.

[0167] [Explanation of Symbols]

[0168] 102: Conductive layer

[0169] 103: Chalcogenide layer

[0170] 104: Conductive layer

[0171] 106: Crystallization promoting layer

[0172] 107: Chalcogenide layer

[0173] 109: Conductive layer

[0174] MC: Storage Unit

[0175] MCA: Memory Cell Array

[0176] PC: Peripheral circuit.

Claims

1. A semiconductor memory device comprising: The first electrode and the second electrode; and Multiple phase transition layers and multiple first layers are alternately disposed between the first electrode and the second electrode; and The phase transition layer contains at least one of germanium (Ge), antimony (Sb), and tellurium (Te). The first layer includes Aluminum (Al) and antimony (Sb), or Tellurium (Te), and at least one of zinc (Zn), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb) and lutetium (Lu).

2. The semiconductor memory device according to claim 1, wherein The first layer contains a crystal with a first lattice constant. The phase transition layer comprises a crystal with a second lattice constant. The first lattice constant is greater than 90% of the second lattice constant, but less than 110%.

3. The semiconductor memory device according to claim 1, wherein... The melting point of the first layer is higher than that of the phase change layer.

4. The semiconductor memory device according to claim 1, wherein The band gap of the first layer is larger than the band gap of the phase change layer.

5. The semiconductor memory device according to claim 1, wherein... The thermal conductivity of the first layer is lower than that of the phase change layer.

6. The semiconductor memory device according to claim 1, wherein The first layer contains cubic crystals.

7. The semiconductor memory device according to claim 1, wherein The phase transition layer comprises cubic crystals.

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