Time-to-digital converter based on memory cell ring

Abstract

In the described example, a memory cell ring includes circularly coupled memory cells. Each memory cell (201) includes: a respective capacitor (Ccp) for generating a respective integrated voltage in response to a respective duration of selecting the respective memory cell; a respective threshold converter (240) for generating a respective threshold signal for indicating whether the respective integrated voltage has crossed a threshold; and a respective selection circuit system (210) configured to generate a respective selection signal in response to a selection signal generated by a respective adjacent memory cell. The ring is coupled to a corresponding selection circuit system for generating a conversion value (TDC‑OUT) in response to the generated respective integrated voltage and the respective selection signal. <n:1>The loop is coupled to an analog quantizer (140) for generating a cycle count value (TDC‑OUT) in response to changes in the values ​​of at least some of the corresponding threshold signals.<M+3:N+1> ) of a cycle counter (130). The conversion value and the cycle count value may include a time measurement (TDC-OUT<M+3+N:1> ).< / n:1>

Description

Background Art

[0001] In some electronic systems, digital circuits are arranged to control and / or measure the electrical quantities of various electronic circuits (e.g., analog circuits). In some such electronic circuits, timing information of electronic signals is measured and converted to numerical values. The measurements can be used to control and / or monitor the timing of the generation of the electronic signals being measured. The stability, resolution, and speed of such measurements and conversions are limited by the size, speed, and power consumption of the various components used in the conversions. Summary of the invention

[0002] In the described examples, a ring of memory cells includes circularly coupled memory cells. Each memory cell includes: a respective capacitor for generating a respective integrated voltage in response to a respective duration of selecting the respective memory cell; a respective threshold converter for generating a respective threshold signal for indicating whether the respective integrated voltage has crossed a threshold; and a respective selection circuit system configured to generate a respective selection signal in response to a selection signal generated by a respective adjacent memory cell. The ring is coupled to an analog quantizer for generating conversion values ​​in response to the generated respective integrated voltages and respective selection signals. The ring is coupled to a cycle counter for generating cycle count values ​​in response to changes in the values ​​of at least some of the respective threshold signals. The conversion values ​​and the cycle count values ​​may include time measurements. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 is a system diagram showing an example of a time-to-digital converter (TDC) based on a bidirectional memory cell ring, including analog-to-digital converters and cycle counters for respectively generating less significant bits and more significant bits of the resulting conversion.

[0004] Figure 2 is a system diagram showing an example bidirectional storage unit of a time-to-digital converter (TDC).

[0005] Figure 3 It is a waveform diagram of the bidirectional operation of the example six storage unit ring.

[0006] Figure 4 is a system diagram showing an example bidirectional memory cell ring-based time-to-digital converter (TDC) coupled to a phase frequency detector (PFD).

[0007] Figure 5A and Figure 5B is an instance map containing columns of instance values ​​generated in response to operation of a loop counter.

[0008] Figure 6 is a schematic diagram of an example analog sampling circuit of an example time-to-digital converter (TDC) based on a bidirectional memory cell ring.

[0009] Figure 7 is included Figure 4 A waveform diagram of the waveform of an example simulation of an example system.

[0010] Figure 8 is included Figure 7 Waveform plot of the waveform of an example simulation at a smaller scale.

[0011] Fig. 9 is included Figure 4 A waveform diagram of the waveform of an example double-sampling simulation of an example system.

[0012] Fig.10 is included Fig. 9 Waveform plot of the waveform of an example simulation at a smaller scale.

[0013] Fig.11 is used for Figure 4 A flow chart of an example method for time-to-digital conversion of an example system. DETAILED DESCRIPTION

[0014] In the drawings, like reference numerals refer to like elements, and the various features are not necessarily drawn to scale.

[0015] Various electronic circuits include analog-to-digital converters for converting a time domain signal into a threshold signal (e.g., which may include at least one numerical value, code, number, or value). Such circuits may be used in various end-user applications (e.g., stopwatches, signal conditioning, and feedback control). The techniques described herein may be applied to nearly any such end-user application. One such application includes at least one digital phase-locked loop (PLL) circuit, wherein an oscillation frequency of the PLL is compared to a frequency of a reference signal, at least one feedback signal is generated in response to an amount of the reference signal, and an oscillation of the PLL is controlled in response to the feedback signal. The oscillation of the PLL may be controlled so as to match the frequency of the reference signal (e.g., lock to the frequency of the reference signal).

[0016] The digital PLL includes a time-to-digital converter (TDC). The TDC may be configured to convert a time or phase difference between a reference clock and a feedback clock (e.g., generated in response to a previous value of a feedback signal). The time or phase difference is converted into a corresponding digital code. The digital code is processed by calculation to generate a feedback signal. The feedback signal is input by an oscillator that generates a feedback clock. The oscillator is configured to tune the frequency of the oscillator in response to the feedback signal (e.g., so that the feedback clock is a feedback control clock controlled by the feedback signal, and so that the feedback clock is locked to the reference clock).

[0017] The TDC is adapted to receive an indication of a phase relationship (e.g., a phase offset) between an output reference clock and a feedback control clock. The indication of the phase relationship between the reference clock and the feedback control clock includes an indication of a start time and an indication of a stop time. In response to the indication of the phase relationship, the TDC is adapted to convert a time difference between two events represented in the analog domain (e.g., a rising or falling edge of the reference clock and a rising or falling edge of the feedback control clock) into a discrete value in the digital domain. For example, time may be measured as an approximate value in an infinitesimal analog domain and converted by the TDC into a digital code. The performance of a particular kind of TDC may make the particular kind of TDC suitable or unsuitable for a particular end-user application.

[0018] The performance (e.g., accuracy, speed, or resolution) of the TDC is subject to operational limitations imposed by the technology and architecture comprised by the TDC. In a first example, the resolution (e.g., temporal resolution) of the TDC is limited by the period of a clock (e.g., a high-speed clock) used to switch a counter corresponding to an input phase error (e.g., a phase error existing between a reference clock and a feedback clock). In a second example where the TDC comprises an analog-to-digital converter (ADC), the resolution (e.g., voltage resolution) is limited by the resolution of the ADC, which is adapted to convert (e.g., sample) an input phase error voltage into a digital code (e.g., the input phase error may be converted to a corresponding voltage by a PFD charge pump).

[0019] As described herein, an example TDC includes an 8-stage bidirectional storage cell ring (BDSCR). The BDSCR can oscillate (e.g., propagate oscillations) in a first direction (e.g., clockwise, CW) or a second direction (e.g., counterclockwise, CCW). The BDSCR is adapted to oscillate in the CW or CCW direction in response to an input phase error such that the direction of the BDSCR oscillation is maintained for a duration corresponding to the input phase error. The BDSCR oscillation includes a "ring edge" (described below with respect to Figure 5A and Figure 5B Description), which indicates the leading edge of the digitally propagated oscillating signal in the cycle within the BDSCR.

[0020] During BDSCR oscillation (e.g., when the BDSCR oscillates in the CW or CCW direction), the number of ring edges is counted using a cycle counter. The BDSCR oscillation may be stopped so that a stored BDSCR oscillation quantity (e.g., an internal voltage) may be sampled. For example, the oscillation may be stopped for periodic sampling, wherein the time resolution of the TDC may be determined in response to the sampling period.

[0021] In response to the assertion signal stopping the BDSCR oscillation, two outputs of the BD-SCR (from two adjacent SCRs) hold analog voltages, and the other six outputs hold digital voltage values ​​(where each discrete voltage for representing a binary value can be generated in response to the corresponding power rail "Vdd" or "Vss"). One of the two analog voltages is sampled and forwarded to the ADC to convert the analog voltage into a corresponding digital code. The corresponding digital code indicates the value of a portion (e.g., less than the entire) propagation time (e.g., inter-cell partial propagation time) from a first storage cell to an adjacent storage cell. The ADC output value and the cycle counter value (e.g., generated each sampling period) provide a less fine resolution portion and a finer resolution portion of the output bit of the TDC, respectively (e.g., the time resolution of the conversion value of the ADC is more accurate than the time resolution of the cycle count value). The cycle counter, BDSCR, and ADC are reinitialized at each sampling period (e.g., in response to receiving a phase error input in a consecutive sampling period).

[0022] Figure 1 1 is a system diagram showing an example bidirectional memory cell loop-based time-to-digital converter (TDC) including analog-to-digital converters and cycle counters for respectively generating the less significant bits and more significant bits of the resulting conversion. In general, TDC 100 is an example TDC including loop 110, analog quantizer 140, and cycle counter 130. Loop diagram 120 is a conceptual flow diagram of loop 110.

[0023] The TDC 100 includes at least one input for receiving a signal for which its time measurement is to be determined. In an example, the two inputs are adapted to receive an up signal (UP) and a down signal (DOWN). The UP and DOWN signals may be received from a phase frequency detector (PFD), such as the PFD 450 described below. Figure 4 Describe the operation of TDC and PFD.

[0024] The TDC 100 includes an output bus for outputting digital values ​​of time measurements. In an example, the digital output of the cycle counter 130 can be cascaded as more significant bits to less significant bits output by the analog quantizer 140, so that a combined conversion result can be produced that includes a higher resolution than the resolution inherent in an ADC (e.g., ADC 444 described below) included by the analog quantizer 140. In an example, the less significant bits of a digital value (e.g., a digital word or digital output) are no more significant than the most significant bits of the digital value, and the more significant bits of the digital value are more significant than the least significant bits of the digital value.

[0025] Combining the cycle counter 130 digital output with the ADC digital output to form a higher resolution digital output (as described herein) can reduce the complexity of the ADC, which would otherwise require a complex ADC to obtain the same resolution of the ADC's digital output. In addition, the reduced complexity of the ADC facilitates a smaller layout and higher speed of the conversions performed by the ADC.

[0026] Ring 110 is an example bidirectional memory cell ring configured as a ring oscillator. Ring 110 is coupled to a timing output (eg, Figure 4 450) and includes memory cells coupled in a loop. The loop may include eight memory cells, such as memory cell 111, memory cell 112, memory cell 113, memory cell 114, memory cell 115, memory cell 116, memory cell 117, and memory cell 118. The memory cells are coupled to each other in the loop such that each memory cell has a logically adjacent memory cell in a clockwise direction and a logically adjacent memory cell in a counterclockwise direction. Each such memory cell includes a timing input coupled to receive an UP signal and a DOWN signal (e.g., coupled from a timing output of PFD 450, such as described below) such that ring 110, for example, may be selectively configured to oscillate in a clockwise or counterclockwise direction. Ring 110 is configured as a ring oscillator that is configured to begin oscillating in response to an indication of a start time and configured to stop oscillating in response to an indication of a stop time.

[0027] Each memory cell includes an input for receiving a left signal (L), a right signal (R), an S(-2) signal, and an S(+2) signal. The left signal (L) is coupled to the Dx output of the first CW-adjacent memory cell, the right signal (R) is coupled to the Dx output of the first CCW-adjacent memory cell, the S(-2) signal is coupled to the S output of the second CW-adjacent memory cell CW-adjacent to the first CW-adjacent memory cell, and the S(+2) signal is coupled to the S output of the second CCW-adjacent memory cell CCW-adjacent to the first CCW-adjacent memory cell. In an example, the first and last memory cells of the linear arrangement of memory cells may be a pair of adjacent memory cells in a memory cell ring (e.g., where the Dx output of the first cell is <1> The S output is coupled to the R input of the last cell.) The S output of each memory cell is cascaded bitwise to form a select bus S (e.g., S<8:1>). (In various examples, the adjacent memory cells are logically adjacent memory cells, where a ring edge can propagate from a first memory cell to a second memory cell without first propagating through any other memory cell, regardless of the oscillation direction of the ring edge.)

[0028] Each memory cell is configured to generate a cell select (S) signal (at the memory cell output) in response to the L signal and the R signal and to generate an analog output (Ax) signal and a digital output (Dx) signal in response to the UP signal and the DOWN signal. Fewer memory cells can be used in the ring (e.g., six memory cells total, compared to eight memory cells), but using fewer memory cells in the ring tends to increase design complexity because, for example, base seven or less arithmetic is used to count the number of memory cells that have been propagated through along the ring. Figure 2 Describes an instance storage unit.

[0029] Loop diagram 120 is a conceptual flow diagram of loop 110 for showing clockwise (CW) and counterclockwise (CCW) oscillations (e.g., propagation of oscillations) of loop 110. In an example, loop 110 is configured to selectively oscillate in a first direction during a first period of time and in a second direction during a second period of time following the first period of time. In a CW rotation, the ring propagates from node A1 (associated with storage cell 111 and node D1), then to node A8 (associated with storage cell 118 and node D8), then to node A7 (associated with storage cell 117 and node D7), then to node A6 (associated with storage cell 116 and node D6), then to node A5 (associated with storage cell 115 and node D5), then to node A4 (associated with storage cell 114 and node D4), then to node A3 (associated with storage cell 113 and node D3), then to node A2 (associated with storage cell 112 and node D2), then to node A1, then to node A8, and so on, until a sampling indication is received. In the CCW direction, the ring propagates from node A1, then to node A2, then to node A3, then to node A4, then to node A5, then to node A6, then to node A7, then to node A8, then to node A1, and so on, until a sampling indication is received. Figure 3 and Figure 5A and Figure 5B Describes ring edge propagation.

[0030] The analog (Ax) signal outputs of each memory cell are grouped together to form an analog bus A<8:1>, the digital (Dx) signal outputs of each memory cell are grouped together to form a digital bus D<8:1>, and the select (Sx) signal outputs of each memory cell are grouped together to form a state bus S<8:1>. The analog bus A<8:1> is coupled to the select input of the analog quantizer 140 (e.g., which includes eight terminals). Figure 4 and Figure 6 The operation of the analog quantizer 140 is described. The digital bus D<8:1> is coupled to the input of the cycle counter 130 (eg, which includes eight terminals). Figure 4The operation of the cycle counter 130 is described. The state bus S<8:1> is coupled to the select input of the analog quantizer (eg, it includes eight terminals). Figure 4 The operation of the analog quantizer 140 is described.

[0031] The cycle counter 130 is configured to have an “M+3” bit output bus TDC-OUT<M+3:1> (eg, 8-bit width), and the analog quantizer 140 is configured to have an N-bit (eg, 8-bit) output bus TDC-OUT <n:1>. Output bus TDC-OUT <n:1>Appended as less significant bits to the output bits of cycle counter 130 (e.g., output bus TDC-OUT<M+3+N:N+1> ) to form the output bus TDC-OUT<M+3+N:1> .

[0032] Figure 2 1 is a system diagram showing an example bidirectional memory cell of a time-to-digital converter (TDC). In general, circuit 200 is an example circuit including memory cell 201. Memory cell 201 is a memory cell such as memory cell 111. Memory cell 201 includes an analog output Ax (C_ANALOG <x>), coupled to the digital output Dx (D_DIGITAL <x>) and a selection output (Sx) coupled to the state bus S<8:1>. In an example, each memory cell 201 includes a corresponding capacitor (e.g., capacitor 225) and a corresponding switch (e.g., high-side switch 223), wherein the corresponding capacitor (e.g., capacitor 225) is configured to integrate in response to a duration during which the corresponding switch (e.g., high-side switch 223) coupled to the corresponding capacitor (e.g., capacitor 225) is closed to integrate a corresponding integrated voltage at a corresponding analog output.

[0033] The analog quantizer 140 is configured to quantize the charge pump capacitor C of the selected memory cell (eg, memory cell 201). cp The stored integrated voltage (e.g., generated in response to pumping charge) is sampled. Analog quantizer 140 includes an ADC that can be selectively coupled to any of the analog voltages of C_ANALOG<8:1>. The stored charge indicates the duration that the memory cell has been selected. The stored charge (when selected for sampling) is sampled in response to a sample and hold circuit (described below with respect to Figure 6 The hold voltage from the sample and hold circuit is converted to the bus TCD_OUT <n:1>The memory cell selected for analog-to-digital conversion is selected in response to the logic states of adjacent bits of the state bus S<8:1> (eg, where the first and last memory cells coupled in a cycle are considered adjacent).

[0034] The cycle counter 130 is configured to generate a signal for the bus TDC-OUT in response to a bit transition of the digital bus D<8:1>.<M+3+N:N+1> In general, the digital value output by the cycle counter 130 indicates the position of the ring edge as the memory cell ring oscillates, and indicates the number of memory cells that the ring edge has traversed through. In an example, the less significant portion of the digital value of D<8:1> indicates the position of the ring edge (e.g., within a cycle) as the memory cell ring oscillates, and the more significant portion of the digital value of D<8:1> can be used to indicate the number of cycles (e.g., the number of times the ring edge has traversed the entire memory cell ring). The output of the cycle counter 130 and the output of the analog quantizer 140 are cascaded to form the output bus TDC-OUT<M+3+N:1> , so that the time-to-digital conversion can be determined to have a greater (e.g., more precise) voltage resolution than the resolution of the output of the cycle counter 130. The low latency of the memory cell can increase the oscillation rate of the memory cell ring including the memory cell 201, so that, for example, 1 picosecond resolution measurements can be made (as described below with respect to Figure 7 , Figure 8 , Fig. 9 , Fig.10 describe).

[0035] The memory cell 201 includes a controller 210 , a charge pump 220 , a discharge / pre-charge circuit 230 , and a threshold converter 240 .

[0036] Controller 210 is a selection circuit including inputs coupled to receive a left signal (L), a right signal (R), a DOWN signal, and an UP signal, respectively. Controller 210 is configured to assert (at a first output) an S signal (which indicates that storage cell 201 has been selected) in response to a left adjacent cell being selected (e.g., by the L signal being digitally high) and in response to a right adjacent cell being unselected (e.g., by the R signal being digitally low). In an example, controller 210 is configured to generate a corresponding selection signal at a selection output to select a storage cell (e.g., storage cell 201, which includes controller 210) included therein in response to the value of the corresponding selection signal output of the corresponding adjacent storage cell. Controller 210 is configured to output a corresponding selection signal (e.g., Sx) at a corresponding selection signal output S. For each storage cell (e.g., 201) in a ring (e.g., 110), a corresponding selection circuit (e.g., controller 210) is configured to generate a corresponding selection signal at a selection output (e.g., Sx) of each corresponding selection circuit.

[0037] The controller 210 is configured to assert a local DOWN signal (at a second output of the controller 210) in response to the received DOWN signal and the S signal. The second output is coupled to a control terminal of a low-side switch 224 of the charge pump 220. The charge pump 220 is configured to assert a local DOWN signal in response to the local DOWN signal and the current I conducted by the current source 222. cp The charge pump capacitor C is controlled (eg, at a controlled rate) to draw the cp The voltage is the charge in the charge pump capacitor C cp The high side (eg, the charge pump 220 output node C_ANALOG <x>). The integrated voltage indicates a period corresponding to the duration of assertion of the local DOWN signal (eg, a period in which the memory cell 201 has been selected).

[0038] Controller 210 is configured to assert a local UP signal (at a third output of controller 210) in response to the received UP signal and S signal. The third output is coupled to a control terminal of high-side switch 223 of charge pump 220. Charge pump 220 is configured to assert a local UP signal in response to the local UP signal and the current I conducted by current source 221. cp While the charge pump capacitor C cp The voltage ANALOG <x>is the charge pump capacitor C cp An analog voltage generated at the high side of , which indicates a period corresponding to the duration of assertion of the local UP signal (eg, a period in which memory cell 201 has been selected).

[0039] The discharge / precharge circuit 230 is coupled to the charge pump 220 output node C_ANALOG <x>Discharge / precharge circuit 230 includes switch 234 having a control terminal coupled to the S(-2) signal, such that switch 234 is configured to discharge charge pump capacitor C in response to the S(-2) signal (e.g., in response to the memory cell coupled to the second leftmost CW neighboring memory cell being selected). cp Discharge / precharge circuit 230 includes switch 233 having a control terminal coupled to the S(+2) signal, such that switch 233 is configured to discharge charge pump capacitor C in response to the S(+2) signal (e.g., in response to the memory cell coupled to the second rightmost CCW-neighboring memory cell being selected). cp The strength (eg, current capacity) of switches 233 and 234 is stronger than the current capacity of high-side switch 223 and low-side switch 224 of charge pump 220 (eg, so that the output node C_ANALOG of charge pump 220 is <x>The memory cell ring including the memory cell 201 may be fully charged or discharged during each oscillation).

[0040] Threshold converter 240 includes a voltage coupled to output node C_ANALOG of charge pump 220. <x>The input and coupled to the output C_DIGITAL <x>The threshold converter 240 is configured to output the charge pump 220 at the output node C_ANALOG <x>The analog voltage generated at the output is converted into a digital value (e.g., bit) and output at C_DIGITAL <x>For example, the threshold converter 240 is configured to output a threshold signal. The threshold signal is output at the charge pump 220 output node C_ANALOG <x>When the voltage generated at the charge pump 220 exceeds the first threshold, the output is logic 1 (high), and the charge pump 220 output node C_ANALOG <x>The output is a logic 0 (low) when the voltage generated at the first threshold is lower than the second threshold. The first threshold is a voltage greater than or equal to the second threshold. For each storage cell (e.g., 201) in the ring (e.g., 110), a corresponding threshold converter (e.g., 240) is configured to generate a corresponding threshold signal at a corresponding digital output for indicating whether the corresponding integrated voltage has crossed the threshold.

[0041] In another example of memory cell 201, one of the inputs of the signal UP or DOWN is coupled to ground, causing the memory cell ring comprising the memory cell ring to oscillate in a single direction. In response to the input of the UP signal being coupled to ground (and the DOWN signal being asserted), the memory cell ring comprising memory cell 201 is configured to oscillate in the CCW direction (causing the charge pump 220 output node C_ANALOG <x>In response to the S(+2) signal, the charge pump 220 outputs the node C_ANALOG. <x>In response to the DOWN signal being coupled to ground (and the UP signal being asserted), the memory cell ring including memory cell 201 is configured to oscillate in the CW direction (such that the charge pump 220 output node C_ANALOG <x>In response to the S(-2) signal, the charge pump 220 is discharged and the output node C_ANALOG <x>charging in response to a DOWN signal).

[0042] In one example, each memory cell includes a corresponding selection circuit (eg, Figure 1 111 and / or Figure 2 210), which has a first input (e.g., input L) coupled to the output (output Dx) of the corresponding adjacent memory cell (e.g., 118) and a second input (e.g., input UP) coupled to the timing output, wherein each memory cell includes a corresponding capacitor (e.g., 225) and a corresponding switch (e.g., 223), the corresponding switch includes a control terminal coupled to the selection output (e.g., output UP) of the corresponding selection circuit (e.g., 210) and includes a current terminal coupled to the corresponding capacitor (e.g., 225), and wherein each memory cell (e.g., 111) includes a corresponding threshold converter (e.g., 240) having an input coupled to the corresponding capacitor (e.g., 225).

[0043] Figure 3 3 is a waveform diagram of an example bidirectional operation of an example six memory cell ring of an example TDC. Waveform 300 is an example waveform including UP, DOWN, A1, A2, A3, A4, A5, and A6 signals. Waveform 300 may be generated by an example six memory cell ring configured similarly to ring 110 including eight memory cells.

[0044] In general, the UP and DOWN signals may be generated by a phase frequency detector (e.g., PFD 450 described below). The PFD is configured to assert an UP signal in response to the phase of the feedback clock lagging behind the phase of the reference clock and to assert a DOWN signal in response to the phase of the feedback clock leading the phase of the reference clock. The feedback clock and the reference clock are generated independently, which may cause the phase of the feedback clock to drift forward and backward in time relative to the phase of the reference clock. During period 301, the phase of the feedback clock lags behind the reference clock (e.g., causing the UP signal to be asserted). During period 302, the phases of the feedback clock and the reference clock are substantially equal (e.g., substantially equal so that both the DOWN signal and the UP signal are not asserted). During period 303, the phase of the feedback clock leads the reference clock (e.g., causing the DOWN signal to be asserted). As an example, both the UP and DOWN signals are asserted during period 304 (e.g., in response to a periodic timing signal indicating that TDC timing sampling is to be performed). High resolution (eg, fine) timing information may be generated from analog values ​​stored as semaphores 343 and 353 during period 302 , and may be generated from analog values ​​stored as semaphores 326 and 336 during period 304 .

[0045] At the beginning of period 301, the DOWN signal is low (not asserted) and the UP signal transitions to high (asserted), causing the UP signal to transition from a low voltage state to a high voltage state. In response to the assertion of the UP signal, the example six memory cell ring is configured to oscillate in the CCW direction, wherein the A4 signal of the first memory cell begins to transition from a low value to a high value. In response to the A4 signal crossing the first threshold, the D4 signal is switched to high. In response to the D4 signal being switched to high, the signal S5 is switched to high, which responsively drives the S(-2) input of the first memory cell (e.g., which includes the A1 signal output) to a logic high level. In response to the signal received at the S(-2) input of the first memory cell, the A1 signal of the first memory cell discharges to a low voltage state. The other memory cells are configured to be charged and discharged in sequence similarly and continuously (e.g., in the CCW direction) so that a series of rising ring edges can propagate in a CCW cycle around the memory cell ring (e.g., where a rise of signal A4 triggers a rise of signal A5, a rise of signal A5 triggers a rise of signal A6, a rise of signal A6 triggers a rise of signal A1, a rise of signal A1 triggers a rise of signal A2, a rise of signal A2 triggers a rise of signal A3, a rise of signal A3 triggers a rise of signal A4, and so on).

[0046] In response to the L signal input of the first storage unit being driven high (e.g., by the sixth storage unit asserting the D6 signal on an output coupled to the L signal input, or by an initialization pulse generated in response to the rising edge of the UP signal), the A1 signal rises with transition 311. The A1 signal rises in response to the charge pump 220 of the first storage unit being activated in response to the UP signal. As the A1 signal rises, the voltage of the input of the converter (e.g., threshold converter 240) rises above the threshold, causing the D1 output (which is coupled to the L signal input of the second storage unit for generating A2) to be switched high (e.g., driven high). In response to the D1 output being driven high, the charge pump of the second storage unit (for driving signal A2) is activated so that (in response to the activated charge pump of the second storage unit) signal A2 rises to have transition 321.

[0047] Transition 321 is delayed by a period TST (eg, the charge pump capacitor C cp The oscillation rate of the example six memory cell ring can be determined in response to the time period TST of each memory cell. Each memory cell of the example six memory cell ring has a similar design (and is formed using the same process and the same substrate), so that the operating parameters (such as delay and drive strength) of each component of the six memory cells are similar to the corresponding components. For example, the charge pump 220 of the first memory cell can be configured to have the same structural design as the charge pump 220 in other charge pumps in the same memory cell ring.

[0048] Transition 331 is triggered in response to transition 321 (e.g., triggered in response to assertion of signal S at the output of the second storage unit, which is coupled to the signal L input of the third storage unit). In a manner similar to transition 331 being triggered by transition 321, signal A4 subsequently transitions high at transition 341 in response to transition 331.

[0049] Similarly, signal A5 then transitions high at transition 351 in response to transition 341 of signal A4. In response to transition 351 of signal A5, the controller of the fifth storage unit asserts the S signal at the output of the fifth storage unit, which is coupled to the S(-2) input of the first storage unit. In response to the S(-2) input of the first storage unit being driven high, the discharge switch (e.g., switch 234) of the first storage unit is closed so that the A1 signal is discharged to a low voltage state.

[0050] In a manner similar to the initialization of transition 351 of signal A5, signal A6 then transitions high with transition 361 in response to transition 351 of signal A5. In response to transition 361, signal A1 rises with transition 312.

[0051] Thus, in the period extending from the start of transition 311 to the start of transition 312, a sequence of ring edges has completed a full cycle (around the memory cell ring). The series of rising ring edges continues to propagate until the end of period 301 (and until the beginning of period 302), when the UP signal is driven low. The reversal of the UP signal isolates and maintains the charge pump capacitor C of each memory cell held at the instant of the reversal of the UP signal. cp Stored charge.

[0052] In the particular example shown, during period 302, signal A4 includes signal quantity 343 and signal A5 includes signal quantity 353. Signal quantity 343 indicates when the fifth storage unit has been selected (eg, during which the fifth storage unit has been primarily selected). Figure 6 An example operation of ADC conversion of signal quantity 343 is described.

[0053] At the beginning of period 303, the DOWN signal is asserted and the UP signal remains low, so that the six memory cell ring is configured to oscillate in the CW direction. In response to the assertion of the DOWN signal, the A6 signal of the sixth memory cell is initially charged to a high voltage state. In response to the S(+2) input of the second memory cell and / or in response to an initialization pulse generated by the rising edge of the DOWN signal, the A6 signal of the sixth memory cell is charged to a high voltage state. The other memory cells are similarly and continuously (e.g., in the CW direction) and are sequentially charged (e.g., so that the ring edge of the falling edge can propagate in a cycle around the memory cell ring).

[0054] In response to the R signal input of the sixth storage unit being driven low (e.g., by the first storage unit asserting a low D1 signal on an output coupled to the R signal input, or by an initialization pulse generated in response to the rising edge of the DOWN signal), the A6 signal falls with transition 364. The A6 signal falls in response to the charge pump 220 of the first storage unit being activated in response to the DOWN signal. As the A6 signal falls, the voltage of the input of the converter (e.g., threshold converter 240) falls below the threshold, causing the output D6 (which is coupled to the R signal input of the fifth storage unit for generating A5) to be switched low (e.g., driven low). In response to the D6 output being driven low, the charge pump of the fifth storage unit (for driving signal A5) is activated so that (in response to the activated charge pump of the fifth storage unit) the signal A5 falls to have transition 354.

[0055] Transition 354 is delayed by a period TST from transition 364. The oscillation rates of the example six memory cell ring on CW and CCW are substantially equal (e.g., substantially equal to within 10% of each other). Each memory cell of the example six memory cell ring has a similar design (and is formed using the same process and the same substrate), so that the operating parameters (e.g., delay and drive strength) of each component of the six memory cells are similar to the corresponding components. For example, current source 221 and current source 222 are configured to generate substantially equal (e.g., substantially equal to within 10% of each other) currents I cp .

[0056] Transition 344 of signal A4 is triggered in response to transition 354 (e.g., triggered in response to assertion of signal S at the output of the fifth storage unit, the output of the fifth storage unit being coupled to the signal R input of the fourth storage unit), causing signal A4 to fall. In a manner similar to transition 344 being triggered by transition 354, signal A3 subsequently transitions to low at transition 334 in response to transition 344.

[0057] Similarly, signal A2 then transitions low in response to transition 334 of signal A3. In response to transition 334 of signal A3, the controller of the second storage unit asserts the S signal at the output of the second storage unit, which is coupled to the S(+2) input of the sixth storage unit. In response to the S(+2) input of the second storage unit being driven high, the precharge switch (e.g., switch 233) of the first storage unit is closed such that the A1 signal is precharged to a high voltage state.

[0058] In a manner similar to the transition of signal A2, signal A1 then transitions low with transition 314 in response to the downward transition of signal A2. The start of transition 314 is delayed from the start of transition 324 by period TST 306. In response to transition 314, signal A6 falls with transition 365.

[0059] Thus, a sequence of falling edges has completed a full cycle (around the memory cell ring), where the full cycle begins at the start of transition 364 and ends at the start of transition 365. The edges continue to propagate until the end of period 303 (and the beginning of period 304), at which time the UP signal is driven high. The assertion of the UP and DOWN signals isolates and maintains (e.g., for sampling purposes) each charge pump capacitor C of each memory cell held at the instant of the UP signal's reversal. cp Stored charge.

[0060] In the particular example shown, during period 304, signal A2 includes signal quantity 326 and signal A3 includes signal quantity 336. Signal quantity 336 indicates a time when the third storage unit has been selected (e.g., the third storage unit has been primarily selected during this period). Signal quantity 326 is converted by analog quantizer 140 to a digital value that indicates a fine resolution time measurement (e.g., relative to the value generated by cycle counter 130).

[0061] Figure 4 4 is a system diagram showing an example bidirectional memory cell loop-based time-to-digital converter (TDC) coupled to a phase frequency detector (PFD). System 400 is an example system configured to measure a phase difference between a reference clock and a feedback clock, wherein the phase / frequency of the feedback clock can be adjusted in response to the phase measurement (e.g., time measurement). For example, the TDC of system 400 is an example TDC including loop 110, an analog quantizer 440 (e.g., analog quantizer 140), and a cycle counter 430 (e.g., cycle counter 130). The TDC can be configured to measure a phase difference (e.g., in time) between a reference clock signal and a feedback clock signal generated (e.g., by a digitally controlled oscillator) in response to the phase difference measurement. In general, the TDC is configured to receive an indication of a time difference (e.g., a phase difference) from a PFD (e.g., PFD 450) (e.g., at a timing input of loop 110) so that the TDC can measure the time difference in response to the indication received from PFD 450.

[0062] In an example, PFD 450 is a detector including a reference clock (REF CLK) input, a feedback clock (FB CLK) input, a PFD reset signal output, and a detector output including an UP signal output and a DOWN signal output. The detector output is coupled to a timing input of loop 110, the timing input including an UP signal input and a DOWN signal output. PFD 450 is configured to compare an input phase of a reference clock with a phase of a feedback clock. PFD 450 is configured to assert an UP signal in response to the phase of the feedback clock lagging behind the phase of the reference clock and to assert a DOWN signal in response to the phase of the feedback clock leading the phase of the reference clock. In response to the assertion of the UP and DOWN signals, loop 110 is configured to generate at least one analog signal for indicating a first measurement of the phase comparison, and is configured to generate at least one binary signal for indicating a second measurement of the phase comparison (e.g., where the second measurement has a voltage resolution that is less than the voltage resolution of the first measurement). In at least one example, the PFD 450 includes timing outputs (eg, an UP signal output and a DOWN signal output) suitable for generating an indication of a start time and an indication of a stop time.

[0063] The PFD reset signal may be asserted in response to, for example, a periodic timing signal indicating that TDC timing sampling is to be performed. The higher the speed of the TDC, the more frequently the timing samples may be measured (e.g., so that the frequency fidelity of the feedback clock to the reference clock may be improved). Concurrent assertion of the UP and DOWN signals (e.g., so that a portion of the UP signal waveform is high while a portion of the DOWN signal is high) may be in response to the PFD reset signal and / or the periodic timing signal. The periodic timing signal may be generated in response to a clock input (e.g., a reference clock) to the PFD 450.

[0064] The PFD reset output is coupled to the input of the delay chain and pulse generator 452. The delay chain and pulse generator 452 includes an output where an enable ADC (EN_ADC) signal is generated (e.g., generated by the delay chain and pulse generator 452). The SAMPLE_ADC waveform 730 (described below with respect to Figure 7 ) is an example waveform of the signal EN_ADC. In at least one example, the EN_ADC signal is a pulse generated in response to a periodic timing signal, wherein a first edge of the pulse is delayed relative to a value or value change of the periodic timing signal, and wherein a second edge of the pulse is delayed relative to the first edge of the pulse.

[0065] The EN_ADC signal output of the delay chain and pulse generator 452 is coupled to the EN_ADC signal input of the selector 442 of the analog quantizer 440 and the EN_ADC signal input of the delay chain 454. In an example, the analog quantizer 440 is configured to generate a conversion value at a conversion output in response to a selected one of the respective integrated voltages, wherein the selected one of the respective integrated voltages is selected in response to at least one of the respective select signals, and wherein the conversion value indicates a first portion of a time measurement of a duration extending from a start time to a stop time.

[0066] Selector 442 is described below with respect to Figure 6 1. The selector 442 is configured to sample a voltage generated in response to the integration of the charge of the capacitor of the selected memory cell (e.g., as sampled with a sample and hold analog circuit). The selector 442 includes a select input coupled to a corresponding digital output (e.g., a select bus S<8:1>) of the memory cell. A particular memory cell can be selected in response to a bit value (e.g., a pair of adjacent bit values) of the select bus.

[0067] The sample and hold output of selector 442 is coupled to the ADC_IN signal input of ADC 444. ADC 444 may include a resistor ladder and a comparator network such that ADC 444 is configured to output (at a conversion output) a digital value (e.g., as an N-bit value) indicative of an analog voltage generated in response to selector 442 (e.g., where the output value of ADC 444 may be generated without clocking ADC 444).

[0068] Analog quantizer 440 further includes a two's complement code generator 446, a loop direction detector 447, and a multiplexer 448. Two's complement code generator 446 includes an input coupled to the output of ADC 444 and includes an output in which two's complement code generator 446 is configured to generate a two's complement code value in response to a value output by ADC 444. In an example, analog quantizer 440 is configured to output a two's complement number in response to selection of a first direction or a second direction of ring oscillation.

[0069] Cycle direction detector 447 includes a first input (e.g., a D input) coupled to the UP output of PFD 450 and a second input (e.g., a rising edge triggered clock input) coupled to the DOWN output of PFD 450. Cycle direction detector 447 is configured to generate a cycle direction signal in response to the UP and DOWN signals. In an example, the cycle direction signal is low (logic 0) in response to a low value of the UP signal, and the cycle direction signal is high (logic 1) in response to a low-to-high transition of the DOWN signal.

[0070] Multiplexer 448 includes a first input coupled to the output of ADC 444 and includes a second input coupled to the output of two's complement generator 446. Multiplexer 448 is configured to generate a direction-adjusted ADC output (DIRECTION-ADJ.ADC_OUT) signal at the output of the multiplexer. When the cyclic direction signal is low, the direction-adjusted ADC output signal includes (in response to the cyclic direction signal) the ADC_OUT value, and when the cyclic direction signal is high, the direction-adjusted ADC output signal includes a generated two's complement value (e.g., a generated two's complement value of the ADC_OUT signal).

[0071] The delay chain 454 is configured to generate a write_clock (Write_CLK) signal at the Write_CLK signal output of the delay chain 454 (eg, in response to the signal EN_ADC). The Write_CLK waveform 740 (described below with respect to Figure 7 464) is an example waveform of signal Write_CLK. In at least one example, the Write_CLK signal is a pulse generated in response to signal EN_ADC, wherein a first edge of the pulse is delayed relative to a value or value change of signal EN_ADC, and wherein a second edge of the pulse is delayed relative to the first edge of the pulse. The Write_CLK signal output of delay chain 454 is coupled to respective Write_CLK signal inputs (e.g., clock inputs) of D-type flip-flops (DF / F or "latches") 462 and 464. The Write_CLK signal output of delay chain 454 is further coupled to the Write_CLK signal input of delay chain 456.

[0072] Latch 464 includes an n-bit ADC result input coupled to the output of ADC 444. Latch 464 is configured to latch the n-bit ADC result in response to the Write_CLK signal. Latch 464 includes an n-bit TDC-OUT signal in which the latched n-bit ADC result is asserted. <n:1>Output. TDC-OUT<M+3+N:1> TDC-OUT of bus <n:1>The portion contains the less significant bits of the time period being measured (eg, as determined by analog-to-digital conversion).

[0073] Latch 462 includes an "M+3" bit long cycle counter 430 result input coupled to an "M+3" bit cycle counter output. The "M+3" bit output value is a fixed point number indicating an integer number of completed oscillation cycles (indicated by the more significant "M" bits, where "M" is the number of bits indicating the maximum number of cycles that can be counted) and a fraction (e.g., less than 1 fraction) of incomplete oscillation cycles (indicated by the less significant "+3" bits, where "+3" is the binary exponent of the number of storage cells in ring 110). Latch 462 is configured to latch the "M+3" bit cycle counter result in response to the Write_CLK signal. Latch 462 includes an "M+3" bit TDC-OUT latch in which the latched "M+3" bit long cycle counter result is asserted.<M+3+N:N+1> Output. TDC-OUT<M+3+N:1> TDC-OUT of bus <n:1>The portion contains the less significant bits of the time period being measured (eg, as determined by analog-to-digital conversion).

[0074] The delay chain 456 is configured to generate a clear counter (CLR_COUNTER) signal at the CLR_COUNTER signal output of the delay chain 456 (eg, in response to the signal Write_CLK). The CLR_COUNTER waveform 750 (described below with respect to Figure 7 454 is an example waveform of the signal CLR_COUNTER. In at least one example, the CLR_COUNTER signal is a pulse generated in response to the signal Write_CLK, wherein a first edge of the pulse is delayed relative to a value or a change in value of the signal Write_CLK, and wherein a second edge of the pulse is delayed relative to the first edge of the pulse. The CLR_COUNTER signal output of the delay chain 454 is coupled to corresponding CLR_COUNTER signal inputs of a toggle flip-flop (TF / F or "latch") 431 and an M-bit counter 435.

[0075] The cycle counter 430 includes a latch 431, an M-bit counter 435, an EX-NOR gate 432, a full adder 433, a full adder 434, and a multiplexer 436. The inputs of the latch 431 are digital inputs coupled to the respective digital outputs of each storage unit in the ring 110. In example operation, the latch 431 and the M-bit counter 435 are initialized (e.g., cleared) in response to a CLR_COUNTER signal, which is asserted in response to the completion of a previous time measurement (e.g., which is generated in response to a combination of digital and analog quantities generated by the cycle counter 130 and the analog quantizer 140, respectively). Figure 5A and 5B An example operation of the cycle counter 430 is described.

[0076] In an example, an analog quantizer (e.g., 440) has analog inputs (C_ANALOG<8:1>) and digital inputs (S<8:1>), wherein each analog input is coupled to a respective one of respective capacitors (e.g., each capacitor 225 of storage cells 111 to 118 is individually coupled to the analog quantizer), and wherein each digital input is coupled to a respective one of selection outputs of a respective selection circuit (e.g., the output Sx of each of storage cells 111 to 118 is individually coupled to the analog quantizer). The output of the analog quantizer (e.g., 440) is a conversion value including a less significant bit for indicating a measurement of a duration extending from a start time to a stop time.

[0077] In an example, a cycle counter (e.g., 430) has inputs (C_DIGITAL<8:1>), where each input is coupled to a respective one of the outputs of a respective threshold converter (e.g., each respective input of the series of flip-flops of latch 431 is individually coupled to the output of threshold converter 240 of each of storage cells 111 to 118). In an example, the cycle counter (e.g., 430) is configured to generate a cycle count value in response to a change in value of at least some of the respective threshold signals, where the cycle count value indicates a second portion of a time measurement of a duration extending from a start time to a stop time. In an example, the cycle count value includes a more significant bit for indicating a measurement of a duration extending from a start time to a stop time. In an example, the cycle count value includes a number of completed cycle oscillations of the loop counted between the start time and the stop time.

[0078] Figure 5A and Figure 5B is a response to Figure 4 Graph 500 is an example diagram of columns of example values ​​generated by operation of a loop counter of . Graph 500 is an example diagram including a series of columns where the row at the beginning of the respective column includes an initial starting value (e.g., initialized in response to a CLR_COUNTER signal). Successive rows in each column show how certain values ​​in the row may change over time.

[0079] In general, each row indicates values ​​that exist simultaneously (e.g., for each row continuing through column 510, column 520, column 530, column 540, column 550, column 560, and column 570). A first group 501 of eight rows in a column shows a first cycle of oscillations in a memory cell ring (e.g., ring 110), where each row includes a value generated in response to the ring edge traversing from the first memory cell to the adjacent memory cell. A second group 502 of eight rows in a column shows a second cycle of oscillations in the memory cell ring, and a third group 503 of eight rows in a column shows a third cycle of oscillations in the memory cell ring. Reference is made below to Figure 4 , Figure 5A and Figure 5B An example operation of the cycle counter 430 is described.

[0080] Latch 431 includes a digital bus input coupled to a digital bus D<8:1>, which is generated at the C_DIGITAL<8:1> output of ring 110. Latch 431 also includes a set of positive logic outputs Q (e.g., such that each Q output is coupled from a respective output of eight storage cells) and a set of negative logic outputs Qn (e.g., such that each Qn output is coupled from a respective output of eight storage cells). The outputs Q of latch 431 are each coupled to a respective input of the eight-bit input of EX-NOR gate 432 and a respective input of the eight-bit input of full adder 433. The outputs Qn of latch 431 are coupled to the eight-bit input of full adder 434.

[0081] Latch 431 is configured to switch the output state of each output (eg, Q or Qn) in response to a changing positive voltage transition of the corresponding bit at the digital bus input of latch 431. For example, column 510 ( Figure 5A ) shows the value of the digital bus input to latch 431, and the response of latch 431 to the value of the digital bus input is shown in column 520. In the example, column 520 shows the response of latch 431 to the value of column 510, which includes values ​​showing the counter-clockwise direction of oscillation within a memory cell cycle.

[0082] EX-NOR gate 432 includes an output coupled to an input of M-bit counter 435. EX-NOR gate 432 is configured to generate (at the output of EX-NOR gate 432) an indication of a completed cycle of an oscillation ring edge in a memory cell cycle (e.g., see column 530). For example, EX-NOR gate 432 may assert an indication of a completed cycle in response to the C_DIGITAL<8:1> output of ring 110 and / or the Q output of EX-NOR gate 432. As shown in columns 520 and 530, EX-NOR gate 432 is configured to generate an initial indication (e.g., logic 1) in response to all bits of latch 431 output being a first logic state (e.g., logic 1). In an example, EX-NOR gate 432 may assert an indication of a completed cycle in response to each of the respective threshold signals C_DIGITAL<8:1> outputs having the same value (e.g., where each respective threshold signal simultaneously has the same value as the other respective threshold signals). For example, the initial indication can actually be ignored by presetting each count bit of the M-bit counter 435 to a logical 1 (e.g., so that the first indication switches the M-bit counter 435 from the preset value to an output value of 0 (zero), which indicates that a complete cycle has not occurred). In an example, the cycle count value (e.g., see Fig. 9 LOOP COUNTER 980) includes the number of completed cycle oscillations of the loop, and the number of completed cycle oscillations is incremented in response to each corresponding threshold signal having a logic state that is simultaneously the same value as the other corresponding threshold signals.

[0083] EX-NOR gate 432 is configured to generate a first indication of a first complete cycle (e.g., logic 1) in response to all bits output by latch 431 being a second logic state different from the first logic state (e.g., logic 0). EX-NOR gate 432 is configured to generate a third indication of a second complete cycle (e.g., logic 1) in response to all bits output by latch 431 being the first logic state (e.g., logic 1).

[0084] For example, determining that a cycle determined by EX-NOR (e.g., an equivalent logic function in which all input bits have the same logic state) is completed facilitates increasing the oscillation speed of the example memory cell ring because the memory state of the memory cell switches only once per cycle (e.g., such that the memory cell does not need to traverse two logic states during a single cycle of oscillation of the memory cell ring). In the example shown, the first cycle is completed in response to the ring of logic 0 to 1 transitions, and the second cycle is completed in response to the ring of logic 1 to 0 transitions.

[0085] In addition to generating an indication of the number of times a cycle oscillation has been completed, the cycle counter 430 is also configured to determine the number of cells that a partial cycle has traversed through (e.g., the number of cells traversed by the ring edge after completing a full cycle when the cycle oscillation stops). In an example, the cycle counter (e.g., cycle counter 430) includes a first partial cycle indicator generator (e.g., full adder 433), a second partial cycle indicator generator (e.g., full adder 434), and a multiplexer (e.g., multiplexer 436), the multiplexer having a first input coupled to the output of the first partial cycle indicator generator (e.g., full adder 433) and having a second input coupled to the output of the second partial cycle indicator generator (e.g., full adder 434), wherein the multiplexer (e.g., multiplexer 436) is arranged to select one of the first partial cycle indicator generator and the second partial cycle indicator generator in response to the logic state of a less significant bit of the number of times a cycle oscillation has been completed (e.g., the least significant bit of the output of the M-bit counter 435).

[0086] In an example, the propagation ring edge may include a rising edge transition (e.g., from 0 to 1) and may include a falling edge transition (e.g., from 0 to 0). A first partial cycle indicator generator (e.g., full adder 433, where full adder 433 output values ​​are shown in column 540) is configured to indicate (e.g., count) at an output the number of storage cells through which the rising transition ring edge has propagated. When the propagation ring edge includes a falling edge transition (e.g., from 0 to 1), a second partial cycle indicator generator (e.g., full adder 434, where full adder 434 output values ​​are shown in column 550) is configured to indicate (e.g., count) the number of storage cells through which the falling transition ring edge has propagated. In various examples, the partial cycle indicator generator may be a thermometer-type progress indicator.

[0087] Because (e.g.) full adder 434 indicates (e.g., as a 3-bit value) the number of memory cells through which a rising transition ring edge has propagated (e.g., propagated after a complete cycle or reset condition) and because (e.g.) full adder 434 indicates (e.g., as a 3-bit value) the number of memory cells through which a falling transition ring edge has propagated (e.g., propagated after a complete cycle or reset condition), a multiplexer 436 (e.g., MUX) is arranged to alternately select the partial cycle indicator when a full cycle is completed. The output (e.g., 3-bit output) of full adder 433 is coupled to the S(0) input (e.g., first input) of multiplexer 436, the output (e.g., 3-bit output) of full adder 434 is coupled to the S(1) input (e.g., second input), and the less significant bit (e.g., least significant bit) of M-bit counter 435 (e.g., indicating whether an odd or even number of completed cycle oscillations have been counted by M-bit counter 435) is coupled to the select input of multiplexer 436.

[0088] In an example, multiplexer 436 is arranged to select one of a first partial cycle indicator generator (e.g., full adder 433) and a second partial cycle indicator generator (e.g., full adder 434) in response to the logic state of a bit of the number of times that a cycle oscillation has been completed (e.g., where the bit indicates an odd or even number of times that a cycle oscillation has been completed). In an example, a number of storage rings (e.g., ring 110) of storage cells (e.g., any chain of storage cells 111 to 118) that switch their respective threshold signals during less than a 1 fraction of an oscillation cycle propagating during a stop time (e.g., when the ring stops oscillating) switches their respective threshold signals by including a rising transition during a first complete oscillation cycle and by including a falling transition during a consecutive second oscillation cycle following the first complete oscillation cycle. In an example, the cycle count value includes less than a 1 fraction of an oscillation cycle propagating during a stop time, wherein the less than a 1 fraction is determined in response to the number of storage cells (e.g., any chain of storage cells 111 to 118) that switch their respective threshold signals during less than a 1 fraction of an oscillation cycle propagating during a stop time.

[0089] The multiplexer 436 is configured to generate a partial cycle indication at the output of the multiplexer 436 (eg, at MUX output <3:1>) in response to an indication of the number of completed cycle oscillations.<M+3:4> The eight most significant bits of the "M+3" bit long cycle counter 430 result, for example, are shown as the "coarse count" value of column 560, and the multiplexer 436 output, for example, the least significant bits of the "M+3" bit long cycle counter 430 result, is shown as the "fine count" value of column 570. The "coarse count" of column 560 is an indication of the number of cycle oscillations that have been completed, and the "fine count" of column 570 is an indication of the number of memory cells of the ring of memory cells that the ring has propagated through.

[0090] Figure 6 6 is a schematic diagram of an example analog sampling circuit of an example bidirectional memory cell ring-based time-to-digital converter (TDC). Sampling circuit 600 is an example sampling circuit that generally includes selector 610 logic circuitry, switches 611, 612, 613, 614, 615, 616, 617, 618, and 620, and capacitors C1 and C2. For example, the switches may be low resistance analog transmission gates. The switches may be arranged as an analog multiplexer with eight inputs and one output.

[0091] Selector 610 is a logic circuit including inputs S<8:1>, which are coupled (e.g., bitwise coupled) to a state bus S<8:1>, for example, at the corresponding digital outputs of the storage cells of ring 110. Selector 610 logic circuitry is configured to generate a selection signal for sampling the stored charge of the storage cell, wherein the selector 610 selects the state bus S<8:1> in response to a signal pair (e.g., S<8:1>) transmitted by digital bus D<8:1>. <x>and S <y>, where "x" and "y" are the numbers of logically adjacent memory cells) to generate a switch selection signal. In the example, "y" is equal to "x+1".

[0092] For example, switch 611 includes a switch coupled to C_ANALOG <1> The switch 611 is configured to be coupled to the S <1> and S <2> When both are high, the switch 611 is closed. Closing the switch 611 transfers the charge to the capacitor C1, and after the switch 611 is opened, the transferred charge is stored in the capacitor C1.

[0093] In the example, switch 612 includes a switch coupled to C_ANALOG <2> The switch 612 is configured to be coupled to the S <2> and S <3> When both are high, the switch 612 is closed. Closing the switch 612 transfers the charge to the capacitor C1, and after the switch 612 is opened, the transferred charge is stored in the capacitor C1.

[0094] In the example, switch 613 includes a switch coupled to C_ANALOG <3> The switch 613 is configured to be coupled to the S output, the control input coupled to the corresponding output of the selector 610 logic circuit system, and the output coupled to the high-side node of the capacitor C1. <3> and S <4> When both are high, the switch 613 is closed. Closing the switch 613 transfers the charge to the capacitor C1, and after the switch 613 is opened, the transferred charge is stored in the capacitor C1.

[0095] In the example, switch 614 includes a switch coupled to C_ANALOG <4> The switch 614 is configured to be coupled to the S <4> and S <5> When both are high, the switch 614 is closed. Closing the switch 614 transfers the charge to the capacitor C1, and after the switch 614 is opened, the transferred charge is stored in the capacitor C1.

[0096] In the example, switch 615 includes a switch coupled to C_ANALOG <5> The switch 615 is configured to be coupled to the S <5> and S <6> When both are high, the switch 615 is closed. Closing the switch 615 transfers the charge to the capacitor C1, and after the switch 615 is opened, the transferred charge is stored in the capacitor C1.

[0097] In the example, switch 616 includes a switch coupled to C_ANALOG <6> The switch 616 is configured to be coupled to the S <6> and S <7> When both are high, the switch 616 is closed. Closing the switch 616 transfers the charge to the capacitor C1, and after the switch 616 is opened, the transferred charge is stored in the capacitor C1.

[0098] In the example, switch 617 includes a switch coupled to C_ANALOG <7> The switch 617 is configured to be coupled to the S <7> and S <8> When both are high, the switch 617 is closed. Closing the switch 617 transfers the charge to the capacitor C1, and after the switch 617 is opened, the transferred charge is stored in the capacitor C1.

[0099] In the example, switch 618 includes a switch coupled to C_ANALOG <8> The switch 618 is configured to be coupled to the S <8> and S <1> When both are high, the switch 618 is closed. Closing the switch 618 transfers the charge to the capacitor C1, and after the switch 618 is opened, the transferred charge is stored in the capacitor C1.

[0100] Switch 620 has an input coupled to the high-side node of capacitor C1 and an output coupled to the high-side node of capacitor C2 and an analog input (ADC_IN) of an ADC (eg, ADC 444). Switch 620 is configured to respond to EN_ADC (described below with respect to Figure 7 As described above, ADC 444 is configured to generate a digital value (eg, TDC-OUT <n:1>), which indicates the inter-unit partial propagation time.

[0101] The example timing resolution of the memory cell ring described herein can be determined in response to the time period TST (eg, time period TST305). Assuming the high-side power rail Vdd=1 volt, the charge pump capacitor C cp =2 picofarad, charge pump current I cp is 4 mA, and the period TST has the following relationship:

[0102]

[0103] The TST of the period is 2.5×10 -10 Assuming that the ADC output is 8 bits, the number of ADC steps (ADC_steps) is 256. The resolution (Tdc_Resolution) of the TDC can be determined in response to the time period TST and the number of ADC_steps:

[0104]

[0105] The Tdc resolution is 9.766×10 -13 seconds (which can be rounded to 1 picosecond).

[0106] Figure 7 is included Figure 4 Graph 700 includes waveforms of an example simulation of an example system of FIG. 700 using the parameters described above and the parameters selected for the target 65 nanometer process (including the technology for the memory cell ring described herein) used to manufacture the circuit. The example waveforms of graph 700 include signals UP 710, DOWN 720, SAMPLE_ADC 730, Write_CLK 740, CLR_COUNTER 750, C <1> 761, C <2> 762, C <3> 763, C <4> 764, C <5> 765, C <6> 766, C <7> 767, C <8> 768, ADC_OUT 770 and LOOP COUNTER 780.

[0107] In the example simulation, the reference clock (see, for example, Figure 4 ) is selected to lead the feedback clock by a selected phase delay (e.g., SPD) as indicated by a time difference between the assertion of signal UP 710 and the assertion of signal DOWN 720. Signal UP is asserted (e.g., as a low-to-high transition) by a PFD (e.g., PFD 450) in response to the phase of the reference clock, and signal DOWN 720 is asserted (e.g., as a low-to-high transition) by the PFD in response to a phase difference of the DOWN signal relative to the phase of signal UP 710.

[0108] Reset pulse (e.g. by Figure 4 A signal PFD_RESET generated by the PFD 450 is generated by the PFD, which is indicated in simulation as a logical AND function of the signals UP 710 and DOWN 720. SAMPLE_ADC 730 (e.g., an EN_ADC signal generated by the delay chain and pulse generator 452) is generated in response to the reset pulse (e.g., PFD_RESET), a signal Write_CLK 740 is generated in response to the signal SAMPLE_ADC 730, and a signal CLR_COUNTER 750 is generated in response to the signal Write_CLK 740.

[0109] The number of memory cell transitions "st_n" (e.g., the propagation of a ring edge from a first memory cell to a next adjacent memory cell) can be determined as st_n = round(SPD / Tst), where (for example) the number of transitions can be determined as a round function of the amount of a selected phase delay divided by the memory cell capacitor charging time. The number of transitions is captured by a cycle counter (e.g., where the number of completed cycles is output as a "coarse" output of an M-bit counter 435, and where the number of transitions for partially completed cycles is output by a multiplexer 436). Figure 7 and Figure 8 The LOOP COUNTER 780 contains a combined "coarse and fine" digital loop measurement in the analog form.

[0110] Figure 8 is included Figure 7 A waveform diagram of a waveform of an example simulation at a smaller scale. In diagram 800, C <5> The voltage (e.g., analog voltage) of C is sampled in response to the SAMPLE_ADC 730 pulse that begins at approximately 1.838 microseconds. <5> The analog sampling and holding circuit is configured to select (eg, in response to the storage cell ring S<8:1> output) the intermediate analog voltage generated by the fifth storage cell. <5> The conversion value (eg, sampled value) of the ADC and the output of the loop counter are sampled in response to asserting Write_CLK 740 at approximately 1.84 microseconds. The conversion value generated by the ADC is TDC-OUT<M+3+N:1> TDC-OUT of bus <n:1>part, and the output of the cycle counter is TDC-OUT<M+3+N:1> TDC-OUT of bus<M+3+N:N+1> The transition value indicates a first part of a time measurement (e.g., a time measurement value) of a duration between a start time and a stop time (e.g., an oscillation time of a memory cell ring), and the cycle count value indicates a second part of the time measurement of the duration between the start time and the stop time.

[0111] The output of the ADC and the binary complement of the output of the ADC are multiplexed based on the direction of the phase error.For example, the multiplexer 448 is configured to generate a selected output in response to the cyclic direction signal.

[0112] Because the ADC is configured to generate samples shortly after the memory cell ring oscillation stops and because the memory cell ring is reset after each Write_CLK 740 pulse, the voltage drop across the capacitor of each memory cell due to leakage effects does not significantly affect the minimum operating input frequency. Therefore, the frequency of the reference clock can be as high as 100 MHz. In contrast, the maximum operating frequency is usually limited by the speed of the architecture selected for the ADC.

[0113] Fig. 9 is included Figure 4 900 includes waveforms of an example simulation using the parameters described above and parameters of a target process selected for manufacturing the circuit, including the technology for the memory cell ring described herein. The example waveforms of FIG. 900 include signals UP 910, DOWN 920, SAMPLE_ADC 930, Write_CLK 940, CLR_COUNTER 950, C <1> 961, C <2> 962, C <3> 963, C <4> 964, C <5> 965, C <6> 966, C <7> 967, C <8> 968, ADC_OUT 970, LOOP COUNTER 980 and TDC_OUT 990.

[0114] In the example simulation, the reference clock (see, for example, Figure 4 ) is selected to lead the feedback clock by a selected phase difference (e.g., as indicated by a time difference between the assertion of signal UP 910 and the assertion of signal DOWN 920). Signal UP is asserted (e.g., as a low-to-high transition) by a PFD (e.g., PFD450) in response to the phase of the reference clock, and signal DOWN 920 is asserted (e.g., as a low-to-high transition) by the PFD in response to a phase difference of the DOWN signal relative to the phase of signal UP 910.

[0115] Reset pulse (e.g. by Figure 4 A signal PFD_RESET generated by the PFD 450 is generated by the PFD, which is indicated in simulation as a logical AND function of the signals UP 910 and DOWN 920. SAMPLE_ADC 930 (e.g., an EN_ADC signal generated by the delay chain and pulse generator 452) is generated in response to the reset pulse (e.g., PFD_RESET), a signal Write_CLK 940 is generated in response to the signal SAMPLE_ADC 930, and a signal CLR_COUNTER 950 is generated in response to the signal Write_CLK 940. Fig. 9 and Fig.10 The LOOP COUNTER 980 contains a combined "coarse" and "fine" digital loop measurement in analog form.

[0116] Fig.10 is included Fig. 9 A waveform diagram of the waveform of an example simulation at a smaller scale. Fig.10 In, C <5> The first sample of the voltage (eg, analog voltage) is sampled in response to the SAMPLE_ADC 930 pulse that begins at approximately 1.838 microseconds. <5> The converted value of is shown by ADC_OUT 970, which has a value of 39 (e.g., binary 00100111) for the first sample, and the value of LOOP COUNTER 980 is 00001001. <5> The conversion value (e.g., sampled value) and the output of the cycle counter are sampled in response to asserting Write_CLK 940 at approximately 1.84 microseconds. Because the cycle counter value includes more significant bits "00001001" and because the conversion value includes less significant bits "00100111", the value of TCD_OUT 990 for the first sample is "0000100100100111".

[0117] C <5> A second sample of the voltage (eg, analog voltage) is sampled in response to the SAMPLE_ADC 930 pulse that begins at approximately 1.93 microseconds. <5> The converted value of is shown by ADC_OUT 970, which has a value of 38 (e.g., binary 00100110) for the first sample, and LOOP COUNTER 980 has a value of 00001001. <5> The conversion value (e.g., sampled value) and the output of the cycle counter are sampled in response to asserting Write_CLK 940 at approximately 1.94 microseconds. Because the cycle counter value includes more significant bits "00001001" and because the conversion value includes less significant bits "00100110", the value of TCD_OUT 990 for the first sample is "0000100100100110".

[0118] Fig.11 yes Figure 4 1100 is a flowchart of an example method for time-to-digital conversion of an example system of FIG. 1100. Example method 1100 may include various techniques described below. In various embodiments, the operations described need not be performed in the order described. In example method 1100, the method may be initiated at 1102.

[0119] At 1102, the method may include receiving, by a storage unit ring, an indication of a start time and an indication of a stop time.

[0120] At 1104, the method may include oscillating, by the circularly coupled memory cells of the ring of memory cells, in response to the indication of the start time and in response to the indication of the stop time.

[0121] At 1106 , the method may include integrating, by a capacitor of a first memory cell of the circularly coupled memory cells, a voltage at an analog output in response to a duration in which the first memory cell is selected.

[0122] At 1108 , the method may include generating, by the threshold converter, a threshold signal at a digital output indicating whether the integrated voltage has crossed a threshold.

[0123] At 1110, the method may include generating, by a selection circuit at a first selection output, a first selection signal for selecting a first memory cell in response to a second selection signal for selecting a second memory cell logically adjacent to the first memory cell, the selection circuit having a selection input coupled to the selection output of the second memory cell.

[0124] At 1112, the method may include receiving, by an analog quantizer having an input coupled to an analog output, an integrated voltage. Optionally, receiving the integrated voltage may be selected in response to a first selection signal.

[0125] At 1114 , the method may include generating, by the analog quantizer, a conversion value at a conversion output in response to the integrated voltage.

[0126] At 1116 , the method may include generating, by a cycle counter having a digital input coupled to a digital output, a cycle count value in response to a change in value of the threshold signal.

[0127] At 1118, the method optionally includes generating a time measurement value in response to the conversion value and the cycle count value, wherein the conversion value indicates a finer resolution portion of the time measurement value, and wherein the cycle count value indicates a less fine resolution portion of the time measurement value.

[0128] The described embodiments can be modified and other embodiments are possible within the scope of the claims. < / y> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x>

Claims

1. A circuit comprising: a loop coupled to a timing output and having memory cells coupled in the loop, wherein each of the memory cells includes a respective selection circuit having a first input coupled to an output of a respective adjacent memory cell and a second input coupled to the timing output, wherein each of the memory cells includes a respective capacitor and a respective switch including a control terminal coupled to a selection output of the respective selection circuit and including a current terminal coupled to the respective capacitor, and wherein each of the memory cells includes a respective threshold converter having an input coupled to the respective capacitor; an analog quantizer having an analog input and a digital input, wherein each of the analog inputs is coupled to a respective one of the respective capacitors, and wherein each of the digital inputs is coupled to a respective one of the selection outputs of the respective selection circuit; and A cycle counter has inputs, with each input coupled to a respective one of the outputs of the respective threshold converter.

2. The circuit according to claim 1: wherein the timing output is adapted to generate an indication of a start time and an indication of a stop time; wherein the ring is configured as a ring oscillator configured to start oscillating in response to the indication of the start time and to stop oscillating in response to the indication of the stop time; wherein each respective capacitor is configured to integrate a respective integrated voltage at a respective analog output in response to a duration in which the respective switch coupled to the respective capacitor is closed; wherein each respective selection circuit is configured to generate a respective selection signal at the selection output of each respective selection circuit; wherein the analog quantizer is configured to produce a conversion value at a conversion output in response to a selected one of the respective integrated voltages, wherein the selected one of the respective integrated voltages is selected in response to at least one of the respective selection signals, and wherein the conversion value indicates a first portion of a time measurement of a duration extending from the start time to the stop time; wherein each respective threshold converter is configured to generate a respective threshold signal at a respective digital output for indicating whether the respective integrated voltage has crossed a threshold; and wherein the cycle counter is configured to generate a cycle count value in response to a change in value in at least some of the respective threshold signals, and wherein the cycle count value is indicative of a second portion of the time measurement of the duration extending from the start time to the stop time. 3 . The circuit of claim 2 , wherein a time resolution of the conversion value is more precise than a time resolution of the cycle count value.

4. The circuit of claim 2, wherein the cycle count value includes more significant bits for indicating a measurement of the duration extending from the start time to the stop time.

5. The circuit of claim 4, wherein the conversion value includes less significant bits for indicating the measure of the duration extending from the start time to the stop time. 6 . The circuit of claim 5 , wherein the cycle count value comprises a number of completed cycle oscillations of the loop counted between the start time and the stop time.

7. The circuit of claim 6, wherein the number of completed cycle oscillations is incremented in response to a logic state in which each respective threshold signal simultaneously has the same value as the other respective threshold signals.

8. The circuit of claim 7, wherein the cycle count value comprises a fraction less than 1 of the oscillation cycle propagating during the stop time.

9. The circuit of claim 8, wherein the fraction less than one is determined in response to a number of memory cells that switch their respective threshold signals during the fraction less than one of the oscillation cycles of the stop time propagation.

10. The circuit of claim 9, wherein the number of storage cells that switch their respective threshold signals during the fraction less than 1 of the oscillation cycle of the stop time propagation switch their respective threshold signals by including a rising transition during a first complete oscillation cycle and by including a falling transition during a consecutive second oscillation cycle following the first complete oscillation cycle.

11. The circuit of claim 10 , wherein the cycle counter further comprises a first partial cycle indicator generator, a second partial cycle indicator generator, and a multiplexer having a first input coupled to an output of the first partial cycle indicator generator and having a second input coupled to an output of the second partial cycle indicator generator, wherein the multiplexer is arranged to select one of the first partial cycle indicator generator and the second partial cycle indicator generator in response to a logic state of a less significant bit of the number of completed cycle oscillations.

12. The circuit of claim 11, wherein the ring is adapted to selectively oscillate in a first direction during a first period and in a second direction during a second period following the first period.

13. The circuit of claim 12, wherein the analog quantizer is configured to output a two's complement number in response to selection of the first direction or the second direction.

14. A system comprising: a detector adapted to receive a reference clock and a feedback control clock, wherein the detector is configured to produce an indication of a phase relationship between the reference clock and the feedback control clock at a timing output; a loop coupled to the timing output and having memory cells coupled in a loop, wherein each of the memory cells includes a respective selection circuit having a first input coupled to an output of a respective adjacent memory cell and a second input coupled to the timing output, wherein each of the memory cells includes a respective capacitor and a respective switch including a control terminal coupled to a selection output of the respective selection circuit and including a current terminal coupled to the respective capacitor, and wherein each of the memory cells includes a respective threshold converter having an input coupled to the respective capacitor; an analog quantizer having an analog input and a digital input, wherein each of the analog inputs is coupled to a respective one of the respective capacitors, and wherein each of the digital inputs is coupled to a respective one of the selection outputs of the respective selection circuit; and A cycle counter has inputs, with each input coupled to a respective one of the outputs of the respective threshold converter.

15. The system of claim 14, wherein the indication of the phase relationship between the reference clock and the feedback control clock includes an indication of a start time and an indication of a stop time, wherein each respective capacitor is configured to integrate a respective integrated voltage, wherein the analog quantizer is configured to generate a conversion value at a conversion output in response to a selected one of the respective integrated voltages, wherein the conversion value is indicative of a first portion of a time measurement of a duration extending from the start time to the stop time, wherein each respective threshold converter is configured to generate a respective threshold signal at a respective digital output for indicating whether the respective integrated voltage has crossed a threshold, wherein the cycle counter is configured to generate a cycle count value in response to a change in value of at least some of the respective threshold signals, and wherein the cycle count value is indicative of a second portion of the time measurement of the duration extending from the start time to the stop time.

16. The system of claim 15, wherein the cycle count value comprises a number of completed cycle oscillations of the loop, and wherein the number of completed cycle oscillations is incremented in response to a logic state in which each respective threshold signal simultaneously has the same value as the other respective threshold signals.

17. The system of claim 16, wherein the cycle count value comprises a fraction less than 1 of the oscillation cycles propagated during the stop time, wherein the fraction less than 1 is determined in response to a number of storage cells that toggle their respective threshold signals during the fraction less than 1 of the oscillation cycles propagated during the stop time.

18. A method comprising: receiving, by the storage unit ring, an indication of a start time and an indication of a stop time; oscillating by circularly coupled memory cells of said ring of memory cells in response to said indication of said start time and in response to said indication of said stop time; integrating an integrated voltage at an analog output by a capacitor of a first one of the circularly coupled storage cells in response to a duration during which the first storage cell is selected; generating, by the threshold converter, a threshold signal at a digital output for indicating whether the integrated voltage has crossed a threshold; generating, by a select circuit at a first select output, a first select signal for selecting the first memory cell in response to a second select signal for selecting a second memory cell logically adjacent to the first memory cell, the select circuit having a select input coupled to the select output of the second memory cell; receiving the integrated voltage by an analog quantizer having an input coupled to the analog output; generating, by the analog quantizer, a conversion value at a conversion output in response to the integrated voltage; generating a cycle count value by a cycle counter having a digital input coupled to the digital output in response to a change in value of the threshold signal; and A time measurement value is generated in response to the conversion value and the cycle count value, wherein the conversion value indicates a finer resolution portion of the time measurement value and wherein the cycle count value indicates a less fine resolution portion of the time measurement value. The method of claim 18 , wherein receiving the integrated voltage is selected in response to the first selection signal.

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