Semiconductor module and method for manufacturing a semiconductor module

Abstract

A semiconductor module includes an insulating circuit substrate having a circuit pattern formed on one surface, a semiconductor chip placed on the insulating circuit substrate, and a wiring portion electrically connecting the semiconductor chip and the circuit pattern, the wiring portion having a chip connection portion connected to the semiconductor chip, a surface of the chip connection portion having a plurality of recessed portions and a flat surface portion disposed between two of the recessed portions.

Description

Technical Field

[0001] This invention relates to a semiconductor module and a method for manufacturing the semiconductor module. Background Technology

[0002] Conventionally, semiconductor modules are known to mount semiconductor chips on an insulating circuit board and connect the semiconductor chips to the circuit patterns of the insulating circuit board using wiring portions such as lead frames. In such semiconductor modules, various resins are used for encapsulation to protect the semiconductor chips (see, for example, Patent Document 1).

[0003] Patent Document 1: WO2017 / 163583 Summary of the Invention

[0004] Technical issues

[0005] The aim is to suppress the peeling between the wiring components, such as the lead frame, and the resin encapsulation.

[0006] Technical means

[0007] To address the aforementioned issues, in one aspect of the present invention, a semiconductor module is provided. The semiconductor module may include: an insulating circuit board on one side having a circuit pattern formed thereon; a semiconductor chip disposed on the insulating circuit board; and a wiring portion electrically connecting the semiconductor chip and the circuit pattern. The wiring portion may have a chip connection portion for connection to the semiconductor chip. The surface of the chip connection portion may have a plurality of recesses. The surface of the chip connection portion may have a planar portion disposed between two recesses.

[0008] In a second aspect of the present invention, a semiconductor module is provided. The semiconductor module may include: an insulating circuit board having a circuit pattern formed on one side; a semiconductor chip mounted on the insulating circuit board; a wiring portion having at least a portion on its surface having a rough surface area with an unfolded area ratio of 0.2 or more, and connecting the semiconductor chip to the circuit pattern; and a resin encapsulation protecting the semiconductor chip.

[0009] In a third aspect of the present invention, a semiconductor module is provided. The semiconductor module may include: an insulating circuit board on which a circuit pattern is formed on one side; a semiconductor chip mounted on the insulating circuit board; a wiring portion connecting the semiconductor chip to the circuit pattern; and a resin encapsulation protecting the semiconductor chip. The wiring portion may include: a chip connection portion connected to the semiconductor chip; a circuit pattern connection portion connected to the circuit pattern; and a bridging portion connecting the chip connection portion and the circuit pattern connection portion. The chip connection portion may have a lower surface opposite to the semiconductor chip. The lower surface of the chip connection portion may have a first side furthest from the bridging portion. A step or inclined portion may be provided along the first side for more than half the length of the first side on the lower surface of the chip connection portion.

[0010] In a fourth aspect of the present invention, a semiconductor module is provided. The semiconductor module may include: an insulating circuit board having a circuit pattern formed on one side; a semiconductor chip mounted on the insulating circuit board; and a wiring portion electrically connecting the semiconductor chip and the circuit pattern. The wiring portion may have a chip connection portion for connecting to the semiconductor chip. The chip connection portion may have a main material portion. The chip connection portion may have a barrier portion formed of a material with lower solder wettability than the main material portion, and disposed exposed at its front end face.

[0011] In a fifth aspect of the present invention, a method for manufacturing a semiconductor module is provided. The semiconductor module may include: an insulating circuit board having a circuit pattern formed on one side; a semiconductor chip mounted on the insulating circuit board; and a wiring portion electrically connecting the semiconductor chip and the circuit pattern, the wiring portion possibly having a chip connection portion connected to the semiconductor chip. In the manufacturing method, a laser may be irradiated onto the surface of the chip connection portion to form a plurality of recesses and a planar portion disposed between two recesses.

[0012] In a sixth aspect of the present invention, a method for manufacturing a semiconductor module is provided. The semiconductor module may include: an insulating circuit board having a circuit pattern formed on one side; a semiconductor chip mounted on the insulating circuit board; and a wiring portion electrically connecting the semiconductor chip and the circuit pattern, the wiring portion possibly having a chip connection portion connected to the semiconductor chip. In the manufacturing method, a mold can be used to transfer a shape onto the upper surface of the chip connection portion, forming a plurality of recesses and a planar portion disposed between two recesses. Attached Figure Description

[0013] Figure 1 This is a diagram illustrating an example of a semiconductor module 100 according to one embodiment of the present invention.

[0014] Figure 2 This is a diagram showing an example of an insulating circuit board 160.

[0015] Figure 3 yes Figure 2 AA section diagram.

[0016] Figure 4 yes Figure 3 Enlarged view of lead frame 50.

[0017] Figure 5 This is an enlarged view of the vicinity of the circuit pattern connection part 56.

[0018] Figure 6 yes Figure 3 A magnified view of the vicinity of the front face 66.

[0019] Figure 7 This is a graph showing the relationship between the unfolded area ratio of the lead frame 50 and the bonding strength.

[0020] Figure 8 This is a perspective view showing other structural examples of the lead frame 50.

[0021] Figure 9 It is shown Figure 8 The diagram shows the lower surface 62 of the chip connection portion 52.

[0022] Figure 10 It is shown Figure 9 The diagram of the BB section.

[0023] Figure 11 It is shown Figure 9 The diagram of the CC section.

[0024] Figure 12 It is applicable. Figure 8 An enlarged view of the area near the front end face 66 in the case of lead frame 50.

[0025] Figure 13 This is a diagram showing another example of the lower surface 62 of the chip connection portion 52.

[0026] Figure 14 It is shown Figure 13 The diagram of the DD section.

[0027] Figure 15 It is shown Figure 13 The diagram shows the EE section.

[0028] Figure 16 This is a diagram showing another example of the lower surface 62 of the chip connection portion 52.

[0029] Figure 17 It is shown Figure 16 The diagram shows the FF section.

[0030] Figure 18It is shown Figure 16 The diagram of the GG section.

[0031] Figure 19 This is a diagram showing another example of the lower surface 62 of the chip connection portion 52.

[0032] Figure 20 It is shown Figure 19 The diagram of the HH section.

[0033] Figure 21 It is shown Figure 19 The diagram of section II in the figure.

[0034] Figure 22 This is a diagram showing the chip connection portion 152 of the reference example.

[0035] Figure 23 This is an enlarged view of the area near vertex 201 of the chip connection part 152.

[0036] Figure 24 This is a diagram showing other examples of the lead frame 50.

[0037] Figure 25 This is an enlarged view of the vicinity of the front end face 66 of the chip connection part 52.

[0038] Figure 26 This is a diagram showing an example of the recess 210 and the planar surface 212 at the front end face 66.

[0039] Figure 27 This is a diagram showing an example of the configuration of the recess 210 and the planar surface 212 at the front end face 66.

[0040] Figure 28 This is a diagram showing other configuration examples of the recess 210 and planar surface 212 at the front end face 66.

[0041] Figure 29 This is a diagram illustrating a portion of the manufacturing process of the semiconductor module 100.

[0042] Figure 30 The graph shows the measurement results of Examples 1-3 and Reference Examples 1-3.

[0043] Figure 31 This diagram illustrates the application of laser light to the chip connection section 52.

[0044] Figure 32 It is shown Figure 29 A diagram of an example of laser irradiation in S341.

[0045] Figure 33 It is shown Figure 29 Figures of other examples of laser irradiation in S341.

[0046] Figure 34 It is shown Figure 29 Figures of other examples of laser irradiation in S341.

[0047] Figure 35 It is shown Figure 29 Figures of other examples of laser irradiation in S341.

[0048] Figure 36 This is a diagram showing an example of the surface shape of the recess 210 of the front end face 66 and the recess 210 of the upper surface 64.

[0049] Figure 37 This is a diagram illustrating the shape of the recess 210 on the front end face 66 and the recess 210 on the upper surface 64.

[0050] Figure 38 This is a diagram showing an example of the configuration of the recess 210 on the upper surface 64 and the recess 210 on the front end surface 66.

[0051] Figure 39 This is a diagram showing an example of the configuration of the recess 210 on the upper surface 64 and the recess 210 on the front end surface 66.

[0052] Figure 40 This is a diagram showing an example of the configuration of the recess 210 on the upper surface 64 and the recess 210 on the front end surface 66.

[0053] Figure 41 This is a diagram showing an example of the configuration of the recess 210 on the upper surface 64 and the recess 210 on the front end surface 66.

[0054] Figure 42 This is a diagram showing other configuration examples of the recess 210 and planar surface 212 at the front end face 66.

[0055] Figure 43 This is a diagram showing other configuration examples of the recess 210 and planar surface 212 at the front end face 66.

[0056] Figure 44 This is a diagram showing other configuration examples of the recess 210 and planar surface 212 at the front end face 66.

[0057] Figure 45 This is a diagram showing other configuration examples of the recess 210 and planar surface 212 at the front end face 66.

[0058] Figure 46 This is a diagram illustrating a portion of the manufacturing process of the semiconductor module 100.

[0059] Figure 47 This diagram illustrates the shape transfer of the mold 320 onto the chip connector 52.

[0060] Figure 48 This is a diagram showing an example of the configuration of the recess 210 and the planar surface 212 on the upper surface 64.

[0061] Figure 49 This is a diagram that provides a detailed description of the shape of the recess 210 and the planar surface 212 on the upper surface 64.

[0062] Figure 50 This is a diagram illustrating a portion of the manufacturing process of the semiconductor module 100.

[0063] Figure 51 This diagram illustrates the shape of the chip connection portion 52.

[0064] Figure 52 This is a diagram showing an example of the configuration of the recess 210 and the planar surface 212 of the upper surface 64 and the front end surface 66.

[0065] Figure 53 This is a diagram showing an example of the configuration of the upper surface 64, the front end surface 66, and the recess 210 of the lower surface 62.

[0066] Figure 54 The diagram shows another example of the configuration of the obstruction zone 251.

[0067] Figure 55 It is shown Figure 54 is a diagram showing an example of the arrangement of the recessed portion 210 on the upper surface 64 and the recessed portion 210 on the front end surface 66 .

[0068] Figure 56 This is a diagram showing an example of the chip connection portion 52 of the comparative example.

[0069] Figure 57 The diagram shows another example of the configuration of the obstruction zone 251.

[0070] Figure 58 The diagram shows another example of the configuration of the obstruction zone 251.

[0071] Figure 59 It is shown Figure 58 is a diagram showing an example of the arrangement of the recessed portion 210 on the upper surface 64 and the recessed portion 210 on the front end surface 66 .

[0072] Figure 60 This diagram illustrates the irradiation of a laser onto the chip connection portion 52 of the comparative example.

[0073] Figure 61 The diagram shows another example of the configuration of the obstruction zone 251.

[0074] Figure 62 The diagram shows another example of the configuration of the obstruction zone 251.

[0075] Figure 63 The diagram shows another example of the configuration of the obstruction zone 251.

[0076] Figure 64 It is shown Figure 63 is a diagram showing an example of the arrangement of the recessed portion 210 on the upper surface 64 and the recessed portion 210 on the front end surface 66 .

[0077] Figure 65 This is a diagram illustrating the shape of the overlapping portion 332.

[0078] Figure 66 This is a diagram showing other examples of the lead frame 50.

[0079] Figure 67 This is a diagram showing an example of the configuration of the main material portion 231 and the obstruction portion 230 in the chip connection portion 52.

[0080] Figure 68 This is a diagram showing other examples of the lead frame 50.

[0081] Figure 69 It is Figure 37 An enlarged schematic diagram of the chip connection part 52.

[0082] Figure 70 This is a diagram showing other examples of the lead frame 50.

[0083] Figure 71 This is a diagram showing an example of the configuration of the obstruction portion 230 at the lower surface 62 of the chip connection portion 52.

[0084] Figure 72 It is Figure 70 and Figure 71 An enlarged schematic diagram of the chip connection part 52.

[0085] Figure 73 This is a diagram showing another configuration example of the obstruction portion 230 at the lower surface 62 of the chip connection portion 52.

[0086] Figure 74 This is a diagram showing another configuration example of the main material portion 231 and the obstruction portion 230 in the chip connection portion 52.

[0087] Figure 75 This is a diagram showing another configuration example of the main material portion 231 and the obstruction portion 230 in the chip connection portion 52.

[0088] Figure 76 This is a diagram showing another configuration example of the main material portion 231 and the obstruction portion 230 in the chip connection portion 52.

[0089] Symbol Explanation

[0090] 10. Resin housing; 12. Sealing resin; 13. Coating; 14. Resin encapsulation; 16. Cooling section; 20. Insulating substrate; 22. Heat sink; 24. Bonding layer; 26. Circuit pattern; 30, 32, 34. Bonding layer; 39. Area; 40. Semiconductor chip; 50. Lead frame (wiring section); 51. Rough surface area; 52. Chip connection part, 54···Bridge part, 56···Circuit pattern connection part, 62···Lower surface, 64···Upper surface, 65···Corner, 66···Front end face, 68···Side side, 70···Step, 71···Receding surface, 74···Opening, 81··First side, 82···Second side, 83···Third side, 84···Through hole, 86···Terminal, 88···Protrusion, 9 0··· Tilt, 94··· Space, 100··· Semiconductor Module, 152··· Chip Connector, 160··· Insulating Circuit Board, 181··· Edge, 182··· Edge, 183··· Edge, 198··· Terminal Connector, 201··· Vertex, 202··· Space, 203, 204··· Crack, 210··· Recess, 211··· Center, 212··· Planar Part 214···Recessed area, 216···Raised area, 218···Standard area, 230···Obstruction area, 231···Main material area, 251···Obstruction zone, 310···Light source, 312···Laser, 314··Bottom, 320···Mold, 322···First part, 324···Second part, 332···Overlapping part, 334···Non-overlapping part, 336···Unprocessed part Detailed Implementation

[0091] The present invention will now be described through embodiments thereof, but these embodiments do not limit the scope of the invention as defined in the claims. Furthermore, not all combinations of features described in the embodiments are necessary for the technical solution of the invention. It should be noted that in this specification and the accompanying drawings, elements having substantially the same function or structure are labeled with the same symbols, and repeated descriptions are omitted. Additionally, elements not directly related to the present invention are omitted from the illustrations. Furthermore, in a single drawing, sometimes symbols are representatively used to label elements having the same function or structure, while symbols are omitted for other elements.

[0092] In this specification, one side parallel to the depth direction of the semiconductor substrate is referred to as "upper," and the other side as "lower." Of the two main surfaces of a substrate, layer, or other component, one is referred to as the upper surface, and the other as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the actual direction in which the semiconductor device is mounted.

[0093] In this specification, rectangular coordinate axes of X, Y, and Z are sometimes used to explain technical matters. Rectangular coordinate axes merely determine the relative positions of constituent elements and do not limit specific directions. For example, the Z-axis is not limited to representing the height direction relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite directions to each other. When the Z-axis direction is described without specifying positive or negative, it refers to a direction parallel to the +Z-axis and -Z-axis. In this specification, orthogonal axes parallel to the upper and lower surfaces of the semiconductor chip are designated as the X-axis and Y-axis. Additionally, the axis perpendicular to the upper and lower surfaces of the semiconductor substrate is designated as the Z-axis. In this specification, the direction of the Z-axis is sometimes referred to as the depth direction. Furthermore, in this specification, a direction including the X-axis and Y-axis and parallel to the upper and lower surfaces of the semiconductor substrate is sometimes referred to as the horizontal direction.

[0094] In this specification, the terms "same" or "equal" may also include cases with errors caused by manufacturing deviations, etc. Such errors are, for example, within 10%.

[0095] ==This implementation method==

[0096] Figure 1 This diagram illustrates an example of a semiconductor module 100 according to one embodiment of the present invention. The semiconductor module 100 can function as a power conversion device such as an inverter. The semiconductor module 100 includes one or more insulating circuit boards 160. In this specification, the orthogonal axes in the planes on which one or more insulating circuit boards 160 are provided are designated as the X-axis and Y-axis, and the axis perpendicular to the XY plane is designated as the Z-axis. Figure 1 The image shows an example of the configuration of the components in the XY plane.

[0097] <<Description of Semiconductor Module 100>>

[0098] The semiconductor module 100 in this example has three insulating circuit boards 160, each forming an arm that constitutes a U layer, a V layer, and a W layer, respectively. One or more semiconductor chips 40 are mounted on the insulating circuit boards 160. The semiconductor chips 40 are protected by a resin encapsulation 14, such as a resin housing 10 surrounding the insulating circuit boards 160 and / or a sealing resin 12 filling the resin housing 10.

[0099] Semiconductor chip 40 may include diodes such as insulated gate bipolar transistors (IGBTs), FWD (free wheel diodes), and RC (reverse conducting)-IGBTs composed of these diodes, as well as MOS transistors.

[0100] The resin housing 10 is provided in such a way that it surrounds the space 94 containing the insulating circuit board 160. One or more terminals 86 can be exposed from the resin housing 10. The terminals 86 can be electrically connected to the insulating circuit board 160 via the terminal connection portion 198. In addition, the resin housing 10 may also be provided with through holes 84 for fastening members such as screws for fixing cooling devices to be inserted.

[0101] In this example, the resin shell 10 is molded from a thermosetting resin that can be formed by injection molding or an ultraviolet-curing resin that can be formed by UV molding. The resin may contain one or more polymeric materials selected from, for example, polyphenylene sulfide (PPS) resin, polybutylene terephthalate (PBT) resin, polyamide (PA) resin, acrylonitrile butadiene styrene (ABS) resin, and acrylic resin.

[0102] In this example, the sealing resin 12 is disposed inside the resin housing 10. The sealing resin 12 is, for example, epoxy resin or silicone, but is not limited to these. The sealing resin 12 protects the insulating circuit board 160.

[0103] Figure 2 This is a diagram showing an example of an insulating circuit board 160. While an insulating circuit board 160 constituting one phase arm is shown as a representative example here, insulating circuit boards 160 for other phases have the same configuration. In this example, the insulating circuit board 160 has a circuit pattern 26 provided on at least one side of the insulating substrate 20, and a heat sink 22 provided on the other side (see Figure 160). Figure 3 The circuit pattern 26 and the heat sink 22 can be formed by directly bonding a copper plate or an aluminum plate or a plate made of these materials to an insulating substrate 20 such as silicon nitride ceramic and / or aluminum nitride ceramic, or by bonding via a solder layer.

[0104] In this example, the semiconductor chip 40 is bonded via a solder or other bonding layer 30 (see reference). Figure 3 The semiconductor chip 40 is bonded to the circuit pattern 26 disposed on the upper surface of the insulating substrate 20. Additionally, the upper surface of the semiconductor chip 40 is bonded via a solder layer 32 (see reference 1). Figure 3 The semiconductor chip 40 is connected to the wiring section. In this example, the wiring section is the lead frame 50. The lead frame 50 allows the semiconductor chip 40 to pass through a bonding layer 34 such as solder (see reference). Figure 3It is connected to circuit pattern 26. The lead frame 50 is a component made of a metal material such as copper or aluminum. At least a portion of the surface of the lead frame 50 may also be plated with nickel or the like. Alternatively, at least a portion of the surface of the lead frame 50 may be coated with resin or the like. The lead frame 50 may have a plate-like portion. Plate-like refers to a shape where the area of ​​two opposing main surfaces is larger than the area of ​​other surfaces. At least the portion of the lead frame 50 connected to the semiconductor chip 40 may be plate-like. The lead frame 50 can be formed by bending a metal plate.

[0105] Circuit pattern 26 transmits signals or power through electrical connection with semiconductor chip 40 or lead frame 50. Circuit pattern 26 can be configured to include multiple island regions 26A, 26B, and 26C. Furthermore, multiple semiconductor chips 40 can be arranged in one island region of circuit pattern 26. Figure 2 In this example, multiple semiconductor chips 40 are disposed in island regions 26A and 26B, respectively. Furthermore, multiple semiconductor chips 40 disposed in one island region can be connected to the same island region via a lead frame 50. Figure 2 In this example, multiple semiconductor chips 40 disposed in island region 26A are connected in parallel to the same island region 26B via two lead frames 50 arranged along the Y-axis. Similarly, multiple semiconductor chips 40 disposed in island region 26B are connected in parallel to the same island region 26C via two lead frames 50 arranged along the Y-axis. The distance Y1 in the Y-axis direction between the connection portions of the two lead frames 50 connecting to the same island region 26B or the same island region 26C can be less than the distance Y2 in the Y-axis direction between the two semiconductor chips 40. This reduces the difference in the path length of the current flowing through the two separately disposed semiconductor chips 40.

[0106] In this example, the semiconductor chip 40 is a vertically shaped chip with electrodes (e.g., emitter and collector) formed on its upper and lower surfaces. The semiconductor chip 40 is connected to the circuit pattern 26 via electrodes formed on its lower surface and to the lead frame 50 via electrodes formed on its upper surface. It should be noted that the semiconductor chip 40 is not limited to a vertically shaped chip. The semiconductor chip 40 may also have electrodes on its upper surface connected to the circuit pattern 26. In this case, the circuit pattern 26 and the electrodes can be connected via wires or the like.

[0107] Terminal connection part 198 connects circuit pattern 26 with Figure 1 The terminal 86 shown is connected. The terminal connection portion 198 can be a plate or rod-shaped component formed of metal, or it can be a wire-shaped component. Thus, the semiconductor chip 40 is electrically connected to the terminal 86.

[0108] Figure 3 yes Figure 2 AA section diagram. Figure 3 This diagram shows an example of the configuration of each component when it is projected onto the XZ plane. On this side, the semiconductor module 100 includes an insulating substrate 20, a heat sink 22, a bonding layer 24, a cooling section 16, a circuit pattern 26, bonding layers 30, 32, and 34, a semiconductor chip 40, a lead frame 50, and a sealing resin 12.

[0109] The heat sink 22 may cover at least a portion or all of the lower surface of the insulating substrate 20. A bonding layer 24 bonds the heat sink 22 to the cooling section 16. The bonding layer 24 is solder or the like. The cooling section 16 contains a refrigerant such as water. The cooling section 16 cools the semiconductor chip 40 via the heat sink 22 or the like.

[0110] Circuit pattern 26 is disposed on the upper surface of insulating substrate 20. In this example, circuit pattern 26 can be formed of the same material as heat sink 22, such as copper, or it can be formed of a different material. In this example, semiconductor chip 40 is connected to the upper surface of island regions 26A and 26B of circuit pattern 26 via bonding layer 30. Bonding layer 30 bonds semiconductor chip 40 with conductive material such as solder.

[0111] In this example, the lead frame 50 connects the semiconductor chip 40 to the island regions 26B and 26C of the circuit pattern 26. The lead frame 50 has a chip connection portion 52, a circuit pattern connection portion 56, and a bridging portion 54. The chip connection portion 52 is bonded to the upper surface of the semiconductor chip 40 via a bonding layer 32. The circuit pattern connection portion 56 is connected to the upper surface of the island regions 26B and 26C of the circuit pattern 26 via a bonding layer 34. The chip connection portion 52 and the circuit pattern connection portion 56 can be plate-shaped portions that are substantially parallel to the XY plane. It should be noted that "substantially parallel" means, for example, an angle of 10 degrees or less. In this example, the area of ​​the chip connection portion 52 is configured to be larger than the area of ​​the circuit pattern connection portion 56. The area of ​​the chip connection portion 52 and the area of ​​the circuit pattern connection portion 56 can, for example, be the area of ​​the upper surface of the plate-shaped portion that connects to the semiconductor chip 40 or the island regions 26B and 26C of the circuit pattern 26.

[0112] The bridging portion 54 connects the chip connection portion 52 and the circuit pattern connection portion 56. The bridging portion 54 is disposed separately from conductive components such as the circuit pattern 26. In this example, the bridging portion 54 is disposed above the circuit pattern 26, etc., and is arranged in such a way that it extends from the chip connection portion 52 across the circuit pattern 26 to the circuit pattern connection portion 56.

[0113] The bridging portion 54 may have a bridging surface 54A (see reference) which is a plate-shaped component that is substantially parallel to the XY plane. Figure 4Additionally, the bridging portion 54 may have a foot 54B that connects the chip connection portion 52 to the bridging surface 54A (see reference). Figure 4 Additionally, the bridging portion 54 may have a foot 54C that connects the bridging surface 54A to the circuit pattern connection portion 56 (see reference). Figure 4 Foot 54B and foot 54C may be plate-like portions that are not parallel to the XY plane. For example, leg 54B and leg 54C may be formed at an angle of 45 degrees or more relative to the XY plane. In this example, foot 54B and foot 54C include portions perpendicular to the XY plane.

[0114] An opening 74 is provided in the bridging portion 54 for injecting sealing resin 12 into the lower part of the bridging portion 54 (see reference). Figure 2 In this example, the bridging portion 54 has a plurality of openings 74 located on the inner side of the XY plane of the bridging portion 54 and near the center in the X-axis direction. The plurality of openings 74 may also be located in areas other than near the center in the X-axis direction of the bridging portion 54. It should be noted that the openings 74 are not limited to the bridging portion 54, but may also be located in other parts of the lead frame 50, such as the chip connection portion 52 or the circuit pattern connection portion 56. This allows the sealing resin 12 to reliably cover the top and bottom of the lead frame 50.

[0115] The sealing resin 12 is disposed inside the resin housing 10. The sealing resin 12 can fill the space 94 of the resin housing 10 in a manner that does not expose the semiconductor chip 40, the lead frame 50, and the circuit pattern 26.

[0116] In the aforementioned semiconductor module 100, the semiconductor chip 40 serves as a heat source, and the chip connection portion 52 of the wiring connected to the semiconductor chip 40 repeatedly expands and contracts due to temperature changes. Since the sealing resin 12 surrounding the chip connection portion 52 also repeatedly expands and contracts due to temperature changes, it is desirable for the wiring and the sealing resin 12 to have the same coefficient of linear expansion. However, even if the coefficients of linear expansion are the same, the leading edge surface 66 of the chip connection portion 52 is prone to peeling due to differences in temperature distribution or contraction rate. Furthermore, because the semiconductor chip 40 is a heat source, the chip connection portion 52 is at a higher risk of being repeatedly subjected to thermal stress compared to the circuit pattern connection portion 56. Additionally, in this example, the area of ​​the chip connection portion 52 is configured to be larger than the area of ​​the circuit pattern connection portion 56. In this respect, the risk of the chip connection portion 52 being subjected to thermal stress is also higher than that of the circuit pattern connection portion 56.

[0117] Here, foot 54B (refer to) Figure 4 It is constrained by the sealing resin 12 and therefore difficult to move. Since the foot 54B functions as an axis, the front end face 66 (see reference 54B) is considered a relatively vulnerable part of the chip connection portion 52 due to stress. Figure 4 In other words, in the semiconductor module 100, the part that may become relatively vulnerable due to stress is considered to be the front surface 66.

[0118] The higher the stress generated at the chip connector 52, the higher the likelihood of the chip connector 52 peeling off from the resin. If peeling occurs between the chip connector 52 and the resin, resin cracking may occur starting from this peeling. Therefore, in order to achieve a semiconductor module 100 with high durability, it is preferable to implement countermeasures on the chip connector 52, especially the front end surface 66, to prevent peeling from the resin and thereby suppress resin cracking starting from peeling. Therefore, the semiconductor module 100 in this example can have the configuration described below.

[0119] <<Explanation of Rough Surface Region 51>>

[0120] Figure 4 yes Figure 3 An enlarged view of the lead frame 50. The lead frame 50 has a rough surface region 51 on at least a portion of its surface. Figure 4 In the diagram, dashed lines are used to represent surfaces with roughened areas 51. Roughened areas 51 are regions with an unfolded area ratio (Sdr) of 0.2 or higher.

[0121] The unfolded area ratio represents the increase in surface area of ​​a predefined region relative to its projected area when projected onto a predefined plane. For example, for a perfectly flat region, the unfolded area ratio is 0 because the projected area equals the surface area. In regions with many irregularities, the projected area remains unchanged, but the surface area increases, thus increasing the unfolded area ratio. The unfolded area ratio of the rough surface region 51 can be 0.3 or higher, or 0.4 or higher.

[0122] It should be noted that the arithmetic mean height (Sa) of the rough surface region 51 can be 10 μm or less. The arithmetic mean height is the average height or depth of each bump and depression in the rough surface region 51 relative to the height or depth of the surface obtained by averaging the height of the rough surface region 51. That is, the rough surface region 51 is a region whose unfolded area ratio increases due to minute bumps and depressions. The maximum height (Sz) of the rough surface region 51 can be 100 μm or less. The maximum height represents the distance from the highest point of each bump and depression in the rough surface region 51 to the lowest point.

[0123] In this embodiment, the unfolded area ratio (Sdr), arithmetic mean height (Sa), and maximum height (Sz) can be defined according to ISO 25178, an international standard. Furthermore, the measurement environment for each parameter is shown below. However, it is not limited to this measurement environment; values ​​measured under equivalent conditions can also be used.

[0124] [Examples of environmental measurement]

[0125] Measuring instrument: Keyence VK-X1100

[0126] Controller section: Keyence VK-X1000

[0127] Objective lens: Apo × 50x

[0128] Cutoff value: Gaussian

[0129] S-filter: None

[0130] L-filter: None

[0131] F - Operation - None

[0132] The rough surface region 51 can be formed by irradiating the lead frame 50 with a laser. In this case, the rough surface region 51 can be easily formed locally on the lead frame 50. Alternatively, the rough surface region 51 can be formed by spraying a portion or the entirety of the lead frame 50 with pre-set particles, by immersing a portion or the entirety of the lead frame 50 in a pre-set solution, or by other methods.

[0133] A rough surface area 51 may be provided in the chip connection portion 52. In the semiconductor module 100, the semiconductor chip 40 becomes a heat source. Therefore, stress is easily applied to the chip connection portion 52 connected to the semiconductor chip 40. If stress is applied to the lead frame 50, the lead frame 50 becomes easy to peel off from the sealing resin 12.

[0134] To address this, by providing a roughened surface area 51 in the chip connection portion 52, the contact area between the lead frame 50 and the sealing resin 12 can be increased, thereby suppressing the peeling of the sealing resin 12. Furthermore, by locally providing the roughened surface area 51, the manufacturing cost of the lead frame 50 can be easily reduced.

[0135] The surface of the chip connector 52 furthest from the bridging portion 54 (in this example, the foot 54B) is designated as the front surface 66. Furthermore, the surface of the chip connector 52 opposite to the semiconductor chip 40, i.e., bonded to the semiconductor chip 40, is designated as the lower surface 62; the surface opposite to the lower surface 62 is designated as the upper surface 64; and the surface between the lower surface 62 and the upper surface 64, excluding the front surface 66, is designated as the side surface 68. The lower surface 62 and the upper surface 64 are surfaces substantially parallel to the XY plane. The front surface 66 and the side surface 68 are surfaces not parallel to the XY plane. The front surface 66 and the side surface 68 may be substantially perpendicular to the XY plane.

[0136] Preferably, a roughened surface area 51 is provided on at least a portion of the front end surface 66. As described above, this is because the front end surface 66 is a relatively fragile part, prone to peeling from the sealant 12. By providing a roughened surface area 51 on the front end surface 66, peeling between the lead frame 50 and the sealant 12 can be effectively suppressed. The roughened surface area 51 may be provided over more than half of the front end surface 66, or it may be provided on the entire front end surface 66. When the roughened surface area 51 is provided on a portion of the front end surface 66, it is preferable to provide the roughened surface area 51 on the portion of the front end surface 66 that contacts the lower surface 62. This is because the portion that contacts the lower surface 62 is a portion that may come into contact with the solder or other bonding layer 32, and the solder or other bonding layer 32 may become the starting point for resin peeling. By providing a roughened surface area 51 on this portion, peeling of the sealant 12 can be effectively suppressed.

[0137] A roughened surface area 51 may be provided on at least a portion of the upper surface 64. By providing a roughened surface area 51 on the upper surface 64, peeling between the lead frame 50 and the sealing resin 12 can be further suppressed. The roughened surface area 51 may be provided covering more than half of the upper surface 64, or it may be provided on the entire upper surface 64. When the roughened surface area 51 is provided on a portion of the upper surface 64, it is preferable to provide the roughened surface area 51 on the portion of the upper surface 64 that contacts the front end face 66.

[0138] A roughened surface area 51 may be provided on at least a portion of the side surface 68. By providing a roughened surface area 51 on the side surface 68, peeling between the lead frame 50 and the sealing resin 12 can be further suppressed. The roughened surface area 51 may be provided covering more than half of the side surface 68, or it may be provided on the entire side surface 68. When the roughened surface area 51 is provided on a portion of the side surface 68, it may be provided on the portion of the side surface 68 that contacts the front end face 66. The roughened surface area 51 may also be provided on the side surface 68 that contacts the third side 83 (described later). Additionally, the roughened surface area 51 may be provided on the portion of the side surface 68 that contacts the lower surface 62.

[0139] The rough surface region 51 may not be provided on the lower surface 62. This is because the lower surface 62 is connected to the semiconductor chip 40 via the bonding layer 32.

[0140] In this example, a plurality of protrusions 88 protruding toward the insulating circuit board 160, i.e., the semiconductor chip 40, are provided on the lower surface 62 of the chip connection portion 52. Similarly, a plurality of protrusions 88 protruding toward the island regions 26B and 26C of the insulating circuit board 160, i.e., the circuit pattern 26, can also be provided on the lower surface of the circuit pattern connection portion 56. The length of the protrusions 88 in the X-axis direction can be less than 1 / 4 or less than 1 / 8 of the length of the chip connection portion 52 or the circuit pattern connection portion 56 in the X-axis direction. Similarly, the length of the protrusions 88 in the Y-axis direction can be less than 1 / 4 or less than 1 / 8 of the length of the chip connection portion 52 or the circuit pattern connection portion 56 in the Y-axis direction. By providing the protrusions 88, the lower surface 62 of the chip connection portion 52 or the circuit pattern connection portion 56 can be configured parallel to the upper surface of the island regions 26B and 26C of the semiconductor chip 40 or the circuit pattern 26, enabling the formation of a solder or other bonding layer 32. It should be noted that, for ease of understanding, in Figure 3 , Figure 5 , Figure 6 The illustration of protrusion 88 is omitted in the text.

[0141] Figure 5 This is an enlarged view of the vicinity of the circuit pattern connection portion 56. As described above, the island regions 26B and 26C of the circuit pattern 26 are bonded to the circuit pattern connection portion 56 of the lead frame 50 via the bonding layer 34. The unfolded area ratio in the rough surface region 51 of the chip connection portion 52 can be greater than the unfolded area ratio in the circuit pattern 26. As an example, the unfolded area ratio of the circuit pattern 26 can use the value of the region 39 in contact with the sealing resin 12. The unfolded area ratio of the circuit pattern 26 is 0.08 or less. Although in Figure 5 The example shows and explains the unfolded area ratio of the island region 26B of circuit pattern 26, but the unfolded area ratios of the island regions 26A and 26C of circuit pattern 26 can also be the same.

[0142] Furthermore, the circuit pattern connection portion 56 may or may not have a rough surface area 51. In this example, the circuit pattern connection portion 56 does not have a rough surface area 51. That is, the unfolded area ratio of each surface of the circuit pattern connection portion 56 in this example is smaller than the unfolded area ratio of the rough surface area 51 provided in the chip connection portion 52. The unfolded area ratio of each surface of the circuit pattern connection portion 56 may be less than 0.2. The unfolded area ratio of each surface of the circuit pattern connection portion 56 may also be 0.08 or less.

[0143] The rough surface area 51 can also be provided on the entire surface of the lead frame 50. As a result, the machining of the lead frame 50 is sometimes easier.

[0144] Figure 6 yes Figure 3An enlarged view of the vicinity of the front end face 66. In this example, at least a portion of the surface of the lead frame 50 can be covered by the coating 13. The coating 13 is a thermoplastic, high-heat-resistant film formed of resin. The coating 13 can be formed by spraying the components with a sprayer or the like after the components have been joined with solder or the like and before the sealing resin 12 has been filled. In other examples, the coating 13 can also be formed for each component before the components have been joined with solder or the like. The coating 13 can be applied using a high-performance controlled dispensing device (liquid metering device). The coating 13 can be formed of a resin with higher heat resistance than the sealing resin 12. In addition, the coating 13 can also be formed of a resin with higher flexibility than the sealing resin 12. Although the coating 13 is formed of, for example, a polyamide-based resin, a polyamide-imide-based resin, or a polyimide-based resin, the material is not limited to these.

[0145] The coating 13 can be applied to the surface of the lead frame 50, excluding the surface opposite to the semiconductor chip 40, or it can be applied to the entire surface of the lead frame 50. Preferably, the coating 13 at least covers the rough surface region 51. At the chip connection portion 52, the coating 13 can be applied to cover the front end surface 66, the upper surface 64, and the side surface 68. The film thickness T1 of the coating 13 is, for example, 1 μm or more and 100 μm or less. The film thickness T1 of the coating 13 is preferably 2 μm or more, more preferably 3 μm or more. Here, the film thickness T1 of the coating 13 can be set to an average thickness within a predetermined range. The surface of the coating 13 covering the rough surface region 51 can have unevenness corresponding to the unevenness of the rough surface region 51, or it can be flatter than the rough surface region 51. By providing the coating 13, the peeling of the sealing resin 12 can be further suppressed. The coating 13 is provided with concave and convex parts corresponding to the concave and convex parts of the rough surface region 51, which means that when viewed from a direction perpendicular to the rough surface region 51, the concave parts of the rough surface region 51 and the concave parts of the coating 13 are arranged in an overlapping position, and the convex parts of the rough surface region 51 and the convex parts of the coating 13 are arranged in an overlapping position.

[0146] The coating 13 and the sealing resin 12 can be bonded together chemically. Through chemical, mechanical, and physical bonding, the strength between the coating 13 and the sealing resin 12 can be ensured.

[0147] Here, solder or the like from the bonding layer 32 sometimes seeps between the sealing resin 12 and the lead frame 50. For example, when bonding the lead frame 50, solder or the like sometimes spreads to the front end face 66. When the lead frame 50 is bonded, the coating 13 is applied, and the sealing resin 12 is filled, the adhesion between the bonding layer 32 and the resin is relatively poor, so the possibility of the resin (here, the coating 13) peeling off from the bonding layer 32 starting from this part increases. In this case, by providing the rough surface area 51, the adhesion between the resin and the lead frame 50 is improved, so even if the resin peels off from the bonding layer 32, the progress of resin peeling can be suppressed, preventing the resin from peeling off from the lead frame 50 as well.

[0148] Furthermore, as described above, the chip connection portion 52 is a region where stress is easily applied, and it can be said that this chip connection portion 52 is a part of the durability against resin peeling of the semiconductor module 100. In this example, the unfolded area ratio of the rough surface region 51 of the chip connection portion 52 is greater than the unfolded area ratio of the circuit pattern connection portion 56. As a result, the durability of the chip connection portion 52, which may be a bottleneck, can be improved. In addition, making the unfolded area ratio of the chip connection portion 52, which may be relatively fragile, greater than the unfolded area ratio of the circuit pattern connection portion 56 means that processing is not required in the circuit pattern connection portion 56, so unnecessary additional processes are not added, and cost increases can be suppressed.

[0149] Figure 7 This is a graph showing the relationship between the unfolded area ratio of the lead frame 50 and the bonding strength. Figure 7 In this process, when the force required to separate the resin (here, coating 13) from the lead frame 50 is increased, the magnitude of the force required to peel the resin is set as the adhesion strength. Figure 7 In this experiment, the adhesion strength in each region of the lead frame 50 was determined by varying the ratio of the unfolded area. It should be noted that in this example, the arithmetic mean height (Sa) of the rough surface region 51 was set to below 10 μm, and the maximum height (Sz) of the rough surface region 51 was set to below 100 μm. The experiment was conducted under conditions where the unevenness was neither extremely pronounced nor extremely high. Thus, by setting the arithmetic mean height (Sa) and the maximum height (Sz) of the rough surface region 51 within predetermined ranges, it is possible to avoid affecting the performance of other products.

[0150] like Figure 7As shown, by setting the unfolded area ratio of each region of the lead frame 50 to 0.2 or higher, the adhesion strength with the resin can be ensured. Therefore, by providing a rough surface region 51 with an unfolded area ratio of 0.2 or higher in the lead frame 50, peeling of the sealing resin 12 can be suppressed. It should be noted that although experiments were conducted by changing the parameter from the unfolded area ratio of the rough surface region 51 to the arithmetic mean height (Sa) or maximum height (Sz) of the rough surface region 51, the arithmetic mean height (Sa) or maximum height (Sz) in this case had little effect on the adhesion strength, confirming that the unfolded area ratio of the rough surface region 51 is a parameter used to ensure adhesion strength.

[0151] The preferred lead frame 50 has a structure that suppresses the spread of solder or the like at the front end face 66. The structure for suppressing the spread of solder or the like will be described below.

[0152] <<Explanation of steps 70 degrees or inclines 90 degrees>>

[0153] Figure 8 This is a perspective view showing other structural examples of the lead frame 50. In this example, a step 70 is preferably provided on the lower surface 62 opposite to the semiconductor chip 40 of the chip connection portion 52. Alternatively, the same step 70 as that of the chip connection portion 52 may also be provided on the lower surface of the circuit pattern connection portion 56. It should be noted that... Figure 8 In the lead frame 50, no protrusion 88 is provided in the chip connection part 52 and the circuit pattern connection part 56.

[0154] Figure 9 It is shown Figure 8 The diagram shows the lower surface 62 of the chip connection portion 52. The side furthest from the bridging portion 54 among the edges constituting the shape of the lower surface 62 is designated as the first side 81. In this example, although the lower surface 62 is a generally rectangular shape with two sets of parallel sides, it could also be other shapes. The edges of the lower surface 62 can be straight lines. The first side 81 is connected to the front end face 66. Furthermore, the side of the lower surface 62 closest to the bridging portion 54 is designated as the second side 82. The edge between the first side 81 and the second side 82 of the lower surface 62 is designated as the third side 83. The third side 83 is connected to the side surface 68. The first side 81 and the third side 83 can be connected by a curve.

[0155] Let the length of the first side 81 be L1. In this example, the first side 81 is a line extending along the Y-axis. When the lower surface 62 is rectangular, the length L1 is the distance between the two third sides 83 along the Y-axis. On the lower surface 62, a step 70 is provided along the first side 81 for more than half its length. The step 70 along a predetermined side can mean that the angle between the extension direction of the step 70 and the extension direction of the side is less than 15 degrees, less than 5 degrees, or 0 degrees.

[0156] The step 70 may also contact the first side 81. Furthermore, the distance between the step 70 and the first side 81 may be less than half, less than 1 / 4, or less than 1 / 10 of the distance in the X-axis direction between the first side 81 and the second side 82. The step 70 may be more than 1 / 2 or more than 3 / 4 of the length of the first side 81 in the Y-axis direction. The step 70 may also be provided throughout the entire first side 81. This prevents the solder or other bonding layer 32 from spreading to the front end face 66 where stress is most easily applied.

[0157] The step 70 can also be provided along the third side 83. The step 70 can be provided along more than half the length of the third side 83 on the lower surface 62. The step 70 can also contact the third side 83. Furthermore, the distance between the step 70 and the third side 83 can be less than half, less than 1 / 4, or less than 1 / 10 of the length L1. The step 70 can be provided for more than 1 / 2 or more than 3 / 4 of the length of the third side 83 in the X-axis direction. The step 70 can also be provided throughout the entire third side 83. This can suppress the spread of the solder or other bonding layer 32 to the side 68.

[0158] A step 70 may or may not be provided on the second side 82. In this example, no step 70 is provided on the entire second side 82. The step 70 may be provided along the edges of the lower surface 62 other than the second side 82. With this configuration, in the event of an excess of solder or the like in the bonding layer 32, the overflow of solder or the like from the second side 82 can be suppressed, thus preventing the overflow of solder or the like to the front end face 66.

[0159] It should be noted that, as described below, the aforementioned step 70 can also be an inclined portion. That is, an inclined portion can be provided along the first side 81, in the Y-axis direction of the first side 81, which is more than 1 / 2 or more than 3 / 4 of its length. In addition, an inclined portion can be provided along the third side 83, in the X-axis direction of the third side 83, which is more than 1 / 2 or more than 3 / 4 of its length.

[0160] Step 70 includes at least one of a protrusion and a groove. The protrusion is as follows: Figure 8As shown in the example, it protrudes from the lower surface 62 toward the semiconductor chip 40. The groove is recessed from the lower surface 62 in a direction away from the semiconductor chip 40. The sidewalls of the step 70 can be perpendicular to the lower surface 62 or can be a tapered shape with an angle.

[0161] Figure 10 It is shown Figure 9 The diagram shows the BB section. The BB section is the XZ section. Additionally, although step 70 in this example is a protrusion, it could also be a groove. Step 70 is positioned along the front face 66.

[0162] Figure 11 It is shown Figure 9 The diagram shows the CC section. The CC section is the YZ section. Step 70 is configured along the side 68 connected to the front face 66.

[0163] Figure 12 It is applicable. Figure 8 This is an enlarged view of the vicinity of the front end face 66 in the case of the lead frame 50. In this example, the step 70 is a protrusion configured to contact the front end face 66. The height (or depth) of the step 70 relative to the lower surface 62 in the Z-axis direction can be less than half or less than 1 / 4 of the thickness of the chip connection portion 52 in the Z-axis direction. Figure 12 As shown, by providing the step 70, the position of the end of the bonding layer 32, such as solder, can be easily defined. That is, the position of the end of the bonding layer 32 can easily coincide with the position of the end of the step 70. As a result, the spread of the bonding layer 32 to the front end face 66, etc., can be suppressed.

[0164] The lead frame 50 with step 70 may or may not have a rough surface area 51. In addition, the lead frame 50 may or may not be covered by the coating 13.

[0165] In this example, at least a portion of the area on the lower surface 62 of the lead frame 50 where the step 70 is provided is also provided with a rough surface area 51. Alternatively, the rough surface area 51 can be provided over the entire step 70. This further suppresses the peeling of the sealing resin 12. Additionally, at least a portion of the area on the lower surface 62 where the step 70 is provided can also be covered by the coating 13.

[0166] Figure 13 This is a diagram showing another example of the lower surface 62 of the chip connection portion 52. In this example, the step 70 is a groove configured to contact the front end surface 66. Other configurations of the step 70 are shown below. Figures 9 to 12The step 70 described herein is the same. In this example, step 70 is also provided along the first side 81 and the third side 83. Specifically, step 70 is provided in contact with the first side 81 and the third side 83. It should be noted that step 70 may be in contact with each side or may be separate from each side.

[0167] In this example, a plurality of protrusions 88 are provided on the lower surface 62 of the chip connection portion 52. The lengths of the protrusions 88 in the X and Y axes are shorter than the lengths of the step 70 in the X and Y axes. The length of the protrusions 88 in the X axis can be less than 1 / 4 or less than 1 / 8 of the length of the chip connection portion 52 in the X axis. Similarly, the length of the protrusions 88 in the Y axis can be less than 1 / 4 or less than 1 / 8 of the length of the chip connection portion 52 in the Y axis. Furthermore, the height of the protrusions 88 in the Z axis is lower than the height of the step 70 in the Z axis. By providing the protrusions 88, the distance between the semiconductor chip 40 and the chip connection portion 52 can be maintained.

[0168] Figure 14 It is shown Figure 13 The diagram shows the DD section. The DD section is the XZ section. Figure 15 It is shown Figure 13 The diagram shows the EE section. The EE section is the YZ section. The step 70 is arranged along the front face 66 and the side face 68 connected to the front face 66. As a result, a solder foot (lower hem portion) of a solder joint layer 32 is formed on the rear face 71 of the step 70, which is a groove portion, which can suppress the spread of solder and the like to the front face 66 and the side face 68.

[0169] Figure 16 This is a diagram showing another example of the lower surface 62 of the chip connection portion 52. In this example, the step 70 is a groove configured separately from the front end surface 66 and the side surface 68, which is connected to the front end surface 66. Other configurations of the step 70 are shown below. Figures 9 to 15 The step 70 described herein is the same. In this example, the step 70 is also provided along the first side 81 and the third side 83. The step 70 may contact each side or be separate from each side. In this example, the step 70, which serves as a groove, is provided separate from the first side 81 and the third side 83. In addition, a plurality of protrusions 88 are provided on the lower surface 62 of the chip connection portion 52.

[0170] Figure 17 It is shown Figure 16 The diagram shows the FF section. The FF section is the XZ section. Figure 18 It is shown Figure 16The diagram shows the GG section. The GG section is the YZ section. The step 70 is arranged along the front face 66 and the side face 68 connected to the front face 66. The step 70 is arranged between the protrusion 88 and the front face 66 or between the protrusion 88 and the side face 68, which is connected to the front face 66. By accommodating the solder or other bonding layer 32 as a groove in the step 70, and forming solder or other solder feet starting from this point, it is possible to suppress the spread of solder or other materials to the front face 66 and the side face 68.

[0171] Figure 19 This is a diagram showing another example of the lower surface 62 of the chip connection portion 52. In this example, an inclined portion 90 is provided on the lower surface 62 of the chip connection portion 52. The inclined portion 90 is inclined at a predetermined angle such that the further outward it moves from the lower surface 62, the further away it is from the semiconductor chip 40. Other structures are the same as those of the chip connection portion 52 described above. The height of the protrusion 88 in the Z-axis direction can be lower than that of the inclined portion 90.

[0172] Figure 20 It is shown Figure 19 The diagram shows the HH section. The HH section is an XZ section. The inclined portion 90 is disposed in contact with the front end face 66. Specifically, the inclined portion 90 extends from the lower surface 62 to the front end face 66. That is, the inclined portion 90 is formed by chamfering the corner of the lower surface 62, i.e., the corner formed by connecting the lower surface 62 and the front end face 66. The angle between the inclined portion 90 and the lower surface 62 can be 20 degrees or more and 70 degrees or less.

[0173] By providing a tapered inclined portion 90, the solder feet of the bonding layer 32 are stabilized in a shape corresponding to the angle of the inclined portion 90. Therefore, the shape of the solder feet of the bonding layer 32 can be stabilized. Thus, resin peeling caused by deviations in the shape of the solder feet of the bonding layer 32 can be suppressed. Furthermore, the inclined portion 90 can be formed by chamfering the corners, making it easy to process.

[0174] Figure 21 It is shown Figure 19 The diagram shows section II. Section II is the YZ section. The inclined portion 90 is configured to contact the side surface 68, which is connected to the front end face 66. Figure 20Similarly, the inclined portion 90 is angled relative to the lower surface 62. The inclined portion 90 extends from the lower surface 62 to the side surface 68 connected to the front end surface 66. That is, the inclined portion 90 is formed by chamfering the corner of the lower surface 62, i.e., the angle between the lower surface 62 and the side surface 68, which is connected to the front end surface 66. The angle between the inclined portion 90 and the lower surface 62 can be more than 20 degrees and less than 70 degrees. This allows for the stabilization of the solder joint shape of the bonding layer 32. In this example, although the inclined portion 90 is inclined at a predetermined angle such that it moves further away from the semiconductor chip 40 towards the outer edge of the lower surface 62, it can also be formed such that it moves closer to the semiconductor chip 40 towards the outer edge of the lower surface 62.

[0175] <<Explanation of Obstacle Zone 251>>

[0176] Figure 22 This is a diagram showing a reference example of a chip interconnect portion 152. The chip interconnect portion 152 has the same structure as the chip interconnect portion 52, except that it does not have a rough surface area 51. The front end surface 66 or the side surface 68 of the chip interconnect portion 152 has solder wettability. Therefore, solder 32 sometimes spreads along the front end surface 66 or the side surface 68.

[0177] If the solder 32 spreads along the front face 66 or side face 68 to form the coating 13, the solder 32 may become positioned between the front face 66 of the chip connection portion 152 and the coating 13, or between the side face 68 and the coating 13. The bonding strength between the coating 13 and the solder 32 is relatively weak. Therefore, the coating 13 may sometimes peel off due to thermal stress, etc. Figure 22 As shown, if the solder 32 spreads to the vicinity of the vertex 201 of the front end surface 66, the contact area between the chip connection portion 52 and the front end surface 66 becomes smaller, thus making it easier to peel off the coating 13. However, if the peeling of the coating 13 progresses, cracks may occur in the sealing resin 12.

[0178] Figure 23 This is an enlarged view of the vicinity of vertex 201 of the chip interconnect 152. As described above, if solder 32 spreads to the vicinity of vertex 201, the coating 13 may peel off near vertex 201. Figure 23 The space 202 created by the peeling of coating 13 is shown in the figure.

[0179] If the peeling of coating 13 progresses further, the adhesion strength between solder 32 and coating 13 will be insufficient. Therefore, solder 32 is prone to movement due to thermal stress, which may cause cracks 203 in coating 13. If cracks 203 reach the sealing resin 12, cracks 204 may also occur in the sealing resin 12. If cracks 204 occur, the lead frame 50 and semiconductor chip 40 cannot be adequately protected.

[0180] Figure 24 This is a diagram showing another example of the lead frame 50. In this example, the lead frame 50 has a barrier region 251 on the surface of the chip connection portion 52 instead of... Figures 1 to 21 The rough surface region 51 is described in the text. The structure other than the obstruction region 251 can be... Figures 1 to 21 The same applies to any of the methods described herein.

[0181] The barrier region 251 hinders the wetting and propagation of the solder. That is, the barrier region 251 is a region where the solder wetting property is lower than that of the lead frame 50 surface without the barrier region 251. Solder wetting property can be represented by the area obtained by projecting the region after solder propagation onto a plane when a predetermined mass of solder is placed on the target surface and heated under predetermined conditions. Alternatively, solder wetting property can be represented by the height to which the solder spreads on the target surface when a predetermined mass of solder is placed at the lower end of the vertically arranged target surface and heated under predetermined conditions.

[0182] A barrier region 251 is provided at least on the front end face 66 of the chip interconnect portion 52. The barrier region 251 may be provided in a portion of the front end face 66 or on the entire front end face 66. This suppresses the spread of solder at the front end face 66, where thermal stress is most easily concentrated, and also suppresses the peeling of the coating 13. The barrier region 251 may also be provided on at least one side 68 of the chip interconnect portion 52. The barrier region 251 may be provided on each side 68. The barrier region 251 may be provided in a portion of the side 68 or on the entire side 68. The barrier region 251 may also be provided on the upper surface 64 of the chip interconnect portion 52. The barrier region 251 may be provided in a portion of the upper surface 64 or on the entire upper surface 64. The barrier region 251 may or may not be provided on the circuit pattern interconnect portion 56. Figure 24 In this example, the obstruction area 251 is not provided in the circuit pattern connection portion 56. The obstruction area 251 may also be provided on the entire surface of the lead frame 50.

[0183] Figure 25 This is an enlarged view of the vicinity of the front end face 66 of the chip connection portion 52. Figure 25 The obstruction area 251 provided on the front end face 66 and the upper surface 64 is shown, while the obstruction area 251 on the side face 68 is omitted.

[0184] In this example, the obstruction area 251 is the region on the surface of the lead frame 50 where multiple recesses 210 and multiple planar portions 212 are formed. By providing multiple recesses 210 on the surface of the lead frame 50, steps are formed on the surface of the chip interconnect portion 52, which can suppress the wetting and spreading of solder 32.

[0185] Figure 26This figure shows an example of a recess 210 and a planar portion 212 at the front end face 66. It should be noted that obstruction areas 251 formed on other surfaces may also have the same structure as obstruction areas 251 on the front end face 66. The recess 210 is a portion that is more recessed than the surface S of the front end face 66. The planar portion 212 is a portion of the front end face 66 that remains without a recess 210. Multiple planar portions 212 can be arranged on the same surface (in...). Figure 26 (The middle part is the surface S).

[0186] A planar portion 212 is disposed between two adjacent recesses 210 in a predetermined direction. Multiple recesses 210 can be arranged two-dimensionally on the front end face 66. Multiple recesses 210 can be arranged periodically along at least two directions. The period (or interval) of the recesses 210 in one direction can be constant or variable. Figure 26 The diagram shows a recess 210 and a planar surface 212 arranged with a constant period in the height direction (Z-axis direction).

[0187] The maximum width W of each recess 210 can be 10 μm or more. The maximum width W refers to the largest width among the recesses 210 on surface S. For example, if the recess 210 on surface S is circular, the maximum width W is the diameter of the recess 210. If the recess 210 on surface S is square, the maximum width W is the length of the diagonal of the recess 210. By increasing the size of the recesses 210, solder can be retained within the recesses 210, and solder wetting and propagation can be suppressed. The maximum width W can be 15 μm or more, 20 μm or more, or 30 μm or more.

[0188] The depth D of each recess 210 can be 1 μm or more. Depth D refers to the maximum depth of the recess 210 relative to the surface S. By increasing the depth D, the height difference of the surface S can be increased, and the volume of the recess 210 can also be increased. This helps to suppress solder wetting and propagation. The depth D can be 3 μm or more, 5 μm or more, or 10 μm or more. It should be noted that the depth D can be less than the maximum width W, or less than half of the maximum width W.

[0189] The spacing P between the centers 211 of adjacent recesses 210 can be 10 μm or more. The center 211 is the center of the recess 210 on the surface S. The center 211 can refer to the centroid of the geometry of the recess 210 on the surface S. If the spacing P becomes too small, solder wetting and spreading cannot be suppressed. For example, if the spacing P is smaller than the maximum width W, the recesses 210 overlap. In this case, solder easily spreads across the overlapping recesses 210. Preferably, the spacing P is greater than the maximum width W. The spacing P can be 1 μm or more, 3 μm or more, or 5 μm or more larger than the maximum width W. The length L of the planar portion 212 can be 1 μm or more. The length L is the shortest distance between two adjacent recesses 210. The length L can be 3 μm or more, or 5 μm or more. It should be noted that both the spacing P and the length L can be greater than the depth D.

[0190] Figure 27 This is a diagram showing an example of the arrangement of the recess 210 and the planar surface 212 at the front end face 66. It should be noted that in each diagram, the number of recesses 210 arranged on the front end face 66 is an example, and the number of recesses 210 is not limited to the example shown.

[0191] The recesses 210 are periodically arranged in at least two directions of the front end face 66. Figure 27 In this example, the components are periodically arranged in two directions: the lateral direction (Y-axis direction) parallel to the lower surface 62 of the chip connection portion 52 and the vertical direction (Z-axis direction) perpendicular to the lower surface 62. The lateral and vertical directions are perpendicular to each other.

[0192] The planar portion 212 is disposed between two adjacent recesses 210 in any direction. Figure 27 In the example, the area on the front end face 66 where no recess 210 is formed is the planar portion 212. For example, the planar portion 212 is disposed between two adjacent recesses 210 in the lateral direction and between two adjacent recesses 210 in the height direction. In addition, the planar portions 212 at the front end face 66 can be connected to each other.

[0193] Figure 28 This is a diagram showing other configuration examples of the recess 210 and planar surface 212 at the front end face 66. In this example, the recess 210 of the front end face 66 is periodically configured in a direction that is consistent with... Figure 27 The examples differ. Other structures are different. Figure 27 The examples are the same.

[0194] The recesses 210 are periodically arranged along the first and second directions. Figure 27 In the example, the first direction and the second direction are orthogonal. In this example, the first direction and the second direction intersect at an angle. As an example, the first direction is the Y-axis direction, and the second direction is a direction that intersects the Y-axis at an angle.

[0195] Multiple recesses 210 are configured to have a predetermined gap in a transverse direction (Y-axis direction) parallel to the lower surface 62 of the chip connection portion 52. A flat portion 212 can be disposed within this gap. Figure 28 In the example, a flat portion 212-1 is disposed between the recess 210-1 and the recess 210-2.

[0196] The plurality of recesses 210 include a recess 210-3 arranged side by side with the gap (flat portion 212-1) in the height direction (Z-axis direction). The recess 210-3 is a recess 210 adjacent to the recess 210-1 in the second direction. The recess 210-3 may be arranged in the transverse direction (Y-axis direction) at the center of the recesses 210-1 and 210-2.

[0197] In this example, the planar portion 212 is arranged in a straight line along the Z-axis direction from the lower surface 62 to the upper surface 64 to prevent solder from spreading from the lower surface 62 to the upper surface 64 over the shortest distance. In the transverse direction (Y-axis direction), it is preferable that the width of the recess 210 is greater than the width of the gap (planar portion 212-1). The width of the gap (planar portion 212-1) is the shortest distance between the two recesses 210-1 and 210-2 that sandwich the gap in the transverse direction.

[0198] <<Manufacturing method of rough surface area 51 and obstruction area 251; Explanation of laser roughening>>

[0199] Figure 29 This diagram illustrates a portion of the manufacturing process of the semiconductor module 100. In this example, the surface of the chip connection portion 52, specifically at least the front end surface 66, is irradiated with a laser to form a plurality of recesses 210 and planar surfaces 212 (S341). In S341, the plurality of recesses 210 and planar surfaces 212 may also be formed on each side surface 68 and the upper surface 64.

[0200] Next, the lead frame 50 is soldered to the semiconductor chip 40 using solder 32 (S342). Since a recess 210 and a flat surface 212 are formed on the front end surface 66 and the like before S342, the spread of solder 32 on the front end surface 66 and the like can be suppressed.

[0201] Next, coating 13 is formed (S343). In S343, coating 13 can be formed on the surfaces of lead frame 50 and solder 32. After S343, lead frame 50 and semiconductor chip 40, etc., can be encapsulated using sealing resin 12. Thus, semiconductor module 100 can be formed.

[0202] Figure 30This diagram illustrates the measurement results of Examples 1-3 and Reference Examples 1-3. In Examples 1-3, irradiation was performed in a manner that prevented laser overlap on the surface of the chip connection portion 52, i.e., multiple recesses 210 and planar portions 212 disposed between two recesses 210 were formed. It should be noted that in Example 2, the recesses 210 were circular in shape, so even if the interval P was the same as the maximum width W, planar portions 212 were generated between the circles. As described above, the length L is the shortest distance between two adjacent recesses 210, in other words, the minimum length L. Therefore, the length in the Z-axis direction between the circles is not constant, and planar portions 212 are generated in the portion that is not the shortest distance. Reference Examples 1-3 are examples of overlapping laser printing on the surface of the chip connection portion 52. In detail, in Reference Examples 1-3, laser printing was performed in a manner that prevented the generation of planar portions 212 between two recesses 210. In Reference Example 1, the laser irradiation interval P during overlapping printing is larger than the laser irradiation interval during overlapping printing in Reference Examples 2 and 3.

[0203] Figure 30 Solder spread is an indicator of the area after solder spreads. Figure 30 In this context, the solder spread of the front end face 66 without the recess 210 is set to 0. Compared to the front end face 66 without the recess 210, a positive value is used to represent the degree of solder spread when it is large, and a negative value is used to represent the degree of solder spread when it is small. Figure 30 As shown, compared to the case where no recess 210 is formed, in embodiments 1 to 3 where a flat portion 212 is provided between two recesses 210, a tendency for solder spread to be smaller was observed. Furthermore, compared to reference examples 1 to 3 where only recesses 210 are provided without a flat portion 212, a tendency for solder spread to be smaller was also observed in embodiments 1 to 3 where a flat portion 212 is provided between two recesses 210.

[0204] It should be explained that Figures 24 to 29 The example illustrates that the lead frame 50 can have Figures 1 to 23 The rough surface region 51 is described in the text. The front end surface 66 may have a rough surface region 51, the side surface 68 may also have a rough surface region 51, and the upper surface 64 may also have a rough surface region 51. Figures 24 to 29 The obstruction region 251 described herein can also function as the rough surface region 51. That is, the unfolded area ratio of the obstruction region 251 can be 0.2 or higher. Furthermore, the unfolded area ratio of the entire front end surface 66 can also be 0.2 or higher. Additionally, the rough surface region 51 can also be formed on the flat portion 212. For example, after forming the rough surface region 51 on the front end surface 66, multiple recesses 210 can be formed by laser irradiation or the like. The following description... Figures 31-45 The lead frame 50 is the same.

[0205] In Examples 1 and 2, the ratio of the unfolded area of ​​the barrier region 251 is 0.2 or more, and the barrier region 251 functions as a rough surface region 51. Therefore, it can hinder the wetting and spreading of solder and improve the adhesion of the coating 13 and the resin and lead frame 50.

[0206] It should be explained that, for example Figure 25 As shown, at least a portion of the recess 210 in the front end face 66 can contact the solder 32. By forming the recess 210 in the area contacting the solder 32, the propagation of the solder 32 can be suppressed. Solder 32 (bonding layer 32) can be disposed inside at least a portion of the recess 210. A portion of the recess 210 in the front end face 66 can contact the coating 13. The recess 210 closest to the upper surface 64 can contact the coating 13, and the recess 210 closest to the lower surface 62 can contact the solder 32.

[0207] Figure 31 This diagram illustrates the application of laser light to the chip connection portion 52. Figure 31 The image schematically shows the vicinity of the front end face 66 of the chip connection portion 52 and the light source 310. In this example, the light source 310 irradiates the surface of the chip connection portion 52 with a laser 312. By irradiating the surface of the chip connection portion 52 with a laser 312 once, a recess 210 can be formed. The surface remaining without forming a recess 210 becomes a flat portion 212. Figure 31 In the process, the front end face 66 is irradiated with a laser to form a concave portion 210 and a flat portion 212.

[0208] Figure 32 It is shown Figure 29 This diagram illustrates an example of laser irradiation in step S341. In step S341, the light source 310 irradiates the surface of the chip connection portion 52 with laser 312 without moving the chip connection portion 52. That is, in this example, the configuration of the chip connection portion 52 is fixed. Then, by changing the laser irradiation angle of the light source 310, laser 312 is irradiated at multiple positions on the surface of the chip connection portion 52. The light source 310 sequentially irradiates multiple lasers 312 onto the surface of the chip connection portion 52. As a result, multiple recesses 210 and flat portions 212 disposed between two recesses 210 can be formed on the surface of the chip connection portion 52, and obstruction areas 251 can be provided on the surface of the chip connection portion 52. In this example, multiple recesses 210 and flat portions 212 disposed between two recesses 210 are formed on the surface of the front end surface 66. In addition, the light source 310 can irradiate multiple lasers 312 without changing the focal position. In this example, the focal position can be aligned to any position on the front end surface 66. The shape or size of each recess 210 may also be different.

[0209] It should be noted that although in this example, multiple recesses 210 and planar portions 212 disposed between two recesses 210 are formed on the surface of the front end face 66, multiple recesses 210 and planar portions 212 disposed between two recesses 210 can also be formed on the surface of the upper surface 64. In this case, by moving the chip connection portion 52, multiple recesses 210 and planar portions 212 disposed between two recesses 210 can be formed on the surface of the upper surface 64. It should be noted that moving the chip connection portion 52 means changing the relative position of each surface of the chip connection portion 52 with respect to the light source 310. Alternatively, multiple light sources 310 can be used to irradiate the surface of the chip connection portion 52 with laser 312. For example, one light source 310 irradiates the surface of the front end face 66 with laser 312, and another light source 310 irradiates the surface of the upper surface 64 with laser 312. In this configuration, obstruction areas 251 can also be provided on the surface of the front end face 66 and the surface of the upper surface 64. Furthermore, although... Figure 32 The light source 310 changes its illumination angle in the XZ plane, but it can also change its illumination angle in the YZ plane. That is, although... Figure 32 The light source 310 scans the surface of the chip connection portion 52 in one direction, but the light source 310 can also scan the surface of the chip connection portion 52 in multiple directions. The light source 310 can also be a device capable of simultaneously irradiating multiple lasers 312.

[0210] Figure 33 It is shown Figure 29 Figure S341 shows another example of laser irradiation. The light source 310 irradiates at least two surfaces of the chip connection portion 52 with a common light source 310, without moving the chip connection portion 52. In this example, laser 312 is irradiated by changing the irradiation angle relative to each surface of the chip connection portion 52 without changing the configuration of the laser light source. That is, with the configuration of the chip connection portion 52 fixed, the light source 310 irradiates multiple lasers 312 onto at least two surfaces of the chip connection portion 52 by changing the irradiation angle of the light source 310. The light source 310 can sequentially irradiate multiple lasers 312 onto the surfaces of the chip connection portion 52. By operating in this way, multiple recesses 210 and a flat portion 212 disposed between two recesses 210 can be formed on at least two surfaces of the chip connection portion 52, and obstruction areas 251 can be provided on at least two surfaces of the chip connection portion 52. In this example, a plurality of recesses 210 are formed on the surface of the front end face 66 and the surface of the upper surface 64, and a planar portion 212 is disposed between two recesses 210.

[0211] In this example, the light source 310 illuminates the laser 312 at an angle to each surface of the chip interconnect. Figure 33In this configuration, the light source 310 illuminates the entire surface of the front end face 66 and the surface of the upper surface 64 at an angle. That is, the laser 312 does not illuminate perpendicularly to the surfaces of the front end face 66 and the upper surface 64. By illuminating the laser 312 at an angle, at least two surfaces of the chip connection portion 52 can be illuminated with the laser 312 using the common light source 310 without moving the chip connection portion 52.

[0212] The light source 310 can irradiate multiple laser beams 312 onto each surface of the chip connection portion 52 without changing the focal position. By irradiating multiple laser beams 312 without changing the focal position, multiple laser beams 312 can be irradiated continuously, and processing time can be shortened. The focal position is, for example, aligned with angle 65. Angle 65 is the portion where the two surfaces of the chip connection portion 52 intersect. Figure 33 In this example, the portion where the upper surface 64 intersects with the front surface 66 is designated as angle 65. The focal point can also be aligned with any position on the front surface 66. The focal point can also be aligned with any position on the upper surface 64. If a laser is irradiated onto a point near the focal point, the depth of the recess 210 increases. The focal point can be aligned with angle 65. By forming a deeper recess 210 near angle 65, it is possible to suppress the peeling between the chip connection portion 52 and the sealing resin 12 near angle 65, where stress is prone to concentrate. Alternatively, the focal point can also be aligned with the front surface 66. By deepening the recess 210 formed on the front surface 66, it is possible to suppress solder propagation on the front surface 66.

[0213] Figure 34 , Figure 35 It is shown Figure 29 Figures of other examples of laser irradiation in S341. Figure 34 , Figure 35 The position of the light source 310 and Figure 33 Different. With Figure 33 In comparison, Figure 34 In the middle, the light source 310 is positioned further to the side of the front face 66. (Compared to...) Figure 33 In comparison, Figure 35 In the middle, the light source 310 is positioned further to the side of the upper surface 64.

[0214] Figure 36 This is a diagram showing an example of the surface shape of the recess 210 on the front end face 66 and the recess 210 on the upper surface 64. Figure 36 In, it is shown Figure 34 , Figure 35 An example of the surface shape of the recess 210. Additionally, in Figure 36 In the middle, the long side direction of the surface shape of the recess 210 of the front end face 66 ( Figure 34 , Figure 35The length of the Z-axis direction is set to L1, and the length of the long side of the surface shape of the recess 210 on the upper surface 64 is set to L1. Figure 34 , Figure 35 The length of the X-axis direction is set as L2.

[0215] and Figure 33 In comparison, Figure 34 In the middle, the light source 310 is positioned further to the side of the front face 66. Therefore, compared with... Figure 33 In comparison, the angle between the upper surface 64 and the laser 312 incident on the upper surface 64 is smaller. Therefore, the length L2 of the long side of the surface shape of the recess 210 on the upper surface 64 is greater than the length L1 of the long side of the surface shape of the recess 210 on the front end face 66. In this example, L1 / L2 is 0.5.

[0216] and Figure 33 In comparison, Figure 35 In the middle, the light source 310 is positioned further to the upper surface 64. Therefore, compared with... Figure 33 In comparison, the angle between the front end face 66 and the laser 312 incident on the front end face 66 is smaller. Therefore, the length L1 of the long side of the surface shape of the recess 210 of the front end face 66 is greater than the length L2 of the long side of the surface shape of the recess 210 of the upper surface 64. In this example, L1 / L2 is 1.2.

[0217] By changing the relative position of the light source 310 and the chip connection portion 52, the surface shapes of the recess 210 on the front end surface 66 and the recess 210 on the upper surface 64 can be changed. L1 / L2 can be 0.5 or more. L1 / L2 can be 1.2 or less.

[0218] Figure 37 This diagram illustrates the shape of the recess 210 on the front end face 66 and the recess 210 on the upper surface 64. Figure 37 In the middle, recesses 210-1 and 210-2 are provided on the upper surface 64. Recess 210-1 is located on the front end face 66 side closer to recess 210-2. Furthermore, the center of recess 210-1 in the X-axis direction is designated as C1, and the center of recess 210-1 in the X-axis direction is designated as C2. Figure 37 In the middle, a recess 210-3 and a recess 210-4 are provided on the front end surface 66. The recess 210-3 is located on the side of the upper surface 64 of the recess 210-4. In addition, the center of the recess 210-3 in the Z-axis direction is set as C3, and the center of the recess 210-4 in the Z-axis direction is set as C4.

[0219] In this example, laser 312 is irradiated at an angle to each surface of the chip connection portion 52. Therefore, the position of the bottom 314 of the recess 210 is offset from the center of the recess 210. In this example, the bottom 314 of at least one recess 210 formed on the upper surface 64 is positioned relative to the center of the recess 210, closer to the side opposite to the front end face 66 of the chip connection portion 52. That is, the bottom 314-1 of recess 210-1 is positioned relative to the center C1 of recess 210-1, closer to the side opposite to the front end face 66. The bottom 314-2 of recess 210-2 is positioned relative to the center C2 of recess 210-2, closer to the side opposite to the front end face 66.

[0220] Furthermore, the bottom 314 of at least one recess 210 formed on the front end surface 66 can be positioned on the opposite side of the upper surface 64 of the chip connection portion, relative to the center of the recess 210. That is, the bottom 314-3 of recess 210-3 can be positioned on the opposite side of the upper surface 64, relative to the center C3 of recess 210-3. The bottom 314-4 of recess 210-4 can be positioned on the opposite side of the upper surface 64, relative to the center C4 of recess 210-4. The bottom 314 of at least one recess 210 formed on the front end surface 66 can also be positioned substantially aligned with the center of the recess 210.

[0221] When the focal point is aligned with angle 65, the depth of recess 210 becomes shallower with distance from angle 65. Therefore, the depth of recess 210 formed on the upper surface 64 becomes shallower with distance from the front end face 66. The depth of recess 210 refers to the depth at the bottom 314. In this example, the depth D2 of recess 210-2 is less than the depth D1 of recess 210-1. Furthermore, the depth of recess 210 formed on the front end face 66 becomes shallower with distance from the upper surface 64. That is, the depth D4 of recess 210-4 is less than the depth D3 of recess 210-3.

[0222] Although Figure 33 , Figure 34 as well as Figure 35 The recess 210 formed in the middle is the same on the upper surface 64 and the front end surface 66, but in Figure 33 , Figure 34 as well as Figure 35 The recess 210 formed in the middle can also have Figure 37 The shape of the recess 210. That is, in Figure 33 , Figure 34 as well as Figure 35 In this configuration, the bottom 314 of at least one recess 210 formed on the upper surface 64 can also be positioned relative to the center of the recess 210, on the side opposite to the front end face 66 of the chip connection portion 52. Figure 33 , Figure 34 as well as Figure 35 In this case, the bottom 314 of at least one recess 210 formed on the front end surface 66 can also be configured at a position opposite to the upper surface 64 of the chip connection portion, relative to the center of the recess 210. Figure 33 , Figure 34 as well as Figure 35 In this case, the depth of the recess 210 formed on the upper surface 64 can also become shallower as it moves away from the front end face 66. Figure 33 , Figure 34 as well as Figure 35 Alternatively, it may only have in the recess 210 formed on the front end face 66. Figure 37 The shape of the recess 210.

[0223] Figure 38 , Figure 39 , Figure 40 as well as Figure 41 This is a diagram showing an example of the arrangement of the recess 210 on the upper surface 64 and the recess 210 on the front end surface 66. In all the figures, the Y-axis direction of the upper surface 64 and the front end surface 66 is shown in a common manner. Figure 38 As shown, the recess 210 can be positioned on a straight line. For example... Figure 39 As shown, the recess 210 can be configured in a grid pattern. Furthermore, for the recess 210, as... Figure 40 and Figure 41 As shown, the recess 210 may not be provided on the entire upper surface 64. Figure 40 and Figure 41 In the middle, on the upper surface 64, recesses 210 are provided only near the front end face 66 and the side face 68. Although in Figure 38 , Figure 39 , Figure 40 as well as Figure 41 The arrangement of the recess 210 on the upper surface 64 and the recess 210 on the front end surface 66 is shown, but the recess 210 can also be arranged on the lower surface 62 and the front end surface 66.

[0224] Figure 42 This is a diagram showing other configuration examples of the recess 210 and planar surface 212 of the front end face 66. The shape of the recess 210 of the front end face 66 in this example is similar to... Figure 27 or Figure 28 The examples differ. Other structures are different. Figure 27 or Figure 28 The examples are the same.

[0225] In this example, the width of the recess 210 in the lateral direction (Y-axis direction) is greater than its width in the height direction (Z-axis direction). According to this example, the path from the lower surface 62 through the planar portion 212 to the upper surface 64 can be lengthened. Therefore, solder propagation can be further suppressed. The recess 210 can have a shape such as an oblong, elliptical, or rectangular shape on the front end face 66. The lateral width of the recess 210 can be more than 1.5 times, more than 2 times, or more than 3 times the width in the height direction. It should be noted that multiple recesses 210 are provided in the lateral direction. That is, the lateral width of the recess 210 is less than half the lateral width of the front end face 66.

[0226] Figure 43 This is a diagram showing other configuration examples of the recess 210 and planar surface 212 of the front end face 66. The shape of the recess 210 of the front end face 66 in this example is similar to... Figure 27 , Figure 28 ,or Figure 42 The examples differ. Other structures are different. Figure 27 , Figure 28 ,or Figure 42 The examples are the same.

[0227] In this example, the recess 210 of the front end face 66 has a recessed portion 214. The recessed portion 214 is the part of the recess 210 that is recessed from the lower surface 62 side to the upper surface 64 side. The flat portion 212 that contacts the recessed portion 214 is surrounded by the recessed portion 210 in three directions: upper side, lateral side, and both sides. Therefore, it is possible to prevent solder that has reached the recessed portion 214 from spreading further to the upper surface 64 side.

[0228] Figure 44 This is a diagram showing other configuration examples of the recess 210 and planar surface 212 at the front end face 66. The configuration of the recess 210 at the front end face 66 in this example is similar to... Figure 27 , Figure 28 , Figure 42 or Figure 43 The examples differ. Other structures are different. Figure 27 , Figure 28 , Figure 42 or Figure 43 The examples are the same.

[0229] In this example, the density of the recesses 210 in the transverse direction (Y-axis direction) is higher than the density of the recesses 210 in the height direction (Z-axis direction). The density of the recesses 210 can be the reciprocal of the spacing between two adjacent recesses 210 in each direction. The spacing of the recesses 210 is... Figure 26 The interval P is described in the text. Figure 42In this example, the spacing PY of the lateral recesses 210 is smaller than the spacing PZ of the recesses 210 in the height direction. The spacing PZ can be more than 1.5 times or more than 2 times the spacing PY. According to this example, the lateral spacing PY of the recesses 210 is small, thus suppressing solder from passing between the two recesses 210 arranged in the lateral direction.

[0230] Figure 45 This is a diagram showing other configuration examples of the recess 210 and planar surface 212 of the front end face 66. The configuration of the recess 210 of the front end face 66 in this example is similar to... Figure 27 , Figure 28 or Figures 42 to 44 The examples differ. Other structures are different. Figure 27 , Figure 28 or Figures 42 to 44 The same as any of the examples in the text.

[0231] In this example, the density of the recesses 210 in the height direction (Z-axis direction) increases further away from the lower surface 62. As an example, the spacing PZ of adjacent recesses 210 in the height direction, closest to the upper surface 64, is designated as PZ1, and the spacing of the group closest to the lower surface 62 is designated as PZ2. Spacing PZ2 is greater than spacing PZ1. Spacing PZ2 can be more than 1.5 times or more than 2 times the spacing PZ1. According to this example, the spacing PZ of the recesses 210 near the upper surface 64 is small, therefore, the closer to the upper surface 64, the better the solder propagation is suppressed.

[0232] In the above Figures 31 to 45 In the example, the front face 66 is shown and explained. However, similar to S341, obstruction areas 251 can also be provided on each side face 68, as with the front face 66. That is, multiple recesses 210 and planar surfaces 212 can be formed on the front face 66, each side face 68, and the upper surface 64 to constitute obstruction areas 251. In addition, in Figures 31 to 45 The lead frame 50 illustrated in the example can also have... Figures 1 to 23 The rough surface region 51 is described in the diagram. The obstruction region 251 can also function as the rough surface region 51.

[0233] <<Manufacturing method of rough surface area 51 and obstruction area 251; Explanation of mold roughening>>

[0234] Figure 46 This diagram illustrates a portion of the manufacturing process of the semiconductor module 100. In this example, a shape is transferred onto the surface of the chip connector 52, specifically the upper surface 64 of the chip connector 52, using a mold, and a barrier region 251 (S441) is formed with a plurality of recesses 210 and planar surfaces 212.

[0235] Next, the lead frame 50 is soldered to the semiconductor chip 40 using solder 32 (S442). Before S442, a recess 210 and a planar surface 212 are formed on the front end surface 66, etc., thus suppressing the propagation of solder 32 at the front end surface 66, etc. S442 can be... Figure 29 The same process as S342.

[0236] Next, coating 13 is formed (S443). In S443, coating 13 can be formed on the surfaces of lead frame 50 and solder 32. After S443, lead frame 50 and semiconductor chip 40 can be encapsulated using sealing resin 12. Thus, semiconductor module 100 can be formed. S443 can be related to... Figure 29 The same process as S343.

[0237] Figure 47 This diagram illustrates the shape transfer process of the die 320 onto the chip connector 52. In this example, the die 320 transfers the shape onto the surface of the chip connector 52. By transferring the shape onto the surface of the chip connector 52, recesses 210 and planar portions 212 can be formed. In this example, the shape is transferred onto the upper surface 64 to form three recesses 210 and planar portions 212. That is, in this example, the three recesses 210 are die holes formed by stamping. It should be noted that the stamping process that forms these three recesses 210 may not require the lower surface 62, which is the side opposite to the upper surface 64, to be ejected. That is, the shape of the lower surface 62 of the chip connector 52 may remain flat without changing before and after forming the die holes. In contrast, when forming the protrusion 88 by stamping, the upper surface 64 may be recessed, and the lower surface 62 may be ejected by the amount of the recess in the upper surface 64, thereby forming a protrusion that becomes the protrusion 88.

[0238] The mold 320 has a first portion 322 and a second portion 324. The mold 320 is capable of transferring the shape of the first portion 322. As an example, the first portion 322 is a square pyramid shape. Preferably, the first portion 322 is a shape that is easy to remove after the shape is transferred. The second portion 324 is connected to the three first portions 322.

[0239] In this example, the die 320 is used to press and compress the chip connector 52, thereby forming the recess 210 and the flat surface 212. Therefore, the recess 210 is more compressed than the other surfaces. The recess 210 can be more compressed than the flat surface 212. The compression of the recess 210 can also mean that the hardness of the recess 210 is higher than that of the other surfaces. Furthermore, the compression of the recess 210 can also mean that the density of the recess 210 is higher than that of the other surfaces.

[0240] The surface of the chip connector 52 can be a rough surface area with an unfolded area ratio of 0.1 or higher. Alternatively, the surface of the chip connector 52 can be a rough surface area with an unfolded area ratio of 0.4 or lower, preferably 0.35 or lower, and more preferably 0.3 or lower. By using the mold 320 to form the recess 210 and the planar surface 212, the surface of the chip connector 52 can be made into a rough surface area.

[0241] Figure 48 This is a diagram showing an example of the configuration of the recess 210 and the planar surface 212 on the upper surface 64. (See diagram) Figure 48 As shown, the recess 210 can be positioned on a straight line. The upper surface of the recess 210 can be polygonal. In this example, the upper surface of the recess 210 is quadrilateral.

[0242] Figure 49 This diagram provides a detailed description of the shape of the recess 210 and the planar surface 212 on the upper surface 64. Figure 49 The diagram shows the shape of the recess 210 and the planar portion 212 formed using a mold. In this example, the planar portion 212 has a raised portion 216 and a standard portion 218. By forming the recess 210 using a mold, the raised portion 216 is formed adjacent to the recess 210. The raised portion 216 is a portion whose height in the height direction is the same as or higher than that of the standard portion 218 in the height direction. In this example, the raised portion 216 is higher than that of the standard portion 218 in the height direction. The standard portion 218 is, for example, a portion whose height does not change from the surface before the recess 210 is formed. The standard portion 218 is adjacent to the raised portion 216. The standard portion 218 may be recessed relative to the raised portion 216 in the height direction. In addition, at least a portion of the recess 210 is configured to be recessed relative to the standard portion 218 in the height direction. The raised portion 216 is held between the recess 210 and the standard portion 218.

[0243] As a method for distinguishing between the raised portion 216, the standard portion 218, and the recess 210, their heights in the respective height directions can be compared. The height difference d1 between the standard portion 218 and the recess 210 in the height direction is greater than the height difference d2 between the raised portion 216 and the standard portion 218 (which can also be considered the depth of the recess 210). d2 can be less than 30% of d1. d2 can be less than 20% of d1. When d2 is less than d1, the raised portion 216, the standard portion 218, and the recess 210 can be distinguished. Another method for distinguishing between the raised portion 216, the standard portion 218, and the recess 210 can also be achieved by observing the upper surface 64 (for example, referring to...). Figure 48 The portion observed from above is identified as standard part 218.

[0244] d1 can be 20 μm or more. d1 can be 200 μm or less. d1 is more preferably 50 μm or more and 150 μm or less. Additionally, the width d3 of the recess 210 can be 50 μm or more. d3 can be 250 μm or less. d3 is more preferably 100 μm or more and 200 μm or less. Additionally, the spacing width d4 of the recess 210 can be 200 μm or more. d4 can be 700 μm or less. d4 is more preferably 300 μm or more and 600 μm or less. Additionally, the minimum length d7 of the planar portion 212 can be 150 μm or more. d7 can be 450 μm or less. d7 is more preferably 200 μm or more and 400 μm or less. The minimum length d7 can be set to the length obtained by extending the standard portion 218 along the horizontal direction (X-axis direction or Y-axis direction). Figure 49 In this design, the minimum length d7 of the planar portion 212 is set as the minimum length between the recesses 210 when the standard portion 218 extends in the horizontal direction (X-axis direction or Y-axis direction). However, the minimum length d7 can also be approximated by the minimum length of the portion in which no recesses 210 are formed when viewed from above.

[0245] Although this example shows the shape of the recess 210 and the flat surface 212 formed by using a mold, the recess 210 and the flat surface 212 formed by laser irradiation can also have the same shape. That is, the flat surface 212 formed by laser irradiation can also have a raised portion 216 and a standard portion 218. In the case of being formed by laser irradiation, as an example, d1 is 10 μm.

[0246] In the above Figures 46 to 49 In examples such as S441, multiple recesses 210 and planar surfaces 212 can be formed on the front end face 66, each side face 68, and the upper surface 64 to constitute an obstruction area 251; alternatively, an obstruction area 251 can be formed only on the upper surface 64. It should be noted that... Figures 46 to 49 The lead frame 50 illustrated in the example can also have Figures 1 to 23 The rough surface region 51 is described in the diagram. The obstruction region 251 can also function as the rough surface region 51.

[0247] <<Manufacturing method of rough surface area 51 and obstruction area 251; Explanation of liquid roughening>>

[0248] Although the method of forming the rough surface region 51 using laser irradiation and a mold has been described, the rough surface region 51 can also be formed using a roughening liquid. The roughening liquid can be a commercially available product. When using a roughening liquid, a mask can be used on the surface where the rough surface region 51 is not formed, or the entire surface can be roughened without using a mask.

[0249] <<Combined use of roughening methods (laser roughening, mold roughening, liquid roughening)>>

[0250] Figure 50 This diagram illustrates a portion of the manufacturing process of the semiconductor module 100. In this example, a mold is used to transfer a shape onto the surface of the chip interconnect portion 52, specifically the upper surface 6 of the chip interconnect portion 52, forming a plurality of recesses 210 and planar surfaces 212 (S541). S541 can be... Figure 46 The same process as S441.

[0251] After the shape is transferred using a mold (S541), the surface of the chip connection portion 52, specifically at least the front end surface 66, is irradiated with a laser to form a plurality of recesses 210 and planar surfaces 212, and an obstruction area 251 is provided (S542). In S542, a plurality of recesses 210 and planar surfaces 212 may also be formed on each side surface 68 and the upper surface 64.

[0252] Next, the lead frame 50 is soldered to the semiconductor chip 40 using solder 32 (S543). Before S543, recesses 210 and planar surfaces 212 are formed on the front end surface 66, etc., thus suppressing the propagation of solder 32 at the front end surface 66, etc. S543 can be... Figure 29 The same process as S342.

[0253] Next, coating 13 is formed (S544). In S544, coating 13 can be formed on the surfaces of lead frame 50 and solder 32. After S544, lead frame 50 and semiconductor chip 40 can be encapsulated using sealing resin 12. Thus, semiconductor module 100 can be formed. S544 can be related to... Figure 29 The same process as S343.

[0254] Figure 51 This diagram illustrates the shape of the chip connector 52. In this example, a shape is transferred onto the upper surface 64 of the chip connector 52 using a mold. After the shape is transferred using the mold, a laser is irradiated onto the front end face 66 of the chip connector 52. Therefore, the recess 210 formed on the upper surface 64 is a mold hole. Additionally, the recess 210 formed on the front end face 66 is a laser hole.

[0255] Furthermore, the depth of the mold hole is greater than the depth of the laser hole. That is, the depth d5 ​​of the recess 210 formed on the upper surface 64 is greater than the depth d6 of the recess 210 formed on the front end face 66. This structure can be achieved by providing a mold hole on the upper surface 64 and a laser hole on the front end face 66.

[0256] Figure 52 This is a diagram showing an example of the configuration of the recess 210 and the planar portion 212 of the upper surface 64 and the front end surface 66. Figure 52The upper surface 64 and the front end surface 66 are shown in the Y-axis direction in common. The recess 210 is formed by obliquely irradiating the front end surface 66 and the upper surface 64 of the chip connection portion 52 with a laser 312. On the upper surface 64, the recesses 210 formed by laser irradiation are disposed only near the front end surface 66 and the side surface 68. In addition, the recesses 210 formed by a mold are disposed on the upper surface 64. The recesses 210 formed by laser irradiation have curves. In this example, the recesses 210 formed by laser irradiation are circular. In addition, the shape of the front end surface 66 of the recess 210 is curved. In addition, the recesses 210 formed by the mold are polygonal. In this example, the recesses 210 formed by the mold are quadrilaterals.

[0257] In this example, laser irradiation is performed in a manner that overlaps at least a portion of the plurality of recesses 210 formed by mold transfer. That is, on the upper surface, the recesses 210 formed by laser irradiation overlap at least a portion of the recesses 210 formed by the mold. By adopting such a structure, a barrier region 251 can be provided across the entire upper surface 64.

[0258] Figure 53 This is a diagram showing an example of the configuration of the recess 210 on the upper surface 64, the front end surface 66, and the lower surface 62. Figure 53 The upper surface 64, the front end surface 66, and the lower surface 62 are shown in the Y-axis direction. The recess 210 is formed by obliquely irradiating the front end surface 66 and the lower surface 62 of the chip connection portion 52 with laser 312. In addition, a recess 210 formed by a mold is disposed on the upper surface 64. By making such a configuration, obstruction areas 251 can be provided on the upper surface 64, the front end surface 66, and the lower surface 62. It should be noted that each side surface 68 can also have obstruction areas 251 formed in the same way as the front end surface 66.

[0259] In the above Figures 50 to 53 In examples such as S541 and S542, multiple recesses 210 and planar surfaces 212 can be formed on the front end face 66, each side face 68, and the upper surface 64 to constitute an obstruction area 251; alternatively, an obstruction area 251 can be formed only on the upper surface 64. It should be noted that... Figures 50 to 53 The lead frame 50 illustrated in the example can also have Figures 1 to 23 The rough surface region 51 described herein. The obstruction region 251 can also function as the rough surface region 51. In this case, the unfolded area ratio of the region of the upper surface 64 where the mold hole is formed can be 0.1 or more. The unfolded area ratio of the regions of the front end face 66 and each side face 68 where the laser hole is formed can be 0.2 or more.

[0260] In the above description, although an example of using laser roughening and mold roughening together has been given, this embodiment is not limited to this. For example, laser roughening and liquid roughening can be used together, or mold roughening and liquid roughening can be used together.

[0261] <<Explanation of other examples of the configuration of obstruction zone 251>>

[0262] Figure 54 This is a diagram illustrating another example of the configuration of the obstruction zone 251. Figure 54 The diagram shows an example of the arrangement of the obstruction region 251 on the upper surface 64 of the chip connection portion 52. Figure 54 In the diagram, the obstruction area 251 is represented by shading. In other examples of the arrangement of the obstruction area 251, a plurality of recesses 210 are periodically arranged in at least two directions on at least any one side of the chip connection portion 52. Moreover, at least one side of the chip connection portion 52 has periodically arranged unprocessed portions 336 that are interrupted. It should be noted that the unprocessed portions 336 may be planar portions 212.

[0263] Figure 55 It is shown Figure 54 A diagram showing an example of the configuration of the recess 210 on the upper surface 64 and the recess 210 on the front end surface 66. Figure 55 The diagram shows the arrangement of multiple recesses 210 and planar surfaces 212. An obstruction region 251 can be formed by forming multiple recesses 210 and planar surfaces 212. The obstruction region 251 can also function as a rough surface region 51. That is, in addition to the structure and function described as an obstruction region 251, the obstruction region 251 can also have any of the structures and functions described as a rough surface region 51.

[0264] like Figure 54 , Figure 55 As shown, a plurality of recesses 210 and planar surfaces 212 are formed on the upper surface 64 of the chip connection portion 52. Additionally, as... Figure 55 As shown, a plurality of recesses 210 and planar surfaces 212 are formed on the front end surface 66 of the chip connection portion 52. Additionally, although not shown, a plurality of recesses 210 and planar surfaces 212 may also be formed on the side surface 68 of the chip connection portion 52, similar to the front end surface 66.

[0265] The edge furthest from the bridging portion 54 among the edge edges constituting the shape of the upper surface 64 is designated as edge 181. In this example, although the upper surface 64 is a generally rectangular shape with two sets of parallel sides, it could also be other shapes. The edge edge of the upper surface 64 can be a straight line. Edge 181 is connected to the front end face 66. That is, the upper surface 64 and the front end face 66 are connected at edge 181. Furthermore, the edge closest to the bridging portion 54 among the edge edges of the upper surface 64 is designated as edge 182. Edge 182 is connected to the side face 68. That is, the upper surface 64 and the side face 68 are connected at edge 182. The edge between edge 181 and edge 182 among the edge edges of the upper surface 64 is designated as edge 183. Edge 183 is connected to the side face 68. That is, the upper surface 64 and the side face 68 are connected at edge 183. Edge 181 and edge 183 can be connected using a curve when viewed from above.

[0266] In this example, the multiple recesses 210 and planar surfaces 212 are formed by laser roughening. The multiple recesses 210 and planar surfaces 212 can also be formed by mold roughening. The multiple recesses 210 and planar surfaces 212 can also be formed by liquid roughening.

[0267] In this example, the obstruction area 251 is not provided near end edges 181 and 183. That is, unprocessed portions 336 can be present near end edges 181 and 183. Figure 55 In the middle, the shortest distance A1 between the recess 210 and the end edge 181 is greater than the interval A3 between adjacent recesses 210. The interval A3 between adjacent recesses 210 can be the minimum length of the planar portion 212 (in Figure 49 In the example, it is d7). The shortest distance A1 can be more than twice, more than five times, or more than ten times the interval A3. Additionally, in Figure 55 In this case, the shortest distance A2 between the recess 210 and the end edge 183 is greater than the interval A3 between adjacent recesses 210. The shortest distance between the recess 210 formed on the upper surface 64 and at least one end edge of the surface (upper surface 64) can be greater than the interval A3 between adjacent recesses 210. The shortest distance A2 can be more than 5 times, more than 10 times, or more than 20 times the interval A3.

[0268] Figure 56 This is a diagram showing an example of the chip connection portion 52 in a comparative example. If at the end edge of the upper surface 64 (in...) Figure 56 In the example, setting a barrier region 251 near the end edge 181 results in a recess 210-5 forming on both the upper surface 64 and the front end face 66 (or side face 68). The recess 210-5 facilitates solder wetting and propagation from the front end face 66 (or side face 68) to the upper surface 64. Figure 54 , Figure 55In the example, no obstruction area 251 is provided near the end edge 181 and end edge 183, thus suppressing the formation of the recess 210-5 and suppressing the wetting and spreading of solder. It should be noted that, from the viewpoint of suppressing the wetting and spreading of solder, it is preferable to set the unfolded area ratio of the upper surface 64 on which the plurality of recesses 210 are formed to 0.7 or less.

[0269] The shortest distance A1 between the recess 210 and the end edge 181 can be 0.3 mm or more and 1.5 mm or less. The shortest distance A2 between the end edge 183 and the recess 210 can be 0.3 mm or more and 1.5 mm or less. The interval A3 between adjacent recesses 210 can be 30 μm or more and 60 μm or less.

[0270] Furthermore, the shortest distance A1 between the recess 210 and the end edge 181 can be greater than the thickness of the chip connection portion 52 in the Z-axis direction. The shortest distance A2 between the recess 210 and the end edge 183 can be greater than the thickness of the chip connection portion 52 in the Z-axis direction. The thickness of the chip connection portion 52 in the Z-axis direction can be 0.3 mm or more, preferably 0.5 mm or more.

[0271] The shortest distance A1 between the recess 210 formed on the upper surface 64 of the chip interconnect and the end edge 181 can be greater than the shortest distance between the recess 210 formed on the front end surface 66 of the chip interconnect 52 and the end edge 181. For example... Figure 55 As shown, the recess 210 can be provided near the edge 181 on the front end face 66 of the chip connection portion 52. Similarly to the front end face 66, the shortest distance A2 between the recess 210 formed on the upper surface 64 of the chip connection portion and the edge 183 can be greater than the shortest distance between the recess 210 formed on the side surface 68 of the chip connection portion 52 and the edge 183 (not shown). The recess 210 may also not be provided near the edge 181 on the front end face 66 of the chip connection portion 52. That is, the shortest distance between the recess 210 formed on the front end face 66 of the chip connection portion 52 and the edge 181 can also be greater than the interval A3 between adjacent recesses 210.

[0272] Figure 57 The diagram shows another example of the configuration of the obstruction zone 251. Figure 57 and Figure 54 The difference is that the obstruction area 251 is not provided near the end edge 182. That is, an unprocessed portion 336 may be present near the end edge 182. Figure 57 Other than this, the composition can be with Figure 54 same.

[0273] The shortest distance A8 between the recess 210 and the end edge 182 can be greater than the interval A3 between adjacent recesses 210 (see reference). Figure 55The shortest distance A8 between the recess 210 and the end edge 182 can be 0.3 mm or more and 1.5 mm or less. By having such a configuration, it is possible to suppress the wetting and propagation of solder near the bridging portion 54.

[0274] Figure 58 This is a diagram illustrating another example of the configuration of the obstruction zone 251. Figure 58 The diagram shows an example of the arrangement of the obstruction region 251 on the upper surface 64 of the chip connection portion 52. Figure 58 In the middle, shadows are used to represent the obstruction area 251.

[0275] Figure 59 It is shown Figure 58 A diagram showing an example of the configuration of the recess 210 on the upper surface 64 and the recess 210 on the front end surface 66. Figure 59 The diagram shows the configuration of multiple recesses 210 and planar surfaces 212. An obstruction region 251 can be formed by creating the multiple recesses 210 and planar surfaces 212. The obstruction region 251 can also function as a roughened surface region 51. In this example, the multiple recesses 210 and planar surfaces 212 are formed by laser roughening.

[0276] In this example, end edge 183-1 is opposite to end edge 183-2. End edge 183-1 is an example of the first end edge. End edge 183-2 is an example of the second end edge. End edge 181 is an example of the third end edge.

[0277] In this example, the obstruction area 251 is not located near the center line CL of the upper surface 64 of the chip connection portion 52. That is, an unprocessed portion 336 can be present near the center line CL. The center line CL refers to the line passing through the center C of the upper surface 64 of the chip connection portion 52. The center line CL is parallel to the X-axis direction. The center C of the upper surface 64 of the chip connection portion 52 can be the center in the XY plane of the upper surface 64 of the chip connection portion 52, or it can be the centroid of the upper surface 64 of the chip connection portion 52. The maximum distance A4 between the recesses 210 sandwiched by the end edges 183-1 and 183-2 is greater than the first shortest distance A5 between the recesses 210 formed on the upper surface 64 of the chip connection portion 52 and the end edge 183-1 (see reference). Figure 59 Furthermore, the maximum distance A4 between the recesses 210 sandwiched by end edges 183-1 and 183-2 is greater than the second shortest distance (not shown) between the recesses 210 formed on the upper surface 64 of the chip connection portion 52 and the end edge 183-2.

[0278] Figure 60 This diagram illustrates the irradiation of a laser onto the chip connection portion 52 of the comparative example. Consider, for example... Figure 33In cases where a common light source 310 is used to irradiate at least two surfaces of the chip interconnect 52 without moving the chip interconnect 52, for example, laser 312 is irradiated at an angle towards edge 183-1 and edge 183-2. In this case, it is assumed that the laser beams (irradiation positions) will overlap near the center line CL of the upper surface 64 of the chip interconnect 52. In this case, solder will easily wet and spread near the center line CL of the upper surface 64 of the chip interconnect 52. In this example, the obstruction region 251 is not provided near the center line CL of the upper surface 64 of the chip interconnect 52, thus preventing the laser beams from overlapping near the center line CL of the upper surface 64 of the chip interconnect 52. Therefore, solder wetting and spreading can be suppressed.

[0279] As an example, the maximum distance A4 between the recesses 210 sandwiched between edge 183-1 and edge 183-2 can be 0.3 mm or more and 1.5 mm or less. The first shortest distance A5 between the recess 210 formed on the upper surface 64 of the chip connection portion 52 and edge 183-1 can be 30 μm or more and 60 μm or less. The second shortest distance between the recess 210 formed on the upper surface 64 of the chip connection portion 52 and edge 183-2 can be 30 μm or more and 60 μm or less.

[0280] The spacing of the recesses 210 at the center C between the end edges 183-1 and 183-2 of the upper surface 64 of the chip connection portion 52 can be greater than the first shortest distance A5 and the second shortest distance. By making the spacing of the recesses 210 at the center greater than the first shortest distance A5 and the second shortest distance, it is possible to prevent the spot beams that cause laser irradiation from overlapping each other near the center C. The maximum distance A4 among the spacings of the recesses 210 sandwiched between the end edges 183-1 and 183-2 can be the spacing of the recesses 210 at the center C. That is, the spacing of the recesses 210 can be the maximum at the center C between the end edges 183-1 and 183-2. Alternatively, the spacing of the recesses 210 at the center C may not be the maximum.

[0281] Furthermore, the shortest distance A6 between the recess 210 formed on the upper surface 64 of the chip interconnect portion 52 and the end edge 181 is greater than the first shortest distance A5. Additionally, the shortest distance A6 between the recess 210 formed on the upper surface 64 of the chip interconnect portion 52 and the end edge 181 is greater than the second shortest distance. Therefore, since no obstruction area 251 is provided near the end edge 181, solder wetting and propagation can be suppressed.

[0282] The shortest distance A6 between the recess 210 formed on the upper surface 64 of the chip interconnect portion 52 and the edge 181 is greater than the shortest distance A7 between the recess 210 formed on the front end surface 66 of the chip interconnect portion 52 and the edge 181. That is, a barrier region 251 is provided on the front end surface 66 near the edge 181. By providing a barrier region 251 on the front end surface 66 near the edge 181, solder wetting and spreading can be suppressed. It should be noted that the shortest distance A7 between the recess 210 formed on the front end surface 66 of the chip interconnect portion 52 and the edge 181 can be greater than the interval A3 between adjacent recesses 210.

[0283] Figure 61 The diagram shows another example of the configuration of the obstruction zone 251. Figure 61 and Figure 58 The difference is that the obstruction area 251 is located near the end edge 182. Figure 61 Other than this, the composition can be with Figure 58 The same applies. Even with this configuration, solder wetting and propagation can be suppressed.

[0284] Figure 62 The diagram shows another example of the configuration of the obstruction zone 251. Figure 62 and Figure 58 The difference is that the obstruction area 251 is not provided near the end edge 183. That is, an unprocessed portion 336 may be present near the end edge 183. Figure 62 Other than this, the composition can be with Figure 58 The same applies. Even with this configuration, solder wetting and propagation can be suppressed.

[0285] Figure 63 This is a diagram illustrating another example of the configuration of the obstruction zone 251. Figure 63 The diagram shows an example of the arrangement of the obstruction region 251 on the upper surface 64 of the chip connection portion 52. Figure 63 In the middle, the obstruction area 251 has an overlapping part 332 and a non-overlapping part 334, which are represented by different shades respectively.

[0286] Figure 64 It is shown Figure 63 A diagram showing an example of the configuration of the recess 210 on the upper surface 64 and the recess 210 on the front end surface 66. Figure 64The diagram shows the arrangement of multiple recesses 210 and planar surfaces 212. An obstruction region 251 can be formed by creating multiple recesses 210 and planar surfaces 212. The obstruction region 251 can also function as a rough surface region 51. The overlapping portion 332 can be formed by controlling the spot beam of laser irradiation (the irradiation position of the laser irradiation). It should be noted that the arrangement of the recesses 210 in the overlapping portion 332 can be the irradiation position of the laser irradiation. It should be noted that the overlapping portion 332 may also not have a planar portion 212 disposed between two recesses 210. That is, it may not function as an obstruction region 251, but rather as a rough surface region 51.

[0287] In the overlapping portion 332, adjacent recesses 210 overlap. Figure 64 In this configuration, recesses 210 are also provided between adjacent recesses 210. Overlapping portions 332 can be formed by further irradiating a flat portion 212 disposed between adjacent recesses 210 with a laser. The overlapping portion 332 can be a continuous portion of adjacent recesses 210. The flat portion 212 may or may not be provided in the overlapping portion 332. In the non-overlapping portion 334, a flat portion 212 is provided between adjacent recesses 210. Compared to the unfolded area ratio of the non-overlapping portion 334, the unfolded area ratio of the overlapping portion 332 can be larger. Furthermore, compared to the solder in the non-overlapping portion 334, the solder in the overlapping portion 332 is easier to wet and spread.

[0288] In this example, the overlapping portion 332 is positioned further inside the surface (upper surface 64) than the non-overlapping portion 334. That is, the overlapping portion 332 is not located near the end edges 181, 182, and 183 of the upper surface 64. By positioning the overlapping portion 332 further inside than the non-overlapping portion 334, it is possible to increase the unfolded area ratio while suppressing the wetting and spreading of solder from the front end face 66 and the side face 68.

[0289] Figure 65 This diagram illustrates the shape of the overlapping portion 332. In this example, a recess 210 is formed on the upper surface 64 and the front end surface 66 of the chip connection portion 52 by laser irradiation. The recess 210 in this example is a laser aperture. Furthermore, by overlapping the irradiation positions of the laser irradiation, the overlapping portion 332 is formed on the upper surface 64 of the chip connection portion 52.

[0290] The depth d7 of the recess 210 in the overlapping portion 332 is deeper than the depth d8 of the recess 210 in the non-overlapping portion 334. The depth d7 can be at least 1.5 times the depth d8. Furthermore, the depth d7 of the recess 210 in the overlapping portion 332 is deeper than the depth d9 of the recess 210 formed on the front end face 66. The depth d7 can be at least 1.5 times the depth d9. Because the recess 210 in the overlapping portion 332 is deeper than the recesses 210 in other portions besides the overlapping portion 332, it is possible to distinguish between the overlapping portion 332 and the non-overlapping portion 334.

[0291] exist Figures 54 to 65 In the example, the obstruction area 251 of the chip connection portion 52 is shown and explained, but the above configuration can also be applied to the circuit pattern connection portion 56 and / or other surfaces.

[0292] <<Explanation of Obstacle Section 230>>

[0293] Figure 66 This is a diagram showing other examples of the lead frame 50. The lead frame 50 in this example is similar to... Figures 1 to 34 The difference in the example is that the chip connection portion 52 has a main material portion 231 and a blocking portion 230. Other structures can be similar. Figures 1 to 34 The same applies to any of the methods described herein.

[0294] The main material portion 231 is formed of the same material as the lower surface 62. When multiple material portions are exposed on the lower surface 62, the main material portion 231 is formed of the same material as the portion with the largest area on the lower surface 62. The main material portion 231 is, for example, formed of copper or an alloy containing copper. The main material portion 231 may also be formed of the same material as the bridging portion 54.

[0295] The barrier portion 230 is formed of a material with lower solder wettability than that of the main material portion 231. That is, the barrier portion 230 is a portion where solder is more difficult to spread than that of the main material portion 231. The barrier portion 230 is formed of, for example, ceramic, carbon, aluminum, an aluminum-containing alloy, iron, or an iron-containing alloy.

[0296] The barrier portion 230 is exposed at the front end face 66 of the chip interconnect portion 52. This helps to suppress solder propagation at the front end face 66. The barrier portion 230 may also be exposed at the side face 68 of the chip interconnect portion 52. The chip interconnect portion 52 may be formed of a cladding material formed by laminating the main material portion 231 and the barrier portion 230. Alternatively, the barrier portion 230 may be provided between two main material portions 231 in the chip interconnect portion 52.

[0297] Figure 67 This diagram shows an example of the configuration of the main material portion 231 and the obstruction portion 230 in the chip connection portion 52. Figure 67In the image, the obstruction portion 230 is shaded by a diagonal line. Furthermore, the obstruction portion 230, which is covered by the main material portion 231, is also shown through the main material portion 231.

[0298] In the chip connection portion 52 of this example, the plate-shaped main material portion 231 and the plate-shaped obstruction portion 230 are laminated in the height direction. Plate-shaped means that the area of ​​the main surface that is substantially parallel to the upper surface 64 is larger than the area of ​​any side surface that is substantially perpendicular to the upper surface 64. Figure 67 The chip connection portion 52 shown has a main material portion 231-1 exposed on the upper surface 64, a main material portion 231-2 exposed on the lower surface 62, and a blocking portion 230 sandwiched between the two main material portions 231. The blocking portion 230 is exposed on the front end face 66 and each side face 68. The blocking portion 230 is exposed at a predetermined height position on each face in a manner that traverses each face. That is, in the lateral direction, the width of the blocking portion 230 is the same as the width of each face. With this shape, the spread of solder at the front end face 66 and each side face 68 can be suppressed.

[0299] The widths of the main material section 231-1, the main material section 231-2, and the obstruction section 230 in the height direction are respectively set to Z1, Z2, and Z3. The obstruction section 230 may have the same width Z3 on the front end face 66 and each side face 68. The main material section 231-1 may also have the same width Z1 on the front end face 66 and each side face 68. The main material section 231-2 may also have the same width Z2 on the front end face 66 and each side face 68.

[0300] The width Z3 of the obstruction portion 230 is greater than either the width Z1 of the main material portion 231-1 or the width Z2 of the main material portion 231-2. The width Z3 can be greater than the sum of the widths Z1 and Z2. This easily suppresses solder spread at each surface. The width Z1 can be the same as, larger than, or smaller than the width Z2.

[0301] Figure 68 This is a diagram showing other examples of the lead frame 50. In this example, with... Figure 66 and Figure 67 The difference in this example is that the obstruction 230 is exposed on the upper surface 64. Other structures are similar. Figure 66 and Figure 67 The examples are the same.

[0302] Figure 69 It is Figure 68 An enlarged schematic diagram of the chip connection portion 52. As described above, in this example, the obstruction portion 230 is exposed on the upper surface 64. The obstruction portion 230 can be exposed across the entire upper surface 64. The chip connection portion 52 in this example does not have... Figure 67 The main material section 231-1 is shown.

[0303] Figure 70 This is a diagram showing another example of the lead frame 50. In this example, the shape of the obstruction portion 230 is similar to... Figures 66 to 69 The examples differ. Other structures are different. Figures 66 to 69 The same applies to any of the examples. In this example, the obstruction 230 is exposed on the lower surface 62.

[0304] Figure 71 This diagram shows an example of the arrangement of the obstruction portion 230 at the lower surface 62 of the chip connection portion 52. In this example, the obstruction portion 230 is positioned on the lower surface 62 further outward than the protrusion portion 88. "Further outward than the protrusion portion 88" refers to the area between the protrusion portion 88 and the front end surface 66, or between the protrusion portion 88 and the side surface 68.

[0305] The obstruction portion 230 may contact the front end face 66. The obstruction portion 230 may be exposed on the front end face 66. The obstruction portion 230 may contact the side face 68. The obstruction portion 230 may be output from the side face 68. The obstruction portion 230 may be separated from the protrusion 88. According to this example, it is possible to suppress the spread of solder at the front end face 66 and the side face 68 while wetting most of the lower surface 62 with solder.

[0306] Figure 72 It is magnification Figure 70 and Figure 71 A schematic diagram of the chip connection portion 52. As described above, in this example, the obstruction portion 230 is exposed on the lower surface 62. Furthermore, the obstruction portion 230 is exposed on the front end surface 66 and each of the side surfaces 68. Figure 72 As shown, the obstruction 230 in this example is a frame shape that surrounds a predefined area.

[0307] Figure 73 This diagram shows another configuration example of the obstruction portion 230 at the lower surface 62 of the chip connection portion 52. In this example, the obstruction portion 230 is positioned further outward than the protrusion 88 on the lower surface 62. However, the obstruction portion 230 does not contact the front end face 66. That is, the obstruction portion 230 is not exposed on the front end face 66. The obstruction portion 230 does not contact the side face 68. That is, the obstruction portion 230 is not exposed on the side face 68. The obstruction portion 230 can be separated from the protrusion 88. According to this example, it is also possible to suppress the spread of solder at the front end face 66 and the side face 68 while wetting most of the lower surface 62 with solder.

[0308] Figure 74 This is a diagram showing another configuration example of the main material portion 231 and the obstruction portion 230 in the chip connection portion 52. Figure 74 The obstruction portion 230, which is not covered by the main material portion 231, is shown in the diagram. In this example, the obstruction portion 230 is similar to... Figures 66 to 73The difference in this example is that it protrudes further outward than the main material portion 231 in the direction perpendicular to the front end face 66 of the chip connection portion 52 (X-axis direction). Other structures are similar to... Figures 66 to 73 The same applies to any example. On each side 68, the obstruction portion 230 may also protrude further outward than the main material portion 231.

[0309] In this example, steps can be formed on the front face 66 and the side face 68. Therefore, solder propagation can be further suppressed. The obstruction portion 230 can have, for example... Figure 67 or Figure 69 The plate shape is shown. In this case, the area of ​​the obstruction portion 230 at the XY plane is larger than the area of ​​the main material portion 231. The obstruction portion 230 may have the following characteristics: Figure 72 The frame shape is shown. In this case, the main material portion 231 has a portion surrounded by the obstruction portion 230. The main material portion 231 may have a recess on at least one of the front end face 66 and the side face 68 for a portion of the obstruction portion 230 to be inserted.

[0310] Figure 75 This is a diagram showing another configuration example of the main material portion 231 and the obstruction portion 230 in the chip connection portion 52. Figure 75 The obstruction portion 230, which is not covered by the main material portion 231, is shown in the diagram. In this example, the obstruction portion 230 is similar to... Figures 66 to 73 The difference in this example is that, in the direction perpendicular to the front end face 66 of the chip connection portion 52 (X-axis direction), it is recessed further inward than the main material portion 231. Other structures are similar to... Figures 66 to 73 The same applies to any example. On each side 68, the obstruction portion 230 may also be recessed further inward than the main material portion 231.

[0311] In this example, steps can be formed on the front face 66 and the side face 68. Therefore, solder propagation can be further suppressed. The obstruction portion 230 can have, for example... Figure 67 or Figure 69 The plate shape is shown. In this case, the area of ​​the obstruction portion 230 in the XY plane is smaller than the area of ​​the main material portion 231. The obstruction portion 230 may have the following characteristics: Figure 72 The frame shape is shown. In this case, the main material portion 231 has a portion surrounded by the obstruction portion 230.

[0312] Figure 76 This is a diagram showing another configuration example of the main material portion 231 and the obstruction portion 230 in the chip connection portion 52. Figure 76 In the middle, the obstruction part 230 covered by the main material part 231 is also shown through the main material part 231.

[0313] In this example, the obstruction portion 230 is laminated on the surface of the main material portion 231. For example, the obstruction portion 230 is laminated with the main material portion 231 in a direction perpendicular to the front end surface 66 of the chip connection portion 52. The obstruction portion 230 may also be laminated on each side surface 68.

[0314] In this example, a pre-defined material is deposited on the surface of the main material portion 231 using methods such as sputtering or spraying to form a barrier portion 230. The areas on each side of the chip interconnect portion 52 where the barrier portion 230 is exposed are... Figures 66 to 75 The same applies to any of the examples described. Based on this example, solder propagation at the front face 66 and other locations can also be suppressed.

[0315] The obstruction portion 230 can be formed of ceramics such as alumina, aluminum nitride, or silicon nitride, or it can be formed of carbon or metals such as iron. When the obstruction portion 230 is formed by sputtering or spraying, the grain shape of the material irradiated onto the main material portion 231 can be controlled. Therefore, the surface roughness of the obstruction portion 230 can be controlled. A rough surface region 51 can be formed on the surface of the obstruction portion 230. Alternatively, a rough surface region 51 can also be formed on the main material portion 231.

[0316] While the present invention has been described above using embodiments, its technical scope is not limited to those described in the above embodiments. Various changes or modifications can be made to the above embodiments, as will be apparent to those skilled in the art. As can be seen from the claims, such changes or modifications can also be included within the technical scope of the present invention.

[0317] The following methods are also disclosed in this specification and accompanying drawings.

[0318] (Project 1)

[0319] A semiconductor module, comprising:

[0320] An insulating circuit board having a circuit pattern formed on one side;

[0321] Semiconductor chip, which is mounted on the insulating circuit board;

[0322] Wiring section, which connects the semiconductor chip to the circuit pattern; and

[0323] The semiconductor chip is encapsulated in resin to protect it.

[0324] The wiring section has:

[0325] A chip connection portion, which is connected to the semiconductor chip;

[0326] Circuit pattern connection portion, which is connected to the circuit pattern; and

[0327] The bridging section connects the chip connection section and the circuit pattern connection section.

[0328] The chip connection portion has a lower surface opposite to the semiconductor chip.

[0329] The lower surface of the chip connector has a first side furthest from the bridging portion.

[0330] On the lower surface of the chip connection portion, a step or inclined portion is provided along the first side for more than half of the length of the first side.

[0331] (Project 2)

[0332] According to the semiconductor module described in Project 1

[0333] The lower surface of the chip connector has a second side that is closest to the bridging portion.

[0334] The inclined portion or step is provided along one of the sides of the lower surface of the chip connection portion, excluding the second side.

[0335] (Project 3)

[0336] The semiconductor module according to item 1 or 2

[0337] The lower surface of the chip connector is provided with a plurality of protrusions that project toward the semiconductor chip.

[0338] The height of the protrusion is lower than the height of the step or the height of the inclined portion.

[0339] (Project 4)

[0340] The semiconductor module according to any one of items 1 to 3,

[0341] The step is provided on the lower surface of the chip connection portion.

[0342] The step includes at least one of a protrusion and a groove, the protrusion projecting from the lower surface toward the circuit pattern, and the groove recessing from the lower surface toward the direction away from the circuit pattern.

[0343] (Project 5)

[0344] According to the semiconductor module described in Project 4

[0345] The step is the protrusion and is provided in contact with the first edge.

[0346] (Project 6)

[0347] According to the semiconductor module described in Project 4

[0348] The step is the groove and is provided in contact with the first side.

[0349] (Project 7)

[0350] According to the semiconductor module described in Project 4

[0351] The step is the groove and is provided separately from the first side.

[0352] (Project 8)

[0353] The semiconductor module according to any one of items 1 to 3,

[0354] The inclined portion is provided on the lower surface of the chip connection portion.

[0355] The inclined portion is formed by chamfering the corners of the lower surface.

[0356] (Project 9)

[0357] A semiconductor module, comprising:

[0358] An insulating circuit board having a circuit pattern formed on one side;

[0359] Semiconductor chip, which is mounted on the insulating circuit board; and

[0360] The wiring section electrically connects the semiconductor chip to the circuit pattern.

[0361] The wiring section has a chip connection section that connects to the semiconductor chip.

[0362] The chip connection portion has:

[0363] Main materials department; and

[0364] The obstruction section is formed of a material with lower solder wettability than the main material section and is disposed exposed on the front end face.

Claims

1. A semiconductor module, characterized in that, have: An insulating circuit board having a circuit pattern formed on one side; Semiconductor chip, which is mounted on the insulating circuit board; and The wiring section electrically connects the semiconductor chip and the circuit pattern. The wiring section has a chip connection section that connects to the semiconductor chip. The surface of the chip connection portion has: Multiple recesses; and The planar portion is positioned between two recesses. At least the plurality of recesses and the planar portion are formed on the front end surface of the chip connection portion. The plurality of recesses are periodically arranged in at least two directions on the front end face.

2. The semiconductor module according to claim 1, characterized in that, The maximum width of each of the plurality of recesses is 10 μm or more.

3. The semiconductor module according to claim 1, characterized in that, The center-to-center distance between at least two adjacent recesses in the plurality of recesses is more than 10 μm.

4. The semiconductor module according to claim 1, characterized in that, The semiconductor module further includes a bonding layer for bonding the semiconductor chip to the chip connection portion. The bonding layer is provided inside at least a portion of the plurality of recesses.

5. The semiconductor module according to claim 1, characterized in that, The surface having the plurality of recesses has a rough surface area with an unfolded area ratio of 0.2 or higher.

6. The semiconductor module according to claim 1, characterized in that, The surface having the plurality of recesses has a rough surface region with an unfolded area ratio of 0.7 or less.

7. The semiconductor module according to claim 1, characterized in that, The plurality of recesses are periodically arranged in at least two directions on at least any side of the chip interconnect portion. At least one side of the chip connection portion has an unprocessed portion that interrupts the periodic arrangement of the plurality of recesses.

8. The semiconductor module according to claim 1, characterized in that, The plurality of recesses are configured to have a predetermined gap in a lateral direction parallel to the lower surface of the chip connection portion. The plurality of recesses include recesses arranged side-by-side with the gap in a height direction perpendicular to the lateral direction.

9. The semiconductor module according to claim 1, characterized in that, At least a portion of the recesses have a lateral width greater than the width of the gap.

10. The semiconductor module according to claim 1, characterized in that, For at least a portion of the recesses, the width in the lateral direction parallel to the lower surface of the chip connector is greater than the width in the height direction perpendicular to the lateral direction.

11. The semiconductor module according to claim 1, characterized in that, The density of the recesses in the lateral direction, which is parallel to the lower surface of the chip connection portion, is higher than the density of the recesses in the height direction, which is perpendicular to the lateral direction.

12. The semiconductor module according to claim 1, characterized in that, The density of the recesses in the height direction perpendicular to the lower surface of the chip connector is higher the further away from the lower surface of the chip connector.

13. The semiconductor module according to claim 1, characterized in that, The chip connection portion has: Main materials department; and The obstruction portion is formed of a material with lower solder wettability than that of the main material portion, and is disposed exposed on the front end face.

14. The semiconductor module according to claim 13, characterized in that, On the front end face, the width of the obstruction portion in the height direction perpendicular to the lower surface of the chip connection portion is greater than the width of the main material portion in the height direction.

15. The semiconductor module according to claim 13, characterized in that, The obstruction portion is deposited on the main material portion in a height direction perpendicular to the lower surface of the chip connection portion.

16. The semiconductor module according to claim 13, characterized in that, The obstruction portion is deposited on the main material portion in a direction perpendicular to the front end face of the chip connection portion.

17. The semiconductor module according to claim 13, characterized in that, The obstruction portion is more prominent or more recessed than the main material portion in a direction perpendicular to the front end face of the chip connection portion.

18. The semiconductor module according to claim 1, characterized in that, The chip connector has the plurality of recesses and the planar portion formed on its front end face, side face and top surface.

19. The semiconductor module according to claim 1, characterized in that, The surface is provided with: The overlapping portion is formed by the overlapping of adjacent recesses among the plurality of recesses; and The non-overlapping portion has a planar portion provided between adjacent recesses in the plurality of recesses. The overlapping portion is located on the inner side of the surface compared to the non-overlapping portion.

20. The semiconductor module according to claim 1, characterized in that, The plurality of recesses and the planar portion are formed on the upper surface of the chip connection portion. The upper surface has a first end edge and a second end edge opposite to the first end edge. The maximum distance among the recesses sandwiched between the first end edge and the second end edge in the plurality of recesses is greater than the first shortest distance between the recess formed on the upper surface of the chip connection portion and the first end edge, and is also greater than the second shortest distance between the recess formed on the upper surface of the chip connection portion and the second end edge.

21. The semiconductor module according to claim 20, characterized in that, The spacing between the recesses at the center between the first end edge and the second end edge of the upper surface of the chip connection portion in the plurality of recesses is greater than the first shortest distance and greater than the second shortest distance.

22. The semiconductor module according to claim 20, characterized in that, The interval between the recesses at the center between the first end edge and the second end edge of the upper surface of the chip connection portion in the plurality of recesses is called the maximum distance.

23. The semiconductor module according to claim 20, characterized in that, The upper surface also has a third end edge that contacts the first end edge and the second end edge. The shortest distance between the recess formed on the upper surface of the chip connection portion and the third end edge is greater than the first shortest distance and greater than the second shortest distance.

24. The semiconductor module according to claim 23, characterized in that, The plurality of recesses and the planar portion are formed on the front end face of the chip connection portion. The upper surface of the chip connection portion and the front end surface of the chip connection portion are connected at the third end edge. The shortest distance between the recess formed on the upper surface of the chip connector and the third end edge is greater than the shortest distance between the recess formed on the front end surface of the chip connector and the third end edge.

25. A semiconductor module, characterized in that, have: An insulating circuit board having a circuit pattern formed on one side; Semiconductor chip, which is mounted on the insulating circuit board; and The wiring section electrically connects the semiconductor chip and the circuit pattern. The wiring section has a chip connection section that connects to the semiconductor chip. The surface of the chip connection portion has: Multiple recesses; and The planar portion is positioned between two recesses. The wiring section is a lead frame with a plate-like portion. The planar portion has: Standards Department; as well as The raised portion has the same height in the height direction perpendicular to the surface of the chip connection portion as the standard portion in the same height direction, or the raised portion is raised relative to the standard portion in the height direction. At least a portion of the plurality of recesses are configured to be recessed relative to the standard portion in the height direction. The raised portion is disposed adjacent to the recessed portion.

26. The semiconductor module according to claim 25, characterized in that, The surface having the plurality of recesses has a rough surface area with an unfolded area ratio of 0.1 or more.

27. The semiconductor module according to claim 25, characterized in that, The depth of each of the plurality of recesses is more than 20 μm and less than 200 μm.

28. The semiconductor module according to claim 26, characterized in that, The plurality of recesses and the planar portion are formed on the upper surface of the chip connection portion.

29. The semiconductor module according to claim 28, characterized in that, The plurality of recesses and the planar portion are formed on the front end face of the chip connection portion. At least one of the plurality of recesses formed on the upper surface is deeper than at least one recess formed on the front end face.

30. The semiconductor module according to claim 25, characterized in that, The plurality of recesses include mold holes.

31. The semiconductor module according to claim 30, characterized in that, The plurality of recesses include laser holes.

32. The semiconductor module according to claim 25, characterized in that, The plurality of recesses and the planar portion are formed on the upper surface of the chip connection portion. Each of the plurality of recesses has a polygonal shape on its upper surface.

33. The semiconductor module according to claim 32, characterized in that, The plurality of recesses and the planar portion are formed on the front end face of the chip connection portion. Each of the plurality of recesses has a curved shape on its front end face.

34. The semiconductor module according to claim 25, characterized in that, At least a portion of the recesses are more compressed than the planar portion.

35. The semiconductor module according to claim 25, characterized in that, The plurality of recesses and the planar portion are formed on the upper surface and the front end surface of the chip connection portion. At least one of the plurality of recesses formed on the upper surface has its bottom positioned on the opposite side of the front end face of the chip connector, further from the center of the recess.

36. The semiconductor module according to claim 35, characterized in that, The depth of the recess formed on the upper surface among the plurality of recesses becomes shallower as it moves away from the front end face.

37. The semiconductor module according to claim 28, characterized in that, The shortest distance between the plurality of recesses and at least one end edge of the surface is greater than the interval between adjacent recesses among the plurality of recesses.

38. The semiconductor module according to claim 37, characterized in that, The plurality of recesses and the planar portion are formed on the front end face of the chip connection portion. The upper surface of the chip connection portion and the front end surface of the chip connection portion are connected at the end edge. The shortest distance between the recess formed on the upper surface of the chip connector and the end edge is greater than the shortest distance between the recess formed on the front end surface of the chip connector and the end edge.

39. The semiconductor module according to claim 37, characterized in that, The plurality of recesses and the planar portion are formed on the side of the chip connection portion. The upper surface and the side surface of the chip connection portion are connected at the end edge. The shortest distance between the recess formed on the upper surface of the chip connector and the end edge is greater than the shortest distance between the recess formed on the side surface of the chip connector and the end edge.

40. A semiconductor module, characterized in that, have: An insulating circuit board having a circuit pattern formed on one side; Semiconductor chip, which is mounted on the insulating circuit board; The wiring section has at least a rough surface area with an unfolded area ratio of 0.2 or more on its surface, and connects the semiconductor chip to the circuit pattern. as well as The semiconductor chip is encapsulated in resin to protect it. The wiring section has a chip connection section that connects to the semiconductor chip. The surface of the chip connection portion has: Multiple recesses; and The planar portion is positioned between two recesses. At least the plurality of recesses and the planar portion are formed on the front end surface of the chip connection portion. The plurality of recesses are periodically arranged in at least two directions on the front end face.

41. The semiconductor module according to claim 40, characterized in that, The unfolded area ratio of the rough surface region is greater than the unfolded area ratio of the circuit pattern.

42. The semiconductor module according to claim 41, characterized in that, The unfolded area ratio of the circuit pattern is less than 0.

08.

43. The semiconductor module according to claim 40, characterized in that, The arithmetic mean height of the rough surface region is less than 10 μm.

44. The semiconductor module according to claim 40, characterized in that, The maximum height of the rough surface region is less than 100 μm.

45. The semiconductor module according to claim 40, characterized in that, The wiring section is a lead frame with a plate-like portion. The wiring section has: A chip connection portion, which is connected to the semiconductor chip; Circuit pattern connection portion, which is connected to the circuit pattern; and The bridging section connects the chip connection section and the circuit pattern connection section. The rough surface area is located on the chip connection portion.

46. ​​The semiconductor module according to claim 45, characterized in that, The area of ​​the chip connection portion is larger than the area of ​​the circuit pattern connection portion.

47. The semiconductor module according to claim 45, characterized in that, The unfolded area ratio of the circuit pattern connection portion is less than the unfolded area ratio of the rough surface region of the chip connection portion.

48. The semiconductor module according to claim 45, characterized in that, The bridging portion has an opening.

49. The semiconductor module according to claim 45, characterized in that, The lower surface of the chip connection portion or the lower surface of the circuit pattern connection portion has a protrusion that protrudes toward the insulating circuit substrate.

50. The semiconductor module according to claim 45, characterized in that, The semiconductor module also includes a coating that covers at least a portion of the surface of the lead frame and is formed of resin.

51. The semiconductor module according to claim 50, characterized in that, The chip connection portion has a front end surface that is furthest from the bridging portion. The coating is provided on the front end face.

52. The semiconductor module according to claim 50, characterized in that, The coating thickness is greater than 1 μm and less than 100 μm.

53. The semiconductor module according to claim 50, characterized in that, The surface of the coating has irregularities corresponding to the irregularities of the rough surface region.

54. The semiconductor module according to claim 50, characterized in that, The surface of the coating is flatter than the rough surface area.

55. The semiconductor module according to claim 40, characterized in that, The resin encapsulation includes a resin housing surrounding the insulating circuit board and a sealing resin filling the resin housing.

56. The semiconductor module according to claim 45, characterized in that, The chip connection portion has a lower surface opposite to the semiconductor chip. The lower surface of the chip connector has a first side that is furthest from the bridging portion. On the lower surface of the chip connection portion, a step or inclined portion is provided along the first side for more than half of the length of the first side.

57. A manufacturing method, characterized in that, A method for manufacturing a semiconductor module according to any one of claims 1 to 56, the semiconductor module comprising: an insulating circuit substrate having a circuit pattern formed on one side; a semiconductor chip disposed on the insulating circuit substrate; and a wiring portion electrically connecting the semiconductor chip and the circuit pattern, the wiring portion having a chip connection portion connected to the semiconductor chip. In the semiconductor module manufacturing method, a laser is irradiated onto the surface of the chip connection portion to form a plurality of recesses and a planar portion disposed between two recesses.

58. The manufacturing method according to claim 57, characterized in that, Using a common light source, laser light is irradiated onto at least two surfaces of the chip connection portion without moving the wiring portion, forming a plurality of recesses on each surface and a planar portion disposed between two recesses.

59. The manufacturing method according to claim 58, characterized in that, Laser light is irradiated at an angle onto each surface of the chip connection portion.

60. The manufacturing method according to claim 58, characterized in that, Laser is applied to each surface of the chip connection portion without changing the focal position.

61. The manufacturing method according to claim 58, characterized in that, Laser is applied to each surface of the chip connection portion by changing the irradiation angle without changing the configuration of the laser source.

62. The manufacturing method according to claim 57, characterized in that, The shape is transferred onto the upper surface of the chip connector using a mold, forming multiple recesses and a planar portion disposed between two recesses. After the shape is transferred using the mold, a laser is irradiated onto at least the front end face of the chip connection portion to form a plurality of recesses and a planar portion disposed between two recesses.

63. The manufacturing method according to claim 62, characterized in that, A laser is irradiated onto the upper surface of the chip connection portion to form multiple recesses and a planar portion disposed between two recesses.

64. The manufacturing method according to claim 63, characterized in that, The laser is irradiated in a manner that overlaps with at least a portion of the recesses formed by transferring the shape using the mold.

65. A manufacturing method, characterized in that, A method for manufacturing a semiconductor module according to any one of claims 1 to 56, the semiconductor module comprising: an insulating circuit substrate having a circuit pattern formed on one side; a semiconductor chip disposed on the insulating circuit substrate; and a wiring portion electrically connecting the semiconductor chip and the circuit pattern, the wiring portion having a chip connection portion connected to the semiconductor chip. In the semiconductor module manufacturing method, a mold is used to transfer a shape onto the upper surface of the chip connector to form a plurality of recesses and a planar portion disposed between two recesses.

66. The manufacturing method according to claim 65, characterized in that, The mold has a square pyramid shape.

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