Differential amplifier circuit, receiving circuit, and semiconductor integrated circuit

Abstract

The differential amplifier circuit section comprises: a first transistor (205, 206) arranged between a current source circuit and a load circuit, receiving a differential input signal at a gate and generating a differential output signal at a drain; and a third transistor (433) connected between the sources of the first and second transistors and receiving a control signal at a gate. The replica amplifier circuit section comprises: a voltage generating circuit generating a first reference voltage and a second reference voltage; a first replica transistor (416, 417) which is a replica of the first and second transistors, receiving the first and second reference voltages at a gate and generating a replica output signal at a drain; a third replica transistor (415) connected between the sources of the first and second replica transistors and receiving a control signal at a gate; and an operational amplifier (422) generating a control signal according to a difference between at least one of the first and second reference voltages and the replica output signal.

Description

Technical Field

[0001] The present invention relates to a differential amplifier circuit, a receiving circuit and a semiconductor integrated circuit. Background Art

[0002] Patent document 1 discloses a high-speed differential amplifier having a differential amplifier and a control signal generator. The differential amplifier amplifies the voltage difference between a first input signal and a second input signal to generate an output signal. The control signal generator includes a replica differential amplifier that is a replica of the differential amplifier and generates a control signal that controls the gain of the differential amplifier and the replica differential amplifier.

[0003] Patent document 2 discloses a gain amplifier having a first transistor, a second transistor, a resistor, and a third transistor. The first transistor has a first control port, a first input port, and a first output port. The second transistor has a second control port, a second input port, and a second output port. The resistor has a first end connected to the first output port, and a second end connected to the second output port. The third transistor is connected to the first output port and the second output port, and is connected in parallel with the resistor. When a control voltage is applied to the third transistor and an input voltage is applied to the first control port, the second control port is selectively modified by the control voltage at the first input port and the second input port to generate a desired output.

[0004] Patent document 3 discloses a variable gain amplifier circuit having a first amplifier circuit, a second amplifier circuit, a third amplifier circuit, and a current mirror circuit. The first amplifier circuit has: a first transistor and a second transistor to which a differential input voltage is input at a control terminal, a third transistor connected between the first transistor and the second transistor and to which a gain control signal is input at a control terminal, and an output unit that outputs a differential current of a first output current and a second output current corresponding to a current flowing through the first transistor and a current flowing through the second transistor, respectively. The second amplifier circuit has: a fourth transistor and a fifth transistor to which a first voltage and a second voltage are input at a control terminal, respectively, a sixth transistor connected between the fourth transistor and the fifth transistor and to which the gain control signal is input at a control terminal, and an output unit that outputs a differential current of a first current corresponding to a current flowing through the fourth transistor and a current flowing through the fifth transistor, respectively, and a second current smaller than the first current, respectively. The third amplifier circuit has: a seventh transistor and an eighth transistor to which a third voltage and a fourth voltage are input at a control terminal, respectively, a resistor element connected between the seventh transistor and the eighth transistor, and an output unit that outputs a differential current of a third current corresponding to a current flowing through the seventh transistor and a current flowing through the eighth transistor, respectively, and a fourth current smaller than the third current, respectively. The current mirror circuit generates the gain control signal according to a composite current of the first current and the fourth current and a composite current of the second current and the third current.

[0005] Patent Document 1: U.S. Patent Application Publication No. 2011 / 0001562

[0006] Patent Document 2: Japanese Patent Application No. 2018-522490

[0007] Patent Document 3: Japanese Patent Application Publication No. 2002-198755

[0008] The gain of a differential amplifier circuit varies with temperature. When the gain of a differential amplifier circuit is controlled to be constant using parameters, the number of parameters increases, the control becomes complicated, and the response speed decreases. Summary of the invention

[0009] An object of the present invention is to make the gain of a differential amplifier circuit portion constant while maintaining high-speed operation by using simple control in a differential amplifier circuit.

[0010] The differential amplifier circuit includes a differential amplifier circuit section and a replica amplifier circuit section. The differential amplifier circuit section includes: a first transistor and a second transistor, which are provided between a current source circuit and a load circuit, receive differential input signals at gates, and generate differential output signals at drains; and a third transistor, which is connected between sources of the first transistor and the second transistor, and receives a control signal at a gate. The replica amplifier circuit section includes: a voltage generating circuit, which generates a first reference voltage and a second reference voltage; a first replica transistor and a second replica transistor, which are replicas of the first transistor and the second transistor, receive the first reference voltage and the second reference voltage at gates, and generate replica output signals at drains; a third replica transistor, which is connected between sources of the first replica transistor and the second replica transistor, and receives the control signal at a gate; and an operational amplifier, which generates the control signal according to a difference between at least one of the first reference voltage and the second reference voltage and the replica output signal. The operational amplifier generates the control signal so that the gain of the replica amplifier circuit section is constant.

[0011] In the differential amplifier circuit, the gain of the differential amplifier circuit portion can be made constant while maintaining high-speed operation by using simple control. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a diagram showing a configuration example of a semiconductor integrated circuit according to the first embodiment.

[0013] Figure 2 Yes means Figure 1 A circuit diagram showing an example of the configuration of a differential amplifier circuit section within a CTLE.

[0014] Figure 3 Yes means Figure 2 A diagram showing the gain characteristics of a differential amplifier circuit portion with respect to frequency.

[0015] Figure 4 This is a circuit diagram showing a configuration example of a differential amplifier circuit according to the first embodiment.

[0016] Figure 5 : is a circuit diagram showing a configuration example of a differential amplifier circuit according to the second embodiment.

[0017] Figure 6 It is a circuit diagram showing a configuration example of a differential amplifier circuit according to the third embodiment. DETAILED DESCRIPTION

[0018] (First Embodiment)

[0019] Figure 11 is a diagram showing a configuration example of a semiconductor integrated circuit 100 according to the first embodiment. The semiconductor integrated circuit 100 includes a receiving circuit 101 and an internal circuit 102. The receiving circuit 101 includes a termination circuit 113, a continuous time linear equalizer (CTLE) 114, a decision feedback equalizer (DFE) 115, a clock generator 116, and a demultiplexer 117.

[0020] The differential input terminals 111 and 112 receive differential signals. The terminal circuit 113 is connected between the differential input terminals 111 and 112. The terminal circuit 113 is composed of, for example, a resistor element. The CTLE 114 continuously performs equalization processing on the differential signals received by the differential input terminals 111 and 112 on the time axis. The DFE 115 inputs the output signal of the CTLE 114, and performs equalization processing and binary determination based on a feedback loop on the output signal of the CTLE 114. The clock generator 116 outputs a clock signal to the DFE 115. The demultiplexer 117 inputs the output signal of the DFE 115, and converts the output signal of the DFE 115 from serial data to parallel data. The internal circuit 102 processes the output signal of the demultiplexer 117.

[0021] Figure 2 Yes means Figure 1 FIG. 1 is a circuit diagram of a configuration example of a differential amplifier circuit section in a CTLE 114. The differential amplifier circuit section includes current sources 201 and 202, a variable capacitor 203, a resistor 204, p-channel field effect transistors 205 and 206, inductors 207 and 208, and resistors 209 and 210. The differential amplifier circuit section amplifies a differential signal input to differential input terminals Vip and Vin, and outputs the amplified differential signal from differential output terminals Vop and Von.

[0022] Figure 3 Yes means Figure 2 Graph showing the gain characteristics of the differential amplifier circuit unit with respect to frequency. The differential amplifier circuit unit is a high-frequency equalizer, and the gain in the high-frequency band is high. Gain characteristic 301 is the characteristic at -40°C. Gain characteristic 302 is the characteristic at 25°C. Gain characteristic 303 is the characteristic at 125°C. The gain of the differential amplifier circuit unit varies with temperature. If the gain of the differential amplifier circuit unit varies with temperature, it becomes a cause of reception errors in the receiving circuit 101. It is preferred that the gain of the differential amplifier circuit unit is constant regardless of the temperature.

[0023] The differential amplifier circuit section can control the gain of the high frequency band by controlling the value of the variable capacitor 203. In addition, the differential amplifier circuit section can control the DC gain by controlling the value of the resistor 204. When the resistance value of the resistor 204 is made variable and the value of the resistor 204 is controlled so that the DC gain of the differential amplifier circuit section is constant, there is a problem that the number of parameters for variably setting the resistance value increases, the control becomes complicated, and the response speed decreases. Figure 4 A differential amplifier circuit is described which can make the DC gain of the differential amplifier circuit portion constant at high speed by simple control.

[0024] Figure 4 : is a circuit diagram showing a configuration example of the differential amplifier circuit 400 according to the first embodiment. Figure 1 The CTLE 114 includes a differential amplifier circuit 400 . The differential amplifier circuit 400 includes a differential amplifier circuit section 401 , a replica amplifier circuit section 402 , a p-channel field effect transistor 403 , an n-channel field effect transistor 404 , and a BGR (bandgap reference) bias generator 405 .

[0025] The differential amplifier circuit section 401 is a Figure 2 The differential amplifier circuit section is provided with p-channel field effect transistors 431 and 432 corresponding to the current sources 201 and 202, and a p-channel field effect transistor 433 corresponding to the resistor 204. The differential amplifier circuit section 401 includes p-channel field effect transistors 431 to 433, a variable capacitor 203, p-channel field effect transistors 205 and 206, inductors 207 and 208, and resistors 209 and 210.

[0026] The p-channel field effect transistor 431 is a current source circuit, and its source is connected to the power supply potential node. The p-channel field effect transistor 432 is a current source circuit, and its source is connected to the power supply potential node, and its gate is connected to the gate of the p-channel field effect transistor 431.

[0027] The variable capacitor 203 is connected between the drain of the p-channel field effect transistor 431 and the drain of the p-channel field effect transistor 432. The source of the p-channel field effect transistor 433 is connected to the source of the p-channel field effect transistor 205, the gate is connected to the output terminal of the operational amplifier 422, and the drain is connected to the source of the p-channel field effect transistor 206. The p-channel field effect transistor 433 receives a control signal output by the operational amplifier 422 at the gate, and changes the resistance between the drain and the source according to the control signal.

[0028] The source of the p-channel field effect transistor 205 is connected to the drain of the p-channel field effect transistor 431, the gate is connected to the differential input terminal Vip, and the drain is connected to the differential output terminal Von. The source of the p-channel field effect transistor 206 is connected to the drain of the p-channel field effect transistor 432, the gate is connected to the differential input terminal Vin, and the drain is connected to the differential output terminal Vop.

[0029] The series connection circuit of the inductor 207 and the resistor 209 is a load circuit, and is connected between the drain of the p-channel field effect transistor 205 and the reference potential node. The reference potential node is, for example, a ground potential node, which is a node with a lower potential than the power supply potential node. The series connection circuit of the inductor 208 and the resistor 210 is a load circuit, and is connected between the drain of the p-channel field effect transistor 206 and the reference potential node.

[0030] The p-channel field effect transistors 205 and 206 receive differential input signals at differential input terminals Vip and Vin of the gates and generate differential output signals at output terminals Vop and Von of the drains. The operational amplifier 422 controls the control signal of the gate of the p-channel field effect transistor 433, thereby controlling the resistance between the drain and source of the p-channel field effect transistor 433, and controlling the DC gain of the differential amplifier circuit section 401 to be constant.

[0031] The replica amplifier circuit section 402 is a replica of the differential amplifier circuit section 401. The replica amplifier circuit section 402 includes p-channel field effect transistors 411 to 417, resistors 418 to 421, and an operational amplifier 422.

[0032] The p-channel field effect transistor 412 is a replica transistor of the p-channel field effect transistor 431, and has a source connected to the power supply potential node, and a gate connected to the gates of the p-channel field effect transistors 431 and 432. The p-channel field effect transistor 413 is a replica transistor of the p-channel field effect transistor 432, and has a source connected to the power supply potential node, and a gate connected to the gates of the p-channel field effect transistors 431 and 432.

[0033] The p-channel field effect transistor 415 is a replica transistor of the p-channel field effect transistor 433 , has a source connected to the source of the p-channel field effect transistor 416 , a gate connected to the output terminal of the operational amplifier 422 , and a drain connected to the source of the p-channel field effect transistor 417 .

[0034] P-channel field effect transistor 416 is a replica transistor of p-channel field effect transistor 205, and its source is connected to the drain of p-channel field effect transistor 412. P-channel field effect transistor 417 is a replica transistor of p-channel field effect transistor 206, and its source is connected to the drain of p-channel field effect transistor 413.

[0035] The resistor 419 is a load circuit and is a replica of the resistor 209. The resistor 419 is connected between the drain of the p-channel field effect transistor 416 and the reference potential node.

[0036] The resistor 420 is a load circuit and is a replica of the resistor 210. The resistor 420 is connected between the drain of the p-channel field effect transistor 417 and the reference potential node.

[0037] The p-channel field effect transistor 411 and the resistor 418 are a voltage generating circuit, and generate a reference voltage V1. The gate of the p-channel field effect transistor 416 receives the reference voltage V1. The source of the p-channel field effect transistor 411 is connected to the power supply potential node, the gate is connected to the gates of the p-channel field effect transistors 431 and 432, and the drain is connected to the gate of the p-channel field effect transistor 416. The resistor 418 is connected between the drain of the p-channel field effect transistor 411 and the reference potential node.

[0038] The p-channel field effect transistor 414 and the resistor 421 form a voltage generating circuit, and generate a reference voltage V2. The gate of the p-channel field effect transistor 417 receives the reference voltage V2. The source of the p-channel field effect transistor 414 is connected to the power supply potential node, the gate is connected to the gates of the p-channel field effect transistors 431 and 432, and the drain is connected to the gate of the p-channel field effect transistor 417. The resistor 421 is connected between the drain of the p-channel field effect transistor 414 and the reference potential node.

[0039] The operational amplifier 422 has a −input terminal connected to the gate of the p-channel field effect transistor 416 , a +input terminal connected to the drain of the p-channel field effect transistor 417 , and an output terminal connected to the gates of the p-channel field effect transistors 415 and 433 .

[0040] The source of the p-channel field effect transistor 403 is connected to the power supply potential node, and the gate and drain are connected to each other. The drain of the p-channel field effect transistor 404 is connected to the drain of the p-channel field effect transistor 403, the gate is connected to the BGR bias generator 405, and the source is connected to the reference potential node. In addition, the gate of the p-channel field effect transistor 403 is connected to the gates of the p-channel field effect transistors 431 and 432.

[0041] The BGR bias generator 405 generates a BGR (Band Gap Reference) voltage, and supplies the generated BGR voltage as a bias voltage (second bias voltage) to the gate of the p-channel field effect transistor 404. As a result, a bias voltage (first bias voltage) for the current source circuit is generated at the gate of the p-channel field effect transistor 403, and the generated bias voltage is supplied to each gate of the p-channel field effect transistors 411 to 414, 431, and 432.

[0042] The p-channel field effect transistors 403, 411 to 414, 431, and 432 are current mirror circuits. The current Ib flows through the p-channel field effect transistors 412, 413, 431, and 432. In the p-channel field effect transistor 411, for example, by adjusting the transistor size, a current Ib×3 / 2, which is 3 / 2 times the current Ib, flows through. In the p-channel field effect transistor 414, for example, by adjusting the transistor size, a current Ib×1 / 2, which is 1 / 2 times the current Ib, flows through.

[0043] A reference voltage V1 is input to the gate of the p-channel field effect transistor 416. A reference voltage V2 is input to the gate of the p-channel field effect transistor 417. The reference voltages V1 and V2 are different voltages from each other. The reference voltage V1 is higher than the reference voltage V2.

[0044] The p-channel field effect transistors 416 and 417 receive the reference voltages V1 and V2 at the gates and generate replica output signals V3 and V4 at the drains. The replica output signal V3 is a signal at the drain of the p-channel field effect transistor 417. The replica output signal V4 is a signal at the drain of the p-channel field effect transistor 416. The replica amplifier circuit section 402 amplifies the differential input signal of the reference voltages V1 and V2 and outputs the differential output signal of the replica output signals V3 and V4. Since the replica amplifier circuit section 402 does not have replicas of the variable capacitor 203 and the inductors 207 and 208, the gain is substantially constant with respect to the frequency.

[0045] The operational amplifier 422 supplies a control signal to the gates of the p-channel field effect transistors 415 and 433 according to the difference between the replica output signal V3 and the reference voltage V1. The operational amplifier 422 generates a control signal so that the gain of the replica amplifier circuit section 402 is constant.

[0046] In addition, the operational amplifier 422 may also output a control signal according to the difference between the replica output signal V4 and the reference voltage V2.

[0047] The gain of the amplifier circuit section 401 and the replica amplifier circuit section 402 varies according to the temperature. For example, the gain of the amplifier circuit section 401 and the replica amplifier circuit section 402 increases, and the signal of the differential output terminal Vop and the replica output signal V3 increase. In this way, the difference between the replica output signal V3 and the reference voltage V1 increases, and the control signal output by the operational amplifier 422 increases. In this way, the resistance between the drain and the source of the p-channel field effect transistor 415 increases, and the gain of the replica amplifier circuit section 402 decreases. As a result, the replica output signal V3 decreases. Through the above control, the operational amplifier 422 generates a control signal so that the gain of the replica amplifier circuit section 402 is constant.

[0048] Similarly, the resistance between the drain and source of the p-channel field effect transistor 433 increases, and the gain of the differential amplifier circuit section 401 decreases. As a result, the signal of the differential output terminal Vop decreases. The DC gain of the amplifier circuit section 401 is controlled to be constant regardless of the temperature.

[0049] The differential amplifier circuit 400 can make the DC gain of the differential amplifier circuit section 401 constant by simple control by using the replica amplifier circuit section 402. In addition, since the differential amplifier circuit section 401 controls the DC gain using the p-channel field effect transistor 433, no additional element is connected to the pair of input nodes Vip and Vin, and the input load does not increase, so that the high-speed operation of the differential amplifier circuit 400 can be maintained.

[0050] (Second Embodiment)

[0051] Figure 5 : is a circuit diagram showing a configuration example of a differential amplifier circuit 500 according to the second embodiment. Figure 1 The CTLE 114 has a differential amplifier circuit 500. The differential amplifier circuit 500 is relative to Figure 4 The differential amplifier circuit 400 is a circuit in which an n-channel field effect transistor is provided instead of a p-channel field effect transistor, and a p-channel field effect transistor is provided instead of an n-channel field effect transistor.

[0052] The differential amplifier circuit 500 includes a differential amplifier circuit portion 501 , a replica amplifier circuit portion 502 , an n-channel field effect transistor 503 , a p-channel field effect transistor 504 , and a BGR bias generator 405 .

[0053] The differential amplifier circuit section 501 includes n-channel field effect transistors 531 to 533 , the variable capacitor 203 , n-channel field effect transistors 534 and 535 , inductors 207 and 208 , and resistors 209 and 210 .

[0054] The n-channel field effect transistor 531 is a current source circuit, and its source is connected to the reference potential node. The n-channel field effect transistor 532 is a current source circuit, and its source is connected to the reference potential node, and its gate is connected to the gate of the n-channel field effect transistor 531 .

[0055] The variable capacitor 203 is connected between the drain of the n-channel field effect transistor 531 and the drain of the n-channel field effect transistor 532. The source of the n-channel field effect transistor 533 is connected to the source of the n-channel field effect transistor 535, the gate is connected to the output terminal of the operational amplifier 422, and the drain is connected to the source of the n-channel field effect transistor 534. The n-channel field effect transistor 533 receives a control signal output by the operational amplifier 422 at the gate, and changes the resistance between the drain and the source according to the control signal.

[0056] The source of the n-channel field effect transistor 534 is connected to the drain of the n-channel field effect transistor 531, the gate is connected to the differential input terminal Vip, and the drain is connected to the differential output terminal Von. The source of the n-channel field effect transistor 535 is connected to the drain of the n-channel field effect transistor 532, the gate is connected to the differential input terminal Vin, and the drain is connected to the differential output terminal Vop.

[0057] The series connection circuit of the inductor 207 and the resistor 209 is a load circuit connected between the drain of the n-channel field effect transistor 534 and the power supply potential node. The series connection circuit of the inductor 208 and the resistor 210 is a load circuit connected between the drain of the n-channel field effect transistor 535 and the power supply potential node.

[0058] The n-channel field effect transistors 534 and 535 receive differential input signals at differential input terminals Vip and Vin of the gates and generate differential output signals at output terminals Vop and Von of the drains. The operational amplifier 422 controls the control signal of the gate of the n-channel field effect transistor 533, thereby controlling the resistance between the drain and source of the n-channel field effect transistor 533, and controlling the DC gain of the differential amplifier circuit section 501 to be constant.

[0059] The replica amplifier circuit section 502 is a replica of the differential amplifier circuit section 501. The replica amplifier circuit section 502 includes n-channel field effect transistors 511 to 517, resistors 418 to 421, and an operational amplifier 422.

[0060] The n-channel field effect transistor 512 is a replica transistor of the n-channel field effect transistor 531, and has a source connected to the reference potential node, and a gate connected to the gates of the n-channel field effect transistors 531 and 532. The n-channel field effect transistor 513 is a replica transistor of the n-channel field effect transistor 532, and has a source connected to the reference potential node, and a gate connected to the gates of the n-channel field effect transistors 531 and 532.

[0061] The n-channel field effect transistor 515 is a replica transistor of the n-channel field effect transistor 533 , has a source connected to the source of the n-channel field effect transistor 517 , a gate connected to the output terminal of the operational amplifier 422 , and a drain connected to the source of the n-channel field effect transistor 516 .

[0062] N-channel field effect transistor 516 is a replica transistor of n-channel field effect transistor 534, and its source is connected to the drain of n-channel field effect transistor 512. N-channel field effect transistor 517 is a replica transistor of n-channel field effect transistor 535, and its source is connected to the drain of n-channel field effect transistor 513.

[0063] The resistor 419 is a load circuit and is a replica of the resistor 209. The resistor 419 is connected between the drain of the n-channel field effect transistor 516 and the power supply potential node.

[0064] The resistor 420 is a load circuit and is a replica of the resistor 210. The resistor 420 is connected between the drain of the n-channel field effect transistor 517 and the power supply potential node.

[0065] The n-channel field effect transistor 511 and the resistor 418 constitute a voltage generating circuit, and generate a reference voltage V1. The gate of the n-channel field effect transistor 516 receives the reference voltage V1. The source of the n-channel field effect transistor 511 is connected to the reference potential node, the gate is connected to the gates of the n-channel field effect transistors 531 and 532, and the drain is connected to the gate of the n-channel field effect transistor 516. The resistor 418 is connected between the drain of the n-channel field effect transistor 511 and the power supply potential node.

[0066] The n-channel field effect transistor 514 and the resistor 421 form a voltage generating circuit, and generate a reference voltage V2. The gate of the n-channel field effect transistor 517 receives the reference voltage V2. The source of the n-channel field effect transistor 514 is connected to the reference potential node, the gate is connected to the gates of the n-channel field effect transistors 531 and 532, and the drain is connected to the gate of the n-channel field effect transistor 517. The resistor 421 is connected between the drain of the n-channel field effect transistor 514 and the power supply potential node.

[0067] The operational amplifier 422 has a −input terminal connected to the gate of the n-channel field effect transistor 516 , a +input terminal connected to the drain of the n-channel field effect transistor 517 , and an output terminal connected to the gates of the n-channel field effect transistors 515 and 533 .

[0068] The source of the n-channel field effect transistor 503 is connected to the reference potential node, and the gate and drain are connected to the gate of the n-channel field effect transistor 514. The drain of the p-channel field effect transistor 504 is connected to the drain of the n-channel field effect transistor 503, the gate is connected to the BGR bias generator 405, and the source is connected to the power supply potential node.

[0069] The BGR bias generator 405 generates a BGR voltage and supplies the generated BGR voltage as a bias voltage (third bias voltage) to the gate of the n-channel field effect transistor 504. Thus, a bias voltage (first bias voltage) for the current source circuit is generated at the gate of the n-channel field effect transistor 503, and the generated bias voltage is supplied to each gate of the n-channel field effect transistors 511 to 514, 531, and 532.

[0070] The n-channel field effect transistors 503, 511 to 514, 531, and 532 form a current mirror circuit. A current Ib flows through the n-channel field effect transistors 512, 513, 531, and 532. A current Ib×3 / 2 flows through the n-channel field effect transistor 511. A current Ib×1 / 2 flows through the n-channel field effect transistor 514.

[0071] A reference voltage V1 is input to the gate of the n-channel field effect transistor 516. A reference voltage V2 is input to the gate of the n-channel field effect transistor 517. The reference voltages V1 and V2 are different voltages from each other. The reference voltage V1 is lower than the reference voltage V2.

[0072] The n-channel field effect transistors 516 and 517 receive the reference voltages V1 and V2 at the gates and generate replica output signals V3 and V4 at the drains. The replica output signal V3 is a signal at the drain of the n-channel field effect transistor 517. The replica output signal V4 is a signal at the drain of the n-channel field effect transistor 516. The replica amplifier circuit section 502 amplifies the differential input signal of the reference voltages V1 and V2 and outputs the differential output signal of the replica output signals V3 and V4. Since the replica amplifier circuit section 502 does not have replicas of the variable capacitor 203 and the inductors 207 and 208, the gain is substantially constant with respect to the frequency.

[0073] The operational amplifier 422 supplies a control signal to the gates of the n-channel field effect transistors 515 and 533 according to the difference between the replica output signal V3 and the reference voltage V1. The operational amplifier 422 generates a control signal so that the gain of the replica amplifier circuit section 502 is constant.

[0074] In addition, the operational amplifier 422 may also output a control signal according to the difference between the replica output signal V4 and the reference voltage V2.

[0075] The gain of the amplifier circuit section 501 and the replica amplifier circuit section 502 varies according to the temperature. For example, the gain of the amplifier circuit section 501 and the replica amplifier circuit section 502 decreases, and the signal of the differential output terminal Vop and the replica output signal V3 increase. In this way, the difference between the replica output signal V3 and the reference voltage V1 increases, and the control signal output by the operational amplifier 422 increases. In this way, the resistance between the drain and the source of the n-channel field effect transistor 515 decreases, and the gain of the replica amplifier circuit section 502 increases. As a result, the replica output signal V3 decreases. Through the above control, the operational amplifier 422 generates a control signal so that the gain of the replica amplifier circuit section 502 is constant.

[0076] Similarly, the resistance between the drain and source of the n-channel field effect transistor 533 decreases, and the gain of the differential amplifier circuit section 501 increases. As a result, the signal of the differential output terminal Vop decreases. The DC gain of the amplifier circuit section 501 is controlled to be constant regardless of the temperature.

[0077] The differential amplifier circuit 500 can make the DC gain of the differential amplifier circuit section 501 constant by simple control by using the replica amplifier circuit section 502. In addition, since the differential amplifier circuit section 501 controls the DC gain using the n-channel field effect transistor 533, no additional element is connected to the pair of input nodes Vip and Vin, and the input load does not increase, so that the high-speed operation of the differential amplifier circuit 500 can be maintained.

[0078] (Third Embodiment)

[0079] Figure 6 : is a circuit diagram showing a configuration example of a differential amplifier circuit 400 according to the third embodiment. Figure 6 The differential amplifier circuit 400 is relative to Figure 4 The differential amplifier circuit 400 is a circuit in which the variable capacitor 203 and the inductors 207 and 208 are deleted. The resistor 209 is a load circuit connected between the drain of the p-channel field effect transistor 205 and the reference potential node. The resistor 210 is a load circuit connected between the drain of the p-channel field effect transistor 206 and the reference potential node. The gain of the differential amplifier circuit section 401 is substantially constant with respect to the frequency.

[0080] In the third embodiment, similarly to the first embodiment, the operational amplifier 422 generates a control signal so that the gain of the differential amplifier circuit section 401 and the replica amplifier circuit section 402 is constant regardless of the temperature. The differential amplifier circuit 400 can make the gain of the differential amplifier circuit section 401 constant by simple control by using the replica amplifier circuit section 402. In addition, since the differential amplifier circuit section 401 controls the DC gain using the p-channel field effect transistor 433, no additional element is connected to the pair of input nodes Vip and Vin, and the input load does not increase, so that the high-speed operation of the differential amplifier circuit 400 can be maintained.

[0081] In addition, Figure 5 In the differential amplifier circuit 500, the variable capacitor 203 and the inductors 207 and 208 can also be deleted.

[0082] The above embodiments are only embodiments of specific examples for implementing the present invention, and the technical scope of the present invention is not limitedly interpreted by these embodiments. That is, the present invention can be implemented in various ways without departing from its technical ideas or its main features.

[0083] Industrial Applicability

[0084] In the differential amplifier circuit, the gain of the differential amplifier circuit portion can be made constant while maintaining high-speed operation by using simple control.

Claims

1. A differential amplifier circuit, wherein: have: Differential amplifier circuit section; as well as Copy the amplifier circuit section, The differential amplifier circuit section comprises: The first transistor and the second transistor are provided between the current source circuit and the load circuit, receive differential input signals at the gates, and generate differential output signals at the drains; and The third transistor is connected between the sources of the first transistor and the second transistor, and receives a control signal at the gate. The replica amplifier circuit section has: A voltage generating circuit, generating a first reference voltage and a second reference voltage; The first replica transistor and the second replica transistor are replicas of the first transistor and the second transistor, receive the first reference voltage and the second reference voltage at the gate, and generate a replica output signal at the drain; a third replica transistor connected between the sources of the first replica transistor and the second replica transistor, and receiving the control signal at the gate; as well as an operational amplifier, generating the control signal according to a difference between at least one of the first reference voltage and the second reference voltage and the replica output signal, The operational amplifier generates the control signal so that the gain of the replica amplifier circuit section is constant.

2. The differential amplifier circuit according to claim 1, wherein: The current source circuit comprises a fourth transistor and a fifth transistor. The load circuit comprises a first load circuit and a second load circuit. The source of the first transistor is connected to the drain of the fourth transistor. The drain of the first transistor is connected to the first load circuit. The source of the second transistor is connected to the drain of the fifth transistor. The drain of the second transistor is connected to the second load circuit. A gate of the fourth transistor and a gate of the fifth transistor are connected to each other and are supplied with a first bias voltage.

3. The differential amplifier circuit according to claim 2, wherein: The replica amplifier circuit section has: a fourth replica transistor, whose drain is connected to the source of the first replica transistor; a fifth replica transistor, a drain connected to the source of the second replica transistor; A third load circuit connected to the drain of the first replica transistor; as well as a fourth load circuit connected to the drain of the second replica transistor; A gate of the fourth replica transistor and a gate of the fifth replica transistor are connected to each other and are supplied with the first bias voltage.

4. The differential amplifier circuit according to claim 3, wherein: The voltage generating circuit has: a sixth transistor, a drain connected to the gate of the first replica transistor, and a gate connected to the gate of the fourth replica transistor; a first resistor connected to the gate of the first replica transistor; a seventh transistor, a drain of which is connected to the gate of the second replica transistor, and a gate of which is connected to the gate of the fifth replica transistor; and The second resistor is connected to the gate of the second replica transistor.

5. The differential amplifier circuit according to claim 4, wherein: The first bias voltage is supplied to a gate of the sixth transistor and a gate of the seventh transistor.

6. The differential amplifier circuit according to claim 4, wherein: The first to seventh transistors and the first to fifth replica transistors are p-channel field effect transistors. The sources of the fourth to seventh transistors and the sources of the fourth and fifth replica transistors are connected to a power supply potential node. The first load circuit is connected between the drain of the first transistor and a reference potential node having a potential lower than that of the power supply potential node. The second load circuit is connected between the drain of the second transistor and the reference potential node. The third load circuit is connected between the drain of the first replica transistor and the reference potential node. The fourth load circuit is connected between the drain of the second replica transistor and the reference potential node.

7. The differential amplifier circuit according to claim 6, wherein: Also features: an eighth transistor, whose source is connected to the power supply potential node, and whose gate and drain are connected to each other; a ninth transistor, having a drain connected to the drain of the eighth transistor and a source connected to the reference potential node; as well as a bias generator for supplying a second bias voltage to the gate of the ninth transistor; The first bias voltage is generated at the gate of the eighth transistor.

8. The differential amplifier circuit according to claim 4, wherein: The first to seventh transistors and the first to fifth replica transistors are n-channel field effect transistors. The sources of the fourth to seventh transistors and the sources of the fourth and fifth replica transistors are connected to a reference potential node. The first load circuit is connected between the drain of the first transistor and a power supply potential node having a potential higher than the reference potential node. The second load circuit is connected between the drain of the second transistor and the power supply potential node. The third load circuit is connected between the drain of the first replica transistor and the power supply potential node. The fourth load circuit is connected between the drain of the second replica transistor and the power supply potential node.

9. The differential amplifier circuit according to claim 8, wherein: Also features: an eighth transistor, whose source is connected to the reference potential node, and whose gate and drain are connected to each other; a ninth transistor, whose drain is connected to the drain of the eighth transistor and whose source is connected to the power supply potential node; and a bias generator for supplying a third bias voltage to the gate of the ninth transistor; The first bias voltage is generated at the gate of the eighth transistor.

10. The differential amplifier circuit according to any one of claims 1 to 9, wherein: The differential amplifier circuit section includes a capacitor connected between a drain of the first transistor and a drain of the second transistor.

11. The differential amplifier circuit according to any one of claims 3 to 9, wherein: The first load circuit is a series connection circuit of a third resistor and a first inductor. The second load circuit is a series connection circuit of a fourth resistor and a second inductor. The third load circuit is a fifth resistor. The fourth load circuit is a sixth resistor.

12. The differential amplifier circuit according to any one of claims 3 to 9, wherein: The first load circuit is a third resistor. The second load circuit is a fourth resistor. The third load circuit is a fifth resistor. The fourth load circuit is a sixth resistor.

13. The differential amplifier circuit according to any one of claims 1 to 9, wherein: The first reference voltage and the second reference voltage are different voltages from each other.

14. A receiving circuit, wherein: have: Continuous-time linear equalizer; A decision feedback equalizer, inputting the output signal of the above continuous time linear equalizer; A clock generator outputs a clock signal to the decision feedback equalizer; as well as A demultiplexer is input with the output signal of the decision feedback equalizer. The above continuous time linear equalizer has a differential amplifier circuit, The above differential amplifier circuit has: Differential amplifier circuit section; as well as Copy the amplifier circuit section, The differential amplifier circuit section comprises: The first transistor and the second transistor are provided between the current source circuit and the load circuit, receive differential input signals at the gates, and generate differential output signals at the drains; and The third transistor is connected between the sources of the first transistor and the second transistor, and receives a control signal at the gate. The replica amplifier circuit section has: A voltage generating circuit, generating a first reference voltage and a second reference voltage; The first replica transistor and the second replica transistor are replicas of the first transistor and the second transistor, receive the first reference voltage and the second reference voltage at the gate, and generate a replica output signal at the drain; a third replica transistor connected between the sources of the first replica transistor and the second replica transistor, and receiving the control signal at the gate; as well as an operational amplifier, generating the control signal according to a difference between at least one of the first reference voltage and the second reference voltage and the replica output signal, The operational amplifier generates the control signal so that the gain of the replica amplifier circuit section is constant.

15. A semiconductor integrated circuit, wherein: have: receiving circuit; and The internal circuit processes the output signal of the above receiving circuit. The receiving circuit has: Continuous-time linear equalizer; A decision feedback equalizer, inputting the output signal of the above continuous time linear equalizer; A clock generator outputs a clock signal to the decision feedback equalizer; as well as A demultiplexer is input with the output signal of the decision feedback equalizer. The above continuous time linear equalizer has a differential amplifier circuit, The above differential amplifier circuit has: Differential amplifier circuit section; as well as Copy the amplifier circuit section, The differential amplifier circuit section comprises: The first transistor and the second transistor are provided between the current source circuit and the load circuit, receive differential input signals at the gates, and generate differential output signals at the drains; and The third transistor is connected between the sources of the first transistor and the second transistor, and receives a control signal at the gate. The replica amplifier circuit section has: A voltage generating circuit, generating a first reference voltage and a second reference voltage; The first replica transistor and the second replica transistor are replicas of the first transistor and the second transistor, receive the first reference voltage and the second reference voltage at the gate, and generate a replica output signal at the drain; a third replica transistor connected between the sources of the first replica transistor and the second replica transistor, and receiving the control signal at the gate; as well as an operational amplifier, generating the control signal according to a difference between at least one of the first reference voltage and the second reference voltage and the replica output signal, The operational amplifier generates the control signal so that the gain of the replica amplifier circuit section is constant.

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