A chip port transient withstand voltage test circuit, method and test machine

Abstract

The present invention discloses a chip port transient withstand voltage test circuit, method, and tester. The circuit includes: a controllable pulse signal module for generating the pulse signal required by the chip under test and outputting it to a switch module; a controllable DC module for generating the relevant voltage required by the chip under test and outputting it to the switch module; the switch module for outputting a detection signal to the chip under test based on the pulse signal output by the controllable pulse signal module and the relevant voltage output by the controllable DC module, and the chip under test generates a breakdown current based on the detection signal; a detection module for detecting the breakdown current and converting it into a voltage pulse; a sample-and-hold amplifier module for amplifying the voltage pulse and maintaining the maximum detection voltage, and then amplifying the maximum detection voltage again and outputting an amplified signal to a digital-to-analog conversion module; and a digital-to-analog conversion module for obtaining a transient impulse voltage based on the amplified signal. The present invention implements withstand voltage testing of chip ports undergoing slow power-up and fast power-up tests.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to a chip port transient withstand voltage testing circuit, method and testing machine. Background Art

[0002] With the advancement of electronics technology, chip integration is becoming increasingly complex. The BCD process used in chip production also supports the integration of devices with varying withstand voltages on a single chip. This places higher demands on testing, such as requiring non-withstand voltage testing for different ports. Currently, many chip tests only focus on functional testing, leaving incomplete withstand voltage testing solutions.

[0003] However, during production testing, when performing withstand voltage tests on certain special IOs (with a withstand voltage of 10 to 100V and microsecond to millisecond level shocks), the pressure-current measurement solution of an ordinary tester cannot produce results. The reason is that to avoid power-on overshoot, the power-on process of the tester's built-in power voltage and current source is too slow, with a rising edge in the millisecond level. In addition, to avoid excessively fast power switching, corresponding internal delays are also implemented, resulting in the inability to perform withstand voltage tests on IOs in fast power-on mode.

[0004] Therefore, the existing technology still needs to be improved and developed. Summary of the Invention

[0005] In view of the above-mentioned deficiencies in the prior art, the object of the present invention is to provide a chip port transient withstand voltage test circuit, method and test machine to solve the problem that the existing test machine cannot perform withstand voltage test on IO in fast power-on mode.

[0006] The technical solutions of the present invention are as follows:

[0007] A chip port transient withstand voltage test circuit is used to connect to the port of the chip under test, which includes: a controllable pulse signal module, a controllable DC module, a switch module, a detection module, a sampling and holding amplifier module and a digital-to-analog conversion module; wherein,

[0008] The controllable pulse signal module is connected to the switch module, and is used to generate the pulse signal required by the chip under test and output it to the switch module;

[0009] The controllable DC module is connected to the switch module, and is used to generate the relevant voltage required to be applied to the chip under test and output it to the switch module;

[0010] The switch module is also connected to the chip under test, and is used to output a detection signal to the chip under test according to the pulse signal output by the controllable pulse signal module and the voltage correlation output by the controllable DC module, and the chip under test generates a breakdown current according to the detection signal;

[0011] The detection module is connected to the chip under test and is used to detect the breakdown current output by the chip under test and convert it into a voltage pulse;

[0012] The sampling and holding amplifier module is connected to the detection module, and is used to amplify the voltage pulse and maintain the maximum detection voltage, and amplify the maximum detection voltage again and output the amplified signal to the digital-to-analog conversion module;

[0013] The digital-to-analog conversion module is connected to the sample-hold amplification module and is used to obtain a transient impulse voltage according to the amplified signal.

[0014] According to a further configuration of the present invention, the detection module includes: a first resistor, one end of the first resistor is connected to the chip under test, and the other end of the first resistor is grounded.

[0015] According to a further configuration of the present invention, the switch module includes: a second resistor, a third resistor, a fourth resistor, a first capacitor, a first switch tube, and a second switch tube; wherein,

[0016] One end of the second resistor is connected to the controllable DC module and the second end of the first switch tube respectively, and the other end of the second resistor is connected to one end of the third resistor and the first end of the first switch tube respectively;

[0017] The other end of the third resistor is connected to the third end of the second switch tube;

[0018] The third end of the first switch tube is connected to the chip under test;

[0019] The first capacitor is connected in parallel with the second resistor;

[0020] One end of the fourth resistor is connected to the controllable pulse signal module, and the other end of the fourth resistor is connected to the first end of the second switch tube;

[0021] The third terminal of the second switch tube is grounded.

[0022] According to a further configuration of the present invention, the sampling and holding amplification module includes: a first amplification unit, a signal holding unit and a second amplification unit; wherein,

[0023] The first amplifying unit is connected to the first detection module and is used to amplify the voltage pulse;

[0024] The signal holding module is connected to the first amplifying unit and is used to sample and hold the maximum detection voltage output by the first amplifying unit;

[0025] The second amplification unit is connected to the signal holding unit, and is configured to amplify the maximum detection voltage and then output an amplified signal to the digital-to-analog conversion module.

[0026] According to a further configuration of the present invention, the first amplifying unit includes: a fifth resistor, a sixth resistor, a seventh resistor, a first diode and a first amplifier; wherein,

[0027] One end of the fifth resistor is connected to the detection module, and the other end of the fifth resistor is connected to the non-inverting input terminal of the first amplifier;

[0028] The inverting input terminal of the first amplifier is connected to one end of the sixth resistor and one end of the seventh resistor respectively, and the output terminal of the first amplifier is connected to the other end of the seventh resistor and the signal holding unit respectively;

[0029] The other end of the sixth resistor is grounded;

[0030] An anode of the first diode is connected to the other end of the fifth resistor, and a cathode of the first diode is connected to a power supply terminal of the first amplifier.

[0031] According to a further configuration of the present invention, the signal holding unit includes: a second diode and a second capacitor; wherein,

[0032] The anode of the second diode is connected to the output end of the first amplifier, and the cathode of the second diode is connected to one end of the second capacitor and the second amplifying unit respectively;

[0033] The other end of the second capacitor is grounded.

[0034] According to a further configuration of the present invention, the second amplifying unit includes: an eighth resistor, a ninth resistor, a tenth resistor and a second amplifier; wherein,

[0035] One end of the eighth resistor is connected to the cathode of the second diode, and the other end of the eighth resistor is connected to the non-inverting input terminal of the second amplifier;

[0036] The inverting input terminal of the second amplifier is connected to one end of the ninth resistor and one end of the tenth resistor respectively, and the output terminal of the second amplifier is connected to the other end of the tenth resistor and the digital-to-analog conversion module respectively;

[0037] The other end of the ninth resistor is grounded.

[0038] According to a further configuration of the present invention, the controllable pulse control module is a micro control unit; and the digital-to-analog conversion module is a digital-to-analog converter.

[0039] A method for the chip port transient withstand voltage test circuit described above, comprising:

[0040] The controllable DC module generates the relevant voltage required by the chip under test and outputs it to the switch module, and the controllable pulse signal module generates the pulse signal required by the chip under test and outputs it to the switch module;

[0041] The switch module outputs a detection signal to the chip under test according to the pulse signal output by the controllable pulse signal module and the related voltage output by the controllable DC module, so that the chip under test generates a breakdown current and outputs it to the detection module;

[0042] The detection module converts the breakdown current into a voltage pulse and outputs the voltage pulse to the sampling and holding amplification module;

[0043] The sampling and holding amplifier module amplifies the voltage pulse and maintains the maximum detection voltage, and amplifies the maximum detection voltage again and outputs the amplified signal to the digital-to-analog conversion module;

[0044] The digital-to-analog conversion module obtains a transient impulse voltage according to the amplified signal.

[0045] A tester comprises a circuit board and the chip port transient withstand voltage test circuit as described above, wherein the chip port transient withstand voltage test circuit is integrated on the circuit board.

[0046] The present invention provides a chip port transient withstand voltage test circuit, method and test machine. A controllable pulse signal module generates the pulse signal required in the actual application process of the tested chip to quickly control the conduction and cutoff of the switch module, and a controllable DC module generates the relevant voltage required by the tested chip. In this way, the switch module can output a detection signal with adjustable voltage and time and load it onto the tested chip. The breakdown current generated by the chip is reflected by the detection module. The sampling and holding amplifier module amplifies the voltage pulse and maintains the maximum detection voltage. After amplifying the maximum detection voltage again, the amplified signal is output to the digital-to-analog conversion module to obtain the transient impact voltage of the tested chip. It can be seen that the present invention can not only realize the withstand voltage test of the chip port with slow power-on test, but also realize the withstand voltage test of the chip port with fast power-on test. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary personnel in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0048] Figure 1 This is a principle block diagram of the chip port transient withstand voltage test circuit in the present invention.

[0049] Figure 2 It is a circuit principle diagram of the switch module in the present invention.

[0050] Figure 3 This is a circuit diagram of the sampling and holding amplifier module in the present invention.

[0051] Figure 4 It is a flow chart of the chip port transient withstand voltage test method of the present invention.

[0052] The marks in the accompanying drawings are: 100, controllable pulse signal module; 200, controllable DC module; 300, switch module; 400, detection module; 500, sampling and holding amplifier module; 501, first amplifier unit; 502, signal holding unit; 503, second amplifier unit; 600, digital-to-analog conversion module; 700, chip under test. DETAILED DESCRIPTION

[0053] The present invention provides a chip port transient withstand voltage test circuit, method, and tester. To clarify the objectives, technical solutions, and effects of the present invention, the present invention is further described below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0054] In the embodiments and patent claims, unless otherwise specified herein, the words "a," "an," "the," and "the" may include plural forms. If the embodiments of the present invention include descriptions of "first," "second," etc., such descriptions are for descriptive purposes only and should not be understood as indicating or implying their relative importance or implicitly specifying the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include at least one of such features.

[0055] It should be further understood that the term "comprising" as used in the description of the present invention refers to the presence of the stated features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intermediate elements. In addition, "connected" or "coupled" as used herein can include wireless connections or wireless couplings. The term "and / or" as used herein includes all or any units and all combinations of one or more associated listed items.

[0056] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art in the art to which the present invention belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with their meanings in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0057] In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the fact that ordinary technicians in this field can implement them. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0058] Please also see Figures 1 to 3 The present invention provides a preferred embodiment of a chip port transient withstand voltage test circuit.

[0059] like Figure 1 As shown, a chip port transient withstand voltage test circuit provided by the present invention is used to connect to the port of the chip under test 700, which includes: a controllable pulse signal module 100, a controllable DC module 200, a switch module 300, a detection module 400, a sampling and holding amplifier module 500 and a digital-to-analog conversion module 600; wherein, the controllable pulse signal module 100 is connected to the switch module 300 to generate the pulse signal required by the chip under test 700 and output it to the switch module 300; the controllable DC module 200 is connected to the switch module 300 to generate the relevant voltage required to be applied to the chip under test 700 and output it to the switch module 300; the switch module 300 is also connected to the chip under test 700 to The pulse signal output by the pulse signal module 100 and the related voltage output detection signal output by the controllable DC module 200 are sent to the chip under test 700, and the chip under test 700 generates a breakdown current according to the detection signal; the detection module 400 is connected to the chip under test 700, and is used to detect the breakdown current output by the chip under test 700 and convert it into a voltage pulse; the sampling and holding amplifier module 500 is connected to the detection module 400, and is used to amplify the voltage pulse and maintain the maximum detection voltage, and then amplify the maximum detection voltage again and output the amplified signal to the digital-to-analog conversion module 600; the digital-to-analog conversion module 600 is connected to the sampling and holding amplifier module 500, and is used to obtain a transient impulse voltage according to the amplified signal.

[0060] Specifically, the present invention uses the controllable pulse signal module 100 to generate the pulse signal required in the actual application process of the chip under test 700 to quickly control the conduction and cutoff of the switch module 300, and uses the controllable DC module 200 to generate the relevant voltage required by the chip under test 700 according to the product testing requirements, that is, the voltage required to be applied to the chip under test 700. The pulse signal output by the controllable pulse signal module 100 and the relevant voltage output by the controllable DC module 200 are input into the switch module 300. In this way, the switch module 300 can output a detection signal with adjustable voltage and time and load it onto the chip under test 700. Due to the different voltage resistance characteristics of the chip, different breakdown currents will be generated. The breakdown current generated by the chip is converted into a voltage pulse by the detection module 400 for reflection. Thereafter, the sampling and holding amplifier module 500 amplifies the voltage pulse and maintains the maximum detection voltage, and amplifies the maximum detection voltage again and outputs the amplified signal to the digital-to-analog conversion module 600 to obtain the transient impact voltage of the chip under test 700. It can be seen that the present invention, by loading a detection signal with adjustable voltage and time onto the chip under test 700, can not only perform a withstand voltage test on the chip port that is tested slowly with power on, but also perform a withstand voltage test on the chip port that is tested quickly with power on, thereby solving the withstand voltage problem of some chip ports that cannot be tested by ordinary testers.

[0061] See also Figure 1 In a further implementation of an embodiment, the detection module 400 includes: a first resistor R1, one end of the first resistor R1 is connected to the chip under test 700, and the other end of the first resistor R1 is grounded.

[0062] Specifically, the first resistor R1 is a current-limiting resistor, and the breakdown current output by the chip under test 700 can be reflected by the voltage across the first resistor R1.

[0063] See also Figure 1 and Figure 2In a further implementation of an embodiment, the switch module 300 includes: a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, a first switching tube and a second switching tube; wherein, one end of the second resistor R2 is respectively connected to the controllable DC module 200 and the second end of the first switching tube, and the other end of the second resistor R2 is respectively connected to one end of the third resistor R3 and the first end of the first switching tube; the other end of the third resistor R3 is connected to the third end of the second switching tube; the third end of the first switching tube is connected to the chip under test 700; the first capacitor C1 is connected to the second resistor R2 in parallel; one end of the fourth resistor R4 is connected to the controllable pulse signal module 100, and the other end of the fourth resistor R4 is connected to the first end of the second switching tube; and the third end of the second switching tube is grounded.

[0064] Specifically, the first switching tube is a first transistor Q1, and the second switching tube is a second transistor Q2. In some embodiments, the first transistor Q1 is a PNP transistor, the first end of the first transistor Q1 is the base, the second end is the emitter, and the third end is the collector. The second transistor Q2 is an NPN transistor, the first end of the second transistor Q2 is the base, the second end is the emitter, and the third end is the collector.

[0065] When the pulse signal output by the controllable pulse signal module 100 is a low-level signal, the second transistor Q2 is disconnected, the third resistor R3 has no pull-down current, and the first resistor R1 pulls up the base of the first transistor Q1, so that the first transistor Q1 is in the off state, thereby disconnecting the controllable DC module 200 from the device under test. When the pulse signal output by the controllable pulse signal module 100 is a high-level signal, the fourth resistor R4 acts as a current limiter, causing the second transistor Q2 to turn on. In this way, the third resistor R3 will lower the base voltage of the first transistor Q1, causing the first transistor Q1 to turn on. At this time, the switch module 300 and the chip under test 700 are connected, and the DC power output by the controllable DC module 200 can be applied to the port of the chip under test 700. Among them, the first capacitor C1 can slow down the start signal as needed, and the third resistor R3 and the first capacitor C1 act as filters to filter out unwanted interference signals.

[0066] See also Figure 1In a further implementation of an embodiment, the sampling and holding amplification module 500 includes: a first amplifying unit 501, a signal holding unit 502 and a second amplifying unit 503; wherein, the first amplifying unit 501 is connected to the first detection module 400, and is used to amplify the voltage pulse; the signal holding module is connected to the first amplifying unit 501, and is used to sample and hold the maximum detection voltage output by the first amplifying unit 501; the second amplifying unit is connected to the signal holding unit 502, and is used to amplify the maximum detection voltage and output an amplified signal to the digital-to-analog conversion module 600.

[0067] Specifically, the first amplifying unit 501 receives the voltage pulse obtained by the first resistor conversion and performs amplification processing, and then the signal holding unit 502 samples and holds the maximum detection voltage output by the first amplifying unit 501, and then amplifies it through the second amplifying unit 503 and outputs it to the digital-to-analog conversion module 600.

[0068] See also Figure 1 and Figure 2 In some embodiments, the first amplifying unit 501 includes: a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a first diode D1 and a first amplifier A1; wherein one end of the fifth resistor R5 is connected to the detection module 400, and the other end of the fifth resistor R5 is connected to the non-inverting input terminal V+ of the first amplifier A1; the inverting input terminal V- of the first amplifier A1 is respectively connected to one end of the sixth resistor R6 and one end of the seventh resistor R7, and the output terminal VOUT of the first amplifier A1 is respectively connected to the other end of the seventh resistor R7 and the signal holding unit 502; the other end of the sixth resistor R6 is grounded; the anode of the first diode D1 is connected to the other end of the fifth resistor R5, and the cathode of the first diode D1 is connected to the power supply terminal VCC of the first amplifier A1.

[0069] The signal holding unit 502 includes: a second diode D2 and a second capacitor C2; wherein, the anode of the second diode D2 is connected to the output terminal VOUT of the first amplifier A1, and the cathode of the second diode D2 is respectively connected to one end of the second capacitor C2 and the second amplifying unit 503; the other end of the second capacitor C2 is grounded.

[0070] The second amplifying unit 503 includes: an eighth resistor R8, a ninth resistor R9, a tenth resistor R10 and a second amplifier A2; wherein, one end of the eighth resistor R8 is connected to the cathode of the second diode D2, and the other end of the eighth resistor R8 is connected to the non-inverting input terminal V+ of the second amplifier A2; the inverting input terminal V- of the second amplifier A2 is respectively connected to one end of the ninth resistor R9 and one end of the tenth resistor R10, and the output terminal VOUT of the second amplifier A2 is respectively connected to the other end of the tenth resistor R10 and the digital-to-analog conversion module 600; the other end of the ninth resistor R9 is grounded.

[0071] Specifically, the breakdown current output by the chip under test 700 is converted into a voltage pulse by the first resistor R1 and then applied to the fifth resistor R5, and then transmitted to the non-inverting input terminal V+ of the first amplifier A1 through the fifth resistor R5, and the voltage pulse signal is amplified and output.

[0072] The first diode D1 is a Schottky diode, which has a low voltage drop of approximately 0.2V and a high speed, and can protect the amplifier. When the signal is greater than VCC, it is clamped to VCC + 0.2V, thereby protecting the amplifier. The fifth resistor R5, the sixth resistor R6, the seventh resistor R7, and the first amplifier A1 form a first-stage amplifier circuit, which performs primary amplification on the voltage pulse fed back by the first resistor R1.

[0073] The second diode D2 and the third capacitor C3 form a peak sampling and holding unit, which can sample and hold the maximum signal output by the first amplifier A1 to output a sample and hold signal to the second amplifier A2.

[0074] The eighth resistor R8 , the ninth resistor R9 , the tenth resistor R10 and the second amplifier A2 form a secondary amplifier circuit, which can amplify the sample-and-hold signal and output it to the digital-to-analog conversion module 600 .

[0075] In some embodiments, the first amplifier A1 and the second amplifier A2 are high-speed operational amplifiers (actual operational amplifier parameters are 250MHz bandwidth and input bias current 10pA). By utilizing the high-impedance input of the second amplifier A2, the sample-and-hold signal can be amplified with sufficient time for the back-end digital-to-analog conversion module 600 to process it. In addition, due to the low output impedance of the second amplifier A2, the input impedance of the digital-to-analog conversion module 600 does not need to be considered, and thus will not affect the signal itself.

[0076] In some embodiments, the controllable pulse signal module 100 can be a micro control unit capable of generating a pulse signal with a high voltage of 5V and a width of about 1ms. The digital-to-analog conversion module 600 can be a digital-to-analog converter. The controllable DC module 200 is a controllable DC power supply, which is used to facilitate testing to obtain data and result judgment. All of these are existing technologies and will not be repeated here.

[0077] See also Figure 4 In some embodiments, the present invention further provides a method for applying the chip port transient withstand voltage test circuit described above, comprising the steps of:

[0078] S100, the controllable DC module generates the relevant voltage required by the chip under test and outputs it to the switch module, and the controllable pulse signal module generates the pulse signal required by the chip under test and outputs it to the switch module; the specific details are as described in an embodiment of a chip port transient withstand voltage test circuit, which will not be repeated here.

[0079] S200, the switch module outputs a detection signal to the chip under test based on the pulse signal output by the controllable pulse signal module and the related voltage output by the controllable DC module, so that the chip under test generates a breakdown current and outputs it to the detection module; the specific details are as described in an embodiment of a chip port transient withstand voltage test circuit, which will not be repeated here.

[0080] S300, the detection module converts the breakdown current into a voltage pulse and outputs it to the sampling and holding amplification module; the details are as described in an embodiment of a chip port transient withstand voltage test circuit, which will not be repeated here.

[0081] S400, the sampling and holding amplifier module amplifies the voltage pulse and maintains the maximum detection voltage, and amplifies the maximum detection voltage again and outputs the amplified signal to the digital-to-analog conversion module; the specific details are as described in an embodiment of a chip port transient withstand voltage test circuit, which will not be repeated here.

[0082] S500: The digital-to-analog conversion module obtains a transient impulse voltage according to the amplified signal. Specific details are as described in an embodiment of a chip port transient withstand voltage test circuit, which will not be repeated here.

[0083] In some embodiments, the present invention further provides a tester comprising a circuit board and the chip port transient withstand voltage test circuit described above, wherein the chip port transient withstand voltage test circuit is integrated on the circuit board. The chip port transient withstand voltage test circuit, when integrated on the circuit board, is compact and can be directly attached to the chip being tested, facilitating both mid-stage and final chip testing.

[0084] In summary, the chip port transient withstand voltage test circuit, method, and tester provided by the present invention have the following beneficial effects:

[0085] The controllable pulse signal module generates the pulse signal required in the actual application process of the chip under test to quickly control the conduction and cutoff of the switch module, and the controllable DC module generates the relevant voltage required by the chip under test. In this way, the switch module can output a detection signal with adjustable voltage and time and load it onto the chip under test. The breakdown current generated by the chip is reflected by the detection module. The sampling and holding amplifier module amplifies the voltage pulse and maintains the maximum detection voltage. After amplifying the maximum detection voltage again, it outputs the amplified signal to the digital-to-analog conversion module to obtain the transient impact voltage of the chip under test. It can be seen that the present invention can not only realize the withstand voltage test of the chip port with slow power-on test, but also realize the withstand voltage test of the chip port with fast power-on test.

[0086] It should be understood that the application of the present invention is not limited to the above examples. For those skilled in the art, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A chip port transient withstand voltage test circuit, used to connect to the port of the chip under test, characterized in that: include: Controllable pulse signal module, controllable DC module, switch module, detection module, sampling and holding amplifier module and digital-to-analog conversion module; wherein, The controllable pulse signal module is connected to the switch module, and is used to generate the pulse signal required by the chip under test and output it to the switch module; The controllable DC module is connected to the switch module, and is used to generate the relevant voltage required to be applied to the chip under test and output it to the switch module; The switch module is further connected to the chip under test and is configured to output a detection signal to the chip under test based on the pulse signal output by the controllable pulse signal module and the voltage correlated with the output of the controllable DC module. The chip under test generates a breakdown current based on the detection signal. The switch module includes: a second resistor, a third resistor, a fourth resistor, a first capacitor, a first switching transistor, and a second switching transistor. One end of the second resistor is connected to the controllable DC module and the second end of the first switching transistor, respectively, and the other end of the second resistor is connected to one end of the third resistor and the first end of the first switching transistor, respectively. The other end of the third resistor is connected to the third end of the second switching transistor. The third end of the first switching transistor is connected to the chip under test. The first capacitor is connected in parallel with the second resistor. One end of the fourth resistor is connected to the controllable pulse signal module, and the other end of the fourth resistor is connected to the first end of the second switching transistor. The third end of the second switching transistor is grounded. The controllable pulse signal module generates the pulse signal required by the chip under test during actual application to control the conduction and cutoff of the switch module. The first capacitor slows down the turn-on signal as needed, and the third resistor and the first capacitor act as filters to filter out unwanted interference signals. The controllable pulse signal module generates the pulse signal required by the chip under test to quickly control the conduction and cutoff of the switch module, and generates the voltage required to be applied to the chip under test through the controllable DC module according to the product testing requirements. The pulse signal output by the controllable pulse signal module and the related voltage output by the controllable DC module are input to the switch module, and the switch module outputs a detection signal with adjustable voltage and time, which is loaded onto the chip under test; The detection module is connected to the chip under test and is used to detect the breakdown current output by the chip under test and convert it into a voltage pulse; The sampling and holding amplifier module is connected to the detection module, and is used to amplify the voltage pulse and maintain the maximum detection voltage, and then amplify the maximum detection voltage again and output the amplified signal to the digital-to-analog conversion module; the sampling and holding amplifier module includes: a first amplifying unit, a signal holding unit and a second amplifying unit; wherein, The first amplifying unit is connected to the detection module and is used to amplify the voltage pulse; The signal holding unit is connected to the first amplifying unit and is used to sample and hold the maximum detection voltage output by the first amplifying unit; The second amplifying unit is connected to the signal holding unit, and is configured to amplify the maximum detection voltage and output an amplified signal to the digital-to-analog conversion module; The digital-to-analog conversion module is connected to the sample-hold amplification module and is used to obtain a transient impulse voltage according to the amplified signal.

2. The chip port transient withstand voltage test circuit according to claim 1, characterized in that: The detection module includes: a first resistor, one end of the first resistor is connected to the chip under test, and the other end of the first resistor is grounded.

3. The chip port transient withstand voltage test circuit according to claim 1, characterized in that: The first amplifying unit includes: a fifth resistor, a sixth resistor, a seventh resistor, a first diode and a first amplifier; wherein, One end of the fifth resistor is connected to the detection module, and the other end of the fifth resistor is connected to the non-inverting input terminal of the first amplifier; The inverting input terminal of the first amplifier is connected to one end of the sixth resistor and one end of the seventh resistor respectively, and the output terminal of the first amplifier is connected to the other end of the seventh resistor and the signal holding unit respectively; The other end of the sixth resistor is grounded; An anode of the first diode is connected to the other end of the fifth resistor, and a cathode of the first diode is connected to a power supply terminal of the first amplifier.

4. The chip port transient withstand voltage test circuit according to claim 3, characterized in that: The signal holding unit includes: a second diode and a second capacitor; wherein, The anode of the second diode is connected to the output end of the first amplifier, and the cathode of the second diode is connected to one end of the second capacitor and the second amplifying unit respectively; The other end of the second capacitor is grounded.

5. The chip port transient withstand voltage test circuit according to claim 4, characterized in that: The second amplifying unit includes: an eighth resistor, a ninth resistor, a tenth resistor and a second amplifier; wherein, One end of the eighth resistor is connected to the cathode of the second diode, and the other end of the eighth resistor is connected to the non-inverting input terminal of the second amplifier; The inverting input terminal of the second amplifier is connected to one end of the ninth resistor and one end of the tenth resistor respectively, and the output terminal of the second amplifier is connected to the other end of the tenth resistor and the digital-to-analog conversion module respectively; The other end of the ninth resistor is grounded.

6. The chip port transient withstand voltage test circuit according to claim 1, characterized in that: The controllable pulse signal module is a micro control unit; the digital-to-analog conversion module is a digital-to-analog converter.

7. A method for testing a chip port transient withstand voltage circuit according to any one of claims 1 to 6, characterized in that: include: The controllable DC module generates the relevant voltage required by the chip under test and outputs it to the switch module, and the controllable pulse signal module generates the pulse signal required by the chip under test and outputs it to the switch module; The switch module outputs a detection signal to the chip under test according to the pulse signal output by the controllable pulse signal module and the related voltage output by the controllable DC module, so that the chip under test generates a breakdown current and outputs it to the detection module; The detection module converts the breakdown current into a voltage pulse and outputs the voltage pulse to the sampling and holding amplification module; The sampling and holding amplifier module amplifies the voltage pulse and maintains the maximum detection voltage, and amplifies the maximum detection voltage again and outputs the amplified signal to the digital-to-analog conversion module; The digital-to-analog conversion module obtains a transient impulse voltage according to the amplified signal.

8. A testing machine, characterized in that: It comprises a circuit board, and the chip port transient withstand voltage test circuit according to any one of claims 1 to 6, wherein the chip port transient withstand voltage test circuit is integrated on the circuit board.

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