High bandwidth memory system using multi-level signaling

Abstract

A high bandwidth memory system includes a motherboard and a semiconductor package coupled to the motherboard. The semiconductor package includes a package substrate mounted on the motherboard and including signal lines providing lanes, a first semiconductor device mounted on the package substrate and including a first physical layer (PHY) circuit, and a second semiconductor device mounted on the package substrate and including a second PHY circuit. The first semiconductor device and the second semiconductor device exchange data signals with each other through the lanes, the data signals being multi-level signals having M levels, where M is a natural number greater than 2, and the first PHY circuit compensates for distortion of the lanes and compensates for mismatch between the lanes by performing digital signal processing.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0010520, filed on January 26, 2021, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the present invention relate to a high-bandwidth storage system using multilevel signaling. Background Technology

[0004] High-bandwidth memory (HBM) consists of a buffer die and multiple memory dies stacked on the buffer die. The buffer die and the multiple memory dies are electrically connected to each other via silicon vias (TSVs) and microbumps.

[0005] Logic chips such as graphics processing units (GPUs) and HBMs can be integrated onto a silicon interposer and implemented as a single package. This significantly reduces the distance between the logic chip and the HBM, and increases transmission speed.

[0006] Intermediates are microcircuits inserted between a semiconductor chip and a packaging substrate, such as a PCB, when the gaps between the input / output pads of a semiconductor chip manufactured by a microprocessor do not match the gaps between the input / output pads of the chip. Intermediates have a multi-layer wiring structure to redistribute the inputs and outputs of the semiconductor chip.

[0007] In multilevel signals, each voltage level represents one or more data bits. Although multilevel signals offer increased data rates compared to binary signals, the narrow voltage level intervals can cause signal distortion or loss. Summary of the Invention

[0008] An example embodiment provides a high-bandwidth storage system in which digital signal processing functions are mounted on a buffer die and communication is performed using multi-level signal transmission without intermediaries.

[0009] According to an example embodiment, a high-bandwidth storage system includes: a motherboard and a semiconductor package coupled to the motherboard. The semiconductor package includes: a package substrate mounted on the motherboard and including signal lines providing channels; a first semiconductor device mounted on the package substrate and including a first physical layer (PHY) circuit; and a second semiconductor device mounted on the package substrate and including a second PHY circuit. The first semiconductor device and the second semiconductor device exchange data signals with each other through the channels, the data signals being multi-level signals having M levels, where M is a natural number greater than 2, and the first PHY circuit performs digital signal processing to compensate for distortion of the channels and to compensate for mismatches between the channels.

[0010] According to an example embodiment, a high-bandwidth memory system includes: a package substrate including signal lines providing channels; at least one first semiconductor device including a buffer die and memory dies stacked on the buffer die; a second semiconductor device exchanging data signals with the first semiconductor device through the channels; and a connection terminal directly connecting the at least one first semiconductor device and the second semiconductor device to the package substrate. The data signals are multi-level signals having M levels, where M is a natural number greater than 2, and the at least one first semiconductor device compensates for distortion in the channels and compensates for mismatches between the channels.

[0011] According to an example embodiment, a high-bandwidth storage system includes: a buffer die comprising a transmitting circuit and a receiving circuit, the transmitting circuit and the receiving circuit exchanging data signals with a processor through a channel of a package substrate, wherein the data signals are multi-level signals having M levels, and M is a natural number greater than 2; and a storage die stacked on the buffer die and connected to the buffer die via a through electrode. The receiving circuit of the buffer die includes: an analog-to-digital converter (ADC) corresponding to the channel and converting the multi-level signal received through the channel into a digital signal; a first compensation circuit that compensates for distortion of the channel and for mismatch between the channels; a decoder that converts the digital signal into a binary signal; and a driver that outputs the binary signal to the through electrode. Attached Figure Description

[0012] The above and other features of the present invention will become more apparent from the detailed description of exemplary embodiments of the inventive concept with reference to the accompanying drawings, in which:

[0013] Figure 1 This is a cross-sectional view of a high-bandwidth storage system based on a comparative example;

[0014] Figure 2 This is a cross-sectional view of a high-bandwidth storage system according to an exemplary embodiment of the present invention;

[0015] Figure 3 This is a schematic diagram of a storage system according to an example embodiment;

[0016] Figure 4 and Figure 5 This is a diagram illustrating a multi-level signal according to an example embodiment;

[0017] Figure 6 A receiving circuit of a semiconductor device according to an example embodiment is shown;

[0018] Figure 7 A first compensation circuit according to an example embodiment is shown;

[0019] Figure 8 A transmitting circuit of a semiconductor device according to an example embodiment is shown;

[0020] Figure 9 A second compensation circuit according to an example embodiment is shown;

[0021] Figure 10 A high-bandwidth storage system according to an example embodiment is shown. Detailed Implementation

[0022] Exemplary embodiments of the inventive concept will be described more fully below with reference to the accompanying drawings. Throughout the drawings, similar reference numerals may refer to similar elements.

[0023] It will be understood that the terms “first,” “second,” “third,” etc., are used herein to distinguish one element from another, and the elements are not limited by these terms. Thus, the “first” element in the example embodiment may be described as the “second” element in another example embodiment.

[0024] It should be understood that, unless the context clearly indicates otherwise, the description of a feature or aspect within each example embodiment should generally be considered applicable to other similar features or aspects in other example embodiments.

[0025] For ease of description, spatially relative terms (such as "below," "under," "down," "below," "above," "upper," etc.) may be used herein to describe the relationship of one element or feature as shown in the accompanying drawings to other elements or features. It will also be understood that, in addition to the orientations depicted in the drawings, the spatially relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the drawings is flipped, an element described as "below" or "under" or "below" other elements or features will be oriented "above" other elements or features. Thus, the exemplary terms "below" and "below" can cover both above and below orientations.

[0026] It will be understood that when a component, such as a membrane, region, layer, or element, is referred to as being "on" another component, "connected to," "bonded to," or "adjacent to" another component, it can be directly on, directly connected to, directly bonded to, or directly adjacent to the other component, or there may be intermediate components. It will also be understood that when a component is referred to as being "between" two components, it can be the only component between the two components, or there may be one or more intermediate components. It will also be understood that when a component is referred to as "covering" another component, it can be the only component covering the other component, or one or more intermediate components may also cover the other component. Other terms used to describe relationships between components should be interpreted in a similar manner.

[0027] In this specification, "channel" refers to an input / output path used to exchange data between a first semiconductor device and a second semiconductor device. This channel may also be provided by the wiring layer and the signal line of the substrate of the semiconductor device.

[0028] Figure 1 It is a cross-sectional view of a high-bandwidth storage system based on a comparative example.

[0029] Reference Figure 1 The high-bandwidth storage system 100 may include a first semiconductor device 110, a second semiconductor device 120, an intermediary 130, a packaging substrate 150, and a motherboard 170.

[0030] The first semiconductor device 110 may be a memory package. For example, the first semiconductor device 110 may be a high-bandwidth memory (HBM). The second semiconductor device 120 may be a processor (or host), such as a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), an application-specific integrated circuit (ASIC), etc.

[0031] The first semiconductor device 110 may include a plurality of microbumps 111, a buffer die 112, and first to fourth memory dies 113, 114, 115, and 116. The buffer die 112 may be disposed in the lowermost portion of the first semiconductor device 110. The buffer die 112 may be referred to as, for example, a logic die, a base die, etc.

[0032] First memory dies 113 through fourth memory dies 116 may be sequentially stacked on buffer die 112. Buffer die 112 and first memory dies 113 through fourth memory dies 116 may be interconnected via silicon vias (TSVs) 112-1, 113-2, 114-2, and 115-2. Each of the first memory dies 113 through fourth memory dies 116 may include a memory bank, and each memory bank may include a memory cell array comprising memory cells located at the intersections of word lines and bit lines. For example, a memory cell may be a dynamic random access memory (DRAM) cell, etc.

[0033] Several logic functions can be implemented in the buffer die 112. The buffer die 112 may include a circuit region 112-2 and a wiring layer 112-3. The circuit region 112-2 may be a region including a wafer and circuits provided by elements formed on the wafer. Some circuits may constitute a first physical layer circuit PHY1. When the first physical layer circuit PHY1 is a transmitting circuit, the first physical layer circuit PHY1 can be configured as a driver; when the first physical layer circuit PHY1 is a receiving circuit, the first physical layer circuit PHY1 can be configured as a buffer. The circuit region 112-2 may be formed of silicon or the like.

[0034] Multiple TSVs 112-1 can penetrate the buffer die 112. A first memory die 113 is stacked on the buffer die 112, and the buffer die 112 can be electrically connected to the first memory die 113 via the multiple TSVs 112-1. Multiple first microbumps 113-1 can be disposed between the buffer die 112 and the first memory die 113. Each of the multiple first microbumps 113-1 may include, for example, nickel (Ni), copper (Cu), tin (Sn), lead (Pb), etc. Each of the multiple first microbumps 113-1 can be formed in a hemispherical or convex shape. Each of the multiple first microbumps 113-1 can have a size of a few micrometers or tens of micrometers.

[0035] In the manner described above, the buffer die 112 and the plurality of storage dies 113 to 116 can be electrically connected to each other via microbumps 113-1, 114-1, 115-1 and 116-1, TSV 112-1, TSV 113-2, TSV 114-2 and TSV 115-2 and internal wiring circuitry.

[0036] The first semiconductor device 110 can be stacked on the intermediate 130. For example, the first semiconductor device 110 can be stacked on the intermediate 130 by combining the microbumps 111 of the first semiconductor device 110 with the upper pads 131 of the intermediate 130. For example, the first semiconductor device 110 can be electrically connected to the intermediate 130.

[0037] The first semiconductor device 110 may be stacked on the package substrate 150 via an intermediary 130. The intermediary 130 may electrically connect the first semiconductor device 110 to the package substrate 150. The package substrate 150 may be a substrate for packaging (e.g., a printed circuit board (PCB) with circuit patterns), but is not limited thereto.

[0038] The second semiconductor device 120 can be stacked on the interposer 130. For example, the second semiconductor device 120 can be stacked on the interposer 130 through the bonding of microbumps 121 of the second semiconductor device 120 and upper pads 131 of the interposer 130. The second semiconductor device 120 can be stacked on the package substrate 150 via the interposer 130. The interposer 130 can electrically connect the second semiconductor device 120 to the package substrate 150. The second semiconductor device 120 may include a second physical layer circuit PHY2.

[0039] Intermediate 130 may include an upper pad 131, an upper wiring layer, a substrate, a lower wiring layer, a through electrode, and a connection terminal 140. The substrate may be formed of any of, for example, silicon, organic, plastic, and glass substrates. The substrate may have a single-layer or multi-layer structure. When the substrate is a silicon substrate, intermediate 130 may also be referred to as a silicon intermediate. However, intermediate 130 is not limited thereto, and intermediate 130 may include at least one of, for example, silicon, glass, ceramic, or plastic.

[0040] Upper pad 131 may be disposed on the upper surface of the substrate and may be electrically coupled to microbumps of a semiconductor device. Connector terminal 140 may be disposed on the lower surface of the substrate. Connector terminal 140 may be used when the intermediate 130 is stacked on a printed circuit board (PCB) or the like. Connector terminal 140 may be a bump or solder ball based on its shape or material. An upper wiring layer may be disposed below upper pad 131 for electrical connection to upper pad 131, and a lower wiring layer may be connected to the upper wiring layer via a through electrode that penetrates at least a portion of the substrate. Connector terminal 140 may be electrically connected to the through electrode.

[0041] The first semiconductor device 110, the second semiconductor device 120, the intermediate 130, and the packaging substrate 150 can be configured as a semiconductor package PA1, which can be implemented by one of the technologies such as system-in-package (SIP) or multi-chip package (MCP).

[0042] Semiconductor package PA1 can be mounted on motherboard 170 via external connection terminals 160 of package substrate 150. External connection terminals 160 can be bumps or solder balls. Semiconductor package PA1 can be mounted on motherboard 170 via external connection terminals 160 using a ball grid array (BGA) method, but the mounting method is not limited to this.

[0043] The size of the external connection terminal 160 may be larger than the size of the connection terminal 140, and the size of the connection terminal 140 may be larger than the size of the micro bumps 111 and 121, but is not limited thereto.

[0044] Intermediate 130 refers to a microcircuit board as described below: a microcircuit board additionally inserted between the semiconductor chip and the package substrate when the gap between the input and output pads of a semiconductor chip manufactured by a microprocessor mismatches with the gap between the input and output pads of a package substrate 150 such as a PCB. A silicon intermediary can be implemented as intermediary 130. Using a silicon intermediary as intermediary 130 would significantly increase the manufacturing cost of high-bandwidth memory systems.

[0045] In a high-bandwidth memory system according to an exemplary embodiment of the present invention, semiconductor devices can communicate with each other using multiple channels provided by signal lines included in a package substrate without an intermediary. That is, according to the exemplary embodiment, an intermediary such as intermediary 130 is not included in the high-bandwidth memory system. Therefore, there is an effect of reducing the manufacturing cost of the high-bandwidth memory system according to the exemplary embodiment. The high-bandwidth memory system can use multi-level signal transmission. Digital signal processing functions can be used to overcome the degraded signal integrity (SI) environment and mismatch between different channels that may occur when communicating using signal lines included in the package substrate.

[0046] Figure 2 This is a cross-sectional view of a high-bandwidth storage system according to an exemplary embodiment of the present invention.

[0047] Focus on and Figure 1 The difference is different from Figure 1 The high-bandwidth storage system 100, in an example embodiment, Figure 2The high-bandwidth memory system 200 does not include an intermediary between the semiconductor devices 210 and 220 and the package substrate 250. The semiconductor devices 210 and 220 can be stacked on the package substrate 250 using connection terminals 230 and 240 (e.g., general-purpose bumps, solder balls, etc.).

[0048] The first semiconductor device 210, the second semiconductor device 220, and the packaging substrate 250 can be configured as a single semiconductor package PA2, which can be implemented using a technology such as system-in-package (SIP) and multi-chip package (MCP).

[0049] The first semiconductor device 210 may include a buffer die 212 and first to fourth memory dies 213, 214, 215, and 216 sequentially stacked on the buffer die 212. The buffer die 212 may include a circuit region 212-2 and a wiring layer 212-3. The buffer die 212 and the first to fourth memory dies 213-1 and 216 may be electrically connected to each other via microbumps 213-1, 214-1, 215-1, and 216-1, TSV 212-1, TSV 213-2, TSV 214-2, and TSV 215-2, as well as internal wiring circuitry.

[0050] The semiconductor package PA2 can be mounted on the motherboard 270 via external connection terminal 260. External connection terminal 260 can be a bump or solder ball. The semiconductor package PA2 can be mounted on the motherboard 270 via external connection terminal 260 using a ball grid array (BGA) method, but the mounting method is not limited to this.

[0051] The package substrate 250 may include signal lines 280 providing multiple channels, through which the first semiconductor device 210 and the second semiconductor device 220 can communicate with each other via the channels provided by the signal lines of the package substrate 250.

[0052] The first connection terminal 230 can be directly connected to the first semiconductor device 210 and the packaging substrate 250, and the second connection terminal 240 can be directly connected to the second semiconductor device 220 and the packaging substrate 250. The first semiconductor device 210 may include a first physical layer circuit PHY1, and the second semiconductor device 220 may include a second physical layer circuit PHY2.

[0053] Return to reference Figure 1 , corresponding to Figure 1 The HBM of the first semiconductor device 110 example can have increased bandwidth by significantly increasing the number of channels. Semiconductor devices 110 and 120 are connected to each other via intermediate 130 and microbumps 111 and 121 to achieve high-density interconnect (HDI).

[0054] Refer again Figure 2 Semiconductor devices 210 and 220 can be connected to package substrate 250 via connection terminals 230 and 240. Connection terminals 230 and 240 can be general bumps or solder balls. Figure 2 The size of the connection terminals 230 and 240 can be larger than Figure 1 The size of the microbumps 111 and 121. Therefore, the number of connection terminals 230 and 240 between the semiconductor devices 210 and 220 and the package substrate 250 can be less than [the size of the microbumps 111 and 121]. Figure 1 The number of microbumps 111 and 121 between the semiconductor devices 110 and 120 and the intermediate 130. Therefore, by Figure 2 The number of channels provided by the signal lines of the packaging substrate 250 can be less than that provided by the packaging substrate 250. Figure 1 The number of channels provided by the 130 signal line of the intermediary component.

[0055] In the high-bandwidth storage system 200 according to the example embodiment, the data signal exchanged between the first semiconductor device 210 and the second semiconductor device 220 can be a multilevel signal with M levels, where M is a natural number greater than 2. The multilevel signal can be generated based on, for example, Pulse Amplitude Modulation (PAM) 4, PAM 8, PAM 16, etc. For example, the data signal can be generated based on PAM 4 and can be a multilevel signal with four different levels. In M-ary PAM, one symbol can represent log2M bits. Therefore, compared to binary signals, the data rate can be increased when using multilevel signal transmission.

[0056] However, compared to binary signals, multilevel signals have narrower voltage level intervals and can communicate through channels provided by the signal lines of the package substrate 250, leading to inter-symbol interference (ISI). Therefore, the signal integrity (SI) environment may be poor. Furthermore, mismatches may occur between different channels.

[0057] The high-bandwidth storage system 200 of the present invention, according to an example embodiment of the present invention, can overcome the deteriorated SI environment and mismatch between different channels by using digital signal processing functions.

[0058] Figure 3 This is a schematic diagram of a storage system according to an example embodiment.

[0059] Reference Figure 3 The high-bandwidth storage system 300 according to an example embodiment may include a first semiconductor device 310 and a second semiconductor device 320. The first semiconductor device 310 may correspond to... Figure 2 The first semiconductor device 210 and the second semiconductor device 320 can correspond to Figure 2The second semiconductor device 220. The first semiconductor device 310 and the second semiconductor device 320 can exchange data through the channel CH provided by the signal lines of the package substrate.

[0060] The first semiconductor device 310 may include a first transmitting circuit 311 for transmitting data, a first receiving circuit 312 for receiving data, and a first core circuit 313 for controlling the overall operation of the first semiconductor device 310. The first transmitting circuit 311 and the first receiving circuit 312 may be implemented in the physical layer circuitry of the buffer die included in the first semiconductor device 310.

[0061] The second semiconductor device 320 may include a second receiving circuit 321 for receiving data, a second transmitting circuit 322 for transmitting data, and a second core circuit 323 for controlling the overall operation of the second semiconductor device 320.

[0062] In the high-bandwidth storage system 300, the first semiconductor device 310 and the second semiconductor device 320 can exchange data with each other using multi-level signals with M levels, where M is a natural number greater than 2. For example, M can be a power of 2 and can be determined based on the amount of data to be transmitted through each channel CH.

[0063] The first receiving circuit 312 can receive and recover multi-level signals transmitted from the second transmitting circuit 322. For example, the first receiving circuit 312 can convert a multi-level signal with M levels into a digital signal and perform digital signal processing functions on the digital signal. The first receiving circuit 312 can convert the digital signal into a binary signal and send the converted binary signal to multiple memory dies.

[0064] The first transmitting circuit 311 can convert data to be sent to the second receiving circuit 321 into a multi-level signal and output the converted signal. For example, the first transmitting circuit 311 can convert a binary signal into a multi-level signal with M levels and perform digital signal processing on the multi-level signal. The first transmitting circuit 311 can also convert the multi-level signal into an analog signal and send the converted signal to a channel on the packaging substrate.

[0065] The high-bandwidth storage system 300 according to the example embodiment can communicate using multi-level signal transmission without the need for intermediaries. Therefore, the manufacturing cost of the high-bandwidth storage system 300 can be reduced.

[0066] According to an example embodiment, the high-bandwidth storage system 300 can mount digital signal processing functions on the buffer die of the first semiconductor device 310. The high-bandwidth storage system 300 can use the digital signal processing functions to compensate for distortion of channel CH and mismatch between channels CH.

[0067] Figure 4 and Figure 5 This is a diagram illustrating a multilevel signal according to an example embodiment.

[0068] Reference Figure 4 A non-return-to-zero (NRZ) signal can be a binary code that uses low signal levels (LV1) and high signal levels (LV2) to indicate the "1" and "0" information of a digital logic signal. When receiving data using an NRZ signal, one bit of data can be received during one data transmission cycle (PR). For example, each of the two levels, LV1 and LV2, can correspond to a 0 or 1 data bit. An NRZ signal can transmit one bit of data during one data transmission cycle. Figure 4 In the middle, V REF Indicates the reference level.

[0069] Reference Figure 5 Multilevel signals can have four levels: LV1, LV2, LV3, and LV4. Multilevel signals can be generated based on 4-level pulse amplitude modulation-4 (PAM-4). When using a multilevel signal generated based on 4-level pulse amplitude modulation to receive data, two bits of data can be received during one data transmission cycle (PR). Figure 5 In the middle, V LOW Indicates a low level, V MID The level is indicated, and V HIGH Indicator level.

[0070] For example, when natural mapping is applied, the four levels LV1 to LV4 can sequentially correspond to data bits 00, 01, 10, and 11, respectively. Therefore, the storage device can receive two bits (e.g., one of data bits 00, 01, 10, and 11) during a single data transmission cycle PR. As another example, when Gray mapping is applied to significantly reduce the bit error rate, the four levels LV1 to LV4 can sequentially correspond to data bits 00, 01, 11, and 10, respectively. This specification only describes examples of applying natural or Gray mapping when converting NRZ signals to multi-level signals. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0071] Figure 5 The amount of data that a multilevel signal can transmit during one data transmission cycle is Figure 4 The NRZ signal can transmit twice the amount of data during a single data transmission cycle, but with a relatively narrow signal level interval. If the signal level interval is narrow, the signal may be lost due to distortion when transmitted through the channel.

[0072] A high-bandwidth storage system according to an exemplary embodiment of the present invention may include digital signal processing functions. Therefore, signal distortion can be compensated for.

[0073] Figure 6 A receiving circuit of a semiconductor device according to an example embodiment is shown.

[0074] Reference Figure 6 The receiving circuit 400 can receive multi-level signals sDQ[0] to sDQ[K-1] with M levels through K data pins P1 to PK. The receiving circuit 400 converts the multi-level signals sDQ[0] to sDQ[K-1] into binary signals bDQ[0] to bDQ[N-1], and can output the binary signals bDQ[0] to bDQ[N-1] to TSVs (TSV1 to TSVN) through N TSV pins. K is a natural number less than N, and satisfies N = K·log2M.

[0075] The receiver circuit 400 may include an analog front end (AFE) 410, an analog-to-digital converter (ADC) 420, a first compensation circuit 430, a decoder 440, and a TSV driver 450. Figure 6 The components shown can be included in the first physical layer circuit PHY1 of the first semiconductor device 210.

[0076] AFE 410 may include multiple AFEs corresponding to multiple channels. AFE 410 can receive multi-level signals sDQ[0] to sDQ[K-1] with M levels through data pins P1 to PK. AFE 410 can amplify attenuated analog signals from external input, remove noise, and restore the signal to near the original signal.

[0077] The ADC 420 can include multiple ADCs corresponding to multiple channels. An ADC is a circuit that converts analog signals into digital signals. The ADC 420 converts analog signals into digital signals through sampling, quantization, and encoding. Sampling extracts the values ​​of an analog signal at a constant sampling period. By sampling the analog signal, a continuous analog signal can be represented as a discrete-time signal. Quantization represents the levels of the extracted sampled signal in several steps. In quantization, sampled values ​​can be categorized for each segment, and the sampled value can be replaced with a representative value for each segment. Encoding converts values ​​belonging to the levels divided by quantization into binary numbers. In encoding, a binary code can be assigned to each part, and the sampled value can be converted into a binary code.

[0078] The first compensation circuit 430 can receive the digital signal output from the ADC 420 and perform digital signal processing. For example, the first compensation circuit 430 can compensate for channel distortion and channel mismatch. For example, the first compensation circuit 430 can remove ISI phenomenon of the data signal and can compensate for inter-channel timing skew mismatch, inter-channel offset mismatch, inter-channel gain mismatch, and sampling timing mismatch. (See reference...) Figure 7 The first compensation circuit 430 is described in detail.

[0079] Decoder 440 can convert digital signals that have undergone digital signal processing into binary signals bDQ[0] to bDQ[N-1].

[0080] The TSV driver 450 can assign binary signals bDQ[0] to bDQ[N-1] to TSV TSV1 to TSVN via the TSV pin. The binary signals bDQ[0] to bDQ[N-1] can be sent to multiple memory dies via TSV TSV1 to TSVN.

[0081] According to the example embodiment, the receiving circuit 400 can output the multi-level signals sDQ[0] to sDQ[K-1] to TSV TSV1 to TSVN via the TSV pin without converting the multi-level signals sDQ[0] to sDQ[K-1] into binary data. In this case, in the example embodiment, the receiving circuit 400 does not include the decoder 440.

[0082] Figure 7 A first compensation circuit according to an example embodiment is shown.

[0083] Reference Figure 7 The first compensation circuit 430 may include an equalizer 431, a first mismatch compensation circuit 432, and a clock and data recovery (CDR) circuit 433.

[0084] Equalizer 431 can restore a signal distorted during transmission to its original shape. The resistive component of the signal line and the input capacitance at the transmitting / receiving end can cause ISI in the data signal, and equalizer 431 can remove ISI from the data signal.

[0085] The equalizer 431 can be implemented as an analog or digital circuit. For example, a continuous-time linear equalizer (CTLE) can be implemented as an analog circuit, and a feedforward equalizer (FFE) can be implemented as a digital circuit. A decision feedback equalizer (DFE) can be implemented as an analog or digital circuit.

[0086] The first mismatch compensation circuit 432 can compensate for timing skew mismatch, offset mismatch, and gain mismatch between channels.

[0087] Gain mismatch and offset mismatch can be caused by differences in the semiconductor process distribution of an ADC. Gain mismatch refers to the difference in gain between the amplifiers included in the ADC. Gain mismatch leads to differences in signal amplitude. Offset mismatch refers to the difference in offset voltage between the amplifiers included in the ADC. Offset mismatch leads to differences in the average signal level.

[0088] Timing skew mismatch between channels refers to a difference in the physical lengths of the channels. This mismatch causes differences in the arrival times of signals at the ADC. Therefore, timing skew mismatch between channels can be compensated for by compensating for the timing skew between the signals arriving at the ADC.

[0089] CDR circuit 433 can compensate for sampling timing mismatch between channels. CDR circuit 433 can be a circuit that uses the signal received from the first mismatch compensation circuit 432 and an internal clock signal to recover data and a clock synchronized with the data. CDR circuit 433 can output the clock synchronized with the data to the ADC. The sampling period of the ADC can be adjusted based on the clock synchronized with the data.

[0090] According to the example embodiment, when a separate strobe signal, such as the DQS signal, is used in the memory, the function of the mismatch compensation circuit described above can also be applied to the strobe signal.

[0091] Figure 8 A transmitting circuit of a semiconductor device according to an example embodiment is shown.

[0092] Reference Figure 8 The transmitting circuit 500 can receive binary signals bDQ[0] to bDQ[N-1] from the memory die through N TSVs TSV1 to TSVN. The transmitting circuit 500 can convert the binary signals bDQ[0] to bDQ[N-1] into multi-level signals sDQ[0] to sDQ[K-1] with M levels, and can output multi-level signals sDQ[0] to sDQ[K-1] through K data pins P1 to PK. Figure 8 The components shown can be included in the first physical layer circuit PHY1 of the first semiconductor device 210.

[0093] The transmitting circuit 500 may include a TSV buffer 510, an encoder 520, a second compensation circuit 530, a digital-to-analog converter (DAC) 540, and a driver 550.

[0094] TSV buffer 510 can receive binary signals bDQ[0] to bDQ[N-1] from the storage die through N TSV TSV1 to TSVN, and can buffer binary signals bDQ[0] to bDQ[N-1] and output the buffered signals to encoder 520.

[0095] The encoder 520 can convert binary signals bDQ[0] to bDQ[N-1] into multi-level signals with M levels.

[0096] The second compensation circuit 530 can receive multi-level signals and perform digital signal processing. For example, the second compensation circuit 530 can compensate for distortion in the channel through which data is to be transmitted, and can compensate for timing skew mismatch, offset mismatch, and gain mismatch between channels. (See reference...) Figure 9 The second compensation circuit 530 is described in detail.

[0097] The DAC 540 can include multiple DACs corresponding to multiple channels. The DAC 540 can convert digital signals into analog signals.

[0098] The driver 550 may include multiple driver DRVs and can transmit binary signals sDQ[0] to sDQ[K-1] to channels of the package substrate via K data pins P1 to PK.

[0099] Data pins P1 to PK can be connected to bumps mounted on the package substrate.

[0100] According to the example embodiment, the transmitting circuit 500 can transmit multi-level signals sDQ[0] to sDQ[K-1] to channels of the package substrate via data pins P1 to PK. In this case, in the example embodiment, the transmitting circuit 500 does not include the encoder 520.

[0101] Figure 9 A second compensation circuit according to an example embodiment is shown.

[0102] Reference Figure 9 The second compensation circuit 530 may include a precoding circuit 531, a transmission filter 532, and a second mismatch compensation circuit 533.

[0103] The precoding circuit 531 can encode data using a precoding matrix. Precoding refers to changing the data pattern to another pattern by encoding the data to be transmitted using a precoding matrix. For example, when there are too many "1"s, too many "0"s, or too many "1"s and "0"s switching in the data, the precoding circuit 531 can change the data pattern to another pattern.

[0104] For example, a data encoding method such as Data Bus Inversion (DBI) can be used. DBI is an I / O signal transmission technique that reduces DC power consumption by selectively inverting the data bus for systems where there is an asymmetry in power consumption between alternating signal transmission states. When a data bit is inverted, an additional signal called a DBI bit can be set to indicate that the data bit has been inverted. By sending pre-encoded data, the reliability of data transmission can be increased.

[0105] The transmission filter 532 can pre-compensate data based on channel state information and can transmit data. For example, the transmission filter 532 can be a finite impulse response (FIR) filter.

[0106] The second mismatch compensation circuit 533 can compensate for timing skew mismatch, offset mismatch, and gain mismatch between channels transmitting data signals. Aside from some differences, the second mismatch compensation circuit 533 of the transmitting circuit can operate on a similar principle to the first mismatch compensation circuit of the receiving circuit.

[0107] For example, in the case of timing skew mismatch between channels, the first mismatch compensation circuit of the receiving circuit uniformly matches the timing skew that has already occurred between the data signals, while the second mismatch compensation circuit 533 of the transmitting circuit artificially applies timing skew in advance, so that the receiving circuit can receive data signals simultaneously.

[0108] Figure 10 A high-bandwidth storage system according to an example embodiment is shown.

[0109] Reference Figure 10 The high-bandwidth storage system 600 may include multiple HBMs 610, a processor 620, a package substrate 630, and a motherboard 640. The multiple HBMs 610 may correspond to reference... Figures 2 to 9 The first semiconductor device is described. Processor 620 may correspond to a CPU, GPU, etc. Multiple HBMs 610s, processors 620s, and package substrates 630 can be configured as a single semiconductor package PA. The semiconductor package PA can be mounted on a motherboard 640 via external connection terminals.

[0110] Multiple HBM 610s and processors 620s can communicate with each other via channels provided by the signal lines of the package substrate 630. For example, multiple HBM 610s and processors 620s can communicate using multi-level signal transmission without intermediaries. Therefore, the manufacturing cost of the high-bandwidth memory system 600 can be reduced. Digital signal processing functions can be used to prevent or reduce poor SI environments and mismatches between different channels that may occur when using the signal lines of the package substrate 630. The digital signal processing functions can be implemented in the buffer die of the HBM 610.

[0111] As described above, according to the example embodiment, since the storage system includes digital signal processing capabilities, it has the effect of overcoming the poor signal integrity (SI) environment and mismatch between different channels that occur when communication is performed through wiring formed on a package substrate without intermediaries.

[0112] While the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept as defined by the appended claims.

Claims

1. A high-bandwidth storage system, comprising: Motherboard; as well as A semiconductor package, wherein the semiconductor package is coupled to the motherboard. The semiconductor package includes: A packaging substrate, which is mounted on the motherboard and includes signal lines that provide channels; A first semiconductor device, the first semiconductor device being mounted on the packaging substrate and including a first PHY circuit, the PHY being a physical layer; and A second semiconductor device, mounted on the packaging substrate and including a second PHY circuit, wherein... The first semiconductor device and the second semiconductor device exchange data signals with each other through the channel. The data signal is a multi-level signal with M levels, where M is a natural number greater than 2, and The first PHY circuit compensates for the distortion of the channels and the mismatch between the channels by performing digital signal processing.

2. The high-bandwidth storage system according to claim 1, wherein, The first semiconductor device includes a buffer die and at least one memory die stacked on the packaging substrate. The buffer die includes the first PHY circuit.

3. The high-bandwidth storage system according to claim 2, wherein, The first PHY circuit includes: ADC, which corresponds to the channel, wherein the ADC converts the data signal received from the second semiconductor device into a digital signal, the ADC being an analog-to-digital converter; A first compensation circuit, which compensates for distortion in the channels and for mismatch between the channels; and A decoder that converts the digital signal into a binary signal.

4. The high-bandwidth storage system according to claim 3, wherein, The first compensation circuit includes an equalizer that removes inter-symbol interference from the data signal.

5. The high-bandwidth storage system according to claim 3, wherein, The first compensation circuit includes a first mismatch compensation circuit, which compensates for timing skew mismatch, offset mismatch, and gain mismatch between the channels.

6. The high-bandwidth storage system according to claim 3, wherein, The first compensation circuit includes a clock and data recovery circuit, which uses the digital signal and an internal clock signal to recover the data and a clock synchronized with the data.

7. The high-bandwidth storage system according to claim 6, wherein, The clock and data recovery circuit outputs a clock synchronized with the data to the ADC and compensates for sampling timing mismatch between the channels based on the clock synchronized with the data.

8. The high-bandwidth storage system according to claim 1, wherein, The first PHY circuit includes: An encoder that converts a binary signal into the multi-level signal; A compensation circuit that compensates for distortion in the channel transmitting the multi-level signal and compensates for mismatch between the channels; and A digital-to-analog converter, corresponding to the channel, converts the multi-level signal into an analog signal. The analog signal is transmitted to the second semiconductor device through the channel.

9. The high-bandwidth storage system according to claim 8, wherein, The compensation circuit includes a precoding circuit that precodes the data and converts the data mode into another mode.

10. The high-bandwidth storage system according to claim 8, wherein, The compensation circuit includes a mismatch compensation circuit that compensates for timing skew mismatch, offset mismatch, and gain mismatch between the channels that transmit the multi-level signal.

11. A high-bandwidth storage system, comprising: A packaging substrate, the packaging substrate including signal lines providing channels; At least one first semiconductor device, the at least one first semiconductor device comprising a buffer die and a memory die stacked on the buffer die; A second semiconductor device, which exchanges data signals with the first semiconductor device through the channel; as well as A connection terminal that directly connects the at least one first semiconductor device and the second semiconductor device to the package substrate. The data signal is a multi-level signal with M levels, where M is a natural number greater than 2. The at least one first semiconductor device compensates for the distortion of the channel and compensates for the mismatch between the channels.

12. The high-bandwidth storage system according to claim 11, wherein, The buffer die includes: ADC, which corresponds to the channel, converts the data signal received from the second semiconductor device into a digital signal; ADC is an analog-to-digital converter. A first compensation circuit, which compensates for distortion in the channels and for mismatch between the channels; and The decoder decodes the digital signal into a binary signal. The binary signal is sent to the memory die.

13. The high-bandwidth storage system according to claim 12, wherein, The first compensation circuit includes an equalizer that removes inter-symbol interference from the data signal.

14. The high-bandwidth storage system according to claim 12, wherein, The first compensation circuit includes a first mismatch compensation circuit, which compensates for timing skew mismatch, offset mismatch, and gain mismatch between the channels.

15. The high-bandwidth storage system according to claim 12, wherein, The first compensation circuit includes a clock and data recovery circuit, which uses the digital signal and an internal clock signal to recover the data and a clock synchronized with the data.

16. The high-bandwidth storage system according to claim 15, wherein, The clock and data recovery circuit outputs a clock synchronized with the data to the ADC and compensates for sampling timing mismatch between the channels based on the clock synchronized with the data.

17. The high-bandwidth storage system according to claim 11, wherein, The buffer die includes: An encoder that converts a binary signal received from the storage die into the multi-level signal; A compensation circuit that compensates for distortion in the channel through which the multi-level signal is to be transmitted, and compensates for mismatch between the channels; and A digital-to-analog converter, corresponding to the channel, converts the multi-level signal into an analog signal. The analog signal is transmitted to the second semiconductor device through the channel.

18. A high-bandwidth storage system, comprising: A buffer die, comprising a transmitting circuit and a receiving circuit, wherein the transmitting circuit and the receiving circuit exchange data signals with a processor through a channel on a package substrate, wherein the data signals are multi-level signals having M levels, and M is a natural number greater than 2; and Storage dies are stacked on top of buffer dies and connected to the buffer dies via through electrodes. The receiving circuit of the buffer die includes: ADC, which corresponds to the channel, converts the multi-level signal received through the channel into a digital signal; ADC is an analog-to-digital converter. A first compensation circuit compensates for the distortion of the channels and the mismatch between the channels; A decoder that converts the digital signal into a binary signal; and A driver that outputs the binary signal to the through electrode.

19. The high-bandwidth storage system according to claim 18, wherein, The first compensation circuit includes: An equalizer that removes inter-symbol interference from the data signal; A first mismatch compensation circuit compensates for timing skew mismatch, offset mismatch, and gain mismatch between the channels; and A clock and data recovery circuit, which uses the digital signal and an internal clock signal to recover data and a clock synchronized with the data. The clock and data recovery circuit outputs a clock synchronized with the data to the ADC and compensates for sampling timing mismatch between the channels based on the clock synchronized with the data.

20. The high-bandwidth storage system according to claim 18, wherein, The transmitting circuit of the buffer die includes: An encoder that converts the binary signal received from the storage die into the multi-level signal; A second compensation circuit compensates for distortion in the channel transmitting the multi-level signal and compensates for mismatch between the channels; and A digital-to-analog converter, corresponding to the channel, converts the multi-level signal into an analog signal. The analog signal is sent to the processor through the channel.

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