Semiconductor integrated circuit device and method of operating the same

Abstract

The present invention relates to a semiconductor integrated circuit device and an operation method thereof. The semiconductor integrated circuit device according to an embodiment includes: a circuit under test; a pattern generator that provides input data to the circuit under test; a result comparator that compares output data of the circuit under test with expected value data and outputs a test result signal; and a control circuit that controls the pattern generator and the result comparator; the circuit under test and the result comparator are commonly connected to a first clock line, and the pattern generator and the control circuit are commonly connected to a second clock line different from the first clock line.

Description

[0001] Citation of Related Applications

[0002] This application is based on and claims the benefit of priority of a prior Japanese patent application No. 2021-011674 filed on January 28, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor integrated circuit device and an operation method thereof. Background Art

[0004] Conventionally, a built-in self-test (BIST) circuit has been used to test memory circuits such as static random access memory (SRAM), read-only memory (ROM), dynamic random access memory (DRAM), logic circuits such as random logic and processor logic, or analog circuits such as a phase-locked loop (PLL) and an AD / DA converter. Summary of the Invention

[0005] An embodiment of the present invention provides a semiconductor integrated circuit device and an operation method thereof that prevent test omissions in a BIST circuit.

[0006] The semiconductor integrated circuit device according to the embodiment includes: a circuit under test; a pattern generator that provides input data to the circuit under test; a result comparator that compares output data of the circuit under test with expected value data and outputs a test result signal; and a control circuit that controls the pattern generator and the result comparator; the circuit under test and the result comparator are commonly connected to a first clock line, and the pattern generator and the control circuit are commonly connected to a second clock line different from the first clock line.

[0007] One embodiment can provide a semiconductor integrated circuit device and an operation method thereof that prevent test omissions in a BIST circuit. Brief Description of the Drawings

[0008] Figure 1 It is a block diagram of a semiconductor integrated circuit device of a comparative example.

[0009] Figure 2 It is a circuit block diagram of a result comparator of a comparative example.

[0010] Figure 3A (a) to (g) are operation timing charts of a semiconductor integrated circuit device of a comparative example.

[0011] Figure 3B (a) to (g) are timing diagrams of the operation when a clock line of a circuit under test (DUT) in a semiconductor integrated circuit device of a comparative example fails.

[0012] Figure 4A is a circuit block diagram of a semiconductor integrated circuit device according to the first embodiment.

[0013] Figure 4B is a circuit block diagram of the result comparator according to the first embodiment.

[0014] Figure 5A (a) to (g) are timing diagrams when the semiconductor integrated circuit device according to the first embodiment operates normally.

[0015] Figure 5B (a) to (g) are timing diagrams of the operation when a clock line of a circuit under test (DUT) in a semiconductor integrated circuit device according to the first embodiment fails.

[0016] Figure 6A is a circuit block diagram of a semiconductor integrated circuit device according to the second embodiment.

[0017] Figure 6B is a circuit block diagram of the result comparator according to the second embodiment.

[0018] Figure 7A (a) to (h) are timing diagrams when the semiconductor integrated circuit device according to the second embodiment operates normally.

[0019] Figure 7B (a) to (h) are timing diagrams of the operation when a clock line of a circuit under test (DUT) in a semiconductor integrated circuit device according to the second embodiment fails.

[0020] Figure 8A is a circuit block diagram of a semiconductor integrated circuit device according to the third embodiment.

[0021] Figure 8B is a circuit block diagram of the result comparator according to the third embodiment.

[0022] Figure 9A (a) to (h) are timing diagrams when the semiconductor integrated circuit device according to the third embodiment operates normally.

[0023] Figure 9B (a) to (h) are timing diagrams of the operation when a clock line of a circuit under test (DUT) in a semiconductor integrated circuit device according to the third embodiment fails. Detailed implementation manners

[0024] Next, embodiments will be described with reference to the accompanying drawings. In the description of the specification or the drawings below, the same reference numerals are assigned to the same components and the description thereof is omitted. The drawings are schematic diagrams. In addition, the embodiments shown below illustrate devices and methods for embodying a technical idea. The embodiments can be variously modified within the scope of the claims. In the following description, "test omission of the BIST circuit" means that in a semiconductor integrated circuit device having a BIST circuit, the BIST circuit passes without being tested.

[0025] (Semiconductor integrated circuit device of the comparative example) Figure 1 It is a block diagram of the semiconductor integrated circuit device 1 of the comparative example.

[0026] As Figure 1 shown, the semiconductor integrated circuit device 1 includes a circuit under test (DUT: Device Under Test) 8 and a BIST circuit 6. The BIST circuit 6 includes a pattern generator 10, a control circuit 12, and a result comparator 14. The clock control unit (CT) 18 of the semiconductor integrated circuit device 1 controls the first clock CLK1 commonly input to the circuit under test 8 and the result comparator 14 included in the BIST circuit 6, and the clock control unit (CB) 20 controls the second clock CLK2 commonly input to the pattern generator 10 and the control circuit 12 included in the BIST circuit 6. Test judgment is made based on two signals, namely, the pass / fail determination signal, i.e., the test result signal TRS, and the test end signal TES. The test result signal TRS is a signal indicating whether there is a problem with the circuit under test. The test end signal TES is a signal indicating whether the test has been executed to the end.

[0027] The control circuit 12 is a circuit that controls the circuit under test 8, the pattern generator 10, and the result comparator 14 during the execution of BIST. In addition, a monitor terminal MTR can be connected to the control circuit 12, and the monitor terminal MTR is used to observe signals from the result comparator 14 such as the test end signal TES and the test result signal TRS. The result comparator 14 outputs the test result signal TRS. When the test ends, the control circuit 12 determines that the circuit under test 8 has no problem when the test result signal TRS is at a low level L, and determines that the circuit under test 8 has a problem when the test result signal TRS is at a high level H.

[0028] The pattern generator 10 is a circuit for generating input data DI input to the circuit under test 8.

[0029] In the semiconductor integrated circuit device 1, a clock signal CLK1 is supplied to the circuit under test 8 and the result comparator 14, and a second clock signal CLK2 is supplied to the pattern generator 10 and the control circuit 12 via a line different from the first clock signal CLK1. The first clock signal CLK1 and the second clock signal CLK2 may have the same timing.

[0030] The first clock signal CLK1 and the input data DI are supplied to the circuit under test 8. The output data DO of the circuit under test 8 is supplied to the result comparator 14. The test result signal TRS is supplied from the result comparator 14 to the control circuit 12.

[0031] Figure 2 is a circuit block diagram of the result comparator 14. The result comparator 14 includes: an expected value comparison circuit 22 that can be connected to the circuit under test 8; an OR gate 24 connected to the expected value comparison circuit 22; and a result storage circuit 26 connected to the OR gate 24, with an initial value of low level L(0). The result storage circuit 26 has a configuration of a flip-flop circuit such as a D-type flip-flop, for example.

[0032] The expected value comparison circuit 22 compares the output data DO of the circuit under test 8 with the expected value data EV. When the two are the same, it outputs a low level L(0) as the expected value comparison data EO. When the two are different, it outputs a high level H(1) as the expected value comparison data EO. The expected value comparison data EO is input to the OR gate 24.

[0033] The output of the OR gate 24 is input to the result storage circuit 26. In addition, the result storage circuit 26 outputs the test result signal TRS while being input with the clock signal CLK1. The output of the OR gate 24 is the OR output of the expected value comparison data EO and the test result signal TRS.

[0034] Figure 3A is an operation timing chart of the semiconductor integrated circuit device 1. Figure 3B is an operation timing chart when a failure occurs in the first clock line of the circuit under test 8.

[0035] In Figure 3A and Figure 3B , (a) represents the input data DI, (b) represents the clock signal CLK1, (c) represents the output data DO, (d) represents the expected value data EV, (e) represents the clock signal CLK2, (f) represents the test result signal TRS, and (g) represents the test end signal TES.

[0036] (When the result comparator operates normally and there is no problem with the circuit under test 8) (Operation timing chart: Figure 3A)In the result comparator 14, the output data DO is compared with the expected value data EV every timing of the first clock signal CLK1. During the period when the output data DO of the circuit under test 8 is consistent with the expected value data EV, the test result signal TRS continuously maintains the low level L as shown by the solid line. The test end signal TES maintains the low level L during the test process, but changes from the low level L to the high level H after the test ends. Here, the control circuit 12 determines whether there is a problem with the circuit under test 8. Since the test result signal TRS is at the low level L, it is determined that there is no problem with the circuit under test 8.

[0037] (When the result comparator operates normally and there is a problem with the circuit under test 8) (Operation timing diagram: Figure 3A )During the period when the output data DO of the circuit under test 8 is consistent with the expected value data EV, the test result signal TRS continuously outputs the low level L. For example, it is within the range shown by the dotted line A in Figure 3A . When comparing the output data DO with the expected value data EV, if the output data DO of the circuit under test 8 is inconsistent with the expected value data EV and fails halfway, the test result signal TRS becomes the high level H as shown by the dotted line and continuously maintains the high level H. The test end signal TES maintains the low level L during the test process and changes from the low level L to the high level H after the test ends. Here, the control circuit 12 determines whether there is a problem with the circuit under test 8. Since the test result signal TRS is at the high level H, it is determined that there is a problem with the circuit under test 8.

[0038] (When the result comparator does not operate normally) (When a fault occurs in the clock line: Figure 3B )When a fault occurs in the clock line for the circuit under test 8, as shown in Figure 3B (b), the clock signal CLK1 for the circuit under test 8 becomes the low level L. Similarly, as shown in Figure 3B (b), the first clock signal CLK1 for the result comparator 14 becomes the low level L. The circuit under test 8 stops operating. As a result, even if the output data DO is inconsistent with the expected value data EV, since the result comparator 14 also does not operate, the test result signal TRS continuously maintains the initial value, that is, the low level L. Consequently, although there is a problem with the circuit under test 8, it is still determined that there is no problem with the circuit under test 8. That is, although the test is not performed normally, it is still considered that the test has been completed, resulting in a test omission.

[0039] (First Embodiment) Figure 4A A circuit block diagram showing the semiconductor integrated circuit device 2 of the first embodiment. Figure 4B It is a circuit block diagram of the result comparator 141 of the first embodiment.

[0040] The semiconductor integrated circuit device 2 can also use the result comparator 141 to replace the result comparator 14 of the comparative example. A test result signal TRS1 is output from the result comparator 141.

[0041] As Figure 4B shown, the result comparator 141 of the first embodiment includes: an expected value comparison circuit 22 that can be connected to the circuit under test 8; an OR gate 24 connected to the expected value comparison circuit 22; a result storage circuit 26 connected to the OR gate 24 and having an initial value set to a low level L(0); and an additional circuit 28 connected to the result storage circuit 26 and having an initial value set to a high level H(1). The result storage circuit 26 and the additional circuit 28 may have a configuration of a flip-flop circuit such as a D-type flip-flop.

[0042] The output of the result storage circuit 26, that is, the test result signal TRS, is input to the additional circuit 28. In addition, while the additional circuit 28 is input with the clock signal CLK1, it outputs the test result signal TRS1 to the BIST circuit 6. The control circuit 12 determines that there is no problem with the circuit under test 8 and the test proceeds normally when the test result signal TRS1 is at a low level L(0), and determines that there is a problem with the circuit under test 8 or the test does not proceed normally when the test result signal TRS1 is at a high level H(1).

[0043] Figure 5A is a timing diagram when the semiconductor integrated circuit device applying the result comparator of the first embodiment operates normally. Figure 5B is a timing diagram of the operation when a fault occurs in the clock line of the circuit under test 8 and the result comparator 141 in the semiconductor integrated circuit device applying the result comparator of the first embodiment.

[0044] In Figure 5A and Figure 5B , (a) represents the input data DI, (b) represents the clock signal CLK1, (c) represents the output data DO, (d) represents the expected value data EV, (e) represents the clock signal CLK2, (f) represents the test result signal TRS1, and (g) represents the test end signal TES.

[0045] (When the result comparator operates normally and there is no problem with the circuit under test 8)(Timing diagram: Figure 5A)The result comparator 141 first outputs an initial value H according to the test result signal TRS1. After the test starts, when the output data DO of the circuit under test 8 is consistent with the expected value data EV, it receives the low level L of the result storage circuit 26, the state of the addition circuit 28 switches to L, and the test result signal TRS1 outputs the low level L. After that, during the period when the output data DO of the circuit under test 8 is consistent with the expected value data EV, the test result signal TRS1 continuously stores the low level L as shown by the solid line. The test end signal TES stores the low level L during the test process, but changes from the low level L to the high level H after the test ends. Here, the control circuit 12 determines whether there is a problem with the circuit under test 8 or whether the test is proceeding normally. Since the test result signal TRS1 is at the low level L at the end of the test, it is determined that the circuit under test 8 has no problem and passes the test.

[0046] (When the result comparator operates normally and there is a problem with the circuit under test 8)(Operation timing diagram: Figure 5A )During the period when the output data DO of the circuit under test 8 is consistent with the expected value data EV, the test result signal TRS1 continuously stores the low level L. For example, it is in the Figure 5A range shown by the dotted line A. However, when there is a defect in the circuit under test 8 and the output data DO of the circuit under test 8 becomes inconsistent with the expected value data EV, the test result signal TRS1 becomes the high level H as shown by the dotted line and continuously stores this high level H. The test end signal TES stores the low level L during the test process, but changes from the low level L to the high level H after the test ends. Here, the control circuit 12 determines whether there is a problem with the circuit under test 8 or whether the test is proceeding normally. Since the test result signal TRS1 is at the high level H at the end of the test, it is determined that there is a problem with the circuit under test 8 or the test is not proceeding normally and the test fails.

[0047] (When the result comparator does not operate normally)(When there is a fault in the clock line: Figure 5B )When a fault occurs in the clock line CLK1 for the circuit under test 8, as Figure 5B (b) shows, the clock signal CLK1 for the circuit under test 8 becomes the low level L. Similarly, as Figure 5B (b) shows, the clock signal CLK1 for the result comparator 141 becomes the low level L. Both the circuit under test 8 and the result comparator 141 stop operating, so the test result signal TRS1 from the result comparator 141 continuously outputs the initial value 1 of the addition circuit 28, that is, the high level H. The test end signal TES stores the low level L during the test process, but changes from the low level L to the high level H after the test ends. Here, the control circuit 12 determines whether there is a problem with the circuit under test 8 or whether the test is proceeding normally. Since the test result signal TRS1 is at the high level H at the end of the test, it is determined that there is a problem with the circuit under test 8 or the test is not proceeding normally and the test fails.

[0048] (Effect of the First Embodiment) In the first embodiment, even when a failure occurs in the clock line CLK1 of the circuit 8 under test, it can be determined that there is a problem with the circuit 8 under test or the test is not performed normally. Therefore, it is possible to prevent omission of the test.

[0049] (Second Embodiment) Figure 6A A circuit diagram showing the semiconductor integrated circuit device 3 of the second embodiment. Figure 6B A circuit diagram of the result comparator 142 of the second embodiment.

[0050] The semiconductor integrated circuit device 3 uses the result comparator 142 instead of the result comparator 141 of the first embodiment. A test result signal TRS and an additional circuit output signal TIS are output from the result comparator 142.

[0051] As Figure 6B shown, the result comparator 142 of the second embodiment includes: an expected value comparison circuit 22 that can be connected to the circuit 8 under test; an OR gate 24 connected to the expected value comparison circuit 22; a result storage circuit 26 connected to the OR gate 24 and having an initial value of low level L (0); and an additional circuit 30 arranged side by side with the result storage circuit 26 and having an initial value set to 0. An inverted signal FV (fixed value) of the initial value of the result storage circuit 26 may be input to the additional circuit 30.

[0052] The output of the OR gate 24 is input to the result storage circuit 26. In addition, the result storage circuit 26 outputs a test result signal TRS while being input with a clock signal CLK1. The output of the OR gate 24 is an OR output of the expected value comparison data EO and the test result signal TRS.

[0053] An inverted signal FV (fixed value) of the initial value 0 of the result storage circuit 26 is input to the additional circuit 30, and then its value is latched and output as the additional circuit output signal TIS.

[0054] Similar to the result storage circuit 26, the additional circuit 30 may also have a configuration of a flip-flop circuit such as a D-type flip-flop. The control circuit 12 determines that there is no problem with the circuit 8 under test and the test is performed normally when the test result signal TRS is at low level L and the additional circuit output signal TIS is at high level H, determines that there is a problem with the circuit 8 under test but the test is performed normally when the test result signal TRS is at high level H and the additional circuit output signal TIS is at high level H, and determines that the test is not performed normally when the additional circuit output signal TIS is at low level L.

[0055] Figure 7AIt is a timing chart when the semiconductor integrated circuit device 3 applying the result comparator 142 of the second embodiment operates normally. Figure 7B It is an operation timing chart when a failure occurs in the clock lines for the circuit under test 8 and the result comparator 142 in the semiconductor integrated circuit device 3 applying the result comparator 142 of the second embodiment.

[0056] In Figure 7A and Figure 7B , (a) represents the input data DI, (b) represents the clock signal CLK1, (c) represents the output data DO, (d) represents the expected value data EV, (e) represents the clock signal CLK2, (f) represents the test result signal TRS, (g) represents the test end signal TES, and (h) represents the additional circuit output signal TIS.

[0057] (When the result comparator operates normally and there is no problem with the circuit under test 8) (Operation timing chart: Figure 7A ) After the start of the test, the result comparator 142 inputs a high-level H (1), which is the inverted signal of the initial value 0, to the additional circuit 30, and then continuously outputs this value as the additional circuit output signal TIS. When the output data DO of the circuit under test 8 is consistent with the expected value data EV, the result storage circuit 26 outputs a low-level L as the test result signal TRS, and then during the period when the output data DO of the circuit under test 8 is consistent with the expected value data EV, the test result signal TRS continuously stores the low-level L as shown by the solid line. The test end signal TES stores the low-level L during the test process, but changes from the low-level L to the high-level H after the test ends. Here, the control circuit 12 determines whether there is a problem with the circuit under test 8 or whether the test is proceeding normally. At the end of the test, since the test result signal TRS is at the low level L and the additional circuit output signal TIS is at the high level H, it is determined that there is no problem with the circuit under test 8 and the test is proceeding normally and passes.

[0058] (When the result comparator operates normally and there is a problem with the circuit under test 8) (Operation timing chart: Figure 7A ) After the start of the test, the result comparator 142 inputs a high-level H (1), which is the inverted signal of the initial value 0, to the additional circuit 30, and then continuously outputs this value as the additional circuit output signal TIS. During the period when the output data DO of the circuit under test 8 is consistent with the expected value data EV, the test result signal TRS continuously stores the low-level L. For example, in Figure 7AThe range shown by the dashed line A. However, when a defect occurs in the circuit under test 8 and the output data DO of the circuit under test 8 becomes inconsistent with the expected value data EV, the test result signal TRS becomes high level H as shown by the dashed line and the high level H is continuously saved. The test end signal TES saves the low level L during the test, but changes from the low level L to the high level H after the test ends. Here, the control circuit 12 determines whether there is a problem with the circuit under test 8 or whether the test is being performed normally. At the end of the test, the test result signal TRS is at high level H and the additional circuit output signal TIS is at high level H, so it is determined that there is a problem with the circuit under test 8 but the test is being performed normally and the determination fails.

[0059] (When the result comparator does not operate properly) (When a fault occurs in the clock line: Figure 7B ) As Figure 7B (b) shows, when a fault occurs in the clock line of the circuit under test 8, the clock signal CLK1 for the circuit under test 8 is always at low level L. Similarly, as Figure 7B (b) shows, the clock signal CLK1 for the result comparator 142 also becomes low level L. The circuit under test 8 and the result comparator 142 both stop operating, so the additional circuit output signal TIS from the result comparator 142 continuously outputs the initial value 0 of the additional circuit 30, that is, low level L. The test result signal TRS also continuously outputs the initial value 0 of the result storage circuit 26, that is, low level L. The test end signal TES saves the low level L during the test, but changes from the low level L to the high level H after the test ends. Here, the control circuit 12 determines whether there is a problem with the circuit under test 8 or whether the test is being performed normally. At the end of the test, the additional circuit output signal TIS is at low level L, so regardless of the value of the test result signal TRS, it is determined that the test is not being performed normally and the determination is a failure.

[0060] (Effect of the second embodiment) In the first embodiment, even when the determination is a failure, it is possible to distinguish whether there is a problem with the circuit under test 8 or whether the test is not being performed normally. In this embodiment, even when the determination is a failure, it is possible to distinguish whether there is a problem with the circuit under test 8 or whether the test itself is not being performed normally.

[0061] (Third embodiment) Figure 8A The circuit block diagram showing the semiconductor integrated circuit device 4 of the third embodiment. Figure 8B It is the circuit block diagram of the result comparator 143 of the third embodiment.

[0062] The semiconductor integrated circuit device 4 uses the result comparator 143 to replace the result comparator 141 of the first embodiment and the result comparator 142 of the second embodiment. The test result signal TRS and the additional circuit output signal TIS are output from the result comparator 143.

[0063] As Figure 8B shown, the result comparator 143 of the third embodiment includes: an expected value comparison circuit 22 that can be connected to a device under test (DUT) 8; an additional circuit 32 connected to the expected value comparison circuit 22 and initially set to a high level H (1); an additional circuit 34 with an initial value of a low level L (0); an AND gate 36 connected to the additional circuit 32 and the additional circuit 34; an OR gate 38 connected to the AND gate 36; and a result storage circuit 40 connected to the OR gate 38 and initially set to a low level L (0). The output of the result storage circuit 40 is also connected to the OR gate 38. The additional circuit 34 is input with a high level H (1) after the start of the test. The additional circuit 32, the additional circuit 34, and the result storage circuit 40 are configured with flip-flop circuits such as D-type flip-flops, for example. A clock signal CLK1 is input to the additional circuit 32, the additional circuit 34, and the result storage circuit 40.

[0064] The expected value comparison circuit 22 compares the output data DO of the device under test 8 with the expected value data EV and outputs expected value comparison data EO. The expected value comparison data EO is input to the additional circuit 32.

[0065] The output of the additional circuit 32 is input to the AND gate 36. The output of the additional circuit 34 is also input to the AND gate 36. That is, the AND gate 36 outputs the logical product of the expected value comparison data EO and the output of the additional circuit 34. The additional circuit 34 also outputs an additional circuit output signal TIS. Observing the additional circuit output signal TIS can determine the operation state of the result comparator 143. When the test starts normally, the additional circuit output signal TIS changes from a low level L (0) to a high level H (1).

[0066] The output of the additional circuit 34 is input to the AND gate 36. The output of the AND gate 36 is input to the OR gate 38. The output of the OR gate 38 is input to the result storage circuit 40. The result storage circuit 40 outputs a test result signal TRS while being input with the clock signal CLK1. The test result signal TRS is also input to the OR gate 38. That is, the output of the OR gate 38 is the OR output of the output of the AND gate 36 and the test result signal TRS.

[0067] The control circuit 12 determines that the device under test 8 is okay and the test is proceeding normally when the test result signal TRS is at a low level L and the additional circuit output signal TIS is at a high level H, determines that the device under test 8 has a problem but the test is proceeding normally when the test result signal TRS is at a high level H and the additional circuit output signal TIS is at a high level H, and determines that the test is not proceeding normally when the additional circuit output signal TIS is at a low level L.

[0068] Figure 9A This is a timing diagram when the semiconductor integrated circuit device using the result comparator of the third embodiment operates normally. Figure 9B This is the operation timing diagram when a fault occurs in the clock line of the circuit under test 8.

[0069] In Figure 9A and Figure 9B , (a) represents the input data DI, (b) represents the clock signal CLK1, (c) represents the output data DO, (d) represents the expected value data EV, (e) represents the clock signal CLK2, (f) represents the test result signal TRS, (g) represents the test end signal TES, and (h) represents the additional circuit output signal TIS.

[0070] (When the result comparator operates normally and there is no problem with the circuit under test 8) (Operation timing diagram: Figure 9A ) After the start of the test, the result comparator 143 inputs a high level H(1) to the additional circuit 34 at the dotted line D, and then continuously outputs this value as the additional circuit output signal TIS. When the output data DO of the circuit under test 8 is consistent with the expected value data EV, the expected value comparison circuit 22 outputs a low level L, and the additional circuit 32 becomes a low level L. The high level H output from the additional circuit 34 and the low level L output from the additional circuit 32 are input to the AND circuit 36. The output of the AND circuit 36 becomes a low level L and is input to the OR circuit 38. The output from the result storage circuit 40 with an initial value of low level L is input to the OR circuit 38. As a result, the output of the OR circuit 38 becomes a low level L and is input to the result storage circuit 40. In this way, during the period when the output data DO of the circuit under test 8 is consistent with the expected value data EV, the test result signal TRS from the result storage circuit 40 continuously stores the low level L as shown by the solid line. The test end signal TES stores the low level L during the test process, but changes from the low level L to the high level H after the test ends. Here, the control circuit 12 determines whether there is a problem with the circuit under test 8 or whether the test is proceeding normally. At the end of the test, since the test result signal TRS is at a low level L and the additional circuit output signal TIS is at a high level H, it is determined that there is no problem with the circuit under test 8 and the test proceeds normally and passes.

[0071] (When the result comparator operates normally and there is a problem with the circuit under test 8) (Operation timing diagram: Figure 9A)After the test starts, the result comparator 143 inputs a high level H (1) to the append circuit 34, and then continuously outputs this value as the append circuit output signal TIS. When the output data DO of the circuit under test 8 is consistent with the expected value data EV, the expected value comparator circuit 22 outputs a low level L, and the append circuit 32 becomes a low level L. The high level H output from the append circuit 34 and the low level L output from the append circuit 32 are input to the AND circuit 36. The output of the AND circuit 36 becomes a low level L and is input to the OR circuit 38. The output from the result storage circuit 40 with an initial value of low level L is input to the OR circuit 38. As a result, the output of the OR circuit 38 becomes a low level L and is input to the result storage circuit 40. In this way, during the period when the output data DO of the circuit under test 8 is consistent with the expected value data EV, the test result signal TRS from the result storage circuit 40 continuously stores the low level L. For example, it is within the range shown by the dashed line A in Figure 9A . However, there is a problem with the circuit under test 8. When the output data DO of the circuit under test 8 becomes inconsistent with the expected value data EV, the output from the expected value comparator circuit 22 becomes a high level H. The value of the append circuit 32 becomes a high level H. As a result, the output of the AND circuit 36 becomes a high level H, and the output of the OR circuit 38 also becomes a high level H. The result storage circuit 40 also becomes a high level H, and then the test result signal TRS becomes a high level H as shown by the dashed line and continuously stores this high level H. The test end signal TES stores a low level L during the test process, but changes from a low level L to a high level H after the test ends. Here, the control circuit 12 determines whether there is a problem with the circuit under test 8 or whether the test is proceeding normally. At the end of the test, the test result signal TRS is a high level H and the append circuit output signal TIS is a high level H. Therefore, it is determined that there is a problem with the circuit under test 8 but the test is proceeding normally and it is determined as a failure.

[0072] (When the result comparator does not operate properly) (When a fault occurs in the clock line: Figure 9B )As Figure 9B (b) shows, when a fault occurs in the clock line of the circuit under test 8, the clock signal CLK1 for the circuit under test 8 becomes a low level L. The append circuit output signal TIS continuously outputs the initial value of the append circuit 34, which is a low level L. The test result signal TRS continuously outputs the initial value of the result storage circuit 40, which is a low level L. The test end signal TES stores a low level L during the test process, but changes from a low level L to a high level H after the test ends. Here, the control circuit 12 determines whether there is a problem with the circuit under test 8 or whether the test is proceeding normally. At the end of the test, the append circuit output signal TIS is a low level L. Therefore, regardless of the value of the test result signal TRS, it is determined that the test is not proceeding normally and it is determined as a failure.

[0073] (Effects of the Third Embodiment) According to this embodiment, the same effects as those of the second embodiment can also be obtained.

[0074] Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their variations are included in the scope and gist of the invention, and similarly included in the invention described in the claims and its equivalents.

Claims

1. A semiconductor integrated circuit device, comprising: a circuit under test; a pattern generator that provides input data to the circuit under test; a result comparator that compares the output data of the circuit under test with expected value data and outputs a test result signal; and a control circuit that controls the pattern generator and the result comparator; the circuit under test and the result comparator are commonly connected to a first clock line, and the pattern generator and the control circuit are commonly connected to a second clock line different from the first clock line; and when the test result signal is a first signal at the end of the test, the control circuit determines that the test is passed, when the test result signal is a second signal at the end of the test, the control circuit determines that the test is failed; the result comparator includes: an expected value comparison circuit that compares the output data with the expected value data and outputs expected value comparison data; a result storage circuit connected to the subsequent stage of the expected value comparison circuit and outputs a test result signal; and a second additional circuit that outputs an additional circuit output signal; the initial state of the second additional circuit is a state that generates the first signal, when the additional circuit output signal is the second signal after the test ends, the control circuit determines that the test is proceeding normally, when the additional circuit output signal is the first signal after the test ends, the control circuit determines that the test is not proceeding normally.

2. The semiconductor integrated circuit device according to claim 1, further comprising an OR circuit, wherein the OR circuit receives the output of the result storage circuit and the output of the expected value comparison circuit and inputs the output to the result storage circuit.

3. The semiconductor integrated circuit device according to claim 1, wherein, The initial state of the result storage circuit is a state that generates the first signal.

4. The semiconductor integrated circuit device according to any one of claims 1 to 3, wherein, The control circuit includes a monitor terminal for observing the test result signal.

5. A semiconductor integrated circuit device, comprising: a circuit under test; a pattern generator that provides input data to the circuit under test; a result comparator that compares the output data of the circuit under test with expected value data and outputs a test result signal; and a control circuit that controls the pattern generator and the result comparator; the circuit under test and the result comparator are commonly connected to a first clock line, and the pattern generator and the control circuit are commonly connected to a second clock line different from the first clock line; and when the test result signal is a first signal at the end of the test, the control circuit determines that the test is passed, when the test result signal is a second signal at the end of the test, the control circuit determines that the test is failed; the result comparator includes: an expected value comparison circuit that compares the output data with the expected value data and outputs expected value comparison data; a third additional circuit connected to the subsequent stage of the expected value comparison circuit; a fourth additional circuit that outputs an additional circuit output signal; and a result storage circuit arranged in the subsequent stage of the third additional circuit and outputs a test result signal; the initial state of the fourth additional circuit is a state that generates the first signal, and it is input with the second signal after the start of the test, When the output signal of the additional circuit is the second signal after the test ends, the control circuit determines that the test is proceeding normally. When the output signal of the additional circuit is the first signal after the test ends, the control circuit determines that the test is not proceeding normally.

6. The semiconductor integrated circuit device according to claim 5, comprising: an AND circuit to which the output of the third additional circuit and the output of the fourth additional circuit are input; and an OR circuit to which the output of the result storage circuit and the output of the AND circuit are input, and the output of which is input to the result storage circuit.

7. The semiconductor integrated circuit device according to claim 5 or 6, wherein The control circuit includes a monitor terminal for observing the test result signal.

8. An operation method of a semiconductor integrated circuit device, comprising: a pattern generator providing input data to a circuit under test; a result comparator comparing the output data of the circuit under test with expected value data and outputting a test result signal; a control circuit controlling the pattern generator and the result comparator; the circuit under test and the result comparator are commonly connected to a first clock line, and the pattern generator and the control circuit are commonly connected to a second clock line different from the first clock line; the test result signal is determined to pass when it is the first signal at the end of the test; the test result signal is determined to fail when it is the second signal at the end of the test; an expected value comparison circuit of the result comparator compares the output data with the expected value data and outputs expected value comparison data; a result storage circuit of the result comparator is connected to the subsequent stage of the expected value comparison circuit and outputs a test result signal; a second additional circuit of the result comparator outputs an additional circuit output signal; the initial state of the second additional circuit is a state that generates the first signal; when the additional circuit output signal is the second signal after the test ends, the control circuit determines that the test is proceeding normally; when the additional circuit output signal is the first signal after the test ends, the control circuit determines that the test is not proceeding normally.

Images