A single-double track hybrid circuit system of NCL and its operation logic unit

Abstract

This invention discloses a hybrid single- and dual-track NCL circuit system and its operational logic unit. In the hybrid NCL circuit system, the output of the first NCL register is connected to the input of a dual-track to single-track converter, the output of the dual-track to single-track converter is connected to the input of a synchronous combinational logic circuit, the output of the synchronous combinational logic circuit is connected to the input of a single-track to dual-track converter, and the output of the single-track to dual-track converter is connected to the input of the second NCL register. The hybrid NCL circuit system and its operational logic unit in this invention, by employing single-track encoding between the two dual-track NCL registers, combine the advantages of small area overhead and low power consumption of single-track encoding circuits with the advantages of high speed and low latency of dual-track encoding circuits. This significantly reduces the area of ​​the NCL circuit and further reduces power consumption. This invention has wide applications in the field of integrated circuit technology.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a single-dual rail hybrid circuit system of NCL and an operation logic unit thereof. BACKGROUND

[0002] Compared with synchronous circuits, asynchronous circuits have advantages of no clock offset, low power consumption and low delay. Asynchronous circuits use data encoding and handshake protocols for communication. The handshake protocol methods include four-phase handshake protocol and two-phase handshake protocol. The two-phase handshake protocol is based on event triggering, and the request and response of the control signal are represented by rising edge or falling edge, and the 1-0 and 0-1 flips in the encoding are not distinguished, which is also called non-return-to-zero (NRZ) protocol. The four-phase handshake protocol is based on voltage level triggering, and only high level represents the request and response of the control signal, and the control signal has a return-to-zero (RTZ) action, which is also called return-to-zero (RTZ) protocol; RTZ represents that the request and confirmation signal needs to return 0 signal, and NRZ does not need to return 0 signal. Data encoding includes dual rail encoding and single rail encoding, and dual rail encoding needs two lines to represent one bit of data, and the data includes 00, 01, 10 and 11, and dual rail encoding 11 is invalid data. Single rail encoding needs one line to represent one bit of data (1 and 0). The area of the dual rail circuit is 1.5-2 times that of the single rail circuit, and compared with the dual rail circuit, the single rail circuit has advantages in circuit area and power consumption, but the data transmission delay of the single rail circuit is larger than that of the dual rail circuit, which is easy to cause signal distortion and other negative effects. SUMMARY

[0003] In view of the technical problems that the current dual rail circuit and single rail circuit cannot balance small circuit area, low power consumption and low data transmission delay, the purpose of the present application is to provide a single-dual rail hybrid circuit system of NCL and an operation logic unit thereof.

[0004] In one aspect, the embodiment of the present application includes a single-dual rail hybrid circuit system of NCL, which comprises a first NCL register, a dual rail-single rail converter, a synchronous combination logic circuit, a single rail-dual rail converter and a second NCL register; the dual rail-single rail converter is used to convert input dual rail data into single rail data, and the single rail-dual rail converter is used to convert input single rail data into dual rail data.

[0005] The output end of the first NCL register is connected with the input end of the dual rail-single rail converter, the output end of the dual rail-single rail converter is connected with the input end of the synchronous combination logic circuit, the output end of the synchronous combination logic circuit is connected with the input end of the single rail-dual rail converter, and the output end of the single rail-dual rail converter is connected with the input end of the second NCL register.

[0006] Further, the double rail to single rail converter comprises a first inverter and an AND gate, an input end of the first inverter and one input end of the AND gate serving as an input end of the double rail to single rail converter, the input end of the first inverter being connected with another input end of the AND gate, and an output end of the AND gate serving as an output end of the double rail to single rail converter.

[0007] Further, the single rail to double rail converter comprises a second inverter and a buffer, an input end of the second inverter and an input end of the buffer being connected and serving as an input end of the single rail to double rail converter, an output end of the second inverter and an output end of the buffer serving as an output end of the single rail to double rail converter.

[0008] Further, the synchronous combinational logic circuit is used to perform at least one of the following operations on the input data: AND operation, OR operation, XOR operation, NOT operation, left shift operation, right shift operation, addition operation, subtraction operation.

[0009] Further, the synchronous combinational logic circuit is a transmission gate structure.

[0010] Further, the first NCL register and the second NCL register can work in a transmission phase, a holding phase and a reset phase; in the transmission phase, double rail data is transmitted, in the holding phase, the current double rail data is kept unchanged, and in the reset phase, 0 is outputted.

[0011] Further, the single / double rail hybrid circuit system of the NCL further comprises an output completion detection circuit, an input end of the output completion detection circuit being connected with a data end of the second NCL register, an output end of the output completion detection circuit being connected with a data end of the first NCL register, the output completion detection circuit being used to prevent the second NCL register from requesting the first NCL register to send a null signal before receiving all data sent by the first NCL register, and to prevent the second NCL register from requesting the first NCL register to send data before receiving all null signals sent by the first NCL register.

[0012] In another aspect, the embodiments of the present application also include a single-rail hybrid ALU of NCL, which comprises a 9-bit dual-rail register, a 3-bit dual-rail register, a 5-bit dual-rail register, a first output completion detection circuit, a second output completion detection circuit, a first dual-rail to single-rail converter, a second dual-rail to single-rail converter, a third dual-rail to single-rail converter, a first single-rail to dual-rail converter, a second single-rail to dual-rail converter, a logic operation circuit, and a carry logic circuit.

[0013] The first output completion detection circuit is connected with the 9-bit dual-rail register and the 3-bit dual-rail register respectively.

[0014] The second output completion detection circuit is connected with the 9-bit dual-rail register, the 3-bit dual-rail register, and the 5-bit dual-rail register respectively.

[0015] The 9-bit dual-rail register is connected with the first dual-rail to single-rail converter.

[0016] The first dual-rail to single-rail converter is connected with the logic operation circuit.

[0017] The logic operation circuit is connected with the first single-rail to dual-rail converter and the second single-rail to dual-rail converter respectively.

[0018] The first single-rail to dual-rail converter is connected with the 5-bit dual-rail register through the second dual-rail to single-rail converter.

[0019] The second single-rail to dual-rail converter is connected with the third dual-rail to single-rail converter.

[0020] The carry logic circuit is connected with the 9-bit dual-rail register, the 3-bit dual-rail register, the 5-bit dual-rail register, and the third dual-rail to single-rail converter respectively.

[0021] Further, the logic operation circuit is used for performing AND operation, OR operation, XOR operation, NOT operation, left shift operation, right shift operation, addition operation, and subtraction operation on input data.

[0022] Further, the single-rail hybrid ALU of NCL also comprises an 8-track converter, which is connected with the 3-bit dual-rail register and the first dual-rail to single-rail converter respectively, and is used for controlling the logic operation circuit to select a logic operation to be performed.

[0023] The beneficial effects of the present application are: the single-rail and dual-rail hybrid circuit system and the single-rail and dual-rail hybrid ALU of the NCL in the embodiments have the advantages of small area overhead and low power consumption of the single-rail encoding circuit and the advantages of high speed and low time delay of the dual-rail encoding circuit by using the single-rail encoding form between two dual-rail NCL registers, the area of the NCL circuit is obviously reduced, and the power consumption is further reduced. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 The principle schematic diagram of the handshake protocol and the dual-rail encoding in the embodiments;

[0025] Figure 2 The structure schematic diagram of the NCL dual-rail pipeline system in the embodiments;

[0026] Figure 3 The structure schematic diagram of the 4-bit dual-rail non-pipeline ALU in the embodiments;

[0027] Figure 4 The structure schematic diagram of the single-rail and dual-rail hybrid circuit system of the NCL in the embodiments;

[0028] Figure 5 The structure schematic diagram of the dual-rail to single-rail converter in the embodiments;

[0029] Figure 6 The structure schematic diagram of the single-rail to dual-rail converter in the embodiments;

[0030] Figure 7 The structure schematic diagram of the single-rail and dual-rail hybrid ALU of the NCL in the embodiments;

[0031] Figure 8 The layout of the 4-bit dual-rail non-pipeline ALU in the embodiments;

[0032] Figure 9 The layout of the 4-bit single-rail and dual-rail hybrid non-pipeline ALU in the embodiments. DETAILED DESCRIPTION

[0033] For synchronous circuits, a global clock controls all functional modules. The worst-case delay must be less than the clock period, and the states of all functional modules change simultaneously with the clock period. As the size of transistors in synchronous circuits becomes smaller and smaller, many problems become more prominent, such as wire delay and clock skew. Asynchronous circuits are clockless systems, i.e., there is no control of a global clock, and each stage of the circuit has a different static delay. Compared with synchronous circuits, asynchronous circuits have many advantages, including no clock skew, low power consumption, and low delay.

[0034] Asynchronous circuits use data encoding and handshake protocols to communicate. The handshake protocol provides a request (req) - response (ack) mechanism to ensure that there is no conflict in the data flow between two registers (or latches). A simple handshake protocol and double rail encoding are shown in Figure 1 The handshake protocol method can have a four-phase handshake protocol and a two-phase handshake protocol. The two-phase handshake protocol is based on event triggering, and the request and response of the control signal are represented by the rising edge or the falling edge. There is no difference between 1-0 and 0-1 flip in the encoding, also known as non-return-to-zero (NRZ) protocol. The four-phase handshake protocol is based on voltage level triggering, and only the high level represents the request and response of the control signal. The control signal has a zero-return action, also known as return-to-zero (RTZ) protocol; RTZ represents that the request and confirmation signal needs to return a 0 signal, and NRZ does not need to return a 0 signal. Data encoding includes double rail encoding and single rail encoding. Double rail encoding requires two lines to represent one bit of data, and the data includes 00, 01, 10, and 11. Double rail encoding 11 is invalid data. Single rail encoding requires one line to represent one bit of data (1 and 0). The area of the double rail circuit is 1.5-2 times that of the single rail circuit. In comparison, the single rail circuit has an advantage in circuit area and power consumption.

[0035] Referring to Figure 1 Part (a) of the figure represents a four-phase double rail handshake protocol and data encoding, and part (b) of the figure represents a two-phase single rail handshake protocol and data encoding.

[0036] Asynchronous circuits are divided into two-phase single rail asynchronous circuits and four-phase double rail asynchronous circuits. Among them, the two-phase single rail asynchronous circuit includes a bundled data (BD) circuit and the like; the four-phase double rail asynchronous circuit includes a null convention logic (NCL) and the like. The NCL circuit belongs to a delay insensitive (DI) circuit.

[0037] An arithmetic logic unit (ALU) is a core part of a microprocessor, mainly performing arithmetic and logic operations. Its execution speed and power consumption limit the performance of the entire microprocessor. The NCL ALU circuit can provide lower power consumption and higher speed in a clockless environment. However, the NCL ALU achieves high performance (i.e., low power consumption and high speed) at the expense of area overhead, especially a 16-bit or 32-bit NCL ALU needs to consume a large area. At this time, a new NCL circuit structure needs to cater to small area and high performance at the same time, and a single-double rail hybrid circuit structure is a valuable method.

[0038] The NCL circuit is composed of 27 basic threshold gates with state holding behavior. With TH22 as a column, the state holding behavior means that when all inputs are 1, the output of TH22 is 1; when all inputs are 0, the output of TH22 is 0; otherwise, the output of TH22 remains unchanged. Table 1 shows 14 groups of NCL basic threshold gates, each of which corresponds to a logic function. Three gates in Table 1 are not within the scope of basic threshold gates (THxor0, THand0 and TH24comp). According to the logic function, the basic threshold gate can be divided into four types: THnn, TH1n, THmn and THmnWw1. THnn is equivalent to a two-input C cell; TH1n is similar to an n-input OR cell; THmn has the functions of both a Boolean OR cell and a C cell. THmnWw1w2...wr(r<n), where n is the number of inputs, m is the threshold gate, and the weight wr needs to satisfy m≥wr≥1. When the inputs satisfy the following formula, the output is 1

[0039] (w1x A1) + (w2x A2) +... + (wrx Ar) + A(r+1) +... + An≥m (1)

[0040] A1-An corresponds to n input signals of the threshold gate. At least m inputs are 1, and the output is 1. When n inputs are 0, the output is 0. The remaining input state retains its previous output state. The NCL basic gate is shown in Table 1,

[0041] Table 1

[0042]

[0043] The NCL double-track pipelined system is shown in Figure 2 , which is an N-bit double-track NCL register with an output completion detection function. The Ko signal of the current register is recorded as the confirmation signal, and the Ki signal of the previous register is recorded as the request signal. The output completion detection function uses N-way Ko signal to detect DATA (01 or 10) or NULL (00), and its characteristics are as follows: the NCL register will not request NULL until it receives all the current DATA, and the NCL register will not request the next DATA until it receives all the current NULL, i.e., the completion detection circuit ensures that DATA and NULL are performed alternately. The delay TASY of one operation cycle is calculated as follows:

[0044] TASY = 2TR1 + TCL + TR2 + TOCD (2)

[0045] TR1 and TR2 are the delays of the NCL register, including the data value passing through the current NCL register (i.e., data transmission) and the Ki signal from the previous stage passing through the current NCL register (i.e., data reset). TCL is the delay of the DI combinational logic circuit, and TOCD is the delay of the output completion detection circuit.

[0046] A pipelined NCL system uses three-stage NCL registers, while a non-pipelined NCL system uses two-stage NCL registers. The DATA / NULL cycle of a pipelined NCL system is described as follows: When the output signal (Q) of the current register is valid data (DATA), Ko is converted to 1, causing the Ki signal of the previous stage register to be converted to 1 to await the next NULL; when the output signal (Q) of the current register has been converted to NULL, Ko is converted to 0, causing the Ki of the previous register to be converted to 0 to await the next DATA. Therefore, in an NCL circuit, two DATA values ​​are separated by a NULL value to avoid data overwriting.

[0047] like Figure 3 As shown, the 4-bit dual-rail non-pipelined ALU includes dual-rail registers (3-bit / 5-bit / 9-bit), dual-rail multiplexers 1 / 2 / 3, output completion detection circuitry (1 / 2), an 8-rail converter, AND, OR, XOR, NOT, left shift, right shift, add / subtract converters, and carry logic. The dual-rail input signals include A0-A3 (4-bit input signals A), B0-B3 (4-bit input signals B), Cin / Bin (1-bit carry / borrow input signals), and S0-S2 (3-bit selection signals). The dual-rail output signals are F0-F3 (4-bit output signals) and Cout / Bout (1-bit carry / borrow output signals). Table 2 shows the ALU function table. S0-S2 selects the corresponding function via the 8-rail converter. The ALU has eight functions: OR, AND, XOR, NOT, left shift, right shift, add, and subtract.

[0048] Taking the ALU OR function as an example, its operation is as follows: When the reset signal is high, the output signals of the 9-bit dual-rail register and the 3-bit dual-rail register are low; that is, the ALU is NULL, and Ki and Ko are both 1. When the reset signal is low and the 3-bit selection signal is S2S1S0 = 000, the 4-bit input signals A and B perform an OR operation through the dual-rail multiplexer 1 to output the signal. The output signal then passes through the dual-rail multiplexer 2 and the 5-bit dual-rail register to obtain the final result (FF) of A OR B. FF outputs a low signal (Ki = 0) through the completion detection circuit 2. Correspondingly, the detection circuit 1 outputs a low signal (Ko = 0), and the ALU is reset to NULL to wait for the next data.

[0049] Table 2

[0050]

[0051]

[0052] In the embodiment, referring to Figure 4 , the single-double track hybrid circuit system of the NCL comprises a first NCL register, a double track-single track converter, synchronous combination logic circuit, a single track-double track converter and a second NCL register; the double track-single track converter is used for converting input double track encoded data into single track encoded data, and the single track-double track converter is used for converting input single track encoded data into double track encoded data.

[0053] Referring to Figure 4 , the output end of the first NCL register is connected with the input end of the double track-single track converter, the output end of the double track-single track converter is connected with the input end of the synchronous combination logic circuit, the output end of the synchronous combination logic circuit is connected with the input end of the single track-double track converter, and the output end of the single track-double track converter is connected with the input end of the second NCL register.

[0054] In the embodiment, the two NCL registers of the first NCL register and the second NCL register both belong to NCL double track registers, and are used for data transmission, holding and resetting. That is to say, the first NCL register and the second NCL register can both work in a transmission phase, a holding phase and a resetting phase. Taking the first NCL register as an example, when the first NCL register works in the transmission phase, the first NCL register transmits double track data DATA (1 or 0); when the first NCL register works in the holding phase, the first NCL register keeps the current double track data unchanged; when the first NCL register works in the resetting phase, the first NCL register works to reset the output to 0.

[0055] In the embodiment, the structure of the double track-single track converter is as shown in Figure 5 , which comprises a first inverter and an AND gate, the input end of the first inverter and one input end of the AND gate are connected as the input end of the double track-single track converter, the input end of the first inverter is connected with the other input end of the AND gate, and the output end of the AND gate is connected as the output end of the double track-single track converter.

[0056] In the embodiment, the structure of the single track-double track converter is as shown in Figure 6 , which comprises a second inverter and a buffer, the input end of the second inverter is connected with the input end of the buffer and connected as the input end of the single track-double track converter, the output end of the second inverter is connected with the output end of the buffer and connected as the output end of the single track-double track converter.

[0057] In the embodiment, the synchronous combination logic circuit comprises at least one of the following operation circuits: AND operation circuit, OR operation circuit, XOR operation circuit, NOT operation circuit, SHL operation circuit, SHR operation circuit, ADD operation circuit and SUB operation circuit, so that the synchronous combination logic circuit can perform at least one of the following operations on the input data: AND operation, OR operation, XOR operation, NOT operation, SHL operation, SHR operation, ADD operation and SUB operation.

[0058] In the embodiment, the operation circuit in the synchronous combination logic circuit mainly adopts a transmission gate structure. The transmission gate circuit has an advantage over the traditional pull-up and pull-down CMOS network circuit in transmission speed. Specifically, the NOT operation circuit adopts a pull-up and pull-down CMOS network; the OR operation circuit, the AND operation circuit and the XOR operation circuit use a transmission gate logic; the SHL operation circuit and the SHR operation circuit use an NMOS gate; the ADD operation circuit and the SUB operation circuit adopt a full adder, and the SUB operation is essentially the negation of the result of the ADD operation plus 1.

[0059] In the embodiment, with reference to Figure 4 , the single-rail and double-rail hybrid circuit system of the NCL further comprises an output completion detection circuit; an input end of the output completion detection circuit is connected with a data end of the second NCL register, and an output end of the output completion detection circuit is connected with a data end of the first NCL register.

[0060] The output completion detection circuit is used to prevent the second NCL register from requesting the first NCL register to send a null signal before receiving all the data sent by the first NCL register, and to prevent the second NCL register from requesting the first NCL register to send data before receiving all the null signals sent by the first NCL register. Specifically, the second NCL register will not request NULL before receiving all the current DATA, and the second NCL register will not request the next DATA before receiving all the current NULL, so that the completion detection circuit can ensure that the DATA and the NULL are performed alternately.

[0061] In the embodiment, the structure of the single-rail and double-rail hybrid operation logic unit of the NCL is as shown in Figure 7 , which comprises a 9-bit double-rail register, a 3-bit double-rail register, a 5-bit double-rail register, a first output completion detection circuit, a second output completion detection circuit, a first double-rail to single-rail converter, a second double-rail to single-rail converter, a third double-rail to single-rail converter, a first single-rail to double-rail converter, a second single-rail to double-rail converter, a logic operation circuit and a carry logic circuit.

[0062] Referring to Figure 7 , in the single-double rail hybrid Arithmetic Logic Unit (ALU) of NCL, the first output completion detection circuit is connected with the 9-bit double rail register and the 3-bit double rail register respectively; the second output completion detection circuit is connected with the 9-bit double rail register, the 3-bit double rail register and the 5-bit double rail register respectively; the 9-bit double rail register is connected with the first double rail-single rail converter; the first double rail-single rail converter is connected with the logic operation circuit; the logic operation circuit is connected with the first single rail-double rail converter and the second single rail-double rail converter respectively; the first single rail-double rail converter is connected with the 5-bit double rail register through the second double rail-single rail converter; the second single rail-double rail converter is connected with the third double rail-single rail converter; the carry logic circuit is connected with the 9-bit double rail register, the 3-bit double rail register, the 5-bit double rail register and the third double rail-single rail converter respectively.

[0063] An arithmetic logic unit (ALU) based on a single-double rail hybrid circuit system of NCL, as shown in Figure 7 , the arithmetic logic unit is used to realize arithmetic operation and logic operation, including eight operation functions, i.e. OR, AND, XOR, NOT, left shift (SHL), right shift (SHR), addition (ADD) and subtraction (SUB), the arithmetic operation includes subtraction and addition, and the logic operation includes OR, AND, XOR, NOT, left shift, right shift and other operation circuits; the design indicators include power consumption, delay and chip area.

[0064] In this embodiment, the operation circuits such as OR, AND, XOR, NOT, left shift (SHL), right shift (SHR), addition (ADD) and subtraction (SUB) adopt synchronous combinational logic circuits. The operation circuits in the synchronous combinational logic circuits mainly adopt transmission gate structure, the transmission gate circuit has an advantage over the traditional pull-up and pull-down CMOS network circuit in transmission speed, the NOT adopts pull-up and pull-down CMOS network; the OR, AND and XOR use transmission gate logic; the SHL and SHR use NMOS gate; the ADD and SUB adopt full adders, and the SUB is essentially the negation of addition plus 1. The second double rail-single rail converter (synchronous multiplexer) is composed of AND circuit and OR circuit, and uses transmission gate structure; the third double rail-single rail converter (double rail multiplexer) belongs to single rail encoding, and the true value part of 01 in double rail encoding is 0, and the true value part of 10 is 1.

[0065] In this embodiment, referring to Figure 7The single-double rail hybrid operation logic unit of the NCL further comprises an 8-rail converter; the 8-rail converter is connected with the 3-bit double rail register and the first double rail-single rail converter respectively, and is used for controlling the logic operation circuit to select a logic operation to be performed.

[0066] Compared with the double rail NCL pipeline system, the NCL single-double rail hybrid pipeline system has lower power consumption and smaller area consumption under almost the same delay.

[0067] Table 3 is ALU performance comparison 1. After OR operation test, compared with the double rail NCL ALU, the single-double rail hybrid NCL ALU has obvious advantages in the number of transistors, layout area and power consumption; the number of transistors of the single-double rail hybrid NCL ALU is reduced by 392 (14.8%) (2264 vs. 2656), the power consumption is reduced by 2.65 mW (47%) (2.97 vs. 5.62), and the layout area is reduced by 0.16 mm 2 (59%) (0.11 vs. 0.27). Figure 8 is a 4-bit double rail non-pipelined ALU layout, and the layout area is 0.272 mm 2 , Figure 9 is a 4-bit single-double rail hybrid non-pipelined ALU layout, and the layout area is 0.112 mm 2 ; Table 4 is ALU performance comparison 2, which includes comparison of AND, XOR, NOT, SHL and ADD functions. Compared with the double rail NCL ALU, the power consumption of AND, XOR, NOT, SHL and ADD in the NCL single-double rail hybrid ALU is reduced by 47%, 42%, 24%, 45% and 53% respectively; the delay of AND, XOR, NOT, SHL and ADD in the NCL single-double rail hybrid ALU is reduced by 0.09, -0.82, -0.09, -0.02 and 0.86 respectively.

[0068] Table 3

[0069]

[0070] Table 4

[0071]

[0072] It can be seen from the comparison results shown in Tables 3 and 4 that the single-dual rail hybrid circuit system of the NCL and the single-dual rail hybrid operation logic unit of the NCL in the embodiment both include basic devices such as a dual rail-single rail converter, a single rail-dual rail converter and a synchronous combination logic circuit. The 4-bit dual rail NCL pipeline ALU adopts the single-dual rail hybrid circuit system, the single-dual rail hybrid circuit system includes a (dual rail-single rail converter) dual rail multiplexer, a single rail-dual rail converter and a synchronous multiplexer, the operation logic unit adopts a synchronous combination logic circuit, the functions of the synchronous combination logic circuit include or, and, exclusive or, not, left shift, right shift, addition and subtraction, by adopting a single rail encoding form between two dual rail NCL registers, the advantages of small area overhead and low power consumption of a single rail encoding circuit and the advantages of high speed and low time delay of a dual rail encoding circuit are both achieved, the area of the NCL circuit is obviously reduced, and the power consumption is further reduced.

[0073] It should be noted that, unless otherwise specified, when a certain feature is referred to as being "fixed", "connected" to another feature, it can be directly fixed, connected to the other feature, or indirectly fixed, connected to the other feature. In addition, the up, down, left, right and the like used in the present disclosure are only relative to the relative position relationship of the components of the present disclosure in the drawings. The singular forms "a", "an" and "the" used in the present disclosure are also intended to include the plural forms, unless the context clearly indicates otherwise. In addition, unless otherwise defined, all technical and scientific terms used in the present embodiment are the same as those commonly understood by those skilled in the art. The terms used in the present embodiment are only used to describe the specific embodiments, and are not intended to limit the present application. The term "and / or" used in the present embodiment includes any combination of one or more related listed items.

[0074] It should be understood that although the terms first, second, third, etc. can be used in the present disclosure to describe various elements, these elements should not be limited to these terms. These terms are only used to distinguish elements of the same type from each other. For example, without departing from the scope of the present disclosure, the first element can also be referred to as the second element, and similarly, the second element can also be referred to as the first element. The use of any and all examples or exemplary language (for example, "for example", "for example", etc.) provided in the present embodiment is only intended to better illustrate the embodiments of the present application, and unless otherwise required, it does not impose a limitation on the scope of the present application.

[0075] It should be appreciated that embodiments of the present application can be implemented or realized in a computer system having computer hardware, a combination of computer hardware and software, or by computer software configured to be executed by a computer hardware. The methods can be implemented in a computer program which is executable by the computer program using standard programming techniques - including non-transitory computer readable storage medium configured with a computer program, wherein the storage medium so configured causes the computer to operate in a specific and predefined manner as described in the specific embodiments and drawings. Each program can be implemented in a high level procedural or object oriented programming language to be executed in a computer system. However, if required, the programs can be implemented in assembly or machine language. In any case, the language can be a compiled or interpreted language. Moreover, such programs can be able to operate in stand-alone mode or be able to operate by being incorporated into a operating system of the computer platform.

[0076] Further, the operations of the processes described in this embodiment can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The processes described in this embodiment (or variations and / or combinations thereof) can be implemented under the control of one or more computer systems configured with executable instructions (e.g., computer programs, one or more computer programs, or one or more applications) to perform the operations of the processes, by hardware, or combinations thereof. The computer programs include machine instructions operable to cause one or more processors to perform the processes described herein.

[0077] Further, the methods can be implemented in any suitable type of computing platform operably connected to, including but not limited to, a personal computer, mini-computer, mainframe, workstation, networked or distributed computing environment, separate or integrated computer platforms, or in communication with charged particle tools or other imaging devices, etc. Aspects of the present application can be implemented in machine readable code stored on a non-transitory storage medium or device, whether removable or integrated into a computing platform, such as a hard disk, optical read and / or write storage media, RAM, ROM, etc., such that it is readable by a programmable computer and, when the storage medium or device is read by the computer, is operable to configure and operate the computer to perform the processes described herein. Further, the machine readable code, or portions thereof, can be transmitted over wired or wireless networks. The present application described in this embodiment includes these and other different types of non-transitory computer readable storage media when such media include instructions or programs to implement the steps described above in conjunction with a microprocessor or other data processor. The present application also includes the computer itself when programmed according to the methods and techniques described in the present application.

[0078] A computer program can be applied to input data to perform the functions described in this embodiment, thereby transforming the input data to generate output data that is stored to non-volatile memory. The output information can also be applied to one or more output devices such as a display. In a preferred embodiment of the application, the transformed data represents a physical and tangible object, including a particular visual depiction of a physical and tangible object produced on a display.

[0079] The above description is only preferred embodiments of the present application, the present application is not limited to the above-described embodiments, as long as the same means to achieve the technical effects of the present application, any modification, equivalent replacement, improvement, etc. within the spirit and principles of the present application, should be included in the scope of protection of the present application. The technical solutions and / or embodiments within the scope of protection of the present application can have various modifications and changes.

Claims

1. A single-rail hybrid circuit system of NCL, characterized in that: the single-rail hybrid circuit system of NCL comprises a first NCL register, a double-rail to single-rail converter, a synchronous combination logic circuit, a single-rail to double-rail converter and a second NCL register; the double-rail to single-rail converter is used to convert input double-rail data into single-rail data, and the single-rail to double-rail converter is used to convert input single-rail data into double-rail data; an output end of the first NCL register is connected with an input end of the double-rail to single-rail converter, an output end of the double-rail to single-rail converter is connected with an input end of the synchronous combination logic circuit, an output end of the synchronous combination logic circuit is connected with an input end of the single-rail to double-rail converter, and an output end of the single-rail to double-rail converter is connected with an input end of the second NCL register; the single-rail hybrid circuit system of NCL further comprises an output completion detection circuit; an input end of the output completion detection circuit is connected with a data end of the second NCL register, an output end of the output completion detection circuit is connected with a data end of the first NCL register, and the output completion detection circuit is used to prevent the second NCL register from requesting the first NCL register to send a null signal before receiving all data sent by the first NCL register, and to prevent the second NCL register from requesting the first NCL register to send data before receiving all null signals sent by the first NCL register; the second NCL register will not request NULL before receiving all current DATA, and the second NCL register will not request next DATA before receiving all current NULL. The double-rail to single-rail converter comprises a first inverter and an AND gate, an input end of the first inverter and one input end of the AND gate serve as an input end of the double-rail to single-rail converter, the input end of the first inverter is connected with the other input end of the AND gate, and an output end of the AND gate serves as an output end of the double-rail to single-rail converter. The single-rail to double-rail converter comprises a second inverter and a buffer, an input end of the second inverter is connected with an input end of the buffer and serves as an input end of the single-rail to double-rail converter, an output end of the second inverter is connected with an output end of the buffer and serves as an output end of the single-rail to double-rail converter. The synchronous combination logic circuit is used to perform at least one operation of AND operation, OR operation, XOR operation, NOT operation, left shift operation, right shift operation, addition operation and subtraction operation on input data. The synchronous combination logic circuit is a transmission gate structure. The first NCL register and the second NCL register can work in a transmission phase, a holding phase and a reset phase; double-rail data is transmitted in the transmission phase, current double-rail data is kept unchanged in the holding phase, and 0 is output in the reset phase.

2. The single-double rail hybrid circuit system of NCL as claimed in claim 1 wherein, ​ 3. The single double rail hybrid circuit system of NCL as claimed in claim 1 wherein, ​ 4. The single double rail hybrid circuit system of NCL as claimed in claim 1 wherein, ​ 5. The single-double rail hybrid circuit system of NCL as claimed in claim 4, wherein, ​ 6. The single double rail hybrid circuit system of NCL as claimed in claim 1 wherein, ​ 7. A single-rail hybrid ALU of NCL, implemented by the single-rail hybrid circuit system of any one of claims 1 to 6, wherein: the single-rail hybrid ALU of NCL comprises a 9-bit dual-rail register, a 3-bit dual-rail register, a 5-bit dual-rail register, a first output completion detection circuit, a second output completion detection circuit, a first dual-rail to single-rail converter, a second dual-rail to single-rail converter, a third dual-rail to single-rail converter, a first single-rail to dual-rail converter, a second single-rail to dual-rail converter, a logic operation circuit, and a carry logic circuit; the first output completion detection circuit is connected to the 9-bit dual-rail register and the 3-bit dual-rail register, respectively; the second output completion detection circuit is connected to the 9-bit dual-rail register, the 3-bit dual-rail register, and the 5-bit dual-rail register, respectively; the 9-bit dual-rail register is connected to the first dual-rail to single-rail converter; the first dual-rail to single-rail converter is connected to the logic operation circuit; the logic operation circuit is connected to the first single-rail to dual-rail converter and the second single-rail to dual-rail converter, respectively; the first single-rail to dual-rail converter is connected to the 5-bit dual-rail register through the second dual-rail to single-rail converter; the second single-rail to dual-rail converter is connected to the third dual-rail to single-rail converter; and the carry logic circuit is connected to the 9-bit dual-rail register, the 3-bit dual-rail register, the 5-bit dual-rail register, and the third dual-rail to single-rail converter, respectively. The logic operation circuit is configured to perform AND operation, OR operation, XOR operation, NOT operation, left shift operation, right shift operation, addition operation, and subtraction operation on input data. The single-rail hybrid ALU of NCL further comprises an 8-track converter, which is connected to the 3-bit dual-rail register and the first dual-rail to single-rail converter, respectively, and is configured to control the logic operation circuit to select a logic operation to be performed. ​ ​ ​ ​ ​ ​ ​ 8. The single double rail hybrid logic unit of the NCL as claimed in claim 7, wherein, ​ 9. The single double rail hybrid logic operation unit of NCL as claimed in claim 8 wherein, ​

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